Semiconductor device and electronic system including the same

Abstract

To provide semiconductor devices with denser integration density and greater reliability and an electronic system comprising the same.SOLUTION: A semiconductor device comprises: a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, where the horizontal layers include gate horizontal layers disposed in a gate region and first insulating horizontal layers disposed in a first insulating region; a memory vertical structure including a portion penetrating the gate horizontal layers in a vertical direction; dummy vertical structures including a portion penetrating the gate horizontal layers in the vertical direction and separated from the memory vertical structure; a first peripheral contact plug including a portion penetrating the first insulating region in the vertical direction; and gate contact plugs disposed on gate pads of the gate horizontal layers.SELECTED DRAWING: Figure 2a

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic system including the same.

Background Art

[0002] In an electronic system that requires data storage, there is a need for a semiconductor device capable of storing high-capacity data. Accordingly, a solution for increasing the data storage capacity of a semiconductor device has been studied. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor device with improved integration and reliability and an electronic system including the same.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present invention made to achieve the above object includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure, a laminated structure including an interlayer insulating layer alternately and repeatedly laminated on the lower structure, and a horizontal layer including a gate horizontal layer disposed in a gate region and a first insulating horizontal layer disposed in a first insulating region, a memory vertical structure including a portion penetrating the gate horizontal layer in a vertical direction, a dummy vertical structure including a portion penetrating the gate horizontal layer in the vertical direction and separated from the memory vertical structure, a first peripheral contact plug including a portion penetrating the first insulating region in the vertical direction, and a gate contact plug disposed on a gate pad of the gate horizontal layer, the gate contact plug and the first peripheral contact plug having upper surfaces located at the same height level, and at the same height level, each of the dummy vertical structures having a width larger than the width of each of the memory vertical structures, the memory vertical structure including a first material different from the material of the dummy vertical structure, the memory vertical structure and the dummy vertical structure contacting the pattern structure and extending downward from an upper surface of the pattern structure into the pattern structure, and at least some of the dummy vertical structures extending deeper into the pattern structure downward from the upper surface of the pattern structure than the memory vertical structure.

[0006] A semiconductor device according to another aspect of the present invention made to achieve the above object includes a lower structure including a peripheral circuit and a pad pattern electrically connected to the peripheral circuit, an interlayer insulating layer alternately and repeatedly laminated on the lower structure, and a horizontal layer including a gate horizontal layer disposed in a gate region and an insulating horizontal layer disposed in an insulating region. The horizontal layer extends from a memory cell array region to a stepped region adjacent to the memory cell array region and includes a stacked structure including the gate region and the insulating region whose side surfaces are surrounded by the gate region in the stepped region. In the memory cell array region, a memory vertical structure including a portion penetrating the gate horizontal layer in a vertical direction. In the stepped region, a dummy vertical structure including a portion penetrating the gate horizontal layer in a vertical direction. A peripheral contact plug that contacts the pad pattern and extends in a vertical direction to penetrate the insulating region. In the stepped region, a gate contact plug disposed on a gate pad of the gate horizontal layer. The gate contact plug and the peripheral contact plug have upper surfaces located at the same height level as each other. In the stepped region, the stacked structure includes a first stepped region, a second stepped region, and a stepped connection region between the first stepped region and the second stepped region, which are arranged in order in a first direction away from the memory cell array region. Each of the first and second stepped regions includes a stepped shape that becomes lower with a first height difference in the first direction. The upper surface of the stepped connection region is flat in the first direction or has a shape with a height difference smaller than the first height difference in the first direction. A part of the stepped connection region is the insulating region. The memory vertical structure includes a material different from that of the dummy vertical structure.

[0007] An electronic system according to one aspect of the present invention made to achieve the above object includes a main board, a semiconductor device on the main board, and a controller electrically connected to the semiconductor device on the main board. The semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure, a stacked structure including an interlayer insulating layer alternately and repeatedly stacked on the lower structure, and a horizontal layer including a gate horizontal layer disposed in a gate region and an insulating horizontal layer disposed in an insulating region, a memory vertical structure including a portion penetrating the gate horizontal layer in a vertical direction, a dummy vertical structure including a portion penetrating the gate horizontal layer in the vertical direction and separated from the memory vertical structure, a peripheral contact plug including a portion penetrating the insulating region in the vertical direction, and a gate contact plug disposed on a gate pad of the gate horizontal layer. The gate contact plug and the peripheral contact plug have upper surfaces located at the same height level with respect to each other. At the same height level, each of the dummy vertical structures has a width larger than the width of each of the memory vertical structures. The memory vertical structure includes a material different from the material of the dummy vertical structure. The memory vertical structure and the dummy vertical structure are in contact with the pattern structure and extend downward from an upper surface of the pattern structure into the pattern structure. At least some of the dummy vertical structures extend deeper into the pattern structure downward from the upper surface of the pattern structure than the memory vertical structure.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor device with improved integration density and reliability and an electronic system including the same.

[0009] The various and meaningful advantages and effects of the present invention are not limited to the above-described content and can be more easily understood in the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0012] First, with reference to FIGS. 1, 2a, 2b, and 2c, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a plan view schematically showing a semiconductor device 1 according to an embodiment of the present invention, FIG. 2a is a cross-sectional view schematically showing a region cut along line I-I' of FIG. 1, FIG. 2b is a cross-sectional view schematically showing a region cut along line II-II' of FIG. 1, and FIG. 2c is a cross-sectional view schematically showing a region cut along line III-III' of FIG. 2b.

[0013] Referring to FIGS. 1, 2a, 2b, and 2c, the semiconductor device 1 according to the present embodiment includes a lower structure 3, a stacked structure ST, a capping insulating structure 55, a memory vertical structure 58, a dummy vertical structure 72, a separation structure 82, a peripheral contact plug 86p, and a gate contact plug 86g.

[0014] The semiconductor device 1 according to the present embodiment further includes a pattern structure 20.

[0015] The semiconductor device 1 according to the present embodiment further includes a bit line 93, a gate connection wiring 94, and a source connection wiring 95.

[0016] The semiconductor device 1 according to this embodiment further includes a bit line connection pattern 90, a gate connection pattern 91g, a peripheral contact connection pattern (91a, 91b, 91c), a source contact connection pattern 91s, and an outer peripheral contact connection pattern 91d.

[0017] In this embodiment, the lower structure 3 includes a semiconductor substrate 5, a peripheral circuit PC on the semiconductor substrate 5, and a lower insulating structure 18 that covers the peripheral circuit PC on the semiconductor substrate 5. The peripheral circuit PC includes a peripheral element 12 disposed on the semiconductor substrate 5 and a peripheral wiring structure 14 electrically connected to the peripheral element 12 on the semiconductor substrate 5.

[0018] The peripheral element 12 includes a transistor including a peripheral source / drain 10 and a peripheral gate 9g. For example, the peripheral gate 9g is disposed on an active region 7a defined by an element isolation layer 7s on the semiconductor substrate 5, and the peripheral source / drain 10 is disposed in the active region 7a on both sides of the peripheral gate 9g. The peripheral gate 9g includes a peripheral gate dielectric layer 9a and a peripheral gate electrode 9b laminated in sequence. The peripheral wiring structure 14 forms a conductor layer extending in the vertical and horizontal directions.

[0019] In this embodiment, the lower structure 3 further includes a peripheral pad pattern 15p electrically connected to the peripheral wiring structure 14 on the peripheral wiring structure 14. Each peripheral pad pattern 15p has a thickness greater than the thickness of the peripheral gate electrode 9b. The peripheral pad pattern 15p includes a metal material such as tungsten. The peripheral pad pattern 15p includes a first peripheral pad pattern 15p_1, a second peripheral pad pattern 15p_2, a third peripheral pad pattern 15p_3, and an outer peripheral pad pattern 15p_4.

[0020] The lower insulating structure 18 includes a first lower insulating layer 18a that covers the peripheral wiring structure 14 on the semiconductor substrate 5 and surrounds the side surface of the peripheral pad pattern 15p, an etching stop layer 18b on the first lower insulating layer 18a and the peripheral pad pattern 15p, and a third lower insulating layer 18c on the etching stop layer 18b.

[0021] The etching stop layer 18b is formed of the materials of the first and third lower insulating layers (18a, 18c) adjacent to the etching stop layer 18b and other materials. For example, the etching stop layer 18b is formed of silicon nitride or a high-k dielectric material, and the first and third lower insulating layers (18a, 18c) adjacent to the etching stop layer 18b are formed of silicon oxide or a low-k dielectric material.

[0022] In the present embodiment, the lower structure 3 further includes a pattern structure 20.

[0023] In the present embodiment, the pattern structure 20 includes a lower pattern layer 22, a first intermediate pattern layer 25a and a second intermediate pattern layer 25b spaced apart from each other on the lower pattern layer 22, and an upper pattern layer 27 covering the first and second intermediate pattern layers (25a, 25b) on the lower pattern layer 22.

[0024] In the present embodiment, the lower pattern layer 22 includes a first polysilicon, the first intermediate pattern layer 25a includes a second polysilicon, and the upper pattern layer 27 includes a third polysilicon. For example, the lower pattern layer 22, the first intermediate pattern layer 25a, and the upper pattern layer 27 include polysilicon having an N-type conductivity type.

[0025] In the present embodiment, the upper pattern layer 27 contacts the lower pattern layer 22 between the first and second intermediate pattern layers (25a, 25b) and penetrates a part of the second intermediate pattern layer 25b to contact the lower pattern layer 22. The portion where the upper pattern layer 27 and the lower pattern layer 22 contact is referred to as a support portion 27s.

[0026] In one embodiment, the second intermediate pattern layer 25b includes an insulating material.

[0027] In this embodiment, the lower structure 3 further includes a grounding structure. The grounding structure further includes a grounding impurity region 11 formed within the active region 7a of the semiconductor substrate 5, a grounding wiring structure 14g electrically connected to the grounding impurity region 11 on the grounding impurity region 11, a grounding pad pattern 15g electrically connected to the grounding wiring structure 14g on the grounding wiring structure 14g, and a grounding pattern 22V extending from the lower part of the lower pattern layer 22 and electrically connected to the grounding pad pattern 15g. The grounding impurity region 11 has an N-type conductivity type. The grounding pad pattern 15g is formed of the same material as the peripheral pad pattern 15p at the same height level as the peripheral pad pattern 15p.

[0028] In this embodiment, the lower structure 3 further includes a first gap-fill insulating layer 29a, a second gap-fill insulating layer 29b, and a third gap-fill insulating layer 29c that penetrate the pattern structure 20.

[0029] In this embodiment, the lower structure 3 further includes an outer insulating layer 29d surrounding the outer surface of the pattern structure 20.

[0030] In this embodiment, the lower structure 3 further includes an insulating layer 29e that fills a recessed region of the pattern structure 20, for example, a recessed portion above the support portion 27s.

[0031] The stacked structure ST extends from the memory cell array region MCA to the stepped region SA adjacent to the memory cell array region MCA on the lower structure 3.

[0032] The stacked structure ST is formed in a stepped shape within the stepped region SA. For example, within the stepped region SA, the stacked structure ST includes an upper stepped region IS1, a first stepped connection region CS1, an intermediate stepped region IS2, a second stepped connection region CS2, and a lower stepped region IS3 arranged in order in the first direction X away from the memory cell array region MCA.

[0033] In the stacked structure ST, each of the upper, middle, and lower staircase regions (IS1, IS2, IS3) has a stepped shape with a decreasing height in the first direction X, and the upper surface of each of the first and second staircase connection regions (CS1, CS2) is substantially flat in the first direction X or has a height difference smaller than the height difference of the steps of each of the upper, middle, and lower staircase regions (IS1, IS2, IS3).

[0034] The stacked structure ST includes a gate region ST_G and an insulating region ST_I. In the stacked structure ST, the insulating region ST_I includes a first insulating region ST_Ia adjacent to the memory cell array region MCA in the second direction Y orthogonal to the first direction X, a second insulating region ST_Ib in the first staircase connection region CS1, and a third insulating region ST_Ic in the second staircase connection region CS2. In the stacked structure ST, the gate region ST_G is a region other than the insulating region ST_I. Therefore, the insulating region ST_I is surrounded by the gate region ST_G.

[0035] In the present embodiment, the stacked structure ST includes interlayer insulating layers (33, 43) and a horizontal layer 48 alternately and repeatedly stacked on the lower structure 3. The horizontal layer 48 includes a gate horizontal layer (3_{6g}, 4_{6g}) and an insulating horizontal layer (3_{6i}, 4_{6i}). The gate horizontal layer (3_{6g}, 4_{6g}) contains a conductive material, and the insulating horizontal layer (3_{6i}, 4_{6i}) is formed of an insulating material such as silicon oxide.

[0036] The gate horizontal layer (3_{6g}, 4_{6g}) is disposed in the gate region ST_G, and the insulating horizontal layer (3_{6i}, 4_{6i}) is disposed in the insulating region ST_I.

[0037] In the present embodiment, the stacked structure ST includes a lower stacked structure ST1a and an upper stacked structure ST2a on the lower stacked structure ST1a.

[0038] The lower stacked structure ST1a includes lower interlayer insulating layers 33 and lower horizontal layers 36 that are alternately and repeatedly stacked. Among the lower interlayer insulating layers 33 and the lower horizontal layers 36, the topmost layer is the topmost lower interlayer insulating layer 33U, and the lowermost layer is the lowermost lower interlayer insulating layer 33L. The topmost lower interlayer insulating layer 33U among the lower interlayer insulating layers 33 has a thickness greater than the thickness of each of the remaining lower interlayer insulating layers. The lower horizontal layer 36 includes a lower gate horizontal layer 36g and a lower insulating horizontal layer 36i.

[0039] The lower insulating horizontal layer 36i includes a first lower insulating horizontal layer 36i_1 in the first insulating region ST_Ia, a second lower insulating horizontal layer 36i_2 in the second insulating region ST_Ib, and a third lower insulating horizontal layer 36i_3 in the third insulating region ST_Ic.

[0040] The upper stacked structure ST2a includes upper interlayer insulating layers 43 and upper horizontal layers 46 that are alternately and repeatedly stacked. Among the upper interlayer insulating layers 43 and the upper horizontal layers 46, the topmost layer is the topmost upper interlayer insulating layer 43U, and the lowermost layer is the lowermost upper interlayer insulating layer 43L. The topmost upper interlayer insulating layer 43U among the upper interlayer insulating layers 43 has a thickness greater than the thickness of each of the remaining upper interlayer insulating layers. The upper horizontal layer 46 includes an upper gate horizontal layer 46g and an upper insulating horizontal layer 46i.

[0041] The upper insulating horizontal layer 46i includes a first upper insulating horizontal layer 46i_1 in the first insulating region ST_Ia and a second upper insulating horizontal layer 46i_2 in the second insulating region ST_Ib.

[0042] The interlayer insulating layers (33, 43) include the lower interlayer insulating layer 33 and the upper interlayer insulating layer 43. The horizontal layer 48 includes the lower horizontal layer 36 and the upper horizontal layer 46.

[0043] The semiconductor device 1 according to this embodiment further includes a capping insulating structure 55 that covers a part of the stacked structure ST on the lower structure 3. The capping insulating structure 55 has an upper surface that is coplanar with the upper surface of the stacked structure ST, and covers the stepped portion of the stacked structure ST. The capping insulating structure 55 includes a lower capping insulating layer 39 that covers the stepped portion of the lower stacked structure ST1a and an upper capping insulating layer 53 that covers the stepped portion of the upper stacked structure ST2a on the lower capping insulating layer 39.

[0044] The memory vertical structure 58 penetrates the gate region ST_G of the stacked structure ST within the memory cell array region MCA. The memory vertical structure 58 contacts the pattern structure 20.

[0045] The semiconductor device 1 according to this embodiment further includes first, second, third, and fourth upper insulating layers (69, 76, 84, 88) stacked in sequence.

[0046] The dummy vertical structure 72 penetrates the gate region ST_G of the stacked structure ST within the step region SA and extends in the vertical direction Z, and penetrates the first upper insulating layer 69. At least some of the dummy vertical structures 72 penetrate the capping insulating structure 55 between the first upper insulating layer 69 and the stacked structure ST.

[0047] In one embodiment, the dummy vertical structure 72 includes silicon oxide or a low-k dielectric layer.

[0048] The isolation structure 82 extends in the vertical direction Z through the stacked structure ST. The isolation structure 82 extends in the vertical direction Z from the portion that penetrates the stacked structure ST and penetrates the second upper insulating layer 76.

[0049] The isolation structure 82 includes a main isolation structure 82a that separates and spaces the stacked structure ST from each other in the second direction Y and an auxiliary isolation structure 82b that has a length smaller than the length of each of the main isolation structures 82a between the main isolation structures 82a. The isolation structure 82 includes silicon oxide.

[0050] The semiconductor device 1 according to this embodiment further includes a dam structure 80 surrounding the second and third insulating regions (ST_Ib, ST_Ic), respectively. In one embodiment, the dam structure 80 includes a material different from that of the isolation structure 82. For example, the dam structure 80 includes at least one of a material different from that of the isolation structure 82, such as polysilicon and silicon nitride.

[0051] The peripheral contact plugs 86p have upper surfaces located at substantially the same height level. Each of the peripheral contact plugs 86p includes a portion that extends downward through the first to third upper insulating layers (69, 76, 84) and penetrates the insulating region ST_I. For example, the peripheral contact plug 86p includes a first peripheral contact plug 86p_1 including a portion that vertically penetrates the first insulating region ST_Ia in the Z direction, a second peripheral contact plug 86p_b including a portion that vertically penetrates the second insulating region ST_Ib in the Z direction, and a third peripheral contact plug 86p_3 including a portion that vertically penetrates the third insulating region ST_Ic in the Z direction.

[0052] The first peripheral contact plug 86p_1 extends downward through the first gap-fill insulating layer 29a located below the first insulating region ST_Ia and contacts the first peripheral pad pattern 15p_1. The second peripheral contact plug 86p_2 extends downward through the second gap-fill insulating layer 29b located below the second insulating region ST_Ib and contacts the second peripheral pad pattern 15p_2. The third peripheral contact plug 86p_3 extends downward through the third gap-fill insulating layer 29c located below the third insulating region ST_Ic and contacts the third peripheral pad pattern 15p_3.

[0053] The semiconductor device 1 according to this embodiment further includes an outer peripheral contact plug 86op that extends downward through the first to third upper insulating layers (69, 76, 84) and the capping insulating structure 55 outside the pattern structure 20 and contacts the outer pad pattern 15p_4, and a source contact plug 86s that extends into the pattern structure 20 through the first to third upper insulating layers (69, 76, 84) and the capping insulating structure 55 and contacts the lower pattern layer 22 of the pattern structure 20.

[0054] The peripheral contact plug 86p, the source contact plug 86s, and the outer peripheral contact plug 86op have upper surfaces located at substantially the same height level.

[0055] The gate contact plug 86g is electrically connected while contacting the lower gate pad 36p of the lower gate horizontal layer 36g and the upper gate pad 46p of the upper gate horizontal layer 46g. The gate contact plug 86g, the peripheral contact plug 86p, the source contact plug 86s, and the outer peripheral contact plug 86op contain the same conductive material as each other. The gate contact plug 86g, the peripheral contact plug 86p, the source contact plug 86s, and the outer peripheral contact plug 86op have upper surfaces located at substantially the same height level.

[0056] The semiconductor device 1 according to this embodiment further includes contact spacer layers (74s_1, 74s_2, 74s_3, 74s_s, 74s_o) that cover a part of each side surface of the peripheral contact plug 86p, the source contact plug 86s, and the outer peripheral contact plug 86op. For example, the contact spacer layers (74s_1, 74s_2, 74s_3, 74s_s, 74s_o) include a first peripheral contact spacer layer 74s_1 that covers a part of the side surface of the first peripheral contact plug 86p_1, a second peripheral contact spacer layer 74s_2 that covers a part of the side surface of the second peripheral contact plug 86p_2, a third peripheral contact spacer layer 74s_3 that covers a part of the side surface of the third peripheral contact plug 86p_3, a source contact spacer layer 74s_s that covers a part of the side surface of the source contact plug 86s, and an outer peripheral contact spacer layer 74s_o that covers a part of the side surface of the outer peripheral contact plug 86op. The upper ends of the contact spacer layers (74s_1, 74s_2, 74s_3, 74s_s, 74s_o) are located at the same height level.

[0057] The semiconductor device 1 according to this embodiment further includes a bit line 93, a gate connection wiring 94, and a source connection wiring 95. In this embodiment, the bit line 93, the gate connection wiring 94, and the source connection wiring 95 are disposed on the fourth upper insulating layer 88.

[0058] The semiconductor device 1 according to this embodiment includes a bit line connection pattern 90, a gate connection pattern 91g, a first peripheral contact connection pattern 91a, a second peripheral contact connection pattern 91b, a third peripheral contact connection pattern 91c, a source contact connection pattern 91s, and an outer peripheral contact connection pattern 91d.

[0059] The bit line connection pattern 90 electrically connects the bit line 93 and the memory vertical structure 58 between the bit line 93 and the memory vertical structure 58. The gate connection pattern 91g electrically connects the gate connection wiring 94 and the gate contact plug 86g between the gate connection wiring 94 and the gate contact plug 86g.

[0060] The first peripheral contact connection pattern 91a electrically connects the first peripheral contact plug 86p_1 and the bit line 93 between the first peripheral contact plug 86p_1 and the bit line 93. The second and third peripheral contact connection patterns (91b, 91c) electrically connect the second and third peripheral contact plugs (86p_2, 86p_3) and the gate connection wiring 94 between the second and third peripheral contact plugs (86p_2, 86p_3) and the gate connection wiring 94.

[0061] The source contact connection pattern 91s electrically connects the source contact plug 86s and the source connection wiring 95, and the outer peripheral contact connection pattern 91d electrically connects the outer peripheral contact plug 86op and the source connection wiring 95.

[0062] Hereinafter, various examples or various modifications of the components described with reference to FIGS. 1 to 2c will be described. Here, descriptions of components that overlap or are similar to the above-described components will be omitted or directly cited and described.

[0063] First, with reference to FIG. 3a, an embodiment of the gate horizontal layers (36g, 46g) and the memory vertical structure 58 will be described. FIG. 3a is a partial enlarged view of the portion shown at "A1" in FIG. 2c.

[0064] Referring to FIG. 3a, each of the gate horizontal layers (36g, 46g) includes a first gate layer 47a and a second gate layer 47b. The first gate layer 47a covers the upper and lower surfaces of the second gate layer 47b and is interposed between the second gate layer 47b and the memory vertical structure 58.

[0065] In one embodiment, the first gate layer 47a includes a dielectric material, and the second gate layer 47b includes a conductive material. For example, the first gate layer 47a includes a high-k dielectric such as AlO, and the second gate layer 47b includes a conductive material such as TiN, WN, Ti, or W.

[0066] In other embodiments, the first gate layer 47a includes a first conductive material (e.g., TiN or W, etc.), and the second gate layer 47b includes a second conductive material different from the first conductive material (e.g., Ti or W, etc.).

[0067] In still other embodiments, each of the first and second gate layers (47a, 47b) is formed of doped polysilicon, a metal-semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), or a metal (e.g., Ti or W).

[0068] In this embodiment, among the gate horizontal layers (36g, 46g), the lowermost first lower gate horizontal layer 33g_La is a lower erase control gate electrode, and the second lower gate horizontal layer 33g_Lb on the first lower gate horizontal layer 33g_La is a ground selection gate electrode. Among the gate horizontal layers (36g, 46g), the first upper gate horizontal layer 46g_Ua is a string selection gate electrode, and the second upper gate horizontal layer 46g_Ub on the first upper gate horizontal layer 46g_Ua is an upper erase control gate electrode. The first lower gate horizontal layer 33g_La is one or a plurality stacked in the vertical direction Z, and the second upper gate horizontal layer 46g_Ub is one or a plurality stacked in the vertical direction Z.

[0069] In this embodiment, among the gate horizontal layers (36g, 46g), at least some of the intermediate gate horizontal layers (36M, 46M) disposed between the second lower gate horizontal layer 36g_Lb and the first upper gate horizontal layer 46g_Ua are word lines.

[0070] The memory vertical structure 58 includes an insulating core pattern 64, a channel layer 62 covering the side and bottom surfaces of the insulating core pattern 64, an information storage structure 60 disposed on the outer surface and bottom surface of the channel layer 62, and a pad pattern 66 contacting the channel layer 62 on the insulating core pattern 64.

[0071] The insulating core pattern 64 contains silicon oxide. The channel layer 62 contains polysilicon. The pad pattern 66 contains at least one of doped polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W, etc.), and metal-semiconductor compound (e.g., TiSi, etc.).

[0072] The information storage structure 60 includes a first dielectric layer 60a, a second dielectric layer 60c, and an information storage layer 60b between the first dielectric layer 60a and the second dielectric layer 60c. The second dielectric layer 60c contacts the channel layer 62, and the information storage layer 60b is separated from the channel layer 62. The first dielectric layer 60a contains silicon oxide or silicon oxide doped with impurities. The second dielectric layer 60c contains at least one of silicon oxide and high dielectric. The information storage layer 60b contains a region for storing information in a semiconductor device such as a flash memory element. For example, the information storage layer 60b contains a substance for trapping charge, such as silicon nitride.

[0073] The first intermediate pattern layer 25a penetrates the memory vertical structure 58 and contacts the channel layer 62. Therefore, the memory vertical structure 58 is separated into a lower portion 60L and an upper portion 60U by the first intermediate pattern layer 25a.

[0074] The side surface of the memory vertical structure 58 has a bent portion 58V in a region where the upper stacked structure ST2a and the lower stacked structure ST1a are adjacent to each other. For example, the memory vertical structure 58 includes a lower vertical portion 58L disposed in the lower stacked structure ST1a and an upper vertical portion 58U disposed in the upper stacked structure ST2a. The width of the lower region of the upper vertical portion 58U is smaller than the width of the upper region of the lower vertical portion 58L. Due to such a difference in width, the side surface of the memory vertical structure 58 has a bent portion, that is, a bent portion 58V, in a region where the upper vertical portion 58U and the lower vertical portion 58L are adjacent to each other.

[0075] In the present embodiment, the memory vertical structure 58 extends from the upper surface 20s of the pattern structure 20 to a first depth D1a inside the pattern structure 20. Therefore, the memory vertical structure 58 extends into the lower pattern layer 22 through the upper pattern layer 27 and the first intermediate pattern layer 25a in sequence.

[0076] Next, with reference to FIGS. 3b and 3c, an embodiment of the dummy vertical structure 72 will be described. FIG. 3b is a partially enlarged view of the portion indicated as "A2a" in FIG. 2c, and FIG. 3c is a partially enlarged view of the portion indicated as "A2b" in FIG. 2c.

[0077] Referring to FIGS. 3b and 3c, the upper surface of the dummy vertical structure 72 is located at a height level higher than the upper surface of the memory vertical structure (58 in FIG. 3a). The dummy vertical structure 72 is formed of silicon oxide. The memory vertical structure (58 in FIG. 3a) includes a material different from that of the dummy vertical structure 72, for example, the material of the channel layer 62 and the material of the pad pattern 66.

[0078] At any height level, each dummy vertical structure 72 has a width larger than the width of the memory vertical structure 58.

[0079] The dummy vertical structure 72 extends into the lower pattern layer 22 through the upper pattern layer 27 and the second intermediate pattern layer 25b of the pattern structure 20. The second intermediate pattern layer 25b includes, in the present embodiment, a first layer 26a, a second layer 26b, and a third layer 26c in which the second intermediate pattern layer 25b is laminated in sequence. The first and third layers (25a, 25c) of the second intermediate pattern layer 25b are silicon oxide layers, and the second layer 26b is a silicon nitride or polysilicon layer.

[0080] The depth to which the dummy vertical structure 72 extends into the lower pattern layer 22 is greater than the first depth (D1a in FIG. 3a) to which the memory vertical structure 58 extends from the upper surface 20s of the pattern structure 20 into the pattern structure 20. For example, the dummy vertical structure 72 includes a first dummy vertical structure (72a in FIG. 3b) close to the memory cell array region MCA and a second dummy vertical structure (72b in FIG. 3c) far from the memory cell array region MCA.

[0081] The first dummy vertical structure (72a in FIG. 3b) extends from the upper surface 20s of the pattern structure 20 into the pattern structure 20 to a second depth D1b greater than the first depth (D1a in FIG. 3a). The second dummy vertical structure (72b in FIG. 3c) extends from the upper surface 20s of the pattern structure 20 into the pattern structure 20 to a third depth D1c greater than the first depth (D1a in FIG. 3a). The third depth D1c is greater than the second depth D1b.

[0082] Next, with reference to FIGS. 4a, 4b, and 4c, an embodiment of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) and the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) will be described. FIG. 4a is a partial enlarged view of the portion indicated as "B1a" in FIG. 2a, FIG. 4b is a partial enlarged view of the portion indicated as "B1b" in FIG. 2b, and FIG. 4c is a partial enlarged view of the portion indicated as "B1c" in FIG. 2b.

[0083] Referring to FIGS. 4a, 4b, and 4c, each of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) includes a plug conductive pattern 86c, a first conductive liner layer 86b covering the side and bottom surfaces of the plug conductive pattern 86c, and a second conductive liner layer 86a covering the outer and bottom surfaces of the first conductive liner layer 86b. For example, the second conductive liner layer 86a includes a metal such as Ti, the first conductive liner layer 86b includes a metal nitride such as TiN, and the plug conductive pattern 86c includes a metal such as W.

[0084] The horizontal thickness of each of the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) is smaller than the width of each of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3).

[0085] The first peripheral contact spacer layer (74s_1 in Fig. 4a) extends from the upper surface 15s of the first peripheral pad pattern 15p_1 to the inside of the first peripheral pad pattern 15p_1 at the first depth D2a.

[0086] The second peripheral contact spacer layer (74s_2 in Fig. 4b) extends from the upper surface 15s of the second peripheral pad pattern 15p_2 to the inside of the second peripheral pad pattern 15p_2 at a second depth D2b greater than the first depth D2a. The third peripheral contact spacer layer (74s_3 in Fig. 4c) extends from the upper surface 15s of the third peripheral pad pattern 15p_3 to the inside of the third peripheral pad pattern 15p_3 at a third depth D2c greater than the second depth D2b.

[0087] In this embodiment, each of the first to third depths (D2a, D2b, D2c) is greater than the thickness t1 of the etching stop layer 18b.

[0088] Each of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) extends into each of the first to third peripheral pad patterns (within 15p_1, 15p_2, 15p_3) more than the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3). For example, the first peripheral contact plug 86p_1 extends further into the first peripheral pad pattern 15p_1 at the first depth D3a than the lower surface of the first peripheral contact spacer layer 74s_1, the second peripheral contact plug 86p_2 extends further into the second peripheral pad pattern 15p_2 at the second depth D3b than the lower surface of the second peripheral contact spacer layer 74s_2, and the third peripheral contact plug 86p_3 extends further into the third peripheral pad pattern 15p_3 at the third depth D3c than the lower surface of the third peripheral contact spacer layer 74s_3.

[0089] In this embodiment, the first to third depths (D3a, D3b, D3c) of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) are smaller than the first to third depths (D2a, D2b, D2c) of the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3).

[0090] In this embodiment, the first to third depths (D3a, D3b, D3c) of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) are smaller than the respective thicknesses of the horizontal layer 48.

[0091] Next, with reference to FIG. 5, an embodiment of the source contact plug 86s and the source contact spacer layer 74s_s will be described. FIG. 5 is a partially enlarged view of the portion indicated as "C" in FIG. 2b.

[0092] Referring to FIG. 5, the source contact plug 86s includes the same plug conductive pattern 86c as the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3), the first conductive liner layer 86b, and the second conductive liner layer 86a.

[0093] In this embodiment, the portion of the second conductive liner layer 86a that contacts the lower pattern layer 22 is formed of a metal-semiconductor compound layer 86d. The metal-semiconductor compound layer 86d includes a metal silicide such as TiSi.

[0094] The source contact spacer layer 74s_s extends from the upper surface 20s of the pattern structure 20 into the pattern structure 20 at a first depth D4a. The source contact spacer layer 74s_s penetrates the upper pattern layer 27 and the second intermediate pattern layer 25b and extends into the lower pattern layer 22.

[0095] The source contact plug 86s extends further at a first depth D4b within the lower pattern layer 22 from the source contact spacer layer 74s_s. The first depth D4b of the source contact plug 86s is greater than the first to third depths (D3a, D3b, D3c in FIGS. 4a to 4c) of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3 in FIGS. 4a to 4c). The first depth D4b of the source contact plug 86s is greater than the thickness (t1 in FIG. 4a) of the etching stop layer (18b in FIG. 4a).

[0096] Next, with reference to FIGS. 6a and 6b, a modified example of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) and the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) described with reference to FIGS. 4a to 4c will be described. FIG. 6a is a partial enlarged view showing the portions indicated as "B1a" in FIG. 4a, "B1b" in FIG. 4b, and "B1c" in FIG. 4c, respectively, and FIG. 6b is a partial enlarged view enlarging "D1a", "D2a", and "D3a" in the portion indicated as "B1a" in FIG. 6a.

[0097] Referring to FIGS. 6a and 6b, each of the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) has first and second plug side surfaces (86p_s1, 86p_s2) facing each other. In each of the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a), the second plug side surface 86p_s2 is closer to the insulating horizontal layers (36i, 46i) than the first plug side surface 86p_s1. Each of the first to third peripheral contact spacer layers (74s_1a, 74s_2a, 74s_3a) includes a first spacer portion 76s_p1 covering the first plug side surface 86p_s1 of each of the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) and a second spacer portion 76s_p2 covering the second plug side surface 86p_s2 of each of the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a). The first spacer portion 76s_p1 is interposed between the first plug side surface and the first horizontal layer portion, and the second spacer portion 76s_p2 is interposed between the second plug side surface and the second horizontal layer portion. The horizontal thickness of the first spacer portion 76s_p1 is greater than the horizontal thickness of the second spacer portion 76s_p2.

[0098] Next, referring to FIGS. 7a and 7b, a modified example of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) and the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) described with reference to FIGS. 4a to 4c will be described. FIG. 7a is a partial enlarged view showing the portions indicated as "B1a" in FIG. 4a, the portion indicated as "B1b" in FIG. 4b, and the portion indicated as "B1c" in FIG. 4c, respectively, and FIG. 7b is a partial enlarged view in which "D1b", "D2b", and "D3b" in the portion indicated as "B1a" in FIG. 7a are enlarged, respectively.

[0099] Referring to FIGS. 7a and 7b, the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) described with reference to FIGS. 4a to 4c are omitted.

[0100] The first peripheral contact plug 86p_1b includes a lower plug portion 86p_1bL and an upper plug portion 86p_1bU having a width larger than that of the lower plug portion 86_1bL on the lower plug portion 86_1bL. The upper plug portion 86p_1bU is disposed at a level higher than that of the first upper insulating horizontal layer 46i_1 located at the upper part among the insulating horizontal layers (36i, 46i) adjacent to the first peripheral contact plug 86p_1b while contacting the first upper insulating horizontal layer 46i_1 located at the upper part. In the first upper insulating horizontal layer 46i_1, the minimum thickness of the portion of the first upper insulating horizontal layer 46i_1 contacting the upper plug portion 86p_1bU is smaller than the thickness of the remaining portion.

[0101] In the first peripheral contact plug 86p_1b, the upper plug portion 86p_1bU includes a first portion 86pc overlapping the lower plug portion 86_1bL and a second portion 86pa overlapping the insulating horizontal layers (36i, 46i).

[0102] The second peripheral contact plug 86p_2b includes a lower plug portion 86p_2bL and an upper plug portion 86p_2bU having a width larger than that of the lower plug portion 86_2bL on the lower plug portion 86_2bL. The upper plug portion 86p_2bU is disposed at a level higher than that of the second upper insulating horizontal layer 46i_2 located at the upper part among the insulating horizontal layers (36i, 46i) adjacent to the second peripheral contact plug 86p_2b while contacting the second upper insulating horizontal layer 46i_2 located at the upper part.

[0103] The third peripheral contact plug 86p_3b includes a lower plug portion 86p_3bL and an upper plug portion 86p_3bU having a width larger than that of the lower plug portion 86_3bL on the lower plug portion 86_3bL. The upper plug portion 86p_3bU is disposed at a level higher than that of the third lower insulating horizontal layer 36i_3 located at the upper part among the insulating horizontal layers (36i, 46i) adjacent to the third peripheral contact plug 86p_3b while contacting the third lower insulating horizontal layer 36i_3 located at the upper part.

[0104] In the first peripheral contact plug 86p_1b, the vertical length of the upper plug portion 86p_1bU is smaller than the vertical length of the lower plug portion 86p_1bL. In the third peripheral contact plug 86p_3b, the vertical length of the upper plug portion 86p_3bU is larger than the vertical length of the lower plug portion 86p_3bL. The vertical length of the upper plug portion 86p_1bU of the first peripheral contact plug 86p_1b is smaller than the vertical length of the upper plug portion 86p_3bU of the third peripheral contact plug 86p_3b.

[0105] In FIGS. 7a and 7b, the central axes of the respective upper plug portions (86p_1bU, 86p_2bU, 86p_3bU in FIG. 7a) are aligned perpendicular to the central axes of the respective lower plug portions (86p_1bL, 86p_2bL, 86p_3bL in FIG. 7a).

[0106] Next, referring to FIG. 8, a modification of the upper plug portions (86p_1bU, 86p_2bU, 86p_3bU) described with reference to FIGS. 7a and 7b will be mainly described. FIG. 8 is a partial enlarged cross-sectional view corresponding to the partial enlarged cross-sectional view of FIG. 7b. The term "central axis" used in the embodiment means an axis passing through the center between both side surfaces of a certain component.

[0107] Referring to FIG. 8, each of the upper plug portions (86p_1bU, 86p_2bU, 86p_3bU) in FIG. 7a is deformed to have a central axis misaligned with the central axis of the respective lower plug portions (86p_1bL, 86p_2bL, 86p_3bL) in FIG. 7a. For example, in the first peripheral contact plug 86p_1b', the central axis Cz_1a of the upper plug portion 86p_1bU' is misaligned with the central axis Cz_1b of the lower plug portion 86p_1bL.

[0108] Next, with reference to FIGS. 9a and 9b, a modified example of the first to third peripheral contact plugs (86p_1, 86p_2, 86p_3) and the first to third peripheral contact spacer layers (74s_1, 74s_2, 74s_3) described with reference to FIGS. 4a to 4c will be described. FIG. 9a is a partial enlarged view showing the portions indicated as "B1a" in FIG. 4a, the portion indicated as "B1b" in FIG. 4b, and the portion indicated as "B1c" in FIG. 4c, respectively, and FIG. 9b is a partial enlarged view in which "D1c", "D2c", and "D3c" in the portion indicated as "B1a" in FIG. 9a are enlarged, respectively.

[0109] Referring to FIGS. 9a and 9b, the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c) include a lower plug portion (86p_1cL, 86p_2cL, 86p_3cL) having a first width and an upper plug portion (86p_1cU, 86p_2cU, 86p_3cU) having a second width larger than the first width and disposed on the lower plug portion (86p_1cL, 86p_2cL, 86p_3cL). The upper plug portions (86p_1cU, 86p_2cU, 86p_3cU) are disposed at the same height level as the upper plug portions (86p_1bU, 86p_2bU, 86p_3bU) described in FIG. 7a.

[0110] The respective central axes Cz_2a of the upper plug portions (86p_1cU, 86p_2cU, 86p_3cU) are not aligned with the respective central axes Cz_2b of the lower plug portions (86p_1cL, 86p_2cL, 86p_3cL).

[0111] In the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c), each of the lower plug portions (86p_1cL, 86p_2cL, 86p_3cL) has a first lower side surface 86p_s1bL and a second lower side surface 86p_s2bL that face each other, and each of the upper plug portions (86p_1cU, 86p_2cU, 86p_3cU) has a first upper side surface 86p_s1bU and a second upper side surface 86p_s2bU that face each other. The first lower side surface 86p_s1bL and the first upper side surface 86p_s1bU are aligned with each other, and the second upper side surface 86p_s2bU is not aligned with the second lower side surface 86p_s2bL. Therefore, each of the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c) has an asymmetric side surface.

[0112] The first to third peripheral contact spacer layers (74s_1b, 74s_2b, 74s_3b) cover the first lower side surface 86p_s1bL and the first upper side surface 86p_s1bU of the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c). In the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c), the second lower side surface 86p_s2bL contacts the insulating horizontal layers (36i, 46i). The upper plug portions (86p_1cU, 86p_2cU, 86p_3cU) include portions that overlap the insulating horizontal layers (36i, 46i).

[0113] Next, with reference to FIGS. 10a, 10b, and 10c, a modified example of the semiconductor device 1 according to an embodiment of the present invention will be described. FIG. 10a is a cross-sectional view schematically showing a region cut along the line I-I' of FIG. 1, FIG. 10b is a cross-sectional view schematically showing a region cut along the line II-II' of FIG. 1, and FIG. 10c is a partial enlarged view of the portion indicated by "E" in FIG. 10a.

[0114] Referring to FIGS. 10a, 10b, and 10c, in the semiconductor device 1 according to this embodiment, the lower structure 3 further includes buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4) that contact the peripheral pad pattern 15p on the peripheral pad pattern 15p. The ground pattern 22V in FIG. 2b is replaced by a source buffer pad pattern 19s formed of the same material as the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4). The source buffer pad pattern 19s is electrically connected to a source pad pattern 15sp below the source buffer pad pattern 19s. A source wiring structure 14s electrically connected to the source pad pattern 15sp is disposed below the source pad pattern 15sp. A source control element 11s of the peripheral circuit PC electrically connected to the source wiring structure 14s is disposed.

[0115] The upper surfaces of the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4) and the source buffer pad pattern 19s are disposed at substantially the same height level as the upper surface of the lower insulating structure 18.

[0116] In one embodiment, when the source buffer pad pattern 19s is disposed, the source contact plug (86s in FIG. 2b) in FIG. 2b is omitted, and the source connection wiring (95 in FIG. 2b) is replaced by the outer element connection wiring 96.

[0117] The peripheral contact plugs (86p in FIGS. 2a and 2b) and the outer peripheral contact plugs (86op in FIG. 2b) described in FIGS. 2a and 2b are deformed into the peripheral contact plug 186p and the outer peripheral contact plug 186op that contact the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4), respectively. The contact spacer layers (74s_1, 74s_2, 74s_3, 74s_o) described in FIGS. 2a and 2b are deformed into the contact spacer layers (174s_1, 174s_2, 174s_3, 174s_o) that contact the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4). For example, the peripheral contact plug 186p includes a first peripheral contact plug 186p_1 that penetrates the first insulating region ST_Ia and contacts the first buffer pad pattern 19p_1, a second peripheral contact plug 186p_2 that penetrates the second insulating region ST_Ib and contacts the second buffer pad pattern 19p_2, and a third peripheral contact plug 186p_3 that penetrates the third insulating region ST_Ic and contacts the second buffer pad pattern 19p_3.

[0118] The shapes of the portions of the first peripheral contact plug 186p_1 and the first contact spacer layer 174s_1 that contact the first buffer pad pattern 19p_1 are substantially the same as the shapes of the portions of the first peripheral contact plug 86p_1 and the first contact spacer layer 74s_1 that contact the first peripheral pad pattern 15p_1 described in FIG. 4a. The shapes of the portions of the second peripheral contact plug 186p_2 and the second contact spacer layer 174s_2 that contact the second buffer pad pattern 19p_2 are substantially the same as the shapes of the portions of the second peripheral contact plug 86p_2 and the second contact spacer layer 74s_2 that contact the second peripheral pad pattern 15p_2 described in FIG. 4b. The shapes of the portions of the third peripheral contact plug 186p_3 and the second contact spacer layer 174s_3 that contact the third buffer pad pattern 19p_3 are substantially the same as the shapes of the portions of the third peripheral contact plug 86p_3 and the third contact spacer layer 74s_3 that contact the third peripheral pad pattern 15p_3 described in FIG. 4c.

[0119] According to the embodiments, the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) and the first to third contact spacer layers (174s_1, 174s_2, 174s_3) contacting the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) can be deformed in various ways. Thus, the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) and the first to third contact spacer layers (174s_1, 174s_2, 174s_3) that can be deformed in various ways will be described with reference to FIGS. 11a to 11c respectively.

[0120] In a modification, referring to FIG. 11a, the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) and the first to third contact spacer layers (174s_1, 174s_2, 174s_3) in FIGS. 10a and 10b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) and the first to third contact spacer layers (74s_1a, 74s_2a, 74s_3a) in FIGS. 6a and 6b. The partial enlarged view of FIG. 11a shows an enlarged form of the portion where the first peripheral contact plug 186p_1a and the first contact spacer layer 174s_1a contact the first buffer pad pattern 19p_1.

[0121] In a modification, referring to FIG. 11b, the first to third contact spacer layers (174s_1, 174s_2, 174s_3) in FIGS. 10a and 10b are omitted, and the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) in FIGS. 10a and 10b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) in FIGS. 7a and 7b or FIG. 8. The partial enlarged view of FIG. 11b shows an enlarged form of the portion where the first peripheral contact plug 186p_1b contacts the first buffer pad pattern 19p_1.

[0122] In a modified example, referring to FIG. 11c, the first to third peripheral contact plugs (186p_1, 186p_2, 186p_3) and the first to third contact spacer layers (174s_1, 174s_2, 174s_3) in FIGS. 10a and 10b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c) and the first to third contact spacer layers (74s_1b, 74s_2b, 74s_3b) in FIGS. 9a and 9b. The partial enlarged view of FIG. 11c shows an enlarged form of the portion where the first peripheral contact plug 186p_1c, the first contact spacer layer 174s_1b, and the first buffer pad pattern 19p_1 are in contact with each other.

[0123] Next, referring to FIGS. 12a, 12b, and 13, modified examples of the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4) and the source pad pattern 19s described in FIGS. 10a, 10b, and 10c will be described. FIG. 12a is a cross-sectional view schematically showing a region cut along the line I-I' in FIG. 1, FIG. 12b is a cross-sectional view schematically showing a region cut along the line II-II' in FIG. 1, and FIG. 13 is a partial enlarged view of the portion indicated by "F" in FIG. 12a.

[0124] Referring to FIGS. 12a, 12b, and 13, the buffer pad patterns (19p_1, 19p_2, 19p_3, 19p_4) and the source buffer pad pattern 19s described in FIGS. 10a, 10b, and 10c are respectively deformed into buffer pad patterns (131p_1, 131p_2, 131p_3, 131p_4) and a source buffer pad pattern 131s in the form shown in FIGS. 12a, 12b, and 13. For example, the buffer pad patterns (131p_1, 131p_2, 131p_3, 131p_4) contact the peripheral pad pattern 15p and extend upward to penetrate the first to third gap fill insulating layers (29a, 29b, 29c), and the source buffer pad pattern 131s contacts the source pad pattern 15sp and extends upward to penetrate the pattern structure 20. The upper surfaces of the buffer pad patterns (131p_1, 131p_2, 131p_3, 131p_4) and the source buffer pad pattern 131s are arranged at the same height level as the upper surface of the pattern structure 20.

[0125] The peripheral contact plug 186p and the outer peripheral contact plug 186op described in FIGS. 10a and 10b are respectively deformed into a peripheral contact plug 286p and an outer peripheral contact plug 286op that contact the buffer pad patterns (131p_1, 131p_2, 131p_3, 131p_4). The contact spacer layers (174s_1, 174s_2, 174s_3, 174s_o) described in FIGS. 10a and 10b are deformed into contact spacer layers (274s_1, 274s_2, 274s_3, 274s_o) that contact the buffer pad patterns (131p_1, 131p_2, 131p_3, 131p_4). For example, the peripheral contact plug 286p includes a first peripheral contact plug 286p_1 that penetrates the first insulating region ST_Ia and contacts the first buffer pad pattern 131p_1, a second peripheral contact plug 286p_2 that penetrates the second insulating region ST_Ib and contacts the second buffer pad pattern 131p_2, and a third peripheral contact plug 286p_3 that penetrates the third insulating region ST_Ic and contacts the third buffer pad pattern 131p_3.

[0126] The shape of the portions of the first peripheral contact plug 286p_1 and the first contact spacer layer 274s_1 that contact the first buffer pad pattern 131p_1 is substantially the same as the shape of the portions of the first peripheral contact plug 86p_1 and the first contact spacer layer 74s_1 that contact the first peripheral pad pattern 15p_1 described in FIG. 4a. The shape of the portions of the second peripheral contact plug 286p_2 and the second contact spacer layer 274s_2 that contact the second buffer pad pattern 131p_2 is substantially the same as the shape of the portions of the second peripheral contact plug 86p_2 and the second contact spacer layer 74s_2 that contact the second peripheral pad pattern 15p_2 described in FIG. 4b. The shape of the portions of the third peripheral contact plug 286p_3 and the second contact spacer layer 274s_3 that contact the third buffer pad pattern 131p_3 is substantially the same as the shape of the portions of the third peripheral contact plug 86p_3 and the third contact spacer layer 74s_3 that contact the third peripheral pad pattern 15p_3 described in FIG. 4c.

[0127] According to the embodiment, the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) and the first to third contact spacer layers (274s_1, 274s_2, 274s_3) that contact the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) can be deformed in various ways. Thus, various examples of the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) and the first to third contact spacer layers (274s_1, 274s_2, 274s_3) that are deformed in various ways will be described with reference to FIGS. 14a to 14c, respectively.

[0128] In a modified example, referring to FIG. 14a, the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) and the first to third contact spacer layers (274s_1, 274s_2, 274s_3) in FIGS. 12a and 12b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) and the first to third contact spacer layers (74s_1a, 74s_2a, 74s_3a) in FIGS. 6a and 6b. The partial enlarged view of FIG. 14a shows an enlarged form of the portion where the first peripheral contact plug 286p_1a and the first contact spacer layer 274s_1a are in contact with the first buffer pad pattern 131p_1.

[0129] In a modified example, referring to FIG. 14b, the first to third contact spacer layers (274s_1, 274s_2, 274s_3) in FIGS. 12a and 12b are omitted, and the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) in FIGS. 12a and 12b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1a, 86p_2a, 86p_3a) in FIGS. 7a and 7b or FIG. 8. The partial enlarged view of FIG. 14b shows an enlarged form of the portion where the first peripheral contact plug 286p_1b is in contact with the first buffer pad pattern 131p_1.

[0130] In a modified example, referring to FIG. 14c, the first to third peripheral contact plugs (286p_1, 286p_2, 286p_3) and the first to third contact spacer layers (274s_1, 274s_2, 274s_3) in FIGS. 12a and 12b can be deformed in the same manner as the first to third peripheral contact plugs (86p_1c, 86p_2c, 86p_3c) and the first to third contact spacer layers (74s_1b, 74s_2b, 74s_3b) in FIGS. 9a and 9b. The partial enlarged view of FIG. 14c shows an enlarged form of the portion where the first peripheral contact plug 286p_1c and the first contact spacer layer 274s_1b are in contact with the first buffer pad pattern 131p_1.

[0131] With reference to FIGS. 15A to 17B, an example of a method for forming a semiconductor device according to an embodiment of the present invention will be described. In FIGS. 15A to 17B, FIGS. 15A, 16A, and 17A are cross-sectional views schematically showing regions cut along the line I-I' in FIG. 1, FIGS. 15B, 16B, and 17B are cross-sectional views schematically showing regions cut along the line II-II' in FIG. 1, and FIG. 16C is a cross-sectional view schematically showing a region cut along the line III-III' in FIG. 1.

[0132] Referring to FIGS. 1, 15A, and 15B, a lower structure 3 is formed. The lower structure 3 includes a semiconductor substrate 5, peripheral elements (9g, 10), a peripheral wiring structure 14, a peripheral pad pattern 15p, and a lower insulating structure 18, as described with reference to FIGS. 1 to 2C. The lower structure 3 further includes a lower pattern layer 22, an intermediate pattern layer 25, and an upper pattern layer 27 that is laminated in order on the lower insulating structure 18 and penetrates a part of the intermediate pattern layer 25 to contact the lower pattern layer 22. The lower structure 3 includes first to third gap-fill insulating layers (29a, 29b, 29c) and an outer insulating layer 29d, as described with reference to FIGS. 1 to 2C.

[0133] A lower mold laminated structure ST1 is formed on the lower structure 3. The lower mold laminated structure ST1 includes a lower interlayer insulating layer 33 and a preliminary lower horizontal layer 35 that are alternately and repeatedly laminated. The lower mold laminated structure ST1 in the stepped region SA is patterned to form a stepped shape, and a lower capping insulating layer 39 that covers the stepped portion of the lower mold laminated structure ST1 is formed.

[0134] A sacrificial vertical structure 41 that penetrates the lower mold laminated structure ST1 in the memory cell array region MCA is formed.

[0135] Referring to FIGS. 1, 16a to 16c, an upper mold laminate structure ST2 is formed that includes an upper interlayer insulating layer 43 and a preliminary upper horizontal layer 45 that are alternately and repeatedly laminated on a lower mold laminate structure ST1. The upper mold laminate structure ST2 within the stepped region SA is patterned to form a stepped shape, and an upper capping insulating layer 53 is formed that covers the stepped portion of the upper mold laminate structure ST2 and the lower capping insulating layer 39. The capping insulating structure 55 includes lower and upper capping insulating layers (39, 53).

[0136] Within the memory cell array region MCA, a memory vertical structure 58 is formed that penetrates the lower and upper mold laminate structures (ST1, ST2). The sacrificial vertical structure 41 is removed while forming the memory vertical structure 58. The memory vertical structure 58 includes a channel layer 62, an insulating core pattern 64, an information storage structure 60, and a pad pattern 66, as described with reference to FIG. 3a. A first upper insulating layer 69 is formed on the upper mold laminate structure ST2 and the capping insulating structure 55.

[0137] A dummy vertical structure 72 is formed that penetrates the first upper insulating layer 69, the lower and upper mold laminate structures (ST1, ST2), and the capping insulating structure 55.

[0138] An insulating contact pillar 76p is formed together with the dummy vertical structure 72. The insulating contact pillar 76p is formed at positions where the peripheral contact plug 86p, the source contact plug 86s, and the outer peripheral contact plug 86op, and the contact spacer layers (74s_1, 74s_2, 74s_3, 74s_s, 74s_o) described with reference to FIGS. 1 to 2c are disposed. Accordingly, a part of the insulating contact pillar 76p contacts the peripheral pad pattern 15p, and a part contacts the lower pattern layer 22.

[0139] Forming the dummy vertical structure 72 and the insulating contact pillar 76p includes simultaneously forming holes that penetrate the first upper insulating layer 69, the lower and upper mold laminate structures (ST1, ST2), and the capping insulating structure 55 to expose the lower pattern layer 22 and holes that expose the peripheral pad pattern 15p, and forming an insulating material that simultaneously fills the holes.

[0140] Referring to FIGS. 1, 17a, and 17b, a second upper insulating layer 76 is formed on the first upper insulating layer 69. Trenches are formed that penetrate the first and second upper insulating layers (69, 76), the lower and upper mold laminate structures (ST1, ST2 in FIGS. 16a - 16c), the upper pattern layer (27 in FIGS. 16a - 16c), and the intermediate pattern layer (25 in FIGS. 16a - 16c). Of these trenches, a part of the trenches formed within the stepped region SA is formed by the dam structure 80. The intermediate pattern layer exposed by the trenches located within the memory cell array region MCA is replaced with the first intermediate pattern layer 25a as described in FIGS. 1 - 2c. A part of the preliminary lower and upper horizontal layers (35, 45 in FIGS. 6a - 6c) exposed by the remaining trenches among the trenches located within the memory cell array region MCA and the stepped region SA is replaced with the gate horizontal layers (36g, 46g). A part of the preliminary lower and upper horizontal layers (35, 45 in FIGS. 6a - 6c) located in the second direction Y of the memory cell array region MCA in the preliminary lower and upper horizontal layers (35, 45 in FIGS. 6a - 6c) remains and is formed in the first insulating region ST_Ia as described in FIGS. 1 - 2c. The preliminary lower and upper horizontal layers (35, 45 in FIGS. 6a - 6c) surrounded by the dam structure 80 within the stepped region SA are formed in the first and second insulating regions (ST_Ib, ST_Ic) as described in FIGS. 1 - 2c. Thus, a laminate structure ST as described in FIGS. 1 - 2c is formed.

[0141] A third upper insulating layer 84 is formed on the second upper insulating layer 76. Subsequently, as described with reference to FIGS. 1 to 2c, the peripheral contact plug 86p, the source contact plug 86s, the outer peripheral contact plug 86op, and the gate contact plug 86g are simultaneously formed. Forming the peripheral contact plug 86p, the source contact plug 86s, the outer peripheral contact plug 86op, and the gate contact plug 86g includes forming a peripheral contact hole that penetrates the third upper insulating layer 84 and extends downward to penetrate the insulating contact pillar 76p, and a gate contact hole that penetrates the first to third upper insulating layers (69, 76, 84) and the capping insulating structure 55, and forming a conductive material that simultaneously fills the peripheral contact hole and the gate contact hole. The insulating contact pillar 76p, the first to third upper insulating layers (69, 76, 84), and the capping insulating structure 55 are formed of the same material as each other, for example, silicon oxide.

[0142] According to an embodiment, the peripheral contact hole can be formed by etching the insulating contact pillar 76p instead of etching the insulating horizontal layers (36i, 46i) formed of silicon nitride. Therefore, since the gate contact hole and the peripheral contact hole are formed by etching the same material as each other, for example, silicon oxide, it is possible to prevent the occurrence of a punching defect in which the gate horizontal layers (36g, 46g) are penetrated by the gate contact hole while the gate contact hole is formed simultaneously with the peripheral contact hole.

[0143] Subsequently, a wiring process is performed to form the bit line 93, the gate connection wiring 94, and the source connection wiring 95 as described with reference to FIGS. 1 to 2c.

[0144] As in the embodiment, since the peripheral contact plug 86p, the source contact plug 86s, the outer peripheral contact plug 86op, and the gate contact plug 86g can be simultaneously formed without defects, the height of the semiconductor device can be reduced, the integration degree and reliability of the semiconductor device can be improved, and the productivity of the semiconductor device can be improved.

[0145] FIG. 18 is a diagram schematically showing an electronic system including a semiconductor device according to an embodiment of the present invention.

[0146] Referring to FIG. 18, an electronic system 1000 according to an embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 is a storage device including the semiconductor device 1100, or an electronic device including the storage device. For example, the electronic system 1000 is an SSD device (solid state drive device) including the semiconductor device 1100, a USB (Universal Serial Bus), a computing system, a medical device, or a communication device.

[0147] The semiconductor device 1100 is a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 14c. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F can also be arranged beside the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F includes the peripheral circuit PC of the lower structure 3, the peripheral wiring structure 14, and the peripheral pad pattern 15p described above.

[0148] The second structure 1100S is a memory cell structure including bit lines BL, a common source line CSL, word lines WL, first and second upper gate lines (UL1, UL2), first and second lower gate lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0149] The above-described pattern structure 20 includes a silicon layer having an N-type conductivity type, and the silicon layer having the N-type conductivity type is the common source line CSL.

[0150] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to the common source line CSL, upper transistors (UT1, UT2) adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of the lower transistors (LT1, LT2) and the number of the upper transistors (UT1, UT2) can be variously deformed according to embodiments.

[0151] In the present embodiment, the upper transistors (UT1, UT2) include string selection transistors, and the lower transistors (LT1, LT2) include ground selection transistors. The lower gate lines (LL1, LL2) are gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is a gate electrode of the memory cell transistor MCT, and the upper gate lines (UL1, UL2) are gate electrodes of the upper transistors (UT1, UT2), respectively.

[0152] The above-described gate horizontal layers (36g, 46g) constitute gate lower lines (LL1, LL2), word line WL, and gate upper lines (UL1, UL2). For example, the first and second lower gate horizontal layers (36g_La, 36Lb) as shown in FIG. 3a constitute gate lower lines (LL1, LL2), the intermediate gate horizontal layers (36M, 46M) constitute word line WL, and the first and second upper gate horizontal layers (46g_Ua, 46g_Ub) constitute gate upper lines (UL1, UL2).

[0153] In this embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used for an erase operation to erase data stored in the memory cell transistor MCT by utilizing the Gate Induce Drain Leakage (GIDL) phenomenon.

[0154] The common source line CSL, the first and second gate lower lines (LL1, LL2), word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extended to the second structure 1100S within the first structure 1100F.

[0155] The first connection wiring 1115 is composed of the above-described gate contact plug 86g, gate connection wiring 94, and peripheral contact plug 86p.

[0156] The bit line BL is electrically connected to the page buffer 1120 via a second connection wiring 1125 extended to the second structure 1100S within the first structure 1100F.

[0157] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by the logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 via the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via the input / output connection wiring 1135 extended to the second structure 1100S within the first structure 1100F.

[0158] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the electronic system 1000 can include a plurality of semiconductor devices 1100. In this case, the controller 1200 controls the plurality of semiconductor devices 1000.

[0159] The processor 1210 controls the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 operates based on a predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be recorded in the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transferred. The host interface 1230 provides a communication function between the electronic system 1000 and an external host. When receiving a control command from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0160] FIG. 19 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment of the present invention.

[0161] Referring to FIG. 19, an electronic system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are interconnected with the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0162] The main board 2001 includes a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the plurality of pins vary depending on the communication interface between the electronic system 2000 and the external host. In one embodiment, the electronic system 2000 communicates with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In one embodiment, the electronic system 2000 operates by a power supply supplied from the external host via the connector 2006. The electronic system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes the power supply supplied from the external host to the controller 2002 and the semiconductor packages 2003.

[0163] The controller 2002 records data in or reads data from the semiconductor packages 2003 to improve the operating speed of the electronic system 2000.

[0164] DRAM2004 is a buffer memory for alleviating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM2004 included in the electronic system 2000 also operates as a kind of cache memory and provides a space for temporarily storing data in the control operation for the semiconductor package 2003. When the DRAM2004 is included in the electronic system 2000, the controller 2002 further includes a DRAM controller for controlling the DRAM2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0165] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) separated from each other. The first and second semiconductor packages (2003a, 2003b) are semiconductor packages each including a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 includes a semiconductor device according to any one of the embodiments described above with reference to FIGS. 1 to 14c.

[0166] Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0167] The package substrate 2100 is a printed circuit board including package upper pads 2130. Each of the semiconductor chips 2200 includes input / output pads 2210. The input / output pads 2210 are the input / output pads 1101 in FIG. 18.

[0168] In one embodiment, the connection structure 2400 is a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other in a bonding wire manner and are electrically connected to the package top pads 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 can also be electrically connected to each other by a connection structure including through-silicon vias (TSVs) instead of the bonding wire type connection structure 2400.

[0169] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. For example, the controller 2002 and the semiconductor chip 2200 can be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 can be connected to each other by wirings formed on the interposer substrate.

[0170] FIG. 20 is a cross-sectional view schematically showing a semiconductor package according to an embodiment of the present invention. FIG. 20 illustrates an embodiment of the semiconductor package 2003 of FIG. 19 and conceptually shows a region where the semiconductor package 2003 of FIG. 20 is cut along the cutting line IV-IV'.

[0171] Referring to FIG. 20, in semiconductor package 2003, package substrate 2100 is a printed circuit board. Package substrate 2100 includes a package substrate main body 2120, upper package pads 2130 disposed on the upper surface of package substrate main body 2120, lower pads 2125 disposed on the lower surface of package substrate main body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting upper pads 2130 and lower pads 2125 inside package substrate main body 2120. Upper pads 2130 are electrically connected to connection structure 2400. Lower pads 2125 are connected to wiring pattern 2005 of main board 2010 of electronic system 2000 as shown in FIG. 19 via conductive connection portion 2800.

[0172] Each of semiconductor chips 2200 includes a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 stacked in sequence on semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210, bit lines 3240 electrically connected to the memory channel structure 3220, and gate connection wirings (94 in FIG. 2b) electrically connected to the word lines (WL in FIG. 18) of the gate stack structure 3210. The first structure 3100 includes the first structure 1100F in FIG. 18, and the second structure 3200 includes the second structure 1100S in FIG. 18. For example, the partial enlarged region indicated by reference numeral 1 in FIG. 20 shows the cross-sectional structure of FIG. 2b. Therefore, each of semiconductor chips 2200 includes a semiconductor device 1 according to any one of the embodiments described above with reference to FIGS. 1 to 14c.

[0173] Each of the semiconductor chips 2200 is electrically connected to the peripheral wiring 3110 of the first structure 3100 and includes a through-wiring 3245 extending into the second structure 3200. The through-wiring 3245 penetrates the gate stack structure 3210 and is further disposed outside the gate stack structure 3210. The through-wiring 3245 is the peripheral contact plug 86p of any one of the embodiments described above with reference to FIGS. 1 to 14c.

[0174] Each of the semiconductor chips 2200 is electrically connected to the peripheral wiring 3110 of the first structure 3100 and further includes an input / output connection wiring 3265 extending into the second structure 3200 and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0175] Although the embodiments of the present invention have been described in detail with reference to the drawings, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical idea of the present invention.

Explanation of Reference Numerals

[0176] 1 Semiconductor device 3 Lower structure 5 Semiconductor substrate 7a Active region 7s Element isolation layer 9a Peripheral gate dielectric layer 9b Peripheral gate electrode 9g Peripheral gate 10 Peripheral source / drain 11 Ground impurity region 11s Source control element 12 Peripheral element 14 Peripheral wiring structure 14g Ground wiring structure 14s Source wiring structure 15g Ground pad pattern 15p Peripheral pad pattern 15p_1, 15p_2, 15p_3 First to third peripheral pad patterns 15p_4 Outer peripheral pad pattern 15s upper surface 15sp source pad pattern 18 lower insulating structure 18a, 18c first and third lower insulating layers 18b etching stop layer 19p_1, 19p_2, 19p_3, 19p_4 first to fourth buffer pad patterns 19s source buffer pad pattern 20 pattern structure 20s upper surface 22, 27 lower and upper pattern layers 22V ground pattern 25 intermediate pattern layer 25a, 25b first and second intermediate pattern layers 26a, 26b, 26c first to third layers 27s support part 29a, 29b, 29c first to third gap-fill insulating layers 29d outer insulating layer 29e insulating layer 33, 43 lower and upper interlayer insulating layers 33L lowest lower interlayer insulating layer 33U highest lower interlayer insulating layer 35 preliminary lower horizontal layer 36, 46 lower and upper horizontal layers 36g, 46g lower and upper gate horizontal layers 36g_La, 36g_Lb first and second lower gate horizontal layers 36i, 46i lower and upper insulating horizontal layers 36i_1, 36i_2, 36i_3 first to third lower insulating horizontal layers 36M, 46M intermediate gate horizontal layer 36p, 46p lower and upper gate pads 39, 53 lower and upper capping insulating layers 41 sacrificial vertical structure 43L lowest upper interlayer insulating layer 43U highest upper interlayer insulating layer 45 preliminary upper horizontal layer 46g_Ua, 46g_Ub first and second upper gate horizontal layers 46i_1, 46i_2, 46i_3 First to Third Upper Insulating Layers 47a, 47b First and Second Gate Layers 48 Horizontal Layer 55 Capping Insulation Structure 58 Memory Vertical Structure 58L, 58U Lower and Upper Vertical Parts 58V Bend 60 Information Storage Structure 60a, 60c First and Second Dielectric Layers 60b Information Storage Layer 60L, 60U Lower and Upper Parts 62 Channel Layer 64 Insulating Core Pattern 66 Pad Pattern 69, 76, 84, 88 First to Fourth Upper Insulating Layers 72 Dummy Vertical Structure 72a, 72b First and Second Dummy Vertical Structures 74s_1, 74s_1a, 74s_1b First (Peripheral) Contact Spacer Layer 74s_2, 74s_2a, 74s_2b Second (Peripheral) Contact Spacer Layer 74s_3, 74s_3a, 74s_3b Third (Peripheral) Contact Spacer Layer 74s_o Outer Peripheral Contact Spacer Layer 74s_s Source Contact Spacer Layer 76p Insulating Contact Pillar 76s_p1, 76s_p2 First and Second Spacer Parts 80 Dam Structure 82 Separation Structure 82a, 82b Main and Auxiliary Separation Structures 86a, 86b Second and First Conductive Liner Layers 86c Plug Conductive Pattern 86d Metal-Semiconductor Compound Layer 86g Gate Contact Plug 86op, 186op, 286op Outer Peripheral Contact Plugs 86p, 186p, 286p Peripheral Contact Plugs 86p_1, 86p_1a, 86p_1b, 86p_1c, 186p_1, 186p_1a, 186p_1b, 186p_1c, 286p_1, 286p_1a, 286p_1b, 286p_1c First Peripheral Contact Plugs 86p_2, 86p_2a, 86p_2b, 86p_2c, 186p_2, 286p_2 Second Peripheral Contact Plugs 86p_3, 86p_3a, 86p_3b, 86p_3c, 186p_3, 286p_3 Third Peripheral Contact Plugs 86p_1bL, 86p_2bL, 86p_3bL, 86p_1cL, 86p_2cL, 86p_3cL Lower Plug Parts 86p_1bU, 86p_2bU, 86p_3bU, 86p_1cU, 86p_2cU, 86p_3cU Upper Plug Parts 86p_s1, 86p_s2 First and Second Plug Sides 86p_s1bL, 86p_s2bL First and Second Lower Sides 86p_s1bU, 86p_s2bU First and Second Upper Sides 86pa, 86pc Second and First Parts 86s Source Contact Plug 90 Bit Line Connection Pattern 91g Gate Connection Pattern 91a, 91b, 91c First to Third Peripheral Contact Connection Patterns 91d Outer Peripheral Contact Connection Pattern 91s Source Contact Connection Pattern 93 Bit Line 94 Gate Connection Wiring 95 Source Connection Wiring 96 Outer Element Connection Wiring 131p_1, 131p_2, 131p_3, 131p_4 First to Fourth Buffer Pad Patterns 131s Source Buffer Pad Pattern 174s_1, 174s_1a, 174s_1b, 274s_1, 274s_1a First Contact Spacer Layer 174s_2, 274s_2 Second Contact Spacer Layer 174s_3, 274s_3 Third Contact Spacer Layer 174s_o, 274s_o Contact Spacer Layer 1000, 2000 Electronic System 1100 Semiconductor Device 1100F, 1100S First and Second Structures 1101 Input / Output Pad 1110 Decoder Circuit 1115, 1125 First and Second Connecting Wires 1120 Page Buffer 1130 Logic Circuit 1135 Connecting Wire 1200, 2002 Controller 1210 Processor 1220 NAND Controller 1221 NAND Interface 1230 Host Interface 2001 Main Substrate 2003, 200a, 2003b Semiconductor Package 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 Package Substrate 2120 Package Substrate Body 2125, 2130 Upper and Lower Pads 2135 Internal Wiring 2200 Semiconductor Chip 2210 Input / Output Pad 2300 Adhesive Layer 2400 Connecting Structure 2500 Molding Layer 2800 Conductive Connecting Portion 3010 Semiconductor Substrate 3100, 3200 First and Second Structures 3110 Peripheral Wiring 3205 Common Source Line 3210 Gate Stack Structure 3220 Memory Channel Structure 3230 Separation Structure 3240 Bit Line 3245 Through-Wiring 3265 Input / Output Connection Wiring BL Bit Line CS1, CS2 First and Second Staircase Connection Regions CSL Common Source Line CSTR Memory Cell String MCA Memory Cell Array Region MCT Memory Cell Transistor IS1, IS2, IS3 Upper, Middle, and Lower Staircase Regions LL1, LL2 First and Second Gate Lower Lines LT1 Lower Transistor (Lower Erase Control Transistor) LT2 Lower Transistor (Ground Selection Transistor) PC Peripheral Circuit SA Staircase Region ST Stacked Structure ST1, ST2 Lower and Upper Mold Stacked Structures ST_G Gate Region ST_I Insulation Region ST_Ia, ST_Ib, ST_Ic First to Third Insulation Regions ST1a, ST2a Lower and Upper Stacked Structures UL1, UL2 First and Second Gate Upper Lines UT1 Upper Transistor (String Selection Transistor) UT2 Upper Transistor (Upper Erase Control Transistor) WL Word Line

Claims

1. A lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure, A stacked structure including an interlayer insulating layer alternately and repeatedly stacked on the lower structure, and a horizontal layer including a gate horizontal layer disposed in a gate region and a first insulating horizontal layer disposed in a first insulating region, A memory vertical structure including a portion penetrating the gate horizontal layer in a vertical direction, A dummy vertical structure including a portion penetrating the gate horizontal layer in a vertical direction and separated from the memory vertical structure, A first peripheral contact plug including a portion penetrating the first insulating region in a vertical direction, A gate contact plug disposed on a gate pad of the gate horizontal layer, and comprising: The gate contact plug and the first peripheral contact plug have upper surfaces located at the same height level with respect to each other, At the same height level, each of the dummy vertical structures has a width larger than the width of each of the memory vertical structures, The memory vertical structure includes a first material different from the material of the dummy vertical structure, The memory vertical structure and the dummy vertical structure are in contact with the pattern structure and extend downward from an upper surface of the pattern structure into the pattern structure, At least some of the dummy vertical structures extend deeper into the pattern structure from the upper surface of the pattern structure than the memory vertical structure, The lower structure further includes a gap-fill insulating layer penetrating the pattern structure and a pad pattern overlapping the gap-fill insulating layer below the gap-fill insulating layer, The first peripheral contact plug extends downward from a portion penetrating the first insulating region and contacts the pad pattern. A semiconductor device characterized by this.

2. The lower insulating structure includes a first lower insulating layer surrounding a side surface of the pad pattern, an etching stop layer on the first lower insulating layer and the pad pattern, and a second lower insulating layer on the etching stop layer, The etching stop layer includes a material different from the material of the second lower insulating layer, The thickness of the etching stop layer is smaller than the thickness of the second lower insulating layer, The semiconductor device according to claim 1, wherein the first peripheral contact plug penetrates the second lower insulating layer and the etching stop layer to contact the pad pattern.

3. The first peripheral contact plug is further extended downward from the upper surface of the pad pattern into the interior of the pad pattern, The semiconductor device according to claim 2, wherein a vertical height at which the first peripheral contact plug extends from the upper surface of the pad pattern into the interior of the pad pattern is greater than a thickness of the etching stop layer.

4. The semiconductor device further includes an insulating contact spacer layer covering at least a part of a side surface of the first peripheral contact plug, The contact spacer layer contacts the pad pattern, The semiconductor device according to claim 1, wherein a lower end of the contact spacer layer is located at a level higher than a lower part of the first peripheral contact plug.

5. The stacked structure includes a lower stacked structure and an upper stacked structure on the lower stacked structure, At a height level between a top gate horizontal layer of the gate horizontal layers of the lower stacked structure and a bottom gate horizontal layer of the gate horizontal layers of the upper stacked structure, at least a part of a side surface of the memory vertical structure includes a bent portion, The memory vertical structure includes an insulating core pattern, a channel layer covering side and bottom surfaces of the insulating core pattern, and an information storage structure on an outer side surface of the channel layer, The semiconductor device according to claim 1, wherein a first material of the memory vertical structure is a material of the channel layer.

6. The first peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion, The upper plug portion has a larger width than the lower plug portion, In the first peripheral contact plug, a side surface of the lower plug portion extends to a side surface of the upper plug portion while bending in a direction away from a central axis of the lower plug portion. The semiconductor device according to claim 1.

7. The semiconductor device according to claim 6, wherein the upper plug portion includes a portion contacting the lower plug portion and a portion overlapping the first insulating horizontal layer.

8. The semiconductor device according to claim 6, wherein a first central axis of the lower plug portion and a second central axis of the upper plug portion are misaligned.

9. The lower structure further includes a gap-fill insulating layer penetrating the pattern structure, a pad pattern overlapping the gap-fill insulating layer below the gap-fill insulating layer, and a buffer pad pattern disposed on the pad pattern. An upper surface of the buffer pad pattern is at the same height level as an upper surface of the lower insulating structure or is disposed at a height level higher than a lower surface of the pattern structure. The first peripheral contact plug extends downward from a portion penetrating the first insulating region in a vertical direction to contact the buffer pad pattern. The semiconductor device according to claim 1, wherein a part of the first peripheral contact plug extends inside the buffer pad pattern.

10. A bit line electrically connected to the memory vertical structure on the memory vertical structure, and A gate connection wiring electrically connected to the gate contact plug on the gate contact plug, the semiconductor device according to claim 1, further comprising.

11. The semiconductor device according to claim 1, further comprising an insulating contact spacer layer disposed on at least a part of a side surface of the first peripheral contact plug. The contact spacer layer includes a spacer portion interposed between the first peripheral contact plug and the first insulating horizontal layer.

12. The first peripheral contact plug has a first plug side surface and a second plug side surface facing each other. At least one of the first insulating horizontal layers includes a first horizontal layer portion facing the first plug side surface and a second horizontal layer portion facing the second plug side surface. The contact spacer layer includes a first spacer portion interposed between the first plug side surface and the first horizontal layer portion and a second spacer portion interposed between the second plug side surface and the second horizontal layer portion. The semiconductor device according to claim 11, wherein a thickness of the first spacer portion is larger than a thickness of the second spacer portion.

13. The semiconductor device further includes a second peripheral contact plug. The stacked structure further includes a second insulating region separated from the first insulating region. The horizontal layer further includes a second insulating horizontal layer disposed within the second insulating region. The second peripheral contact plug includes a portion that penetrates the second insulating region in the vertical direction. The semiconductor device according to claim 1, wherein the uppermost first insulating horizontal layer among the first insulating horizontal layers is located at a different height level from the uppermost second insulating horizontal layer among the second insulating horizontal layers.

14. A lower structure including a peripheral circuit and a pad pattern electrically connected to the peripheral circuit, An interlayer insulating layer alternately and repeatedly stacked on the lower structure, and a horizontal layer including a gate horizontal layer disposed within a gate region and an insulating horizontal layer disposed within an insulating region, extending from a memory cell array region to a staircase region adjacent to the memory cell array region, and including the gate region and the insulating region whose side surfaces are surrounded by the gate region within the staircase region. A memory vertical structure including a portion that penetrates the gate horizontal layer in the vertical direction within the memory cell array region. A dummy vertical structure including a portion that penetrates the gate horizontal layer in the vertical direction within the staircase region. A peripheral contact plug that contacts the pad pattern and extends vertically to penetrate the insulating region. A gate contact plug disposed on a gate pad of the gate horizontal layer within the staircase region, and includes: The gate contact plug and the peripheral contact plug have upper surfaces located at the same height level as each other. Within the staircase region, the stacked structure includes a first staircase region, a second staircase region, and a staircase connection region between the first staircase region and the second staircase region, arranged in order in a first direction away from the memory cell array region. Each of the first and second staircase regions includes a staircase shape that decreases with a first height difference in the first direction. The upper surface of the staircase connection region has a flat shape in the first direction or a shape having a height difference smaller than the first height difference in the first direction. A part of the staircase connection region is the insulating region. The semiconductor device, wherein the memory vertical structure includes a material different from the material of the dummy vertical structure.

15. Further includes an insulating contact spacer layer covering at least a part of the side surface of the peripheral contact plug. The contact spacer layer contacts the pad pattern. The semiconductor device according to claim 14, wherein a lower end of the contact spacer layer is located at a level higher than a lower end of the peripheral contact plug.

16. The peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion, the upper plug portion has a width larger than that of the lower plug portion, and a central axis of the lower plug portion and a central axis of the upper plug portion are misaligned. The semiconductor device according to claim 14.

17. A main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes a peripheral circuit, a lower insulating structure including a pad pattern covering the peripheral circuit, and a lower structure including a pattern structure on the lower insulating structure including a silicon layer, a stacked structure including an interlayer insulating layer alternately and repeatedly stacked on the lower structure, and a horizontal layer including a gate horizontal layer disposed in a gate region and an insulating horizontal layer disposed in an insulating region, a memory vertical structure including a portion penetrating the gate horizontal layer in a vertical direction, a dummy vertical structure including a portion penetrating the gate horizontal layer in a vertical direction and separated from the memory vertical structure, a peripheral contact plug including a portion penetrating the insulating region in a vertical direction, a gate contact plug disposed on a gate pad of the gate horizontal layer, and an insulating contact spacer layer covering at least a part of a side surface of the peripheral contact plug and contacting the pad pattern. The gate contact plug and the peripheral contact plug have upper surfaces located at the same height level with respect to each other, at the same height level, each of the dummy vertical structures has a width larger than a width of each of the memory vertical structures, the memory vertical structure includes a material different from that of the dummy vertical structure, the memory vertical structure and the dummy vertical structure contact the pattern structure and extend from an upper surface of the pattern structure downward into the pattern structure, and at least some of the dummy vertical structures extend deeper into the pattern structure from the upper surface of the pattern structure downward than the memory vertical structures. An electronic system, wherein a lower end of the contact spacer layer is located at a level higher than a lower end of the peripheral contact plug. **Claim 18** The peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion, wherein the upper plug portion has a width larger than that of the lower plug portion, and a central axis of the lower plug portion and a central axis of the upper plug portion are misaligned, according to the electronic system of claim 17.

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