Copper-based wire and semiconductor device

Abstract

This copper-based wire rod is composed of copper or a copper alloy, and in a cross-section perpendicular to the longitudinal direction of the copper-based wire rod, the average crystal grain size is 20 μm to 150 μm, an accumulation rate of crystal orientation <111> is 40% or less, the Young's modulus is 80 GPa to 120 GPa, and 0.2% yield strength is 20 MPa to 90 MPa.

Description

Technical Field

[0001] The present disclosure relates to copper-based wire materials and semiconductor devices.

Background Art

[0002] In a semiconductor device, a bonding wire is a wire-shaped member that electrically connects a semiconductor chip and an electrode. Usually, the bonding wire is bonded to the semiconductor chip using ultrasonic bonding.

[0003] If the bonding wire is hard, when the bonding wire is pressed against the semiconductor chip, the load on the semiconductor chip increases, and there is a problem that the semiconductor chip may be damaged. Furthermore, in recent years, next-generation power semiconductor chips (such as SiC and GaN) that contribute to higher output and larger current have been developed. However, the semiconductor chips themselves are brittle, and due to the thinning of the semiconductor chips accompanying miniaturization, the requirements for durability have become even more stringent.

[0004] For example, Patent Document 1 describes a lead wire for a solar cell that can suppress non-uniform deformation during winding around a bobbin and unwinding from the bobbin, and the 0.2% proof stress of the lead wire for a solar cell is relatively low. However, Patent Document 1 does not mention the Young's modulus of the lead wire for a solar cell, and it is unclear whether it can withstand the impact when the lead wire for a solar cell is ultrasonically bonded to a semiconductor chip by wedge bonding.

[0005] In addition, Patent Document 2 describes a palladium-coated copper bonding wire that suppresses the formation of shrinkage cavities during ball bonding and can also cope with narrowing the pitch between bonding wires. However, Patent Document 2 does not mention the Young's modulus and 0.2% proof stress of the palladium-coated copper bonding wire, and it is unclear whether the palladium-coated copper bonding wire can withstand the impact when ultrasonically bonded to a semiconductor chip by wedge bonding. Furthermore, due to the final wire diameter of the palladium-coated copper bonding wire being too thin to allow sufficient current to flow, there is a problem in meeting the requirements for higher power and larger current.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] An object of the present disclosure is to provide a soft copper-based wire and a semiconductor device including the copper-based wire as a bonding wire, which have a small load even when pressed against a semiconductor chip and are excellent in impact durability.

Means for Solving the Problems

[0008] [1] A copper-based wire composed of copper or a copper alloy, wherein in a cross-section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain diameter is 20 μm or more and 150 μm or less, and the integration rate of the crystal orientation <111> is 40% or less, and the Young's modulus is 80 GPa or more and 120 GPa or less, and the 0.2% proof stress is 20 MPa or more and 90 MPa or less. [2] In the cross-section, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is 15% or more and 40% or less, and the copper-based wire according to the above [1]. [3] In the cross-section, the length L of the grain boundary where the orientation difference between adjacent crystals is 15 degrees or more B with respect to the length L of the twin grain boundary T of (L T / L B ) is 0.7 or more and 1.0 or less, and the copper-based wire according to the above [1] or [2]. [4] The copper-based wire is a round wire or a ribbon wire, and the copper-based wire according to any one of the above [1] to [3]. [5] The copper-based wire is composed of oxygen-free copper, and the copper-based wire according to any one of the above [1] to [4]. [6] The copper-based wire has a palladium coating layer covering the outer peripheral surface, and the copper-based wire according to any one of the above [1] to [5]. [7] A semiconductor chip and a bonding wire bonded to the semiconductor chip, the bonding wire is composed of copper or a copper alloy, and in the cross-section of the bonding wire perpendicular to the longitudinal direction of the bonding wire at the joint between the electrode provided on the upper part of the semiconductor chip and the bonding wire, the average crystal grain size is 10 μm or more and 100 μm or less, and the integration ratio of the crystal orientation <111> is 40% or less, a semiconductor device. [8] In the cross-section, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is 15% or more and 40% or less, and the semiconductor device according to the above [7]. [9] In the cross-section, the length L of the grain boundary where the orientation difference between adjacent crystals is 15 degrees or more B with respect to the length L of the twin grain boundary T of (L T / L B ) is 0.7 or more and 1.0 or less, and the semiconductor device according to the above [7] or [8].

[10] The bonding wire is composed of oxygen-free copper, and the semiconductor device according to any one of the above [7] to [9].

[11] The bonding wire is the semiconductor device according to any one of [7] to

[10] above, which has a palladium coating layer covering the outer peripheral surface.

Advantages of the Invention

[0009] According to the present disclosure, it is possible to provide a soft copper-based wire having a small load even when pressed against a semiconductor chip and excellent impact durability, and a semiconductor device including the copper-based wire as a bonding wire.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail.

[0012] As a result of intensive studies, the present inventors focused on simultaneously controlling the crystal grain size and crystal orientation of a copper-based wire, and found that the crystal grain size and crystal orientation in the cross section of the copper-based wire affect the Young's modulus and 0.2% proof stress of the copper-based wire. As a result, a soft copper-based wire having a small load even when pressed against a semiconductor chip and excellent impact durability was achieved, and it was found that when the copper-based wire was used as a bonding wire, breakage of the semiconductor chip mounted on the semiconductor device could be suppressed. The present disclosure has been completed based on such findings.

[0013] First, the copper-based wire of the embodiment will be described.

[0014] The copper-based wire of the embodiment is composed of copper or a copper alloy. In a cross-section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain size is 20 μm or more and 150 μm or less, and the integration rate of the crystal orientation <111> is 40% or less, and the Young's modulus is 80 GPa or more and 120 GPa or less, and the 0.2% proof stress is 20 MPa or more and 90 MPa or less.

[0015] The copper-based wire is composed of copper (copper wire) or a copper alloy (copper alloy wire).

[0016] The copper-based wire may be a copper alloy containing a small amount of elements such as silver (Ag), chromium (Cr), and tin (Sn). However, considering ensuring softness and electrical conductivity between the semiconductor chip and the electrode, and taking into account the recent trends of higher output and larger current, it is preferably copper. Among them, since the higher the copper content, the higher the conductivity, it is preferably tough pitch copper which is pure copper composed of 99.90 mass% or more of copper (Cu) and inevitable impurities, and more preferably oxygen-free copper composed of 99.96 mass% or more of Cu, 10 ppm or less of oxygen, and inevitable impurities.

[0017] As the copper alloy constituting the copper-based wire, it preferably has an alloy composition containing at least one element of 0.1 mass% or more and 1.0 mass% or less of Ag, 0.1 mass% or more and 1.0 mass% or less of Cr, and 0.1 mass% or more and 1.0 mass% or less of Sn, with the balance being Cu and inevitable impurities.

[0018] When the contents of Ag, Cr, and Sn are equal to or greater than the lower limit, the tensile durability of the copper-based wire can be improved. Therefore, when the copper-based wire is used as a bonding wire to be bonded to an electrode of a semiconductor chip, the copper-based wire can withstand the tensile load during unwinding, thereby improving the bonding speed. On the other hand, when the contents of Ag, Cr, and Sn exceed the upper limit, the conductivity of the copper-based wire can be reduced. Therefore, when using the copper-based wire as a bonding wire for power semiconductors, it is preferable to add the above elements at low concentrations. From this perspective, when the copper alloy contains Ag, the upper limit of the Ag content is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less. When the copper alloy contains Cr, the upper limit of the Cr content is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less. When the copper alloy contains Sn, the upper limit of the Sn content is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less.

[0019] The remainder other than the above elements are inevitable impurities. The inevitable impurities refer to impurities at a level that is inevitably mixed in during the manufacturing process. Depending on the content of the inevitable impurities, they may be a factor that reduces the electrical conductivity of the copper-based wire rod, so it is preferable that the content of the inevitable impurities is small.

[0020] When the copper-based wire is a copper alloy, examples of the inevitable impurities include elements such as aluminum (Al), beryllium (Be), cadmium (Cd), iron (Fe), magnesium (Mg), nickel (Ni), phosphorus (P), lead (Pd), silicon (Si), and titanium (Ti). When the copper-based wire is copper, the inevitable impurities include, in addition to the above elements, elements that are intentionally contained in the copper alloy and alloy with copper, such as Ag, Cr, and Sn. The upper limit of the content of the inevitable impurities is preferably 20 ppm or less in total of the above elements.

[0021] Also, in a cross-section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain size is 20 μm or more and 150 μm or less, and the integration ratio of the crystal orientation <111> is 40% or less. In the cross-section of the copper-based wire, the integration ratio of the crystal orientation <111> is the ratio of the crystal orientations in the range shifted by ±15° from the crystal orientation <111> with respect to all crystal orientations.

[0022] Here, conventionally, it has been difficult to simultaneously lower the Young's modulus and the 0.2% proof stress, which were in an inverse relationship. However, it has been found that the crystal grain size and crystal orientation affect the Young's modulus and the 0.2% proof stress. From these findings, by controlling the average crystal grain size and the integration ratio of the crystal orientation <111> in the cross-section of the copper-based wire within the above ranges, as described below, the Young's modulus and the 0.2% proof stress of the copper-based wire can be easily controlled within the above ranges.

[0023] In a cross-section perpendicular to the longitudinal direction of the copper-based wire, when the average crystal grain size of the copper-based wire is 20 μm or more, an increase in the 0.2% proof stress of the copper-based wire can be suppressed. Also, when the above average crystal grain size is 150 μm or less, breakage of the copper-based wire due to non-uniform deformation that occurs when the copper-based wire is pulled can be suppressed. From the above viewpoints, regarding the average crystal grain size in the cross-section of the copper-based wire, the lower limit value is 20 μm or more, preferably 30 μm or more, more preferably 40 μm or more, and the upper limit value is 150 μm or less.

[0024] Also, in a cross-section perpendicular to the longitudinal direction of the copper-based wire, when the integration ratio of the crystal orientation <111> of the copper-based wire is 40% or less, an increase in the Young's modulus can be suppressed and the softness is improved. From the above viewpoints, the integration ratio of the crystal orientation <111> in the cross-section of the copper-based wire is 40% or less, preferably 30% or less, more preferably 20% or less.

[0025] Here, in the field of metal materials, crystal grain size and crystal orientation are generally known material factors. However, when the heat treatment temperature is set high for the purpose of increasing the crystal grain size, the crystal orientation also changes depending on the heat treatment temperature, and it has not been possible to control the crystal grain size and the crystal orientation simultaneously. In the present disclosure, by controlling the crystal grain size and the crystal orientation within the above ranges, the Young's modulus and the 0.2% proof stress can be controlled within the above ranges. Therefore, the copper-based wire is soft, has a small load even when pressed against a semiconductor chip, and is excellent in impact durability.

[0026] Also, regarding the Young's modulus of the copper-based wire, the lower limit value is 80 GPa or more, and the upper limit value is 120 GPa or less, preferably 110 GPa or less, more preferably 100 GPa or less.

[0027] Also, regarding the 0.2% proof stress of the copper-based wire, the lower limit value is 20 MPa or more, and the upper limit value is 90 MPa or less, preferably 60 MPa or less, more preferably 40 MPa or less.

[0028] Here, material deformation includes elastic deformation and plastic deformation. In elastic deformation, there is a relationship of σ = Eε (σ: stress, E: Young's modulus, ε: strain), and stress acts in a proportional relationship to the applied strain. That is, the lower the Young's modulus, the more gently it deforms, and thus the load is smaller. Then, when a certain strain region is exceeded, plastic deformation occurs in which the material does not return to its original state, and the stress at which this plastic deformation starts is called the proof stress. For these reasons, the lower the proof stress, the easier it is for plastic deformation to occur and the smaller the load. From the viewpoint of being soft, having a small load even when pressed against a semiconductor chip, and being excellent in impact durability, in the copper-based wire, it is required that the Young's modulus and the proof stress be low.

[0029] When the Young's modulus and 0.2% proof stress of the copper-based wire are within the above ranges, it is soft, the load is small even when pressed against the semiconductor chip, and it has excellent impact durability. Therefore, when manufacturing a semiconductor device using the copper-based wire as a bonding wire, since the load on the semiconductor chip when bonding the copper-based wire to the semiconductor chip is reduced, breakage of the semiconductor chip can be suppressed. In particular, within the above range, the lower the Young's modulus and 0.2% proof stress, the easier the copper-based wire deforms when bonded to the semiconductor chip and the better its impact durability. Also, when the Young's modulus and 0.2% proof stress are equal to or higher than the above lower limit values, in order to bond with the semiconductor chip, when feeding out the copper-based wire from the bobbin for setting it in an ultrasonic bonding machine, breakage due to tension of the copper-based wire can be suppressed.

[0030] Also, there is a material property called the work hardening index (also referred to as the n-value) that represents the tendency to harden during plastic deformation. The n-value is expressed by the formula: σ = C × ε n (σ: true stress, C: strength constant, ε: true strain). The n-value is generally a property contrary to the 0.2% proof stress. If the 0.2% proof stress is low, the n-value is high, and if the 0.2% proof stress is high, the n-value is low. However, when using the copper-based wire as a bonding wire, ideally, after starting plastic deformation, a lower n-value is preferable in terms of being able to deform easily. Therefore, the n-value of the copper-based wire is preferably 0.45 or less, and more preferably 0.35 or less. Note that the n-value is a value that changes during plastic deformation. Considering the ease of deformation as a bonding wire, it is considered that the n-value should be defined at the value in the initial stage of deformation. Here, the n-value was calculated in the range where the nominal strain is 1% to 5%. For samples where a nominal strain of 5% or more cannot be obtained, the n-value was calculated in the range from the nominal strain at which the 0.2% proof stress was calculated by the offset method to the nominal strain at which the maximum tensile strength is obtained.

[0031] In addition, in the cross-section of the copper-based wire, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is preferably 15% or more, more preferably 20% or more, and even more preferably 25% or more. When the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is 15% or more, that is, when the crystal orientations <100> and <110> are oriented in the longitudinal direction of the copper-based wire at a ratio of 15% or more, the Young's modulus tends to be low, and a soft copper-based wire can be easily obtained.

[0032] In addition, in the cross-section of the copper-based wire, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is preferably 40% or less. When the above total integration ratio is 40% or less, it can be more durable against the tensile load when the copper-based wire is drawn out from the bobbin.

[0033] Here, in the cross-section of the copper-based wire, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is the ratio of the total crystal orientation of the crystal orientation within the range of ±15° deviation from the crystal orientation <100> and the crystal orientation within the range of ±15° deviation from the crystal orientation <110> with respect to all crystal orientations.

[0034] In addition, the twin grain boundary is a low-energy grain boundary with high atomic coherence, and it is less likely for dislocations to accumulate during processing than a large-angle grain boundary, and the force applied during bending can be reduced. Therefore, the higher the proportion of twin grain boundaries, the better. Therefore, in the cross-section of the copper-based wire, the length L of the grain boundary where the orientation difference between adjacent crystals is 15 degrees or more B to the length L of the twin grain boundary T of the ratio (L T / L B ) is preferably 0.7 or more and 1.0 or less.

[0035] In addition, regarding the shape of the copper-based wire, it can be appropriately selected according to the current amount required for the semiconductor device, the wiring space, etc., and it is preferably a round wire or a ribbon wire. A round wire has a circular cross-sectional shape of the copper-based wire. Ribbon wires include flat wires, strip wires, and track-shaped wires. A flat wire has a shape in which the cross-section of the copper-based wire is surrounded by four straight lines. A strip wire has a rectangular cross-sectional shape of the copper-based wire. A track-shaped wire has a shape in which the cross-section of the copper-based wire is surrounded by two straight lines and two curves connecting the ends of the two straight lines, i.e., a so-called track shape.

[0036] When the copper-based wire is a round wire, if the wire diameter of the copper-based wire (round wire) is 0.1 mm or more, a relatively high current can flow through the copper-based wire, so the copper-based wire is suitable as a bonding wire for power semiconductors. Also, if the wire diameter of the copper-based wire (round wire) is 0.5 mm or less, it can sufficiently meet the requirement for securing the wiring space for the trend of miniaturization of semiconductor devices, and furthermore, it is easily bendable.

[0037] In addition, when the copper-based wire is a ribbon wire, if the thickness of the copper-based wire (ribbon wire) is 0.1 mm or more, a relatively high current can flow through the copper-based wire, so the copper-based wire is suitable as a bonding wire for power semiconductors. Also, if the thickness of the copper-based wire (ribbon wire) is 0.5 mm or less, it can sufficiently meet the requirement for securing the wiring space for the trend of miniaturization of semiconductor devices, and furthermore, it is easily bendable.

[0038] In addition, in order to prevent oxidation of the outer peripheral surface of the copper-based wire, the copper-based wire may have a metal coating layer covering the outer peripheral surface. Preferably, the metal coating layer is a palladium coating layer. The palladium coating layer covering the outer peripheral surface of the copper-based wire is formed, for example, by plating.

[0039] Such a copper-based wire has a small load even when pressed against a semiconductor chip and is excellent in impact durability and softness, so it is suitably used as a bonding wire for semiconductor devices.

[0040] Next, a method for manufacturing a copper-based wire rod according to an embodiment will be described.

[0041] In the method for manufacturing a copper-based wire rod according to the embodiment, first, a casting process is performed. In the casting process, electrolytic copper is melted in a reducing atmosphere to obtain an ingot called a cylindrical billet.

[0042] After the casting process, an extrusion process or a rolling process is performed. In the extrusion process, the billet is processed into a round bar shape by hot extrusion. The rolling process is continuously performed together with the casting process using a continuous casting and rolling machine. In this case, molten copper is poured into a ring-shaped rotating mold to form an ingot, and rough-drawn wire is obtained by repeating rolling from the vertical or horizontal direction.

[0043] After the extrusion process or the rolling process, a first wire drawing process is performed. In the first wire drawing process, the round bar or rough-drawn wire obtained in the above process is drawn to a predetermined wire diameter. Also, a peeling process for removing surface defects generated up to the above process is included in the first wire drawing process.

[0044] After the first wire drawing process, a first heat treatment process is performed. In the first heat treatment process, in order to simultaneously control the average crystal grain size and the accumulation rate of a predetermined crystal orientation in the cross section of the copper-based wire rod within a predetermined range after the second heat treatment process in the subsequent process, heat treatment is performed at a relatively high temperature.

[0045] When the first heat treatment step is batch heat treatment using a batch annealing furnace, the heat treatment temperature is 400°C or higher and 900°C or lower. If the heat treatment temperature is less than 400°C, it is difficult for crystal grains to grow, and it is difficult to simultaneously achieve an average crystal grain size of 20 μm or more and an accumulation rate of crystal orientation <111> of 40% or less in the cross section of the copper-based wire by the second heat treatment step. In Patent Document 1 mentioned above, heat treatment is performed at 200 - 300°C, but as shown in Comparative Example A2 and Comparative Example A3 described later, either one or both of the average crystal grain size and the accumulation rate of crystal orientation <111> do not satisfy the above-mentioned predetermined range of the present disclosure. On the other hand, if the heat treatment temperature exceeds 900°C, the average crystal grain size in the cross section of the copper-based wire becomes more than 150 μm by the second heat treatment step, and the copper-based wire cannot withstand the tension during pay-out from the bobbin, causing wire breakage.

[0046] Also, when the first heat treatment step is batch heat treatment, the heat treatment time is 10 minutes or more and 6 hours or less. If the heat treatment time is less than 10 minutes, when heating a large number of samples in a batch furnace, it is insufficient in terms of time to uniformly heat-treat the entire sample, so the crystal grains will not be uniform either. Therefore, it is not possible to stably achieve an average crystal grain size of 20 μm or more in the cross section of the copper-based wire by the second heat treatment step. On the other hand, if the heat treatment time exceeds 6 hours, although the average crystal grain size in the cross section of the copper-based wire becomes 20 μm or more by the second heat treatment step, it is too costly industrially.

[0047] When the first heat treatment step is in-line heat treatment where annealing is performed by passing through a heating furnace of a certain length, since the heat treatment time is shorter than that of batch heat treatment, being 6 seconds or more and 15 seconds or less, the heat treatment temperature is set to 700°C or higher and 950°C or lower. The reasons for setting the upper and lower limit values of the heat treatment temperature in in-line heat treatment are the same as those for batch heat treatment.

[0048] After the first heat treatment step, a second wire drawing step is performed. In the second wire drawing step, wire drawing is performed at a working ratio of 10% or more and 70% or less. If the working ratio is less than 10%, the driving force for recrystallization during the second heat treatment step is insufficient, and the second heat treatment step cannot control the accumulation rate of a predetermined crystal orientation in the cross section of the copper-based wire within the desired range. On the other hand, if the working ratio exceeds 70%, the introduced working strain increases, and strain is introduced into the entire sample. Therefore, the second heat treatment step cannot control the accumulation rate of a predetermined crystal orientation in the cross section of the copper-based wire within the desired range, and furthermore, it is difficult to achieve an average crystal grain size of 20 μm or more in the cross section of the copper-based wire. From these viewpoints, the working ratio is preferably 15% or more and 50% or less. The working ratio is expressed as 100 multiplied by the value obtained by dividing the value obtained by subtracting the cross-sectional area of the sample after wire drawing from the cross-sectional area of the sample before wire drawing by the cross-sectional area of the sample before wire drawing.

[0049] After the second wire drawing step, a second heat treatment step is performed. In the second heat treatment step, in the in-line heat treatment, the heat treatment temperature is 500°C or more and 900°C or less, and the heat treatment time is 6 seconds or more and within 15 seconds. In this way, a copper-based wire can be obtained.

[0050] Also, when the copper-based wire has a metal coating layer, it is preferable to perform a plating step on the copper-based wire. In the plating step, first, the copper-based wire is immersed in an alkaline bath, and electricity is passed so that the copper-based wire becomes the cathode to remove organic dirt present on the surface of the copper-based wire. Subsequently, the copper-based wire after washing with water is immersed in a sulfuric acid bath to remove the oxide film on the surface of the copper-based wire. Subsequently, the copper-based wire after washing with water is immersed in a palladium-containing solution, and electroplating is performed at a predetermined current and time to form a palladium coating layer, which is a metal coating layer, on the surface of the copper-based wire. The current and time of electroplating are appropriately set according to the thickness of the metal coating layer.

[0051] Next, the semiconductor device of the embodiment will be described.

[0052] FIG. 1 is a perspective view showing an example of a half-tower body device according to an embodiment. As shown in FIG. 1, the semiconductor device according to the embodiment includes a semiconductor chip and bonding wires bonded to the semiconductor chip. The bonding wires are made of copper or a copper alloy, and in a cross-section of the bonding wire perpendicular to the longitudinal direction of the bonding wire at a joint between an electrode provided on the upper portion of the semiconductor chip and the bonding wire, the average crystal grain size is 10 μm or more and 100 μm or less, and the integration rate of crystal orientation <111> is 40% or less.

[0053] In semiconductor device 1, semiconductor chip 2 is provided on die pad 3, and electrode 2a is further provided on the upper portion of semiconductor chip 2. On the other hand, inner lead 5, which is a substrate electrode, exists, and electrode 2a and inner lead 5 are connected by bonding wire 4. Electrode 2a is, for example, an aluminum electrode or a copper electrode.

[0054] Bonding wire 4 is made of copper (copper wire) or a copper alloy (copper alloy wire).

[0055] The bonding wire may be a copper alloy containing a small amount of elements such as Ag, Cr, and Sn, for example. However, considering the softness and ensuring conductivity between semiconductor chip 2 and inner lead 5, and taking into account the recent trends of higher output and larger current, copper is preferred. Among them, tough pitch copper, which is pure copper composed of 99.90 mass% or more of Cu and inevitable impurities, is preferably used because the higher the copper content, the higher the conductivity. More preferably, it is oxygen-free copper composed of 99.96 mass% or more of Cu, 10 ppm or less of oxygen, and inevitable impurities.

[0056] As the copper alloy constituting bonding wire 4, it preferably has an alloy composition containing at least one element of 0.1 mass% or more and 1.0 mass% or less of Ag, 0.1 mass% or more and 1.0 mass% or less of Cr, and 0.1 mass% or more and 1.0 mass% or less of Sn, with the balance being Cu and inevitable impurities.

[0057] When Ag, Cr, and Sn are at or above the above lower limit values, the tensile durability of the bonding wire 4 can be improved. Therefore, it can withstand the tensile load during the payout of the bonding wire 4 when bonding the bonding wire 4 to the electrode 2a of the semiconductor chip 2, and the bonding speed can be improved. On the other hand, when Ag, Cr, and Sn exceed the above upper limit values, it can be a factor in reducing the conductivity of the bonding wire 4. Therefore, for bonding wires for power semiconductors, it is preferable to add these elements at low concentrations. From this perspective, regarding the content of Ag when the copper alloy contains Ag, the upper limit value is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less. Regarding the content of Cr when the copper alloy contains Cr, the upper limit value is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less. Regarding the content of Sn when the copper alloy contains Sn, the upper limit value is more preferably 0.7% by mass or less, and even more preferably 0.4% by mass or less.

[0058] The balance other than the elements described above is unavoidable impurities. Depending on the content of the unavoidable impurities, it can be a factor in reducing the conductivity of the bonding wire 4, so it is preferable that the content of the unavoidable impurities is low.

[0059] When the bonding wire 4 is a copper alloy, examples of the unavoidable impurities include elements such as aluminum (Al), beryllium (Be), cadmium (Cd), iron (Fe), magnesium (Mg), nickel (Ni), phosphorus (P), palladium (Pd), silicon (Si), and titanium (Ti). When the bonding wire 4 is copper, in addition to the above elements, the unavoidable impurities also include elements that are intentionally contained in the copper alloy and alloyed with copper, such as Ag, Cr, Sn, etc. Note that the upper limit of the content of the unavoidable impurities is preferably 20 ppm or less in total of the above elements.

[0060] Also, in the cross-section of the bonding wire 4 perpendicular to the longitudinal direction of the bonding wire 4 at the joint 6 between the electrode 2a on the semiconductor chip 2 and the bonding wire 4, the average crystal grain size is 10 μm or more and 100 μm or less, and the integration rate of the crystal orientation <111> is 40% or less. In the cross-section of the bonding wire 4, the integration rate of the crystal orientation <111> is the ratio of the crystal orientations in the range shifted by ±15° from the crystal orientation <111> to all crystal orientations. Further, the joint 6 is the portion of the bonding wire 4 that is joined to the electrode 2a on the semiconductor chip 2.

[0061] When the average crystal grain size of the bonding wire 4 and the integration rate of the crystal orientation <111> are within the above ranges in the cross-section of the bonding wire 4 at the joint 6, breakage of the semiconductor chip 2 due to the joining of the semiconductor chip 2 and the bonding wire 4 is suppressed, and a good semiconductor device 1 can be obtained.

[0062] Also, in the cross-section of the bonding wire 4 at the joint 6, the total integration rate of the integration rate of the crystal orientation <100> and the integration rate of the crystal orientation <110> is preferably 15% or more and 40% or less. In the cross-section of the bonding wire 4 at the joint 6, the total integration rate of the integration rate of the crystal orientation <100> and the integration rate of the crystal orientation <110> is the ratio of the total crystal orientations in the range shifted by ±15° from the crystal orientation <100> and the range shifted by ±15° from the crystal orientation <110> to all crystal orientations.

[0063] When the above total integration rate of the bonding wire 4 is within the above range in the cross-section of the bonding wire 4 at the joint 6, the bonding wire 4 becomes softer, has excellent impact durability, and is easily bent during wiring, so that space saving becomes possible.

[0064] Also, in the cross-section of the bonding wire 4 at the joint 6, the length L of the grain boundary where the orientation difference between adjacent crystals is 15 degrees or more B to the length L of the twin grain boundary T of (L T / LB ) is preferably 0.7 or more and 1.0 or less. In the cross section of the bonding wire 4 at the joint 6, the above ratio (L T / L B ) is within the above range, the bonding wire 4 becomes soft, has excellent impact durability, and is easy to bend during routing, so that space saving is possible.

[0065] Further, when the bonding wire 4 is a round wire, if the wire diameter of the bonding wire 4 (round wire) is 0.1 mm or more, and when the bonding wire 4 is a ribbon wire, if the thickness of the bonding wire 4 (ribbon wire) is 0.1 mm or more, a relatively high current can flow through the bonding wire 4. Therefore, the bonding wire 4 is suitable for a bonding wire for a power semiconductor.

[0066] Further, when the wire diameter of the bonding wire 4 (round wire) is 0.5 mm or less, and the thickness of the bonding wire 4 (ribbon wire) is 0.5 mm or less, it is possible to sufficiently secure the wiring space for the trend of miniaturization of the semiconductor device, and furthermore, the bonding wire 4 is easily bent.

[0067] Further, in order to prevent oxidation of the outer peripheral surface of the bonding wire 4, the bonding wire 4 may have a metal coating layer (not shown) that coats the outer peripheral surface. The metal coating layer is preferably a palladium coating layer. The palladium coating layer that coats the outer peripheral surface of the bonding wire 4 is formed, for example, by plating.

[0068] From the viewpoint of suppressing breakage of the semiconductor chip 2 caused by the bonding between the electrode 2a of the semiconductor chip 2 and the bonding wire 4, the bonding wire 4 is preferably a copper-based wire material of the above embodiment.

[0069] Next, a method for joining the semiconductor chip 2 and the bonding wire 4 in the semiconductor device of the embodiment will be described. Here, a method for joining the semiconductor chip 2 and the bonding wire 4 by wedge bonding will be described, but the method for joining the semiconductor chip 2 and the bonding wire 4 is not limited to wedge bonding.

[0070] FIG. 2 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire before wedge bonding, and FIG. 3 is a schematic diagram showing an example of a cross section perpendicular to the longitudinal direction of the bonding wire during wedge bonding.

[0071] The bonding wire 4 is joined to the electrode 2a on the semiconductor chip 2. In wedge bonding, the bonding wire 4 is pressed against the electrode 2a on the semiconductor chip 2 with a wedge-shaped tool 7, and ultrasonic waves are applied at a frequency of 60 kHz or more and 120 kHz or less for a time of 0.1 second or more and 0.8 second or less to join the bonding wire 4 to the electrode 2a of the semiconductor chip 2. Thus, a semiconductor device including the semiconductor chip 2 and the bonding wire 4 joined to the semiconductor chip 2 can be obtained.

[0072] According to the embodiment described above, paying attention to simultaneously controlling the crystal grain size and crystal orientation of the copper-based wire, by controlling the average crystal grain size and the integration rate of the crystal orientation <111> in the cross section of the copper-based wire, the Young's modulus and 0.2% proof stress, which were conventionally in an inverse relationship, can be simultaneously reduced. Therefore, the copper-based wire is soft, has a small load even when pressed against the semiconductor chip, and is excellent in impact durability. Further, when the copper-based wire is used as a bonding wire, when the copper-based wire (bonding wire) is joined to the semiconductor chip mounted on the semiconductor device, the copper-based wire is moderately deformed, so that the load on the semiconductor chip is reduced, and breakage of the semiconductor chip caused by the joining of the semiconductor chip and the bonding wire can be suppressed.

[0073] Although the embodiments have been described above, the present invention is not limited to the above embodiments, but includes all aspects included in the concept of the present disclosure and the scope of the claims, and can be variously modified within the scope of the present disclosure.

Example

[0074] Next, examples and comparative examples will be described, but the present disclosure is not limited to these examples.

[0075] (Examples A1 to A4, A7 to A14 and Comparative Examples A1 to A3) A copper-based material composed of the components shown in Table 1 was subjected to a casting process, an extrusion process, and a first wire drawing process to obtain a wire rod with a wire diameter of 0.56 mm. Subsequently, a first heat treatment process was performed under the conditions shown in Table 2. Subsequently, a second wire drawing process was performed to obtain a wire rod having the shape, wire diameter, thickness, width, and processing rate shown in Table 2. In the second wire drawing process, it was finished into a round wire or a ribbon wire using a round hole die, a flat rectangular die, or a cassette roller die (CRD) that draws through a gap arranged by two rolls. Subsequently, a second heat treatment process was performed under the conditions shown in Table 2. Thus, a copper-based wire rod was obtained.

[0076] (Examples A5 to A6) A copper-based material composed of the components shown in Table 1 was subjected to a casting process, a rolling process, and a first wire drawing process to obtain a strip with a thickness of 0.56 mm. Subsequently, a first heat treatment process was performed under the conditions shown in Table 2. Subsequently, a second wire drawing process was performed to obtain a wire rod having the shape, thickness, width, and processing rate shown in Table 2. In the second wire drawing process, it was rolled to the thickness shown in Table 2, slit processed to cut out a desired width, and finished into a ribbon wire. Subsequently, a second heat treatment process was performed under the conditions shown in Table 2. Thus, a copper-based wire rod was obtained.

[0077] (Example A15) For the copper-based wire rod obtained in Example A1, a plating process was performed. In the plating process, first, the copper-based wire rod was immersed in an alkaline bath composed of caustic soda, sodium carbonate, and sodium silicate, and a current of 5 A / dm was applied so that the copper-based wire rod became the cathode. 2It was energized for 5 seconds to remove the organic dirt present on the surface of the copper-based wire. Subsequently, the washed copper-based wire was immersed in a 10% sulfuric acid bath for 5 seconds to remove the oxide film on the surface of the copper-based wire. Subsequently, the washed copper-based wire was immersed in a palladium-containing solution, and electroplating was performed at a current of 4 - 20 A / dm 2 and the current value and time were adjusted so that the thickness of the palladium coating layer became 1 μm to form a palladium coating layer on the surface of the copper-based wire. The thickness of the palladium coating layer was determined by observing a cross-section perpendicular to the longitudinal direction of the copper-based wire with an optical microscope.

[0078] The palladium-containing solution consisted of 8 g / L of palladium metal (98 g / L of dichlorotetraamminepalladium which is a palladium metal complex), 400 g / L of ammonium nitrate, and 160 g / L of ammonium chloride, and the pH was adjusted to be between 8 - 9 with aqueous ammonia. The temperature of the palladium-containing solution was set at 60°C.

[0079] (Examples B1 - B15 and Comparative Examples B1 - B3) As shown in Table 4, using the copper-based wires obtained in the above examples and comparative examples as bonding wires, the copper-based wires were pressed against electrodes (aluminum electrode pads) provided on a semiconductor chip with a length of 10 mm and a width of 10 mm, and ultrasonic bonding was performed to bond the copper-based wires to the semiconductor chip. The ultrasonic application conditions were a frequency of 60 kHz and a time of 0.3 seconds. Thus, a semiconductor device was obtained by wedge bonding.

[0080] [Evaluation] The following evaluations were performed on the copper-based wires and semiconductor devices obtained in the above examples and comparative examples. The results are shown in Tables 3 - 4.

[0081] [1] Average crystal grain size, integration rate of crystal orientation, and ratio (L T / L B ) Average crystal grain size, crystal orientation, and ratio (L T / L B) was obtained from the crystal orientation analysis data calculated using analysis software (manufactured by TSL, OIM Analysis) from the crystal orientation data continuously measured using an EBSD detector (manufactured by TSL, OIM5.0 HIKARI) attached to a high-resolution scanning analytical electron microscope (manufactured by JEOL Ltd., JSM-7001FA). "EBSD" is an abbreviation for Electron BackScatter Diffraction, which is a crystal orientation analysis technique that utilizes reflection electron Kikuchi line diffraction generated when an electron beam irradiates a measurement sample within a scanning electron microscope (SEM).

[0082] The measurement target was a cross-section obtained by cutting a single copper-based wire perpendicularly to its longitudinal direction and polished to a mirror finish, or as shown in Fig. 1, a cut cross-section obtained by cutting the joint 6 between the semiconductor chip and the bonding wire along a cutting line P perpendicular to the longitudinal direction of the bonding wire and polished to a mirror finish (in Fig. 1, of the two cut cross-sections, the surface of the bonding wire on the front right side of the paper). The measurement area was the entire cross-sectional range. The measurement was performed with an EBSD step size of 1 μm. In the EBSD measurement, n3 (three measurement targets) were measured, and their average value was calculated.

[0083] The average crystal grain size was calculated by selecting chart-grain size (diameter) of the analysis software for the measurement range and using the area method.

[0084] The integration ratio of each crystal orientation was obtained by selecting the orientation parallel to the longitudinal direction of the copper-based wire or bonding wire on the IPFmap and using chart-crystal direction to calculate the ratio of the area of the orientation grains within ±15° from the crystal orientations <111>, <100>, and <110> to the area of all orientation grains as the integration ratio of the crystal orientation <111>, the integration ratio of the crystal orientation <100>, and the integration ratio of the crystal orientation <110>, respectively.

[0085] Also, select 15° or more and 65° or less with Rotation Angle, and set the total length of the crystal orientation difference as L B and select Σ3 with CSL, and set the total length as LT was used. And, L B was divided by L T to calculate the ratio (L T / L B ). Note that CSL is the abbreviation of Coincidence Site Lattice, which means correspondence, and the twin grain boundary is represented by the coincidence grain boundary Σ3.

[0086] [2] Component analysis At the stage of obtaining the rough drawn wire with a wire diameter of 8 mm, the rough drawn wire was pressed into a flat plate shape, and the average value of n3 was calculated using emission spectroscopic analysis.

[0087] [3] 0.2% proof stress In accordance with JIS Z2241, a tensile test was performed using a precision universal testing machine (manufactured by Shimadzu Corporation) to obtain the 0.2% proof stress (MPa) by the offset method. Note that the tensile test was performed on three samples each (n3), and the average value was obtained. The 0.2% proof stress was considered qualified when it was 20 MPa or more and 90 MPa or less.

[0088] [4] Young's modulus Young's modulus measurement was carried out using the Young's modulus measuring device JE-RT (manufactured by Nippon Techno Plus) using the resonance method. The sample was cut to an arbitrary length of 40 mm or more and 60 mm or less so that the amplitude at the resonance frequency during measurement was large, and the weight of the sample was measured to calculate the density. The measurement of n3 was performed, and the average value was calculated. The Young's modulus was considered qualified when it was 80 GPa or more and 120 GPa or less.

[0089] [5] Strain hardening index In accordance with JIS Z2241, a tensile test was performed using a precision universal testing machine (manufactured by Shimadzu Corporation), and the strain hardening index was obtained from the formula: σ = C × ε n (σ: true stress, C: strength constant, ε: true strain, n: strain hardening index).

[0090] [6] Breakage of semiconductor chip A copper-based wire was pressed against an aluminum electrode pad provided on a semiconductor chip, and ultrasonic bonding was performed. The damage state of the semiconductor chip when the copper-based wire was bonded to the semiconductor chip was evaluated. For the semiconductor devices obtained in the examples and comparative examples, the surface of the aluminum electrode pad on the semiconductor chip after ultrasonic bonding was visually observed. Those in which cracks were observed were judged as defective with damage to the semiconductor chip. On the other hand, those in which no cracks were confirmed were judged as qualified without damage to the semiconductor chip.

[0091]

Table 1

[0092]

Table 2

[0093]

Table 3

[0094]

Table 4

[0095] As shown in Tables 1 to 3, in Examples A1 to A15, the average crystal grain size and the integration ratio of the crystal orientation <111> in the cross section of the copper-based wire, as well as the Young's modulus and 0.2% proof stress of the copper-based wire, were controlled within a predetermined range. Therefore, the copper-based wire was soft, the load was small even when pressed against the semiconductor chip, and it had excellent impact durability. Furthermore, as shown in Table 4, in Examples B1 to B15 using the copper-based material obtained in Examples A1 to A15 as a bonding wire, in the cross section of the bonding wire at the joint, the average crystal grain size and the integration ratio of the crystal orientation <111> were within a predetermined range, and the copper-based wire deformed moderately when bonded to the semiconductor chip. Therefore, the load on the semiconductor chip was reduced, and no damage to the semiconductor chip caused by the bonding between the semiconductor chip and the bonding wire occurred.

[0096] On the other hand, in Comparative Example A1, the aggregation rate of the crystal orientation <111> in the cross-section of the copper-based wire and the Young's modulus of the copper-based wire were not controlled within a predetermined range. Further, in Comparative Example B1 in which the copper-based material obtained in Comparative Example A1 was used as a bonding wire, the aggregation rate of the crystal orientation <111> was not within the predetermined range in the cross-section of the bonding wire at the joint. Therefore, in Comparative Example B1, breakage of the semiconductor chip due to the bonding between the semiconductor chip and the bonding wire occurred.

[0097] Also, in Comparative Example A2, the average crystal grain size and the aggregation rate of the crystal orientation <111> in the cross-section of the copper-based wire, and the Young's modulus and 0.2% proof stress of the copper-based wire were not controlled within a predetermined range. Further, in Comparative Example B2 in which the copper-based material obtained in Comparative Example A2 was used as a bonding wire, the average crystal grain size and the aggregation rate of the crystal orientation <111> were not within the predetermined range in the cross-section of the bonding wire at the joint. Therefore, in Comparative Example B2, breakage of the semiconductor chip due to the bonding between the semiconductor chip and the bonding wire occurred.

[0098] Also, in Comparative Example A3, the average crystal grain size in the cross-section of the copper-based wire and the 0.2% proof stress were not controlled within a predetermined range. Further, in Comparative Example B3 in which the copper-based material obtained in Comparative Example A3 was used as a bonding wire, the average crystal grain size was not within the predetermined range in the cross-section of the bonding wire at the joint. Therefore, in Comparative Example B3, breakage of the semiconductor chip due to the bonding between the semiconductor chip and the bonding wire occurred.

Explanation of Signs

[0099] 1 Semiconductor device 2 Semiconductor chip 2a Electrode 3 Die pad 4 Bonding wire 5 Inner lead 6 Joint 7 Wedge-shaped tool

Claims

1. A copper-based wire made of copper or a copper alloy, in a cross-section perpendicular to the longitudinal direction of the copper-based wire, the average crystal grain size is 20 μm or more and 150 μm or less, and the integration ratio of the crystal orientation <111> is 40% or less, the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is 15% or more and 40% or less, the Young's modulus is 80 GPa or more and 120 GPa or less, and the 0.2% proof stress is 20 MPa or more and 90 MPa or less. A copper-based wire for bonding wire.

2. In the cross section, the length L of a grain boundary where the orientation difference between adjacent crystals is 15 degrees or more Ｂ to the length L of a twin grain boundary Ｔ The ratio (L Ｔ / L Ｂ ) is 0.7 or more and 1.0 or less. The copper-based wire according to claim 1

3. The copper-based wire according to claim 1 or 2, wherein the copper-based wire is a round wire or a ribbon wire.

4. The copper-based wire according to claim 1 or 2, wherein the copper-based wire is made of oxygen-free copper.

5. The copper-based wire according to claim 1 or 2, which has a palladium coating layer covering the outer peripheral surface.

6. A semiconductor device comprising a semiconductor chip and a bonding wire bonded to the semiconductor chip, the bonding wire is made of copper or a copper alloy, in a cross-section of the bonding wire perpendicular to the longitudinal direction of the bonding wire at a joint between an electrode provided on the upper part of the semiconductor chip and the bonding wire, the average crystal grain size is 10 μm or more and 100 μm or less, and the integration ratio of the crystal orientation <111> is 40% or less, and the total integration ratio of the integration ratio of the crystal orientation <100> and the integration ratio of the crystal orientation <110> is 15% or more and 40% or less.

7. In the cross section, the length L of a grain boundary where the orientation difference between adjacent crystals is 15 degrees or more Ｂ to the length L of a twin grain boundary Ｔ The ratio (L Ｔ / L Ｂ ) is 0.7 or more and 1.0 or less. The semiconductor device according to claim 6

8. The semiconductor device according to claim 6 or 7, wherein the bonding wire is made of oxygen-free copper.

9. The semiconductor device according to claim 6 or 7, wherein the bonding wire has a palladium coating layer covering the outer peripheral surface.

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