Semiconductor device

Abstract

To provide a semiconductor device including a trench structure and capable of obtaining a high avalanche resistance.SOLUTION: There is provided a semiconductor device 1 including: an SiC substrate 2; an MIS transistor; a plurality of first gate finger trenches 11 composed of extention parts of gate trenches 9 in a gate finger part 4; a gate electrode 22 embedded in the gate trench 9 and in the first gate finger trench 11 via a gate insulation film 23; an electrode film residue 50 formed between a source pad 5 and the SiC substrate 2; and an insulation film residue 49 formed between the electrode film residue 50 and the SiC substrate 2. The electrode film residue 50 exists on the insulation film residue 49. The source pad 5 is brought into contact with a p+-type channel contact region 16 formed in the SiC substrate 2 and the electrode film residue 50 between the gate trenches 9 adjacent to each other.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a trench gate structure.

Background Art

[0002] For example, Patent Document 1 discloses a trench gate vertical MOSFET including an epitaxial layer in which an active cell array and a gate bus area are formed, a gate trench formed in the active cell array, a gate oxide film formed in the gate trench, a gate electrode made of polysilicon embedded in the gate trench, a trench formed in the gate bus area and connected to the gate trench, and a gate bus (gate finger) made of polysilicon embedded in the trench so as to cover the surface of the epitaxial layer in the gate bus area.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to obtain a high avalanche tolerance in a transistor, it is necessary to cause avalanche breakdown at the pn junction in the active portion. That is, when avalanche breakdown occurs (when a high voltage is applied), if the electric field concentrates on the gate finger portion having a lower breakdown voltage tolerance than the active portion, the gate finger portion will reach breakdown first, making it difficult to obtain a sufficient avalanche tolerance.

[0005] One embodiment of the present invention provides a semiconductor device having a trench gate structure capable of obtaining a high avalanche tolerance.

Means for Solving the Problems

[0006] One embodiment of the present invention includes an active portion, a semiconductor layer made of SiC, and a plurality of MIS transistors formed in the active portion. The active portion is partitioned into a plurality of unit cells by a plurality of gate trenches. Each of the MIS transistors includes a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of the first conductivity type that are sequentially arranged along the side surface of the gate trench, a plurality of first gate finger trenches formed at an extension of the gate trench in a gate finger portion, a gate electrode embedded in the gate trench and the first gate finger trench via a gate insulating film, a first bottom impurity region of the second conductivity type formed at least at the bottom of the first gate finger trench, and at least a part of the bottom of the first bottom impurity region has the same depth so as to form a horizontal straight line along the surface of the semiconductor layer in a cross-sectional view, a gate conductive layer electrically connected to the plurality of first gate finger trenches and the gate electrode, a source electrode formed on the semiconductor layer, a first film including a non-conductive material formed on the semiconductor layer between adjacent gate trenches, and a first conductive film formed between the source electrode and the first film. The source electrode has a protruding portion that protrudes in the thickness direction of the semiconductor layer, and forms a boundary with the first conductive film in a direction intersecting the thickness direction of the semiconductor layer. The gate conductive layer is formed at least in the gate finger portion and includes a gate finger connected to the gate electrode. The first gate finger trench is formed in a line shape that extends to the outside across the gate finger below the gate finger. A semiconductor device is provided.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

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Figure 12

Figure 13

Figure 14

Figure 15

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0009] FIGS. 1(a) and 1(b) are schematic plan views of a semiconductor device 1 according to an embodiment of the present invention. FIG. 1(a) shows an overall view, and FIG. 1(b) shows an internal enlarged view.

[0010] The semiconductor device 1 includes a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element (individual element) using SiC (silicon carbide). For example, the length of the semiconductor device 1 in the vertical direction on the paper surface of FIG. 1 is about 1 mm.

[0011] As shown in FIG. 1(a), the semiconductor device 1 includes a SiC substrate 2 as an example of a semiconductor layer. The SiC substrate 2 may be a SiC epitaxial substrate including a base substrate and an active layer formed thereon by epitaxial growth. The SiC substrate 2 is disposed at its central portion and includes an active portion 3 that functions as a field effect transistor and a gate finger portion 4 that surrounds the active portion 3.

[0012] For example, the source pad 5 made of aluminum is formed so as to cover substantially the entire active portion 3. The source pad 5 is substantially square in plan view. A removal region 6 is formed along the gate finger portion 4 at the peripheral portion of the source pad 5 to surround the central portion of the source pad 5. A part of the removal region 6 is selectively recessed toward the central portion of the source pad 5. A gate pad 7 is installed in this recess. For example, the gate finger 8 made of aluminum extends from the gate pad 7 along the gate finger portion 4 across the entire removal region 6. A pair of gate fingers 8 are formed in a symmetrical shape with respect to the gate pad 7.

[0013] As shown in FIG. 1(b), a gate trench 9 and a gate finger trench 10 are formed in the SiC substrate 2 directly below the source pad 5 and the like. The gate trench 9 is formed in the active portion 3. The gate trench 9 is formed in a lattice shape.

[0014] The gate finger trench 10 is formed in the gate finger portion 4. The gate finger trench 10 is formed integrally with the gate trench 9. Also, the gate finger trench 10 is formed with the same width as the gate trench 9. By making them the same width, it is possible to prevent embedding defects when embedding the gate electrode 22 described later.

[0015] The gate finger trench 10 includes a first gate finger trench 11 and a second gate finger trench 12. The first gate finger trench 11 is formed as an extension of the gate trench 9, and is formed in a stripe shape drawn from each end of the gate trench 9 to the gate finger portion 4. That is, the first gate finger trenches 11 are arranged at the same pitch as the grating pitch P1 of the gate trench 9. A plurality of second gate finger trenches 12 are formed in the region between adjacent first gate finger trenches 11. The second gate finger trenches 12 are connected to the portions 14 between the ends in the transverse trench 13 straddling a plurality of ends of the gate trench 9. In FIG. 1(b), two second gate finger trenches 12 are provided in each portion 14 between the ends, but this number is not particularly limited. Also, in this embodiment, each second gate finger trench 12 is parallel to the first gate finger trench 11. In the gate finger portion 4, the gate finger trenches 10 composed of the first gate finger trenches 11 and the second gate finger trenches 12 will be arranged at a pitch P2 narrower than the grating pitch P1.

[0016] Note that the patterns of the gate trench 9 and the gate finger trench 10 are not limited to these shapes. For example, the gate trench 9 may be in a stripe shape, a honeycomb shape, or the like. Also, the gate finger trench 10 may be in a lattice shape, a honeycomb shape, or the like.

[0017] The active portion 3 is further partitioned into a larger number of unit cells 15 by the gate trench 9. A large number of unit cells 15 will be regularly arranged in a matrix (row and column) in the active portion 3. A source trench 47 is formed at the center of each unit cell 15. On the bottom surface of the source trench 47, a p + -type channel contact region 16 (for example, a concentration of 1×10 18 cm -3 ~5×10 21 cm -3 ) is formed, and p +An n-type source region 17 (e.g., with a concentration of 1×10 + cm 18 ~5×10 -3 cm 21 ) is formed so as to surround the p-type channel contact region 16 (source trench 47). The n-type source region 17 forms the side surfaces of each unit cell 15 (the side surfaces of the gate trench 9) and the side surface of the source trench 47. -3 + In the gate finger part 4, the gate fingers 8 are laid along the direction crossing the stripe-shaped gate finger trench 10. In this embodiment, the gate fingers 8 are laid in an inner region rather than at the longitudinal end part (the end part opposite to the gate trench 9) of the gate finger trench 10, and the end part of the gate finger trench 10 protrudes outside the gate fingers 8. In the region further outside this end part, a recessed part 18 dug down across the entire circumference of the gate finger part 4 is formed in the SiC substrate 2. A p-type guard ring or the like (not shown) may be formed in the recessed part 18.

[0018]

[0019] Next, the basic cross-sectional structure of the active part 3 and the gate finger part 4 of the semiconductor device 1 will be described.

[0020] FIGS. 2A, 2B, 2C, and 2D are cross-sectional views of the semiconductor device 1 (the cross-sectional views taken along the lines IIA-IIA, IIB-IIB, IIC-IIC, and IID-IID in FIG. 1(b)), respectively.

[0021] As described above, the semiconductor device 1 includes the SiC substrate 2. The SiC substrate 2 is an n-type SiC substrate in this embodiment. The part below the surface part of the SiC substrate 2 functions as the n-type drain region 20 of the field-effect transistor (e.g., with a concentration of 1×10 14 cm -3 ~1×10 17 cm -3 ).

[0022] ​​ On the surface 21 side of the SiC substrate 2, a gate trench 9 and a gate finger trench 10 are formed. As described above, the active portion 3 is further partitioned into a plurality of unit cells 15 by the gate trench 9. On the upper surface of each unit cell 15, an n + -type source region 17 is formed, and a p-type channel region 19 (for example, a concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ) is formed. That is, as shown in FIG. 2A, the gate trench 9 penetrates the n + -type source region 17 and the p-type channel region 19 and reaches the n-type drain region 20.

[0023] A gate electrode 22 made of, for example, polysilicon is collectively embedded in the gate trench 9 and the gate finger trench 10. A gate insulating film 23 is interposed between the gate electrode 22 and the SiC substrate 2.

[0024] In the active portion 3, the gate electrode 22 is embedded in the gate trench 9 up to the surface 21 of the SiC substrate 2, as shown by the hatched lines in FIG. 1(b), for example. As a result, the gate electrode 22 is also formed in a lattice shape, and the upper surface of each unit cell 15 is exposed without being covered by the gate electrode 22. On the other hand, in the gate finger portion 4, it has an overlap portion 24 formed so as to cover the surface 21 of the SiC substrate 2 from the open end of the gate finger trench 10. The overlap portion 24 is formed so as to cross the stripe-shaped gate finger trench 10 along the gate finger 8.

[0025] The gate insulating film 23 integrally includes a side portion 25 on the side surface of the gate trench 9, a bottom portion 26 on the bottom surface, and a surface portion 27 on the surface 21 of the SiC substrate 2. The surface portion 27 is interposed at least between the overlap portion 24 and the surface 21 of the SiC substrate 2.

[0026] In the active portion 3, the gate electrode 22 is n+ It spans between the p-type source region 17 and the n-type drain region 20 and controls the formation of an inversion layer (channel) on the surface of the p-type channel region 19 (side surface of the gate trench 9). That is, this semiconductor device 1 has a MOSFET with a so-called trench gate structure.

[0027] A source trench 47 is formed at the center of each unit cell 15. The source trench 47 has the same depth as the gate trench 9, while having a wider width than the gate trench 9. The source trench 47 penetrates the n- + type source region 17 and the p-type channel region 19. In plan view, the source trench 47 may have a shape defined only by its outer periphery as shown in FIG. 1(b). In this case, on the cross-sectional surface that appears when the SiC substrate 2 is cut in the depth direction, as shown in FIG. 2A, one source trench 47 appears (the first pattern of the source trench). Specifically, as shown in FIG. 1(b), it may be a square in plan view (positive), or a (positive) hexagon, circle, etc.

[0028] Insulating film residues 49 and electrode film residues 50 remain at the bottom of the source trench 47. The insulating film residues 49 are selectively present at the corner portions and the periphery of the source trench 47 so as to expose the central portion of the bottom surface of the source trench 47. The electrode film residues 50 are present only on the insulating film residues 49. That is, the planar patterns of the insulating film residues 49 and the electrode film residues 50 are aligned with each other.

[0029] Also, in the active portion 3, a p-type region 28 (for example, with a concentration of 1×10 16 cm -3 ~1×10 19 cm -3) is formed. The p-type region 28 is formed along the inner surface of the source trench 47. The p-type region 28 has an outer surface that extends vertically from the p-type channel region 19 along the side surface of the source trench 47 and further extends horizontally along the bottom surface of the source trench 47. The vertical outer surface of the p-type region 28 is arranged at an interval inward from the gate trench 9. Therefore, in the intermediate region between the outer surface and the gate trench 9, there exist the n-type drain region 20 and the p-type channel region 19 connected to the p-type region 28. The p-type region 28 is formed so as to be continuous with the p-type channel region 19, and in the n-type drain region 20, it extends toward the back surface of the SiC substrate 2 to a position d1 deeper than the p-type channel region 19.

[0030] p + type channel contact region 16 is selectively formed at the center of the bottom surface of the source trench 47. Also, the p + type channel contact region 16 is formed with a size straddling the inside and outside of the insulating film residue 49. The p + thickness of the type channel contact region 16 (vertical depth from the bottom surface of the source trench 47) is smaller than the thickness of the p-type region 28. Therefore, the p + type channel contact region 16 is formed in a floating state on the surface portion of the p-type region 28.

[0031] On the surface 21 of the SiC substrate 2, an interlayer film 29 made of, for example, silicon oxide is formed. In the active portion 3, a contact hole 30 is selectively formed in the central region of the p-type channel region 19 in the interlayer film 29. This contact hole 30 selectively exposes the source trench 47. Also, in the gate finger portion 4, a contact hole 31 is selectively formed directly below the gate finger 8 in the interlayer film 29. The contact hole 31 is formed linearly along the gate finger portion 4 so as to surround the active portion 3 at the center in the width direction of the gate finger 8.

[0032] On the interlayer film 29, a source pad 5 and gate fingers 8 (gate pads 7) are formed. The source pad 5 enters all the contact holes 30 collectively, and in each unit cell 15, n + -type source regions 17 and p + -type channel contact regions 16 are connected. Therefore, the n + -type source region 17 has the same potential as the source pad 5. Also, since the p-type channel region 19 is connected to the source pad 5 via the p + -type channel contact region 16, it has the same potential as this source pad 5. The gate fingers 8 enter the contact holes 31 and are connected to the overlap portion 24 of the gate electrode 22. Therefore, the gate electrode 22 embedded in the gate trench 9 is connected to the gate fingers 8 via the overlap portion 24, so it has the same potential as the gate fingers 8 (gate pads 7).

[0033] FIG. 3 is an enlarged cross-sectional view of the gate finger portion 4 of the semiconductor device 1. In FIG. 3, the parts corresponding to the respective parts shown in FIGS. 1 and 2 described above are denoted by the same reference numerals. Also, in FIG. 3, the gate fingers 8 and the interlayer film 29 are omitted.

[0034] The side surface portion 25 of the gate insulating film 23 includes an overhang portion 33 that is selectively thicker than other portions of the side surface portion 25 so as to protrude inward of the gate finger trench 10 at the upper edge 32 of the gate finger trench 10. This overhang portion 33 may be employed at the upper edge (not shown) of the gate trench 9.

[0035] The upper edge 32 is a corner portion including an intersection line formed by the intersection of the side surface of the gate finger trench 10 and the surface 21 of the SiC substrate 2. In FIG. 3, the upper edge 32 is an inclined surface 34 that connects the surface 21 of the SiC substrate 2 and the side surface of the gate finger trench 10. That is, the upper edge 32 of the gate finger trench 10 has a chamfered shape. Instead of this inclined surface 34, a circular surface 39 (see FIG. 6) may be adopted. By the circular surface 39, the upper edge 32 of the gate finger trench 10 becomes rounded without becoming sharp.

[0036] In the semiconductor device 1, when an on-voltage is applied to the gate finger 8, an on-voltage is also applied to the overlapping portion 24 of the gate electrode 22 thereby. Therefore, the electric field generated from the overlapping portion 24 tends to concentrate on the upper edge 32 of the gate finger trench 10. As a result, there is a risk that the gate insulating film 23 breaks down at the upper edge 32 of the gate finger trench 10. However, the overhang portion 33 can improve the breakdown voltage of the gate insulating film 23 at the upper edge 32. Therefore, even if an electric field concentrates on the upper edge 32 when the gate is turned on, it is possible to prevent the gate insulating film 23 from breaking down at the upper edge 32. As a result, the reliability with respect to the gate on-voltage can be improved.

[0037] Regarding the relationship of the thicknesses of each part of the gate insulating film 23, the thickness t2 of the bottom surface portion 26 is equal to or greater than the thickness t1 of the surface portion 27 (t2≧t1), and it is preferable that both the thicknesses t1 and t2 are larger than the thickness t3 of the side surface portion 25 (excluding the overhang portion 33). That is, the relationship of t2≧t1>t3 is satisfied. With this configuration, the capacitance of the capacitor formed by the gate electrode 22 and the SiC substrate 2 facing each other through the bottom surface portion 26 can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. In addition, the breakdown voltage of the bottom surface portion 26 can be improved, so that dielectric breakdown of the bottom surface portion 26 when the gate is off can also be prevented. Also, since the surface portion 27 is thick, the capacitance of the capacitor formed by the gate electrode 22 (overlap portion 24) and the SiC substrate 2 facing each other through the surface portion 27 can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

[0038] The lower edge at the bottom of the gate finger trench 10 is a circular surface 35 that connects the side surface and the bottom surface of the gate finger trench 10. That is, the lower edge of the gate finger trench 10 is not sharp and is rounded by the circular surface 35. With this configuration, the electric field applied to the lower edge when the gate is off can be dispersed within the circular surface 35, so that the electric field concentration at the lower edge can be alleviated.

[0039] Also, on the surface 21 side of the SiC substrate 2, a p-type region 36 (for example, a concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ) is formed as an example of the surface portion impurity region. The p-type region 36 is formed over the entire region 37 (a flat region where the surface 21 of the SiC substrate 2 is continuous from one gate finger trench 10 to the other gate finger trench 10) between adjacent gate finger trenches 10. The p-type region 36 is formed shallower than the gate finger trench 10 and is formed, for example, at the same depth as the p-type channel region 19 (see FIG. 2A) of the active portion 3.

[0040] Also, at the bottom of the gate finger trench 10, a bottom p-type region 38 (for example, with a concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ) is formed as an example of an electric field relaxation region. The bottom p-type region 38 is continuous with the p-type region 36. Specifically, the bottom p-type region 38 is formed on the bottom surface and side surfaces of the gate finger trench 10 so as to hide the n-type drain region 20 exposed in the gate finger trench 10 below the p-type region 36, and is continuous with the p-type region 36 at its upper end. Therefore, in the width direction of the gate finger trench 10, a plurality of bottom p-type regions 38 and p-type regions 36 are alternately and continuously formed. On the other hand, in the longitudinal direction of the gate finger trench 10, as shown in FIG. 2D, the bottom p-type region 38 crosses the boundary between the gate finger trench 10 and the lower step portion 18 at the tip side of the gate finger trench 10 and reaches the lower step portion 18. On the other hand, at the base end side of the gate finger trench 10 (the side of the gate trench 9), it is also formed at the bottom of the horizontal trench 13 and is integrated with the p-type channel region 19 at the side portion of the horizontal trench 13. Thereby, the bottom p-type region 38 is electrically connected to the p-type channel region 19. Of course, the p-type region 36 is also electrically connected to the p-type channel region 19 via the bottom p-type region 38. Also, the depth d2 of the bottom p-type region 38 is preferably the same as or smaller than the depth d1 of the deepest part of the p-type impurity region in the active portion 3 (in this embodiment, the bottom of the p-type region 28) (d1≧d2). By maintaining this magnitude relationship between the depths d1 and d2, the effect of relaxing the electric field concentration on the gate finger portion 4 when a high voltage is applied can be further enhanced.

[0041] FIG. 4 is a flowchart for explaining a manufacturing method of the semiconductor device 1.

[0042] To manufacture the semiconductor device 1, for example, impurities are selectively implanted into the surface 21 of the SiC substrate 2 and annealed (step S1). Thereby, the p-type channel region 19, n+ -type source region 17, p + Impurity regions such as the p-type channel contact region 16 are formed. Next, by etching the SiC substrate 2 from the surface 21 in a predetermined pattern, a gate trench 9, a gate finger trench 10, and a source trench 47 are simultaneously formed in the SiC substrate 2 (step S2).

[0043] The next step is the formation of the p-type region 28 and the bottom p-type region 38. The formation of the p-type region 28 and the bottom p-type region 38 is performed by ion implantation and annealing (step S3). For example, a mask is formed on the SiC substrate 2 to cover regions other than the regions where the p-type region 28 and the bottom p-type region 38 are to be formed, and p-type impurities (ions) are implanted through the mask. The bottom p-type region 38 is formed by the p-type impurities implanted on the side surface and the bottom surface of the gate finger trench 10. After implantation, an annealing process is performed.

[0044] The next step is the formation of the gate insulating film 23 (step S4). The gate insulating film 23 is formed by depositing an insulating material in the gate trench 9 and the gate finger trench 10 using the CVD method under predetermined conditions (gas flow rate, gas species, gas ratio, gas supply time, etc.) such that an overhang portion 33 that is selectively thicker than other portions is formed at the upper edge 32 of the gate finger trench 10. Thereby, the gate insulating film 23 having the overhang portion 33 is formed.

[0045] Here, when forming the inclined surface 34 on the upper edge 32 as shown in FIG. 3, the SiC substrate 2 is thermally oxidized after the formation of the gate trench 9 and before the formation of the gate insulating film 23. Specifically, as shown in FIG. 5, by thermally oxidizing the SiC substrate 2, a sacrificial oxide film 40 is formed. When forming the sacrificial oxide film 40, oxidation starts uniformly from both the surface 21 of the SiC substrate 2 and the side surfaces of the gate finger trench 10 in the vicinity of the gate finger trench 10. Therefore, at the upper edge 32, the oxide film advancing from the surface 21 of the SiC substrate 2 and the oxide film advancing from the side surfaces of the gate finger trench 10 are integrated earlier than in other regions. As a result, an inclined surface 34 is formed below the integrated oxide film. Then, the sacrificial oxide film 40 is removed, and the gate insulating film 23 may be formed by the CVD method.

[0046] On the other hand, when forming the circular surface 39 on the upper edge 32, the SiC substrate 2 is subjected to H2 annealing after the formation of the gate finger trench 10 and before the formation of the gate insulating film 23. Specifically, as shown in FIG. 6, by subjecting the SiC substrate 2 to H2 annealing (H2 etching) at 1400 °C or higher, a circular surface 39 is formed on the upper edge 32.

[0047] Returning to FIG. 4 again, after the formation of the gate insulating film 23, the gate trench 9 and the gate finger trench 10 are filled back, and polysilicon is deposited until the entire gate trench 9 and the gate finger trench 10 are hidden (step S5). Then, by patterning the deposited polysilicon, in the active portion 3, the polysilicon outside the gate trench 9 is removed, and at the same time, in the gate finger portion 4, the polysilicon remains as the overlap portion 24. At this time, an electrode film residue 50 made of the remaining polysilicon material is formed in the source trench 47.

[0048] Next, an interlayer film 29 is formed on the SiC substrate 2 by the CVD method (step S6). Next, by patterning the interlayer film 29, contact holes 30 and 31 are simultaneously formed (step S7). At this time, a part of the gate insulating film 23 remains as an insulating film residue 49 in a portion sandwiched between the electrode film residue 50 and the inner surface of the source trench 47 in the source trench 47.

[0049] Next, a metal material such as aluminum is deposited on the interlayer film 29 by sputtering or vapor deposition (step S8). Thereby, the source pad 5, the gate pad 7, and the gate finger 8 are formed. Through the above steps and the like, the semiconductor device 1 is obtained.

[0050] According to the semiconductor device 1, since the bottom p-type region 38 is formed, a depletion layer generated by the junction (pn junction) between the bottom p-type region 38 and the n-type drain region 20 can be generated near the gate finger trench 10. And due to the presence of this depletion layer, the equipotential surface can be moved away from the gate insulating film 23. As a result, the electric field applied to the gate insulating film 23 at the bottom of the gate finger trench 10 can be relaxed. Also, since the bottom p-type region 38 of the gate finger portion 4 can be formed in the same process as the p-type region 28 of the active portion 3, the manufacturing process of the semiconductor device 1 can be simplified.

[0051] Furthermore, since the pitch P2 of the gate finger trench 10 is made narrower than the lattice pitch P1 of the gate trench 9 (see FIG. 2B), the density of the bottom p-type region 38 can be increased in the gate finger portion 4. Therefore, when a high voltage is applied, the electric field concentration on the gate finger portion 4 can be relaxed, and the occurrence of avalanche breakdown in the gate finger portion 4 can be reduced. As a result, since avalanche breakdown can be preferentially generated in the active portion 3, a high avalanche breakdown voltage can be realized.

[0052] For example, according to the experimental results of the inventors of the present application, in the semiconductor device 1 having the structure shown in FIGS. 1 to 3, when the pitch P2 is narrowed from 6 μm to 2 μm, it has been found that the electric field applied to the bottom of the gate finger trench 10 during high voltage application can be relaxed to about 0.7 times. As a result, it has been found that it can withstand an avalanche current about 8 times that before the pitch change.

[0053] Moreover, since the structure for relaxing the electric field of the gate finger portion 4 is the bottom p-type region 38 formed at the bottom of the gate finger trench 10, an electric field relaxation region deeper than the bottom of the gate finger trench 10 can be easily formed to such an extent that a p-type impurity region is formed relatively shallowly from the bottom of the gate finger trench 10.

[0054] FIGS. 7 to 13 are diagrams for explaining an embodiment of the gate finger portion 4 of the semiconductor device 1. FIGS. 14 and 15 are diagrams for explaining an embodiment of the active portion 3 of the semiconductor device 1.

[0055] As shown in FIG. 7, the semiconductor device 1 may not have the second gate finger trench 12 between the first gate finger trenches 11. In this case, the region between adjacent first gate finger trenches 11 is formed as a flat region 37, and the p-type region 36 is formed over the entire flat region 37. In FIG. 7, the structure for electric field relaxation of the gate finger portion 4 is formed as a p-type protruding region 41. The p-type protruding region 41 is continuous with the p-type region 36 and selectively protrudes downward from the p-type region 36. The protruding position is, for example, the formation position of the aforementioned second gate finger trench 12. The p-type protruding region 41 may be formed at the same depth d2 as the bottom p-type region 38 of the first gate finger trench 11. Further, the p-type protruding region 41 may be in a stripe shape parallel to the first gate finger trench 11 similar to the second gate finger trench 12, or may have a shape that selectively protrudes along the longitudinal direction of the first gate finger trench 11. Note that the p-type protruding region 41 may be formed by an ion implantation and annealing process for forming the p-type region 28.

[0056] According to this configuration, in the gate finger portion 4, the pitch P2 of the p-type region deeper than the first gate finger trench 11 can be made smaller than the lattice pitch P1 of the gate trench 9. Therefore, in the gate finger portion 4, the density of the bottom p-type region 38 and the p-type protruding region 41 can be increased. As a result, when a high voltage is applied, the electric field concentration on the gate finger portion 4 can be alleviated, and the occurrence of avalanche breakdown in the gate finger portion 4 can be reduced. As a result, avalanche breakdown can be preferentially generated in the active portion 3, so that a high avalanche breakdown voltage can be realized.

[0057] Furthermore, since the p-type protruding region 41 is formed in the flat region 37 of the SiC substrate 2, even if a mask misalignment occurs during ion implantation, the p-type protruding region 41 can be formed at the target depth position with a high probability.

[0058] For example, when a p-type impurity region is formed in the SiC substrate 2 by ion implantation, its depth is controlled by the implantation energy. The greater the implantation energy, the deeper the p-type impurity region can be formed from the surface 21 of the SiC substrate 2. Since the implantation energy is determined according to the target depth position, if a mask misalignment occurs in the previous stage of implantation, it may not be possible to form an impurity region at the target depth position. For example, as described above, the energy conditions for forming the bottom p-type region 38 of the gate finger trench 10 are determined according to the depth from the ion implantation surface (the bottom surface of the gate finger trench 10) as a reference surface. However, if the mask is laterally displaced with respect to the gate finger trench 10, the reference surface of the depth rises to the surface 21 of the SiC substrate 2 (the open end of the gate finger trench 10), and there is a risk that the impurity region will be formed only at a position shallower than the target position. However, according to this configuration, since the p-type protruding region 41 is formed in the flat region 37, even if a mask misalignment occurs, the height position of the reference surface of the ion implantation hardly changes. Therefore, the above effects can be obtained.

[0059] Further, instead of the p-type protruding region 41 in FIG. 7, the semiconductor device 1 may have a p-type floating region 42 formed at a distance downward from the p-type region 36 as shown in FIG. 8. The formation position of the p-type floating region 42 is, for example, the formation position of the second gate finger trench 12 described above. Further, the p-type floating region 42 may be in a stripe shape parallel to the first gate finger trench 11, similar to the second gate finger trench 12, or may be selectively scattered along the longitudinal direction of the first gate finger trench 11.

[0060] As shown in FIG. 9, the semiconductor device 1 may have a p-type region 43 that extends across the entire lower portion of the p-type region 36. The p-type region 43 is continuous and integrated with the bottom p-type region 38 of the first gate finger trench 11 in the lateral direction along the surface 21 of the SiC substrate 2. Further, the p-type region 43 may be formed at the same depth d2 as the bottom p-type region 38 of the first gate finger trench 11. As a result, in the flat region 37, a p-type impurity region is continuously formed in a region deeper than the first gate finger trench 11 from one first gate finger trench 11 to the other first gate finger trench 11. That is, the region between adjacent first gate finger trenches 11 is entirely covered by a p-type region deeper than the first gate finger trench 11. Therefore, the density of the p-type region in the gate finger portion 4 can be increased.

[0061] As shown in FIG. 10, the semiconductor device 1 may have an n + -type region 44 within the p-type region 36. The n + -type region 44 may be formed at the same depth position as the n + -type source region 17 (see FIG. 2A) of the active portion 3.

[0062] As shown in FIG. 11, the semiconductor device 1 may have a second gate finger trench 45 extending in a direction intersecting the first gate finger trench 11 instead of the second gate finger trench 12 parallel to the first gate finger trench 11. A plurality of second gate finger trenches 45 may be formed at intervals in the longitudinal direction of the first gate finger trench 11. As a result, the gate finger trenches 10 as a whole may be formed in a lattice shape by the first gate finger trench 11 extending in one direction and the second gate finger trench 45 extending in the other direction intersecting it. And in the second gate finger trench 45 as well, a bottom p-type region 38 may be formed in the same manner as the trench 11 of the first gate finger (see FIG. 3). Thereby, in the region along the second gate finger trench 45, as shown in FIG. 12, a p-type impurity region deeper than the first gate finger trench 11 can be continuously formed from one first gate finger trench 11 to the other first gate finger trench 11.

[0063] As shown in FIG. 13, the semiconductor device 1 does not necessarily have an inclined surface 34 or a circular surface 39 at the upper edge 32 of the gate finger trench 10. That is, the upper edge 32 may be sharp.

[0064] Also, as shown in FIG. 14, the semiconductor device 1 may include a source trench 48 instead of the source trench 47. The source trench 48 has a shape defined by both the outer periphery and the inner periphery in plan view (the left figure in FIG. 14). In this case, in the cross-sectional plane that appears when the SiC substrate 2 is cut in the depth direction, as shown in the cross-section along line A-A, two source trenches 48 appear (the second pattern of the source trench). Specifically, as shown in the left figure in FIG. 14, it may be a (regular) square ring shape in plan view, or a (regular) hexagonal ring shape, a circular ring shape, etc. As a result, a convex portion 51 (mesa portion) defined by the inner periphery of the source trench 48 is formed in the inner region of the source trench 48. Also, the source trench 48 has the same depth and width as the gate trench 9.

[0065] The p-type region 28 is formed over the entire outer edge of the source trench 48 and the inner region thereof, in the same configuration as that shown in FIG. 2A. Therefore, the p-type region 28 has an outer surface that extends vertically along the side surface of the source trench 48 from the p-type channel region 19 and extends horizontally along the bottom surface of the source trench 48, and further has an outer surface that extends horizontally along the surface of the SiC substrate 2 below the convex portion 51. Thus, in the configuration of FIG. 14, below the convex portion 51, there is a p-type region 28 formed deeper than the source trench 48. In this embodiment, most of the convex portion 51 except for the surface portion is composed of the p-type region 28. p + The p-type channel contact region 16 may be formed over the entire surface portion of the convex portion 51.

[0066] Further, as shown in FIG. 15, the semiconductor device 1 may not include the source trenches 47 and 48. p + The p-type channel contact region 16 is formed in the central region of each unit cell 15, and an n + -type source region 17 may be formed so as to surround the p + -type channel contact region 16. In this case, the semiconductor device 1 may include a p-type pillar layer 46 (for example, with a concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ) that is continuous with the p-type channel region 19. The p-type pillar layer 46 is formed in the inner region of the p-type channel region 19 of each unit cell 15. More specifically, the p-type pillar layer 46 may be formed, for example, in a region substantially at the center of the p-type channel region 19 in a shape similar to the p-type channel region 19 (a quadrilateral in plan view in the layout of FIG. 1(b)). That is, the p-type pillar layer 46 is formed substantially in a columnar shape (substantially in a quadrangular columnar shape in the layout of FIG. 1(b)). Thereby, on the SiC substrate 2, the p-type pillar layers 46 arranged at an appropriate pitch and the n-type drain regions 20 sandwiched between adjacent p-type pillar layers 46 are alternately arranged in the direction along the surface 21.

[0067] As described above, embodiments of the present invention have been explained. However, the present invention can also be implemented in other forms.

[0068] For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is reversed may be adopted. For example, in the semiconductor device 1, a p-type portion may be an n-type and an n-type portion may be a p-type.

[0069] Also, the semiconductor employed in the semiconductor device 1 is not limited to SiC, and may be, for example, Si, GaN, diamond, or the like.

[0070] Also, the overlap portion 24 is not limited to the gate finger portion 4 and may be formed in the active portion 3. For example, by covering only the periphery of the opening end of the gate trench 9 so that the upper surface of each unit cell 15 is not hidden, the overlap portion 24 may also be formed in the active portion 3. In this case, if the overhang portion 33 is also formed in the gate trench 9, the same breakdown voltage improvement effect as described above can be obtained. That is, the structure directly under the gate finger 8 is merely an example showing the breakdown voltage improvement effect by the overhang portion 33 of the present invention, and any structure capable of obtaining the same effect is not limited to the gate finger portion only.

[0071] In addition, various design changes can be made within the scope of the matters described in the claims.

[0072] Also, the following features can be extracted from the above-described embodiments.

[0073] A semiconductor layer including an active portion and a gate finger portion, an MIS transistor formed in the active portion, the MIS transistor including a gate trench, a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of the first conductivity type that are sequentially along a side surface of the gate trench, a plurality of first gate finger trenches formed as an extension of the gate trench in the gate finger portion, a gate electrode embedded in the gate trench and the first gate finger trenches via a gate insulating film, a first bottom impurity region of the second conductivity type formed at least at a bottom of the first gate finger trench, a gate finger that crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and an electric field relaxation region of the second conductivity type formed deeper than a bottom of the first gate finger trench between adjacent first gate finger trenches. A semiconductor device is extracted.

[0074] According to this configuration, due to the presence of the electric field relaxation region, the pitch of the impurity region of the second conductivity type (a region including both the first bottom impurity region and the electric field relaxation region) in the gate finger portion can be made narrower than the pitch of the gate trench. Thereby, since the density of the impurity region of the second conductivity type in the gate finger portion can be increased, when a high voltage is applied, the electric field concentration on the gate finger portion can be relaxed, and the occurrence of avalanche breakdown in the gate finger portion can be reduced. As a result, since avalanche breakdown can be preferentially generated in the active portion, a high avalanche withstand voltage can be realized.

[0075] The semiconductor device may further include a second gate finger trench formed between adjacent first gate finger trenches and integrated with the gate trench, and the electric field relaxation region may include a second bottom impurity region formed at least at a bottom of the second gate finger trench.

[0076] According to this configuration, since the depth of the second gate finger trench can be included in the depth of the electric field relaxation region, an electric field relaxation region deeper than the bottom of the first gate finger trench can be easily formed to such an extent that an impurity region is formed relatively shallowly from the bottom of the second gate finger trench.

[0077] In the semiconductor device, the second gate finger trench may extend along the first gate finger trench, or may extend in a direction intersecting the first gate finger trench.

[0078] In the semiconductor device, the region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench. The semiconductor device further includes a surface portion impurity region of a second conductivity type formed shallower than the bottom of the first gate finger trench in the flat region. In this case, the electric field relaxation region may include a region formed to be continuous with the surface portion impurity region, or may include a region formed at a distance below the surface portion impurity region.

[0079] For example, when the electric field relaxation region is formed by ion implantation, its depth is controlled by the implantation energy. The larger the implantation energy, the deeper the position where the electric field relaxation region can be formed from the semiconductor surface. Since the implantation energy is determined according to the target depth position, if a mask misalignment occurs in the previous stage of implantation, an impurity region may not be formed at the target depth position. For example, when an impurity region is formed at the bottom of a trench, the energy conditions are determined according to the depth from the implantation surface (the bottom surface of the trench) as a reference surface. However, if the mask is laterally displaced with respect to the trench, the reference surface of the depth rises to the surface of the semiconductor (the opening end of the trench), and there is a possibility that the impurity region is formed only at a position shallower than the target position.

[0080] According to this configuration, since the electric field relaxation region is formed in the flat region of the semiconductor layer, even if a mask misalignment occurs, the height position of the reference plane of ion implantation hardly changes. Therefore, it is possible to form at a high probability at a depth position targeting the electric field relaxation region.

[0081] In the semiconductor device, the MIS transistor further includes a region of a second conductivity type that is continuous with the channel region and formed deeper than the electric field relaxation region.

[0082] According to this configuration, the effect of relaxing the electric field concentration on the gate finger portion when a high voltage is applied can be further enhanced.

[0083] Also, a semiconductor layer including an active portion and a gate finger portion, an MIS transistor formed in the active portion, a gate trench formed at a predetermined pitch P1, a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of a first conductivity type that are sequentially along the side surface of the gate trench, and in the gate finger portion, a plurality of gate finger trenches formed at a pitch P2 narrower than the pitch P1 of the gate trench and integrated with the gate trench, a gate electrode embedded in the gate trench and the gate finger trench via a gate insulating film, a bottom impurity region of a second conductivity type formed at least at the bottom of the gate finger trench, and a gate finger that crosses the plurality of gate finger trenches and is electrically connected to the gate electrode are included, and a semiconductor device is extracted.

[0084] According to this configuration, since the density of the impurity region of the second conductivity type can be increased in the gate finger portion, when a high voltage is applied, the electric field concentration on the gate finger portion can be relaxed, and the occurrence of avalanche breakdown in the gate finger portion can be reduced. As a result, since avalanche breakdown can be preferentially generated in the active portion, a high avalanche tolerance can be realized.

[0085] In the semiconductor device, the gate trenches are formed in a lattice pattern, and the gate finger trenches are constituted by extension portions of the gate trenches and include a plurality of first gate finger trenches arranged at the lattice pitch of the gate trenches and second gate finger trenches formed between adjacent first gate finger trenches.

[0086] In the semiconductor device, the MIS transistor further includes a region of a second conductivity type that is continuous with the channel region and is formed deeper than the bottom impurity region.

[0087] According to this configuration, the effect of alleviating the electric field concentration on the gate finger portion when a high voltage is applied can be further enhanced.

[0088] In the semiconductor device, the bottom impurity region is electrically connected to the channel region.

[0089] According to this configuration, the potential of the bottom impurity region can be maintained at the potential of the channel region.

[0090] In the semiconductor device, the gate electrode has an overlap portion that overlaps the surface of the semiconductor layer at the upper edge of the trench in which the gate electrode is embedded, and the gate insulating film includes an overhang portion that protrudes inward of the trench at the upper edge. This trench includes the gate trench, the gate finger trench, the first gate finger trench, and the second gate finger trench.

[0091] According to this configuration, since the overhang portion is formed at the upper edge of the trench, the breakdown voltage of the gate insulating film at the upper edge can be improved. Therefore, even if an electric field is concentrated at the upper edge when the gate is turned on, dielectric breakdown of the gate insulating film at the upper edge can be prevented. As a result, the reliability with respect to the gate turn-on voltage can be improved.

[0092] In the semiconductor device, the upper edge includes an inclined surface that connects the surface of the semiconductor layer and the inner surface of the trench.

[0093] According to this configuration, when the gate is turned on, the electric field applied to the upper edge can be dispersed within the inclined surface, thereby alleviating the electric field concentration.

[0094] In the semiconductor device, the upper edge includes a circular surface that connects the surface of the semiconductor layer and the inner surface of the trench.

[0095] According to this configuration, when the gate is turned on, the electric field applied to the upper edge can be dispersed within the circular surface, thereby alleviating the electric field concentration.

[0096] In the semiconductor device, the gate insulating film on the bottom surface of the trench is thicker than the gate insulating film on the side surface of the trench.

[0097] According to this configuration, the capacitance of the capacitor formed by the gate electrode and the semiconductor layer facing each other through the gate insulating film on the bottom surface of the trench can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. In addition, the breakdown voltage of the gate insulating film on the bottom surface of the trench can be improved, so that dielectric breakdown of the gate insulating film when the gate is off can also be prevented.

[0098] In the semiconductor device, the gate insulating film further includes a portion thicker than the gate insulating film on the side surface of the trench on the surface of the semiconductor layer.

[0099] According to this configuration, the capacitance of the capacitor formed by the gate electrode (overlap portion) and the semiconductor layer facing each other through the gate insulating film on the surface of the semiconductor layer can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

[0100] In the semiconductor device, the lower edge of the trench includes a circular surface that connects the side surface and the bottom surface of the trench.

[0101] According to this configuration, when the gate is turned off, the electric field applied to the lower edge can be dispersed within the circular surface, thereby alleviating the electric field concentration.

Explanation of Reference Numerals

[0102] 1 Semiconductor device 2 SiC substrate 3 Active portion 4 Gate finger portion 8 Gate finger 9 Gate trench 10 Gate finger trench 11 First gate finger trench 12 Second gate finger trench 17 n + -type source region 19 p-type channel region 20 n-type drain region 22 Gate electrode 23 Gate insulating film 24 Overlap portion 25 Side surface portion (of the gate insulating film) 26 Bottom surface portion (of the gate insulating film) 27 Surface portion (of the gate insulating film) 28 p-type region 32 Upper edge 33 Overhang portion 34 Inclined surface 35 Circular surface 36 p-type region 37 Flat region 38 Bottom p-type region 39 Circular surface 41 p-type protruding region 42 p-type floating region 43 p-type region 45 Second gate finger trench 46 p-type pillar layer

Claims

1. A semiconductor device including an active portion and a semiconductor layer made of SiC, a plurality of MIS transistors formed in the active portion, each MIS transistor including a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of the first conductivity type that are sequentially along a side surface of a corresponding one of the plurality of gate trenches, a plurality of first gate finger trenches each formed by an extension of a corresponding one of the plurality of gate trenches in a gate finger portion, a gate electrode embedded in the gate trench and the first gate finger trench via a gate insulating film, a first bottom impurity region of the second conductivity type formed at least at a bottom of the first gate finger trench, wherein at least a part of a bottom of the first bottom impurity region has the same depth so as to form a horizontal straight line that continuously extends across between the gate finger portion and the active portion along a surface of the semiconductor layer in a cross-sectional view, a gate conductive layer electrically connected to the plurality of first gate finger trenches and the gate electrode, and a source electrode formed on the semiconductor layer, wherein the gate conductive layer is formed at least in the gate finger portion and includes gate fingers connected to the gate electrode, and the first gate finger trench is formed in a line shape that extends outward across the gate finger below the gate finger.

2. The semiconductor device according to claim 1, further including a first film including a non-conductive material formed on the semiconductor layer between adjacent ones of the gate trenches.

3. The semiconductor device according to claim 2, further including a first conductive film formed between the source electrode and the first film.

4. The semiconductor device according to any one of claims 1 to 3, wherein the gate electrode embedded in the first gate finger trench has a protruding portion protruding to an opposite side of a bottom of the first gate finger trench.

5. The semiconductor device according to claim 4, wherein the protruding portion of the gate electrode has a first portion formed directly above each of the first gate finger trenches and a second portion formed on the surface of the semiconductor layer sandwiched between adjacent ones of the first gate finger trenches.

6. The semiconductor device according to claim 5, wherein the gate conductive layer is in direct contact with the first portion and the second portion of the protruding portion of the gate electrode.

7. The protruding portion of the gate electrode has an upper surface that crosses the first portion and the second portion, The semiconductor device according to claim 5 or 6, wherein the upper surface of the protruding portion of the gate electrode is parallel to the bottom of the first bottom impurity region.

8. A second gate finger trench that is formed between adjacent first gate finger trenches and is integral with a gate trench different from the gate trench constituting the first gate finger trench, and an extension thereof; The semiconductor device according to any one of claims 1 to 7, further comprising a second bottom impurity region of a second conductivity type formed at least at the bottom of the second gate finger trench.

9. The semiconductor device according to claim 8, wherein a part of the bottom of the second bottom impurity region forms a part of the horizontal straight line in a cross-sectional view.

10. The semiconductor device according to claim 8 or 9, wherein the second gate finger trench extends along the first gate finger trench.

11. The semiconductor device according to claim 8 or 9, wherein the second gate finger trench extends in a direction intersecting the first gate finger trench.

12. The region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench, The semiconductor device according to any one of claims 1 to 7, wherein the region between adjacent first gate finger trenches further includes a surface portion impurity region of a second conductivity type in the flat region.

13. The semiconductor device according to claim 12, wherein the first bottom impurity region includes a region formed to be continuous with the surface portion impurity region.

14. The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor layer includes a wide bandgap semiconductor.

15. The semiconductor device according to any one of claims 1 to 14, wherein a lower edge of a trench including the gate trench and the first gate finger trench includes a circular surface that connects the side surface and the bottom surface of the trench.

16. The gate electrode has an overlap portion that overlaps the surface of the semiconductor layer at the upper edge of the trench in which the gate electrode is embedded. The semiconductor device according to any one of claims 1 to 14, wherein the gate insulating film includes an overhang portion that protrudes inward of the trench at the upper edge.

17. The semiconductor device according to claim 16, wherein the upper edge includes an inclined surface that connects the surface of the semiconductor layer and the inner surface of the trench.

18. The semiconductor device according to claim 16 or 17, wherein the upper edge includes a circular surface that connects the surface of the semiconductor layer and the inner surface of the trench.

19. The semiconductor device according to any one of claims 16 to 18, wherein the gate insulating film on the bottom surface of the trench is thicker than the gate insulating film on the side surface of the trench.

20. The semiconductor device according to any one of claims 16 to 19, wherein the gate insulating film further includes a portion that is thicker than the gate insulating film on the side surface of the trench on the surface of the semiconductor layer.

21. The semiconductor device according to any one of claims 1 to 20, wherein avalanche breakdown preferentially occurs in the active portion rather than in the gate finger portion.

Images