Semiconductor device assembly including a monolithic silicon structure for heat dissipation and method of manufacturing the same

Abstract

A semiconductor device assembly is provided that includes a first semiconductor device including a plurality of electrical contacts on a top surface thereof, a monolithic silicon structure having a bottom surface in contact with the top surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the bottom surface into a body of the monolithic silicon structure, and a second semiconductor device disposed within the cavity and including a plurality of interconnects, the plurality of interconnects each operably coupled to a corresponding one of the plurality of electrical contacts.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application includes subject matter related to the subject matter of a co - pending U.S. patent application entitled "SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICON STRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME". The related application, the disclosure of which is incorporated herein by reference, is assigned to Micron Technology, Inc. and is identified by Attorney Docket Nos. 010829 - 9680.US00 and 010829 - 9681.US00.

[0002] Technical Field The present disclosure generally relates to semiconductor device assemblies, and more particularly, to semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same.

Background Art

[0003] Microelectronic devices generally have dies (i.e., chips) that include integrated circuits with very small components in high density. Typically, a die includes an array of very small bond pads electrically connected to the integrated circuit. The bond pads are external electrical contacts through which supply voltages, signals, etc. communicate with the integrated circuit. After the dies are formed, they are "packaged" to connect the bond pads to a larger array of electrical terminals that can be more easily connected to various power lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically connecting the bond pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particles, static electricity, and physical impacts).

Brief Description of the Drawings

[0004]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

DETAILED DESCRIPTION OF THE INVENTION

[0005] Some embodiments of semiconductor devices, as well as specific details of related systems and methods, are described below. Those skilled in the relevant art will recognize that the appropriate stages of the methods described herein can be implemented at the wafer level or the die level. Therefore, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or an individualized die-level substrate. Further, unless the context indicates otherwise, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0006] Some semiconductor device assemblies include structures configured to assist in extracting heat from one or more semiconductor devices within the assembly. These structures are often formed from metals having high thermal conductivity, such as copper, silver, aluminum, or alloys thereof. Since the coefficient of thermal expansion (CTE) of these metals can be significantly different from the CTE of the semiconductor devices within the assembly, delamination, cracking, or other types of mechanical damage due to thermal cycling can pose challenges to these assemblies. Further, the manufacturing techniques used to form the structures from these metals and to shape them to accommodate additional devices within the assembly require machine tools that are different from those used in most other assembly processes, and the cost of the assemblies into which they are incorporated can increase significantly.

[0007] To address these and other drawbacks, various embodiments of the present application provide semiconductor device assemblies in which a monolithic silicon structure for heat dissipation is provided between the surface of the lower die of a multi-die structure and the outer (e.g., upper) surface of the assembly. The monolithic silicon structure may include a cavity that extends partially or completely therethrough, and additional semiconductor devices (e.g., dies, die stacks, packages, assemblies, etc.) may be provided within the cavity. The additional semiconductor devices may be electrically coupled to the same surface of the lower die to which the monolithic silicon structure is attached (e.g., by oxide-oxide bonding, hybrid bonding, adhesives, or interconnects, etc.). The monolithic silicon structure provides improved thermal management without the risk of damage associated with other thermal management structures due to its high thermal conductivity and the close match of its coefficient of thermal expansion to that of the lower die.

[0008] FIG. 1 is a simplified schematic partial cross-sectional view of a monolithic silicon structure 100 according to an embodiment of the present disclosure. The monolithic silicon structure 100 includes one or more cavities (two are shown) that extend at least partway (e.g., into the body) through the thickness of the monolithic silicon structure 100. The structure 100 can be formed, for example, from a blank silicon wafer in which the cavities are formed (e.g., by masking and directional etching, laser ablation, etc.). The structure 100 can be maintained at the wafer level for subsequent wafer-level processing steps or can optionally be singulated prior to subsequent processing steps.

[0009] According to one aspect of the present disclosure, prior to incorporation into a larger semiconductor device assembly, semiconductor devices can be pre-mounted within the cavity of the monolithic silicon structure 100. FIG. 2 is a simplified schematic cross-sectional view of a monolithic silicon structure 100 with several semiconductor devices arranged according to an embodiment of the present disclosure. As can be seen with reference to FIG. 2, semiconductor devices 102 (e.g., individual dies, vertical stacks of interconnected dies, device packages, device assemblies, etc.) are disposed within the cavity of the monolithic silicon structure 100. Each semiconductor device 102 can be fixed within the corresponding cavity by an adhesive (e.g., a thermal interface material) between the back surface of the semiconductor device and the opposing inner surface of the cavity. The cavity can be sized such that a small gap 103 (optionally filled with, e.g., an adhesive, underfill, or encapsulant) continues to surround the semiconductor device 102 to facilitate the process of placing the semiconductor device 102 within the cavity. In other embodiments, the gap 103 can be minimized or even eliminated by carefully matching the outer dimensions of the semiconductor device 102 and the cavity. To facilitate incorporation of the semiconductor device 102 and the monolithic silicon structure 100 into a larger assembly, a redistribution layer 104 including one or more thermal pads 105 aligned with the monolithic silicon structure 100 (e.g., including copper, silver, aluminum, or other metals compatible with metal-metal bonding operations) and one or more interconnects 106 (e.g., pads, pillars, UBMs, pins, solder balls, etc.) operatively coupled to the semiconductor device 102 can be formed. In other embodiments, the redistribution layer can be omitted, and the semiconductor device 102 can be provided with interconnects (e.g., on the same plane as the bonding surface of the monolithic silicon structure 100) prior to mounting into the monolithic silicon structure 100.

[0010] Referring to FIG. 3, an implemented monolithic silicon structure 100 is shown aligned in preparation for bonding to another semiconductor device (e.g., the aforementioned lower semiconductor device within an assembly) according to one embodiment of the present disclosure. The lower semiconductor device 110 includes a dielectric layer 109 in which electrical contacts 107 and thermal contacts 108 are disposed. The implemented monolithic silicon structure 100 can be bonded to the lower semiconductor device 110 such that a thermal pad 105 is coupled to the thermal contact 107 and an interconnect 106 is coupled to the electrical contact 108 to form a semiconductor device assembly 400 as illustrated according to one embodiment of the disclosure of FIG. 4. The bonding operation can be a hybrid bonding operation, in which a dielectric-dielectric bond (e.g., an oxide-oxide bond) is formed between the dielectric of the redistribution layer 104 and the dielectric layer 109 formed over the lower semiconductor device 110, and metal-metal bonds are formed between corresponding ones of the thermal pad 105 and the thermal contact 107 and between corresponding ones of the interconnect 106 and the electrical contact 108.

[0011] In the foregoing exemplary embodiment, the semiconductor device assembly 400 has been described as being formed through a hybrid bonding operation. However, in other embodiments, the bonding between the implemented monolithic silicon structure and the lower semiconductor device can be achieved using an adhesive layer (e.g., a thermal interface material (TIM)), solder interconnects with or without underfill, or any other bonding method well known to those skilled in the art.

[0012] According to an additional aspect of the present disclosure, the semiconductor device assembly 400 may optionally undergo further processing to remove a portion of the monolithic silicon structure 100 that is over the cavity in which the semiconductor device 102 is disposed, in order to reduce the height of the assembly and / or to provide additional connectivity options. In this regard, FIG. 5 is a simplified schematic cross-sectional view of a semiconductor device assembly 500, in which the assembly as shown in FIG. 4 has undergone a backside thinning operation (e.g., by chemical mechanical polishing (CMP), grinding, etc.) to expose the backside of the semiconductor device 102 and to reduce the overall height of the assembly 500 by removing a portion of the material from the monolithic silicon structure 100.

[0013] In embodiments where the semiconductor device 102 includes backside contacts for additional connectivity, removing a portion of the material from the monolithic silicon structure 100 that covers the backside of the semiconductor device 102 may enable additional devices to be incorporated into the semiconductor device assembly. One such configuration is shown in FIG. 6, which shows a simplified schematic cross-sectional view of a semiconductor device assembly 600. As can be seen with reference to FIG. 6, the assembly as shown in FIG. 5 has an additional semiconductor device 111 (e.g., an individual die, a vertical stack of interconnected dies, a device package, a device assembly, etc.) connected to the exposed backside contacts of the semiconductor device 102 (e.g., through conventional flip-chip interconnects, ball grid arrays, hybrid bonding, etc.). The additional semiconductor device 111 may then be encapsulated by a layer 112 of molding material to provide mechanical protection therefor.

[0014] Alternatively, rather than individually connecting additional semiconductor devices to the exposed back contacts of semiconductor device 102, in another embodiment, one or more additional pre-mounted monolithic silicon structures (e.g., such as those shown in FIG. 2) may be joined to the semiconductor assembly 500 shown in FIG. 5 in order to provide an assembly with high-density devices while maintaining good thermal performance. One such assembly is shown in FIG. 7, which shows a simplified schematic cross-sectional view of a semiconductor device assembly 700, in which the assembly as shown in FIG. 5 has an additional monolithic silicon structure 113 on which the bonded semiconductor devices are mounted.

[0015] As will be readily understood by those skilled in the art, in accordance with one aspect of the present disclosure, the processes shown in FIGS. 5 and 7 may be iteratively repeated such that an additional pre-mounted monolithic silicon structure itself may undergo another backside thinning operation to expose the back contacts of the semiconductor devices therein for joining to yet another pre-mounted monolithic silicon structure.

[0016] Instead of, or in addition to, a backside thinning operation that completely removes the material of the monolithic silicon structure covering the backside of the semiconductor device implemented within the cavity, in another embodiment, the material of the monolithic silicon structure covering the backside of the semiconductor device implemented within the cavity need only be thinned enough to enable the formation of vias (e.g., through-silicon vias (TSVs)) through the thinned material for connection to the backside contacts of the semiconductor device. This can be more readily understood with reference to FIG. 8, which shows an assembly such as that of FIG. 4 that has undergone a backside thinning operation to remove a portion of the material covering the backside of the semiconductor device within the cavity and has further undergone a TSV formation operation (e.g., forming an opening through the silicon material, passivating the opening, removing a passivation portion from the bottom of the opening to expose the backside contact, plating a conductor in the opening, etc.) to provide TSVs 114 that extend through the thinned material to contact the backside contacts of the semiconductor device to facilitate further connectivity.

[0017] Referring to FIG. 9, a simplified schematic cross-sectional view of a semiconductor device assembly 900 is shown, in which the assembly as shown in FIG. 8 has an additional semiconductor device 111 (e.g., an individual die, a vertical stack of interconnected dies, a device package, a device assembly, etc.) connected to TSVs 114 that extend through the monolithic silicon structure 100 to the semiconductor device 102 (e.g., through conventional flip-chip interconnects, ball grid arrays, hybrid bonds, etc.). The additional semiconductor device 111 can be encapsulated by a layer 112 of molding material to provide mechanical protection thereto, as described in more detail above with reference to FIG. 6.

[0018] Alternatively, rather than individually connecting additional semiconductor devices to TSV 114 as shown in FIG. 9, in another embodiment, one or more additional pre-mounted monolithic silicon structures (e.g., such as those shown in FIG. 2) may be joined to the semiconductor assembly shown in FIG. 8 to provide an assembly with high-density devices while maintaining good thermal performance. One such assembly is shown in FIG. 10, which shows a simplified schematic cross-sectional view of a semiconductor device assembly 100, in which the assembly as shown in FIG. 8 has an additional monolithic silicon structure 113 on which bonded semiconductor devices are mounted.

[0019] As described above, the monolithic silicon structure can be fabricated from a blank silicon wafer via conventional etching techniques for forming openings or cavities in silicon. Alternatively or additionally, methods for fabricating the monolithic silicon structure may include highly controllable and high-speed etching processes, as will be described in further detail below, according to various embodiments of the present disclosure.

[0020] Referring to FIG. 11, a simplified partial cross-sectional view of a precursor structure in which a monolithic silicon structure is to be formed in one step of a formation process according to an embodiment of the present disclosure is shown. The precursor structure includes a silicon wafer 1100, on which a passivation layer 1101 (e.g., a dielectric material) is formed, and one or more thermal pads 1102 are formed within the silicon wafer 1100. A mask layer 1103 is formed over the passivation layer 1101 in a pattern corresponding to cavities to be formed within the silicon wafer 1100. More specifically, the mask layer 1103 includes a pattern of small openings (e.g., corresponding to narrow columnar or fin-like structures) that are over regions within the silicon wafer 1100 where the cavities are to be formed. As can be seen by referring to FIG. 12, the small openings 1104 can be etched at least partially into the thickness of the silicon wafer 1100 to remove some of the material from where the cavities are to be formed. The advantage of etching less material from the cavities rather than the entire cavity is that the directional etching operation can be completed more quickly than if the mask openings corresponded to the full size of the final cavity openings. After anisotropically etching these “slivers” of material from the silicon wafer 1100, a subsequent isotropic (e.g., wet) etching operation can be performed to remove the remaining material from the silicon wafer 1100 where the cavities are to be formed. The result of such an operation is shown in FIG. 13, which shows a cavity 1105 formed by this two-step anisotropic and isotropic etching process according to an embodiment of the present disclosure. After removing the residue of the mask layer 1103 (e.g., via chemical and / or mechanical removal processes), as shown in FIG. 14, the monolithic silicon structure 1400 with the thermal pads 1102 and the cavity 1105 is ready to undergo the process described previously in more detail above with reference to FIGS. 2-10.

[0021] Before attaching the monolithic silicon structure to the lower semiconductor device in the assembly, instead of pre-mounting the semiconductor device on the monolithic silicon structure as shown in FIG. 1 or FIG. 14, some embodiments of the present disclosure involve attaching the monolithic silicon structure to the semiconductor device, thinning the back side of the monolithic silicon structure to expose a cavity within the monolithic silicon structure, and then placing the semiconductor device inside the cavity. Such an approach for forming a semiconductor device assembly is shown at various stages of the process of FIGS. 15 - 20 in accordance with various embodiments of the present disclosure.

[0022] Referring to FIG. 15, in accordance with one aspect of the disclosure, the monolithic silicon structure 1400 of FIG. 14 after being bonded to the lower semiconductor device 1401 is shown. In this regard, the monolithic silicon structure 1400 is bonded to the lower semiconductor device 1401 such that the thermal pad 1102 is coupled to the thermal contact 1402 of the lower semiconductor device 1401. The bonding operation can be a hybrid bonding operation, in which a dielectric-dielectric bond (e.g., oxide-oxide bond) is formed between the dielectric 1101 of the monolithic silicon structure and a dielectric layer 1403 formed over the lower semiconductor device 1401, and a metal-metal bond is formed between corresponding ones of the thermal pads 1102.

[0023] After the monolithic silicon structure 1400 is bonded to the lower semiconductor device 1401, as shown in FIG. 16, a backside thinning process (e.g., by chemical mechanical polishing (CMP), grinding, etc.) may be performed to remove a portion of the material from the monolithic silicon structure 1400 to expose the cavity 1105. When the cavity 1105 is thus opened, a semiconductor device (e.g., individual dies, a vertical stack of interconnected dies, a device package, a device assembly, etc.) 1701 may be disposed within the cavity 1105, and an encapsulant (e.g., a molding material) 1702 may be disposed above the semiconductor device 1701 (and optionally, around it depending on the relative sizes of the semiconductor device 1701 and the cavity 1105) to produce a semiconductor device assembly, as shown in FIG. 17. Subsequent processing steps (e.g., singulating, thinning the assembly 1700 from the wafer level or panel level, and providing external connections to the lower semiconductor device 1401, etc.) may be performed at this point (not described for the sake of clarity of the disclosure).

[0024] Alternatively, the semiconductor device assembly 1700 may undergo additional processing operations to remove the portion above the encapsulation material 1702 and expose the back surface of the semiconductor device 1701, similar to the process described above with reference to FIGS. 4 and 5, to thin the assembly 1700 and / or prepare the assembly for additional connectivity. In this regard, FIG. 18 is a simplified schematic cross-sectional view of a semiconductor device assembly 1800, in which the assembly as shown in FIG. 17 undergoes a backside thinning process (e.g., by chemical mechanical polishing (CMP), grinding, etc.) to expose (and optionally planarize) the back surface of the semiconductor device 1701 and to reduce the overall height of the assembly 1800 by removing the portion above the encapsulant 1702.

[0025] In embodiments where the semiconductor device 1701 includes backside contacts for further connectivity, by removing a portion of the material from the encapsulant 1702 that covers the backside of the semiconductor device 1701, additional devices may be incorporated into the semiconductor device assembly as described in more detail above with respect to FIGS. 6 and 7. In this regard, the additional semiconductor device may be attached directly to the exposed backside contacts of the semiconductor device 1701 and may then be encapsulated (e.g., similar to the configuration shown in FIG. 6) by a layer of molding material. Alternatively, rather than connecting the additional semiconductor device individually to the exposed backside contacts of the semiconductor device 1701, in another embodiment, one or more additional pre-mounted monolithic silicon structures (e.g., such as those shown in FIG. 2) may be bonded to the semiconductor assembly 1800 shown in FIG. 18 to provide an assembly with high-density devices while maintaining good thermal performance. In yet another embodiment, to provide an assembly with high-density devices while maintaining good thermal performance, the process shown up to FIG. 18 for the assembly 1800 of FIG. 18 (e.g., placing another monolithic silicon structure 1400 above the assembly 1800, thinning the monolithic silicon structure 1400 to open the cavity 1105 within the monolithic silicon structure 1400, placing an additional semiconductor device within the exposed cavity, encapsulating with molding material, and optionally thinning the overlying molding material) may be repeatedly performed on the assembly 1800 of FIG. 18. As will be readily understood by those skilled in the art, the foregoing processes may be combined, adapted, and repeatedly iterated such that additional tiers of semiconductor devices may be provided until the desired device density is achieved.

[0026] The semiconductor device assembly is shown as being formed above a lower semiconductor device 1401 that has not yet been thinned or that does not have a back contact provided thereon (e.g., on its lower surface in the orientation shown). FIG. 19 illustrates a process according to one aspect of the present disclosure in which the lower semiconductor device 1401 can be thinned and TSVs and back contacts can be provided. As can be seen with reference to FIG. 19, the semiconductor device assembly 1800 is bonded to a temporary carrier wafer 1901 by an adhesive layer 1902 disposed above the exposed back surface of the monolithic silicon structure 1400 and the semiconductor device 1701. While being mechanically supported by the carrier wafer 1901, the back surface of the lower semiconductor device 1401 can be thinned (e.g., by CMP, grinding, etc.) in order to reduce the overall height of the assembly and to enable the formation of TSVs 1903 through the remaining thickness of the lower semiconductor device 1401. Back contacts such as contacts carrying solder balls 1904 (e.g., pads, pillars, under bump metallization (UBM), etc.) can be formed using any one of a number of methods known to those skilled in the art. In another embodiment, rather than forming vias 1904 after thinning the lower semiconductor device 1401, the embedded TSVs already formed within the lower semiconductor device 1401 at an earlier stage of the process can simply be exposed by the thinning operation shown in FIG. 19. Once thinning and contact formation are complete, the temporary carrier wafer 1901 and the adhesive 1902 can be removed, resulting in the completed semiconductor device assembly 2000 as shown in FIG. 20.

[0027] Although the silicon material of the aforementioned monolithic silicon structure enjoys high thermal conductivity, depending on the situation, it may be advantageous to include copper, silver, aluminum, or other highly thermally conductive metals in some regions of the monolithic silicon structure in order to further enhance its thermal management capabilities while minimizing the CTE difference between the structures and the semiconductor device within the assembly. In this regard, FIGS. 21-26 illustrate the manufacture and incorporation of an embodiment of a monolithic silicon structure including a metallic heat extraction structure.

[0028] Referring to FIG. 21, there is shown a simplified partial cross-sectional view of a precursor structure in which a monolithic silicon structure is to be formed in one step of a formation process according to an embodiment of the present disclosure. The precursor structure includes a silicon wafer 2100 having a passivation layer 2101 (e.g., a dielectric material) formed thereon, in which one or more thermal pads (not shown) may optionally be formed. A mask layer 2102 is formed above the passivation layer 2101 with a pattern corresponding to both the cavity formed in the silicon wafer 2100 and the metal heat extraction structure. More specifically, the mask layer 2102 includes a pattern of small openings (e.g., corresponding to narrow columnar or fin-like structures) that are over both the region in the silicon wafer 2100 where the cavity is to be formed and the region in the silicon wafer 2100 where the metal heat extraction structure is to be formed.

[0029] As can be seen by referring to FIG. 22, the small openings 2103 can be etched at least partially into the thickness of the silicon wafer 2100 to remove some of the material from where the cavity is to be formed and to create an opening in which the metal heat extraction structure can be plated. After anisotropically etching these "slivers" of material from the silicon wafer 2100, a plating operation can then be formed to fill the small openings 2103 with a metal structure in both the region where the cavity is to be formed and the region where the metal heat extraction structure 2105 is to be left. The excess metal material can be removed (e.g., by a CMP operation, a grinding operation, a wet etching operation, etc.), another mask structure 2106 can be disposed above the silicon wafer 2100, and the opening exposes the metal material in the region where the cavity is to be formed but does not expose the metal heat extraction structure 2105.

[0030] To remove the metal structure and the remaining silicon material from the silicon wafer 2100 in which the cavity is formed, a subsequent isotropic (e.g., wet) etching operation can be performed. The result of such an operation is shown in FIG. 25, which shows the cavity 2107 and the metal heat extraction structure 2105 formed by this process according to an embodiment of the present disclosure. After removing the residue of the mask layer 2106 (e.g., via chemical and / or mechanical removal processes), the monolithic silicon structure 2500 including the metal heat extraction structure 2105 and the cavity 2107 is ready to undergo the processes described in more detail above with reference to FIGS. 2-10 and / or FIGS. 15-20. In this regard, FIG. 26 shows a simplified schematic cross-sectional view of a semiconductor device assembly 2600 according to an embodiment of the present disclosure. The assembly 2600 includes a monolithic silicon structure 2500 in which a metal heat extraction structure 2105 for extracting heat from the lower semiconductor device 2602 (e.g., through contact with a heat contact within the lower semiconductor device 2602) is disposed. The assembly 2600 further includes one or more semiconductor devices (two are shown) coupled to the lower semiconductor device 2602 within the cavity of the monolithic silicon structure.

[0031] As will be readily understood by those skilled in the art, the foregoing examples have been described using a partial cross-sectional view in which a single lower semiconductor device is joined to a single monolithic structure. However, embodiments of the present disclosure contemplate wafer-level processing in which an un-fragmented wafer including a plurality of lower semiconductor devices is joined to a wafer-level monolithic silicon structure to provide an intermediate structure at the wafer level in which individual assemblies can be fragmented. Alternatively, in another embodiment, the fragmented monolithic silicon structures can be individually joined to an un-fragmented wafer including a plurality of lower semiconductor devices. In yet another embodiment, the fragmented monolithic silicon structures can be individually joined to fragmented lower semiconductor devices.

[0032] In the foregoing exemplary embodiments, the monolithic silicon structure has been illustrated and described as including a thermal pad or a metal heat extraction structure that contacts a corresponding thermal contact on a lower semiconductor device. However, in other embodiments, these mechanisms may be omitted, and the monolithic silicon structure may be bonded directly to the surface of the lower semiconductor device without any intervening intermediate metal structure.

[0033] In the foregoing exemplary embodiments, the monolithic silicon structure has been illustrated and described as including two cavities of the same depth and planar area that each contain a similarly sized semiconductor device therein. However, those skilled in the art will readily understand that the number of cavities is not limited to this, and monolithic silicon structures in other embodiments may have more or fewer cavities, cavities of different planar areas and / or depths, to accommodate semiconductor devices (or other electrical components including passive circuit components) of different sizes and shapes.

[0034] Furthermore, in the foregoing exemplary embodiments, the monolithic silicon structure has been illustrated and described as being disposed above a lower semiconductor die having the same planar area as the monolithic silicon structure. However, those skilled in the art will readily understand that the monolithic silicon structure may be used in other configurations (e.g., bonding to multiple lower dies, bonding to a device substrate, etc.) and need not have the same planar area as the device on which it is mounted.

[0035] According to one aspect of the present disclosure, the semiconductor device assembly illustrated and described above may include a memory die such as a dynamic random access memory (DRAM) die, a negative logic product (NAND) memory die, a negative logic sum (NOR) memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, or a static random access memory (SRAM) die. In embodiments where multiple dies are provided within a single assembly, the semiconductor device may be the same type of memory die (e.g., both NAND, both DRAM, etc.) or different types of memory dies (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly illustrated and described above may include a logic die (e.g., a controller die, a processor die, etc.), or a mixture of a logic die and a memory die (e.g., a memory controller die and the memory die controlled thereby).

[0036] Any one of the semiconductor devices and semiconductor device assemblies described above can be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is system 2700 schematically shown in FIG. 27. System 2700 can include a semiconductor device assembly (e.g., or an individual semiconductor device) 2702, a power supply 2704, a driver 2706, a processor 2708, and / or other subsystems or components 2710. The semiconductor device assembly 2702 can include a mechanism substantially similar to the mechanism of the semiconductor devices described above. The resulting system 2700 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 2700 can include, without limitation, handheld devices (e.g., cellular phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. The components of system 2700 can be housed within a single unit or distributed among multiple interconnected units (e.g., via a communication network). The components of system 2700 can also include remote devices and any of a variety of computer-readable media.

[0037] The devices discussed herein that include memory devices can be formed on a semiconductor substrate or die such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled through doping using various species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0038] The functions described in this specification may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and the appended claims. The mechanisms implementing the functions may be physically located in various positions, including being distributed such that parts of the functions are implemented in different physical locations.

[0039] As used herein, including in the claims, "or" as used in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of") refers to an inclusive list. For example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" would be construed in the same manner as the phrase "based on at least in part."

[0040] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative direction or position of mechanisms within a semiconductor device taking into account the orientation shown in the figures. For example, "upper" or "uppermost" may refer to a mechanism positioned closer to the top of the page than another mechanism. However, these terms should be construed broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations where top / bottom, above / below, up / down, and left / right are interchanged depending on the orientation.

[0041] It should be noted that the methods described above illustrate possible implementations, that operations and steps may be rearranged or modified, and that other implementations are possible. Further, embodiments from two or more of the methods may be combined.

[0042] From the foregoing, while particular embodiments of the invention have been described herein for purposes of illustration, it will be appreciated that various modifications may be made without departing from the scope of the invention. Rather, in the foregoing description, numerous specific details have been set forth in order to provide a thorough and implementable description of embodiments of the technology. One of ordinary skill in the art, however, will recognize that the disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. In general, it should be understood that, in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may be within the scope of the technology.

Claims

1. a first semiconductor device including a plurality of electrical contacts on its upper surface; a monolithic silicon structure having a lower surface that contacts the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into the body of the monolithic silicon structure; a second semiconductor device disposed within the cavity and including a plurality of interconnects, each of the plurality of interconnects being operably coupled to a corresponding one of the plurality of electrical contacts; comprising; the upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region being covered by a first dielectric material and a plurality of thermal contacts; the lower surface of the monolithic silicon structure includes a second dielectric material and a plurality of thermal pads; the lower surface of the monolithic silicon structure is bonded to the upper surface of the first semiconductor device by a dielectric bond between the second dielectric material and the first dielectric material and a plurality of metal-metal bonds between the plurality of thermal contacts and the plurality of thermal pads, a semiconductor device assembly.

2. The monolithic silicon structure has a planar region corresponding in size and shape to the planar region of the first semiconductor device, the semiconductor device assembly according to claim 1.

3. The plurality of thermal contacts are in direct contact with the lower surface of the monolithic silicon structure, the semiconductor device assembly according to claim 1.

4. The plurality of thermal pads are each in direct contact with a corresponding one or more of the plurality of thermal contacts, the semiconductor device assembly according to claim 3.

5. The plurality of interconnects are a first plurality of interconnects, the cavity is a first cavity, the monolithic silicon structure includes a second cavity extending from the lower surface of the monolithic silicon structure into the body, and the semiconductor device assembly further includes a third semiconductor device disposed within the second cavity and including a second plurality of interconnects, each of the second plurality of interconnects being operably coupled to a corresponding one of the plurality of electrical contacts, the semiconductor device assembly according to claim 1.

6. The semiconductor device assembly according to claim 1, wherein the second semiconductor device includes a vertical stack of electrically coupled memory devices.

7. The semiconductor device assembly according to claim 1, wherein one or more of the upper surface of the first semiconductor device and the lower surface of the monolithic silicon structure include a redistribution layer.

8. A first semiconductor device including an upper surface, A monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into the body of the monolithic silicon structure, A second semiconductor device directly coupled to the first semiconductor device and disposed within the cavity such that the back surface and a plurality of sidewalls of the second semiconductor device are completely surrounded within the cavity comprising The upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region being covered by a first dielectric material and a plurality of thermal contacts, The lower surface of the monolithic silicon structure includes a second dielectric material and a plurality of thermal pads, The lower surface of the monolithic silicon structure is joined to the upper surface of the first semiconductor device by a dielectric bond between the second dielectric material and the first dielectric material and a plurality of metal-metal bonds between the plurality of thermal contacts and the plurality of thermal pads, a semiconductor device assembly.

9. The semiconductor device assembly according to claim 8, wherein the cavity is sized such that a gap separates each of the plurality of sidewalls from the inner surface of the cavity.

10. The dielectric bond between the second dielectric material and the first dielectric material is an oxide-oxide bond, the semiconductor device assembly according to claim 8.

11. The back surface of the second semiconductor device is adhered to the inner surface of the cavity, the semiconductor device assembly according to claim 8.

12. The semiconductor device assembly according to claim 8, wherein the second semiconductor device has a bonding surface that is coplanar with the lower surface of the monolithic silicon structure.

13. The semiconductor device assembly according to claim 8, wherein the monolithic silicon structure includes a plurality of outer surfaces that are coplanar with the outer surface of the first semiconductor device.

14. a first semiconductor device including an upper surface; a second semiconductor device directly supported by the upper surface of the first semiconductor device; a monolithic silicon structure having a lower surface that contacts the upper surface of the first semiconductor device, the lower surface extending into a body of the monolithic silicon structure and including a cavity that surrounds the second semiconductor device; comprising; the upper surface of the first semiconductor device includes a region corresponding in shape and size to the lower surface of the monolithic silicon structure, the region being covered by a first dielectric material and a plurality of thermal contacts; the lower surface of the monolithic silicon structure includes a second dielectric material and a plurality of thermal pads; the lower surface of the monolithic silicon structure is bonded to the upper surface of the first semiconductor device by a dielectric bond between the second dielectric material and the first dielectric material and a plurality of metal-metal bonds between the plurality of thermal contacts and the plurality of thermal pads, a semiconductor device assembly.

15. The semiconductor device assembly according to claim 14, wherein the monolithic silicon structure has a planar region corresponding in size and shape to a planar region of the first semiconductor device.

16. The semiconductor device assembly according to claim 14, wherein the second semiconductor device has a bonding surface that is in the same plane as the lower surface of the monolithic silicon structure.

17. The semiconductor device assembly according to claim 14, wherein the dielectric bond between the second dielectric material and the first dielectric material is an oxide-oxide bond.

18. The semiconductor device assembly according to claim 14, wherein the cavity is sized such that a gap separates each of a plurality of sidewalls of the second semiconductor device from an inner surface of the cavity.

Images