Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device which reduces contact resistance and enhances stability of electric characteristics.SOLUTION: The method includes: sequentially forming an electron transit layer 14 on a substrate 10, an electron supply layer 16 thereon, a protective film 22 thereon, a zinc oxide film 72 thereon, and a sacrificial film 74 thereon; forming a first opening 33 and a second opening 43 in the sacrificial film and the zinc oxide film, and a third opening 30 which continues to the first opening and a fourth opening 40 which continues to the second opening, in the protective film, the electron supply layer and the electron transit layer, respectively; forming a first cavity portion 34 on a first portion which is exposed to the first opening of the zinc oxide film, and a second cavity portion 44 on a second portion which is exposed to the second opening of the zinc oxide film, by an acid treatment which uses a weakly acidic solution, respectively; after the acid treatment, forming a source region which contains a first conductivity type of impurity on a bottom face 30B of the third opening, and a drain region which contains the first conductivity type of impurity on a bottom face 40B of the fourth opening, respectively; and after the step of forming the regions, removing the zinc oxide film.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] A method has been proposed for reducing the contact resistance, which indicates the total resistance component between the source electrode and the drain electrode and the two-dimensional electron gas (2DEG), in a high electron mobility transistor (HEMT). In this method, openings are formed in the electron supply layer and the electron transport layer, and a GaN (n + GaN) layer is regrown and n + The source and drain electrodes are formed on the GaN layer (regrowth layer). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-125600 A [Patent Document 2] U.S. Patent No. 9,515,161 Summary of the Invention [Problem to be solved by the invention]

[0004] When semiconductor devices are manufactured using conventional methods, it is sometimes difficult to stabilize the electrical characteristics.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can improve the stability of electrical characteristics while suppressing contact resistance. [Means for solving the problem]

[0006] a third opening connected to the first opening and a fourth opening connected to the second opening in the protective film, the electron supply layer, and the electron transit layer; forming a first void in a first portion of the zinc oxide film exposed in the first opening and a second void in a second portion of the zinc oxide film exposed in the second opening by an acid treatment using a weak acid solution; forming, after the acid treatment, a source region containing impurities of a first conductivity type on a bottom surface of the third opening and a drain region containing impurities of the first conductivity type on a bottom surface of the fourth opening; and removing the zinc oxide film after the steps of forming the source region and the drain region. [Effects of the Invention]

[0007] According to the present disclosure, the stability of electrical characteristics can be improved while suppressing contact resistance. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6]FIG. 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes forming an electron transit layer above a substrate, forming an electron supply layer above the electron transit layer, forming a protective film above the electron transit layer, forming a zinc oxide film on the protective film, forming a sacrificial film on the zinc oxide film, forming a first opening and a second opening in the sacrificial film and the zinc oxide film, and forming a third opening connected to the first opening and a fourth opening connected to the second opening in the protective film, the electron supply layer, and the electron transit layer. a step of forming a first void portion in a first portion of the zinc oxide film exposed to the first opening and a second void portion in a second portion of the zinc oxide film exposed to the second opening by an acid treatment using a weak acid solution; after the acid treatment, a step of forming a source region containing impurities of a first conductivity type on a bottom surface of the third opening and a drain region containing impurities of the first conductivity type on a bottom surface of the fourth opening; and a step of removing the zinc oxide film after the step of forming the source region and the drain region.

[0011] Since the source and drain regions are formed separately from the electron transit layer and electron supply layer, contact resistance can be reduced. Furthermore, since a weakly acidic solution is used for the acid treatment, the size of the first and second voids can be easily controlled. Therefore, the source and drain regions can be formed with high precision, improving the stability of electrical characteristics.

[0012] [2] In [1], the pH of the weakly acidic solution may be equal to or higher than 3.0 and lower than 7.0. If the pH of the weakly acidic solution is too low, it may be difficult to control the size of the first void portion and the second void portion.

[0013] [3] In [1], the pH of the weakly acidic solution may be 6.86. In this case, particularly excellent stability in the solubility of the ZnO film in the weakly acidic solution can be obtained.

[0014] [4] In the above items [1] to [3], the weak acid solution may contain phosphoric acid, in which case the pH is less likely to change even as etching of the ZnO film progresses.

[0015] [5] In any of [1] to [4], the formation of the third opening and the fourth opening may be performed before the acid treatment. In this case, the formation of the first opening and the second opening and the formation of the third opening and the fourth opening can be performed consecutively in one processing chamber.

[0016] [6] In any of [1] to [4], the step of forming the third opening and the fourth opening may be performed before the formation of the third opening and the fourth opening. In this case, the electron supply layer and the electron transit layer are not exposed to the weak acid solution, and therefore, adhesion of substances contained in the weak acid solution to the electron supply layer and the electron transit layer can be suppressed.

[0017] [7] In [6], the weakly acidic solution may contain sodium hydroxide, which makes it easier to adjust the pH of the weakly acidic solution.

[0018] [8] In any of [1] to [7], a silicon nitride film may be formed as the protective film, which makes it easier to ensure a large etching selectivity between the zinc oxide film and the protective film.

[0019] [9] In any of [1] to [8], an aluminum oxide film or a silicon nitride film may be formed as the sacrificial film, which makes it easier to ensure a large etching selectivity between the zinc oxide film and the sacrificial film.

[0020]

[10] In any of [1] to [9], the concentration of the first conductivity type impurity in each of the source region and the drain region is 5×10 18 cm -3 Over 2×10 19 cm -3 In this case, the contact resistance can be easily reduced.

[0021] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0022] (First embodiment) A first embodiment will be described. The first embodiment relates to a method for manufacturing a semiconductor device including a GaN-HEMT whose main constituent material is a nitride semiconductor. Figures 1 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0023] First, as shown in FIG. 1 , a buffer layer 12, an electron transit layer 14, an electron supply layer 16, and a cap layer 18 are formed on a substrate 10. The substrate 10 is, for example, a silicon carbide (SiC) substrate whose upper surface has a (0001) plane orientation. The buffer layer 12 is, for example, an AlN layer having a thickness of 5 nm to 100 nm. The electron transit layer 14 is, for example, an undoped GaN layer having a thickness of approximately 1000 nm. The electron supply layer 16 is, for example, an n-type AlGaN layer having a thickness of approximately 20 nm. The cap layer 18 is, for example, an n-type GaN layer having a thickness of approximately 5 nm. The n-type impurity used in this embodiment is, for example, silicon (Si) or germanium (Ge). The stacking direction of the buffer layer 12, the electron transit layer 14, the electron supply layer 16, and the cap layer 18 is, for example, the

[0001] direction. The buffer layer 12, the electron transit layer 14, the electron supply layer 16, and the cap layer 18 are formed by, for example, an MOCVD method. The 2DEG 52 is present near the top surface of the electron transit layer 14 .

[0024] Next, as shown in FIG. 2, a protective film 22 is formed on the cap layer 18. The protective film 22 is, for example, a silicon nitride (SiN) film. The silicon nitride film can be formed by, for example, a CVD (chemical vapor deposition) method. Next, a zinc oxide (ZnO) film 72 is formed on the protective film 22. The ZnO film 72 can be formed by, for example, a sputtering method or a sol-gel method. Next, a sacrificial film 74 is formed on the ZnO film 72. The sacrificial film 74 is, for example, an aluminum oxide (Al2O3) film or a silicon nitride film. The aluminum oxide film can be formed by, for example, an atomic layer deposition (ALD) method, and the silicon nitride film can be formed by, for example, a CVD method.

[0025] Next, as shown in FIG. 3, a resist mask 80 is formed on the sacrificial film 74. The resist mask 80 has an opening 31 that exposes a portion of the sacrificial film 74 and an opening 41 that exposes another portion of the sacrificial film 74. The distance between the opening 31 and the opening 41 is, for example, about 1 μm to 200 μm. Next, a first opening 33 and a second opening 43 are formed in the sacrificial film 74 and the ZnO film 72 by reactive ion etching (RIE). A reactive gas containing fluorine (F) may be used to etch the sacrificial film 74. A reactive gas containing chlorine (Cl) may be used to etch the ZnO film 72.

[0026] Next, a third opening 30 and a fourth opening 40 are formed in the protective film 22, the cap layer 18, the electron supply layer 16, and the electron transit layer 14. The third opening 30 is connected to the first opening 33, and the fourth opening 40 is connected to the second opening 43. The third opening 30 has a bottom surface 30B, and the fourth opening 40 has a bottom surface 40B. A reactive gas containing fluorine (F) may be used to etch the protective film 22. A reactive gas containing chlorine (Cl) may be used to etch the cap layer 18, the electron supply layer 16, and the electron transit layer 14.

[0027] 4, the resist mask 80 is removed. The resist mask 80 can be removed using, for example, an organic solvent.

[0028] Next, as shown in FIG. 5 , a weak acid solution is used to perform an acid treatment to form first voids 34 in first portions of the ZnO film 72 exposed to the third openings 30, and second voids 44 in second portions of the ZnO film 72 exposed to the fourth openings 40. The acid treatment is performed for a time sufficient to reduce the sizes of the first voids 34 and the second voids 44 to approximately 500 nm to 1000 nm in the direction in which the third openings 30 and the fourth openings 40 are aligned. The weak acid solution may be, for example, a phosphate buffer solution with a pH of 6.86. The acid treatment forms overhanging portions on the sacrificial film 74 above the first voids 34 and the second voids 44.

[0029] Next, as shown in FIG. 6 , a semiconductor layer 60 is formed in the third opening 30 and the fourth opening 40 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. The semiconductor layer 60 is formed on the bottom surface 30B of the third opening 30 and on the bottom surface 40B of the fourth opening 40. The semiconductor layer 60 grows in the third opening 30 and the fourth opening 40 while lattice-matching to the electron transit layer 14. The semiconductor layer 60 is also formed on the sacrificial film 74. The semiconductor layer 60 may also be formed on the side surface of the sacrificial film 74 exposed in the first opening 33 and the side surface of the sacrificial film 74 exposed in the second opening 43. The semiconductor layer 60 in contact with the sacrificial film 74 is, for example, polycrystalline. The semiconductor layer 60 is, for example, an n-type GaN layer. The semiconductor layer 60 contains, for example, n-type impurities at a higher concentration than the electron supply layer 16. The concentration of n-type impurities in the semiconductor layer 60 is, for example, 5×10 18 cm -3 Over 2×10 19 cm -3 It is about the following.

[0030] When the semiconductor layer 60 is formed, the temperature of the substrate 10 is maintained at a temperature at which the semiconductor layer 60 can grow. The semiconductor layer 60 is grown while being doped with n-type impurities such as Si. When forming the semiconductor layer 60, it is preferable to continue to maintain the temperature of the substrate 10 at a temperature at which the n-type impurities doped into the semiconductor layer 60 remain dissolved in the semiconductor layer 60, for example, at about 700°C, until the formation of the semiconductor layer 60 is completed. By performing such temperature control, it is possible to suppress the generation of nitrogen compounds of the n-type impurities in the semiconductor layer 60.

[0031] Next, as shown in FIG. 7 , the ZnO film 72 is removed. The removal of the ZnO film 72 also removes the sacrificial film 74, and the removal of the sacrificial film 74 also removes the portion of the semiconductor layer 60 that was formed on the sacrificial film 74. Meanwhile, the portions of the semiconductor layer 60 within the third opening 30 and the fourth opening 40 are not removed, and the source region 32 is obtained within the third opening 30, and the drain region 42 is obtained within the fourth opening 40. The ZnO film 72 can be removed using, for example, a strong acid solution. For example, a hydrofluoric acid solution with a concentration of 5% by mass (wt%) can be used as the strong acid solution. The strong acid solution has a dissolving power 1,000 times or more greater than that of the weak acid solution used to form the first void 34 and the second void 44. Therefore, the ZnO film 72 can be removed in approximately 5 to 10 minutes.

[0032] Next, as shown in FIG. 8, a source electrode 38 is formed on the source region 32, and a drain electrode 48 is formed on the drain region 42. The source electrode 38 and the drain electrode 48 can be formed by, for example, evaporation, lift-off, and alloying heat treatment. The source electrode 38 and the drain electrode 48 include, for example, a Ta film and an Al film. The source electrode 38 and the drain electrode 48 make ohmic contact with the 2DEG 52 via the source region 32 and the drain region 42, respectively.

[0033] Next, as shown in FIG. 9 , a fifth opening 50 is formed in the protective film 22. To form the fifth opening 50, for example, RIE is performed using an electron beam resist (not shown) as a mask. A reactive gas containing F is used to etch the protective film 22. Next, a gate electrode 58 is formed on the protective film 22. The gate electrode 58 can be formed by, for example, vapor deposition and lift-off. The gate electrode 58 includes, for example, a Ni film and an Au film. The gate electrode 58 makes Schottky contact with the cap layer 18 through the fifth opening 50.

[0034] 10, an insulating film 24 is formed to cover the gate electrode 58, the source electrode 38, and the drain electrode 48. The insulating film 24 may be, for example, an aluminum oxide film or a silicon nitride film. The aluminum oxide film may be formed by, for example, the ALD method. The silicon nitride film may be formed by, for example, the plasma CVD method. Next, an opening 35 that exposes a portion of the source electrode 38 and an opening 45 that exposes a portion of the drain electrode 48 are formed in the insulating film 24. The openings 35 and 45 are formed by, for example, RIE using a resist mask (not shown).

[0035] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 100 including the GaN-HEMT can be manufactured.

[0036] In the first embodiment, the source region 32 and the drain region 42 are formed separately from the electron transit layer 14 and the electron supply layer 16, so that the contact resistance can be reduced.

[0037] Furthermore, because a weak acid solution is used for the acid treatment, the size of the first voids 34 and the second voids 44 can be easily controlled. For example, instead of a weak acid solution, a strong acid solution similar to that used to remove the ZnO film 72 can be used for the acid treatment. However, if a strong acid solution is used, etching of the ZnO film 72 proceeds rapidly, making it difficult to control the size of the first voids 34 and the second voids 44. It is also possible to reduce the dissolving power of the strong acid solution by diluting it. For example, if hydrochloric acid with a concentration of 360 ppm by mass (wtppm) is used, the size of the first voids 34 and the second voids 44 can be controlled by time control over a period of approximately 30 to 60 seconds. However, it is not easy to maintain the concentration of hydrochloric acid at a constant 360 ppm by mass (wtppm) even before use. Furthermore, the ion concentration in the hydrochloric acid supplied for the acid treatment easily changes as etching progresses, resulting in a significant change in dissolving power. For this reason, even if a low-concentration strong acid solution is used, it is difficult to control the size of the first voids 34 and the second voids 44.

[0038] In contrast, in the first embodiment, a weakly acidic solution is used, and therefore the change in dissolving power is small even as etching progresses. Therefore, it is easy to control the size of the first void portion 34 and the second void portion 44. For example, the size of the first void portion 34 and the second void portion 44 can be controlled based on the etching time.

[0039] Furthermore, since the sizes of the first void portion 34 and the second void portion 44 can be easily controlled, the source region 32 and the drain region 42 can be formed with high precision, and stable electrical characteristics can be obtained.

[0040] The pH of the weakly acidic solution is preferably 3.0 or more and less than 7.0, more preferably 6.0 or more and less than 7.0, and even more preferably 6.5 or more and less than 7.0. If the pH of the weakly acidic solution is too low, it may be difficult to control the size of the first voids 34 and the second voids 44. It is particularly preferable that the pH of the weakly acidic solution is 6.86, as this provides excellent stability of the dissolving power.

[0041] The weak acid solution preferably contains phosphoric acid, because the pH is less likely to change even as etching of the ZnO film 72 progresses. The weak acid solution may also contain citric acid, hydrobromic acid, or the like.

[0042] In the first embodiment, the formation of the third opening 30 and the fourth opening 40 (see FIG. 4) is performed before the acid treatment (FIG. 5). Therefore, the formation of the first opening 33 and the second opening 43 and the formation of the third opening 30 and the fourth opening 40 can be performed consecutively in one processing chamber while leaving the resist mask 80.

[0043] By forming a silicon nitride film as the protective film 22, it is easy to ensure a large etching selectivity between the ZnO film 72 and the protective film 22. Furthermore, by forming an aluminum oxide film as the sacrificial film 74, it is easy to ensure a large etching selectivity between the ZnO film 72 and the sacrificial film 74.

[0044] The concentration of n-type impurities in each of the source region 32 and the drain region 42 is, for example, 5×10 18 cm -3 Over 2×10 19 cm -3 less than or equal to 1×10 19 cm -3 Over 2×10 19 cm -3 This is because the contact resistance of the source electrode 38 and the drain electrode 48 can be easily reduced.

[0045] The impurity concentrations in the source region 32 and the drain region 42 can be measured by, for example, secondary ion mass spectrometry (SIMS).

[0046] The material of the source region 32 and the drain region 42 is not limited to GaN. The material of the semiconductor layer 60 may be AlGaN, AlN, InAlN, InAlGaN, or the like.

[0047] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the order of forming the third opening 30 and the fourth opening 40 and performing the acid treatment. Figures 11 to 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment.

[0048] First, in the same manner as in the first embodiment, the buffer layer 12, the electron transit layer 14, the electron supply layer 16, and the cap layer 18 are formed (see FIG. 1), and the protective film 22, the ZnO film 72, and the sacrificial film 74 are formed (see FIG. 2). Next, as shown in FIG. 11, a resist mask 80 is formed on the sacrificial film 74. The resist mask 80 has an opening 31 that exposes a portion of the sacrificial film 74 and an opening 41 that exposes another portion of the sacrificial film 74. The openings 31 and 41 can be formed by the same process as in the first embodiment.

[0049] 12, the resist mask 80 is removed without etching the protective film 22, etc. The resist mask 80 can be removed using, for example, an organic solvent.

[0050] 13, an acid treatment using a weak acid solution is performed to form a first void 34 in a first portion of the ZnO film 72 exposed to the third opening 30, and a second void 44 in a second portion of the ZnO film 72 exposed to the fourth opening 40. The acid treatment can be performed in the same manner as in the first embodiment.

[0051] 14, a third opening 30 and a fourth opening 40 are formed in the protective film 22, the cap layer 18, the electron supply layer 16, and the electron transit layer 14. The third opening 30 and the fourth opening 40 can be formed by the same process as in the first embodiment.

[0052] Thereafter, similarly to the first embodiment, the processes subsequent to the formation of the semiconductor layer 60 are carried out (see FIGS. 6 to 10). In this manner, a semiconductor device including a GaN-HEMT can be manufactured.

[0053] According to the second embodiment, as in the first embodiment, the contact resistance can be reduced and stable electrical characteristics can be obtained.

[0054] In the second embodiment, the acid treatment (FIG. 13) is performed before the formation of the third opening 30 and the fourth opening 40 (see FIG. 14). Therefore, the electron supply layer 16 and the electron transit layer 14 are not exposed to the weak acid solution. This prevents the attachment of substances (foreign matter) contained in the weak acid solution to the electron supply layer 16 and the electron transit layer 14. For example, the weak acid solution may contain sodium hydroxide (NaOH) for pH adjustment or the like. If Na adheres to the electron supply layer 16 and the electron transit layer 14, the electrical characteristics of the semiconductor device may fluctuate. According to this embodiment, such fluctuations in electrical characteristics due to the attachment of foreign matter can be prevented. The weak acid solution may contain ammonia for pH adjustment or the like.

[0055] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0056] 10: Circuit board 12: Buffer layer 14: Electron transit layer 16:Electron supply layer 18: Cap layer 22:Protective film 24: insulating film 30: Third opening 30B: Bottom 31, 35: Opening 32: Source area 33: First opening 34:First cavity 38: Source electrode 40: 4th opening 40B: Bottom 41, 45: Opening 42: Drain region 43: Second opening 44:Second cavity 48: Drain electrode 50: 5th opening 58: Gate electrode 60: Semiconductor layer 72:ZnO film 74: Sacrificial membrane 80: Resist mask 100: Semiconductor device

Claims

1. forming an electron transit layer above the substrate; forming an electron supply layer above the electron transit layer; forming a protective film above the electron transit layer; forming a zinc oxide film on the protective film; forming a sacrificial film on the zinc oxide film; forming a first opening and a second opening in the sacrificial film and the zinc oxide film; forming a third opening connected to the first opening and a fourth opening connected to the second opening in the protective film, the electron supply layer, and the electron transit layer; forming a first void portion in a first portion of the zinc oxide film exposed to the first opening and a second void portion in a second portion of the zinc oxide film exposed to the second opening by an acid treatment using a weak acid solution; forming, after the acid treatment, a source region containing impurities of the first conductivity type on a bottom surface of the third opening and a drain region containing impurities of the first conductivity type on a bottom surface of the fourth opening; removing the zinc oxide film after the step of forming the source region and the drain region; A method for manufacturing a semiconductor device having the above structure.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the pH of the weakly acidic solution is equal to or greater than 3.0 and less than 7.

0.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the weakly acidic solution has a pH of 6.

86.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the weak acid solution contains phosphoric acid.

5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the third opening and the fourth opening are formed before the acid treatment.

6. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the acid treatment is performed before the third opening and the fourth opening are formed.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the weak acid solution contains sodium hydroxide.

8. 8. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon nitride film is formed as the protective film.

9. 9. The method for manufacturing a semiconductor device according to claim 1, wherein an aluminum oxide film or a silicon nitride film is formed as the sacrificial film.

10. The concentration of the impurity of the first conductivity type in each of the source region and the drain region is 5×10 １８ cm －３ 2 x 10 or more １９ cm －３ 10. The method for manufacturing a semiconductor device according to claim 1, wherein:

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