Class D amplifier circuit

Abstract

To suppress overshoot or undershoot generated during a dead time period when driving a load including an inductance.SOLUTION: A class D amplifier circuit comprises a high-side N-channel DMOS power transistor, a low-side N-channel DMOS power transistor, a high-side gate drive circuit, and a low-side gate drive circuit, and further comprises a high-side dead time cancel circuit or a low-side dead time cancel circuit. The high-side dead time cancel circuit cancels a dead time in a case where a potential difference between an output power supply terminal and an output terminal becomes small in a state where an input signal is high. The low-side dead time cancel circuit cancels the dead time in a case where a potential difference between a ground terminal and the output terminal is small in a state where the input signal is low.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a class D amplifier circuit. [Background technology]

[0002] Due to their high power efficiency, Class D amplifier circuits are used in a variety of applications, such as portable music players, and amplify input signals (PWM modulated audio signals) using Class D amplification. The output signal amplified by a Class D amplifier circuit has low impedance and is output from the output terminal to a load circuit such as a speaker.

[0003] FIG. 4 is a circuit diagram showing a conventional class-D amplifier circuit 101", and FIG. 5 is a time chart showing an example of operation of the class-D amplifier circuit 101" in FIG. 4. The class-D amplifier circuit 101" includes a high-side gate drive circuit 102" and a low-side gate drive circuit 103". The high-side gate drive circuit 102" generates a predetermined dead time DTH-1 in the dead time generation circuit X104H when the input signal Vin goes high, turning on the high-side N-channel DMOS power transistor M101H, and turns off the high-side N-channel DMOS power transistor M101H when the input signal Vin goes low. The low-side gate drive circuit 103" generates a predetermined dead time DTL-1 in the dead time generation circuit X104L when the input signal Vin goes low, turning on the low-side N-channel DMOS power transistor M101L, and turns off the low-side N-channel DMOS power transistor M101L when the input signal Vin goes high.

[0004] In the class-D amplifier circuit 101'', the high-side gate drive circuit 102'' and the low-side gate drive circuit 103'' operate in this manner, so that the high-side N-channel DMOS power transistor M101H and the low-side N-channel DMOS power transistor M101L are not turned on at the same time. This prevents current consumption due to a large through current flowing through the high-side N-channel DMOS power transistor M101H and the low-side N-channel DMOS power transistor M101L, and prevents element damage due to the large current.

[0005] In addition, in FIG. 4, the class D amplifier circuit 101'' is further configured to include an output power supply V101, a high-side gate drive circuit power supply V102, a low-side gate drive circuit power supply V103, a level shifter X101H, inverters X101L, X105H, and X105L, P-channel MOS transistors M102H and M102L, and N-channel MOS transistors M103H and M103L.

[0006] Fig. 6 is a schematic diagram showing an example of an output LC filter-less application of the class-D amplifier circuit 101'' of Fig. 4. For example, in a BTL output configuration that handles a ternary pulse width modulation signal as the signal generator X101 for receiving the input signal Vin, as shown in Fig. 6, the potential difference between the load terminals is zero when there is no audio signal, so a so-called output LC filter-less configuration is possible that does not use an LC filter for removing frequency components unnecessary for the load (load resistance R), which has the advantage of reducing application costs.

[0007] In such a class D amplifier circuit, the higher the required output power, the higher the voltage of the output power supply V101 that must be used for operation, which increases the radiation noise generated in the class D amplifier circuit. To suppress radiation noise, it is effective to add an LC filter between the output terminal OUT and the load (load resistance R), as shown in Figure 7. Figure 7 is a schematic diagram showing an improved example of Figure 6, and Figure 8 is a time chart showing an example of operation in Figure 7.

[0008] In Fig. 7, an LC filter consisting of an inductance L and a capacitor C is provided between the output terminal OUT of the class-D amplifier circuit 101'' and a load (load resistance R) such as a speaker. In this improved example, the provision of the LC filter makes it possible to suppress radiation noise, but on the other hand, as shown in Fig. 8, overshoot and undershoot occur in the output signal Vout from the output terminal OUT during each of the dead times DTH-1 and DTL-1, respectively.

[0009] Such overshoot and undershoot are caused by current flowing through a body diode generated by an IC constituting the class-D amplifier circuit 101'', and can cause malfunction of the class-D amplifier circuit 101''. FIG. 9 is a cross-sectional view showing a simplified peripheral configuration of the low-side N-channel DMOS power transistor M101L of FIG. 4. FIG. 9 shows the peripheral configuration including the N-well region NWL corresponding to the analog circuit block excluding the low-side N-channel DMOS power transistor M101L. As shown in FIG. 9, a parasitic NPN transistor Q101 is generated between the low-side N-channel DMOS power transistor M101L and the N-well region NWL. When the output terminal OUT becomes negative voltage due to the influence of inductor energy stored in inductance L constituting the LC filter, the parasitic NPN transistor Q101 is turned on, and current flows from the N-well region NWL, which operates on the output power supply V101. This lowers the output power supply V101, resulting in an undershoot (overshoot also occurs due to the same principle).

[0010] A technology for preventing malfunctions during such dead time periods is disclosed, for example, in Patent Document 1. Patent Document 1 aims to prevent malfunctions by reducing the influence of overshoot or undershoot that occurs during the dead time period by making the dead time period as short as possible. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Patent No. 5596582 Summary of the Invention [Problem to be solved by the invention]

[0012] In the above Patent Document 1, the dead time is reduced to prevent malfunctions, but the dead time still exists to a considerable extent, so the above problem cannot be fundamentally solved.

[0013] At least one embodiment of the present disclosure has been made in consideration of the above circumstances, and aims to provide a class D amplifier circuit that can prevent malfunction by suppressing overshoot or undershoot that occurs during a dead time period when driving a load that includes an inductance. [Means for solving the problem]

[0014] In order to solve the above problem, a class D amplifier circuit according to at least one embodiment of the present disclosure comprises: a high-side N-channel DMOS power transistor having a drain connected to an output power supply terminal and a source connected to an output terminal; a low-side N-channel DMOS power transistor having a source connected to a ground terminal and a drain connected to the output terminal; a high-side gate drive circuit that turns on the high-side N-channel DMOS power transistor after a dead time has elapsed when an input signal becomes high level, and turns off the high-side N-channel DMOS power transistor when the input signal becomes low level, and is operable by a high-side gate drive circuit power supply referenced to the output terminal; a class D amplifier circuit having a low-side gate drive circuit that can operate using a low-side gate drive circuit power supply referenced to the ground terminal, the low-side N-channel DMOS power transistor being turned on after a dead time has elapsed when the input signal becomes low level, and the low-side N-channel DMOS power transistor being turned off when the input signal becomes high level; a high-side dead time cancellation circuit capable of canceling the dead time by turning on the high-side N-channel DMOS power transistor when a potential difference between the output power supply terminal and the output terminal becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit capable of canceling the dead time by turning on the low-side N-channel DMOS power transistor when the potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the above is provided.

[0015] In order to solve the above problem, a class D amplifier circuit according to at least one embodiment of the present disclosure comprises: a high-side P-channel DMOS power transistor having a source connected to an output power supply terminal and a drain connected to an output terminal; a low-side N-channel DMOS power transistor having a source connected to a ground terminal and a drain connected to the output terminal; a high-side gate drive circuit that turns on the high-side P-channel DMOS power transistor after a dead time has elapsed when an input signal becomes high level, and turns off the high-side P-channel DMOS power transistor when the input signal becomes low level, and that is operable by a high-side gate drive circuit power supply having a positive voltage terminal connected to the output power supply terminal; a class D amplifier circuit having a low-side gate drive circuit that can operate using a low-side gate drive circuit power supply referenced to the ground terminal, the low-side N-channel DMOS power transistor being turned on after a dead time has elapsed when the input signal becomes low level, and the low-side N-channel DMOS power transistor being turned off when the input signal becomes high level; a high-side dead time cancellation circuit capable of canceling the dead time by turning on the high-side P-channel DMOS power transistor when a potential difference between the output power supply terminal and the output terminal becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit capable of canceling the dead time by turning on the low-side N-channel DMOS power transistor when the potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the above is provided. [Effects of the Invention]

[0016] According to at least one embodiment of the present disclosure, it is possible to provide a class D amplifier circuit capable of preventing malfunction by suppressing overshoot or undershoot that occurs during a dead time period when driving a load that includes an inductance. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a circuit diagram illustrating a class D amplifier circuit according to a first embodiment. [Figure 2] 2 is a time chart showing an example of the operation of the class D amplifier circuit of FIG. 1; [Figure 3] FIG. 10 is a circuit diagram showing a class D amplifier circuit according to a second embodiment. [Figure 4] FIG. 1 is a circuit diagram showing a conventional class D amplifier circuit. [Figure 5] 5 is a time chart showing an example of the operation of the class D amplifier circuit in FIG. 4. [Figure 6] FIG. 5 is a schematic diagram illustrating an example of an output LC filterless application of the class-D amplifier circuit of FIG. 4. [Figure 7] FIG. 7 is a schematic diagram showing an improved example of FIG. 6. [Figure 8] 8 is a time chart showing an example of operation in FIG. 7. [Figure 9] 5 is a cross-sectional structural diagram showing a simplified peripheral configuration of the low-side N-channel DMOS power transistor of FIG. 4. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, several embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of components described as embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure. For example, expressions expressing relative or absolute arrangement such as "in a certain direction," "along a certain direction," "parallel," "orthogonal," "center," "concentric," or "coaxial" not only express such an arrangement exactly, but also express a state in which there is a relative displacement with a tolerance or an angle or distance to the extent that the same function is obtained. For example, expressions such as "identical," "equal," and "homogeneous" that indicate that something is in an equal state not only indicate a state of strict equality, but also indicate a state in which there is a tolerance or a difference to the extent that the same function is obtained. For example, expressions representing shapes such as a square shape or a cylindrical shape not only represent shapes such as a square shape or a cylindrical shape in the strict geometric sense, but also represent shapes including uneven portions, chamfered portions, etc., to the extent that the same effect can be obtained. On the other hand, the expressions "comprises," "includes," "has," "includes," or "has" one element are not exclusive expressions that exclude the presence of other elements.

[0019] First Embodiment FIG. 1 is a circuit diagram showing a class-D amplifier circuit 101 according to the first embodiment, and FIG. 2 is a time chart showing an example of the operation of the class-D amplifier circuit 101.

[0020] The class-D amplifier circuit 101 can operate using power supplied from an output power supply V101 (VDD power supply), which is, for example, a lithium-ion battery, and includes a high-side gate drive circuit 102 and a low-side gate drive circuit 103. The high-side gate drive circuit 102 and the low-side gate drive circuit 103 operate using the high-side gate drive circuit power supply V102 and the low-side gate drive circuit power supply V103.

[0021] In the high-side gate drive circuit 102, the input signal Vin is level-shifted by a level shifter X101H to a PWM signal having the amplitude of the high-side gate drive circuit power supply V102. The output from the level shifter X101H is supplied to the gates of a P-channel MOS transistor M102H and an N-channel MOS transistor M103H that constitute the drive circuit via a dead time generation circuit X104H for generating a predetermined dead time and an inverter X105H. The P-channel MOS transistor M102H has a source connected to the positive voltage terminal of the high-side gate drive circuit power supply V102 and a drain connected to the gate of a high-side N-channel DMOS power transistor M101H. The N-channel MOS transistor M103H has a source connected to the drain of an N-channel MOS transistor M106H and a drain connected to the gate of a high-side N-channel DMOS power transistor M101H. The high-side N-channel DMOS power transistor M101H has a drain connected to the positive voltage terminal of the output power supply V101 and a source connected to the output terminal OUT.

[0022] In the low-side gate drive circuit 103, the input signal Vin is input via an inverter X101L to a dead time generation circuit X104L that generates a predetermined dead time, and its output is supplied via an inverter X105L to the gates of a P-channel MOS transistor M102L and an N-channel MOS transistor M103L that constitute the drive circuit. The P-channel MOS transistor M102L has a source connected to the positive voltage terminal of the low-side gate drive circuit power supply V103 and a drain connected to the gate of the low-side N-channel DMOS power transistor M101L. The N-channel MOS transistor M103L has a source connected to the drain of the N-channel MOS transistor M106L and a drain connected to the gate of the low-side N-channel DMOS power transistor M101L. The low-side N-channel DMOS power transistor M101L has a source connected to the ground terminal GND and a drain connected to the output terminal OUT.

[0023] The basic operations (except for the operations described below) of the high-side gate drive circuit 102 and the low-side gate drive circuit 103 are the same as those of the prior art described above with reference to Fig. 4. That is, as shown in Fig. 2, in the high-side gate drive circuit 102, when the input signal Vin becomes high level, the gate voltage V of the high-side N-channel DMOS power transistor M101H, which is off, Hgate becomes high level after a predetermined dead time generated by the dead time generating circuit X104H has elapsed. On the other hand, when the input signal Vin becomes low level, the gate voltage V of the high-side N-channel DMOS power transistor M101H, which is on, Hgate becomes low level.

[0024] In the low-side gate drive circuit 103, when the input signal Vin becomes low level, the gate voltage V of the low-side N-channel DMOS power transistor M101L, which is off, Lgatebecomes high level after a predetermined dead time set by the dead time generating circuit X104L has elapsed. On the other hand, when the input signal Vin becomes high level, the gate voltage V of the low-side N-channel DMOS power transistor M101L, which is on, Lgate becomes low level.

[0025] In the class-D amplifier circuit 101, the high-side gate drive circuit 102 and the low-side gate drive circuit 103 operate in this manner, so that the high-side N-channel DMOS power transistor M101H and the low-side N-channel DMOS power transistor M101L are not turned on at the same time, thereby preventing current consumption due to a large through current flowing through the high-side N-channel DMOS power transistor M101H and the low-side N-channel DMOS power transistor M101L and preventing element damage due to the large current.

[0026] Here, a load circuit Load including an inductance L is connected to the output terminal OUT of the class-D amplifier circuit 101. The load circuit Load includes a load resistor (not shown) such as a speaker, and an LC filter provided between the load resistor and the output terminal OUT to suppress radiation noise. The LC filter is made up of an inductance L101 and a capacitor C101. When the load circuit Load includes an inductance component in this way, as described above with reference to FIG. 8, in the conventional technology, there is a risk of overshoot and undershoot occurring in the output signal Vout from the output terminal OUT during the dead time period. However, in the class-D amplifier circuit 101 according to this embodiment, this problem can be preferably solved by including a high-side dead time cancellation circuit 104 and a low-side dead time cancellation circuit 105, which will be described below.

[0027] The high-side dead time cancellation circuit 104 is configured to cancel the dead time by turning on the high-side N-channel DMOS power transistor M101H when the input signal Vin goes high and the voltage Vout at the output terminal OUT rises, causing the voltage difference between the output power supply V101 and the output terminal OUT to become smaller than a threshold value. To achieve this function, in this embodiment, the high-side dead time cancellation circuit 104 includes an N-channel DMOS transistor M105H, a resistor R101H, an inverter X102H and a NAND circuit X103H, a P-channel MOS transistor M104H, and an N-channel MOS transistor M106H.

[0028] The N-channel DMOS transistor M105H has its drain connected to the positive voltage terminal of the output power supply V101, its gate connected to the positive voltage terminal of the high-side gate drive circuit power supply V102, and its source connected to the output terminal OUT via a resistor R101H, and is always on. By providing this N-channel DMOS transistor M105H between the output power supply 101 and the inverter X102H and NAND circuit X103H, the inverter X102H and NAND circuit X103H, which have relatively low electrical resistance, can be suitably protected from the output power supply V101.

[0029] The connection point between the source of the N-channel DMOS transistor M105H and the resistor R101H is connected to the NAND circuit X103H via the inverter X102H. The output of the NAND circuit X103H is supplied to the gate of the P-channel MOS transistor M104H based on the voltage of the output power supply V101 from the source of the N-channel DMOS transistor M105H, which is always on, and the input signal Vin via the level shifter circuit X101H. The source of the P-channel MOS transistor M104H is connected to the positive voltage terminal of the high-side gate drive circuit power supply V102, and the drain is connected to the gate of the high-side N-channel DMOS power transistor M101H.

[0030] When the input signal Vin changes from low to high, the high-side gate drive circuit 102 generates a predetermined dead time DTH-1, as described above. During this dead time DTH-1, the inductor energy stored in the inductance L causes the potential Vout of the output terminal OUT to suddenly transition from low to high. When the voltage obtained by dividing the potential Vout of the output terminal OUT by the on-resistance of the N-channel DMOS transistor M105H and resistor R101H reaches a predetermined voltage, the P-channel MOS transistor M104H instantaneously turns on the high-side N-channel DMOS power transistor M101H. As a result, the dead time becomes a shorter period DTH-2 than the original period DTH-1, as shown in FIG. 2. At this time, the P-channel MOS transistor M104H turns on faster than the N-channel MOS transistor M103H turns off due to the dead time set by the dead time generating circuit X104H, causing a through current to flow through a path from the P-channel MOS transistor M104H to the N-channel MOS transistor M103H. Therefore, the path is blocked using N-channel MOS transistor M106H. The above operation causes the current generated by the inductor energy to flow through the channel of high-side N-channel DMOS power transistor M101H, thereby suppressing overshoot in the output voltage Vout at output terminal OUT.

[0031] The P-channel MOS transistor M102H and N-channel MOS transistor M103H in the high-side gate drive circuit 102 are set to on-resistances that take into consideration measures to prevent EMI (Electro Magnetic Interference) at the power supply terminals and output terminals caused by the on / off of the high-side N-channel DMOS power transistor M101H during normal operation. In contrast, in the high-side dead time cancellation circuit 104, it is preferable to set the on-resistance of the P-channel MOS transistor M104H to be smaller than the on-resistance of the P-channel MOS transistor M102H. This makes it possible to instantly turn on the high-side N-channel DMOS power transistor M101H in order to suppress overshoot in the output voltage Vout at the output terminal OUT.

[0032] The low-side dead time cancellation circuit 105 is configured to cancel the dead time by turning on the low-side N-channel DMOS power transistor M101L when the input signal Vin goes low, causing the voltage Vout at the output terminal OUT to drop and the voltage difference between the ground terminal GND and the output terminal OUT to become smaller than a threshold value. To achieve this function, in this embodiment, the low-side dead time cancellation circuit 105 includes an N-channel DMOS transistor M105L, a resistor R101L, an inverter X102L and a NAND circuit X103L, a P-channel MOS transistor M104L, and an N-channel MOS transistor M106L.

[0033] The N-channel DMOS transistor M105L has its drain connected to the output terminal OUT, its gate connected to the positive voltage terminal of the low-side gate drive circuit power supply V103, and its source connected to the ground terminal GND via a resistor R101L, and is always on. By providing this N-channel DMOS transistor M105L between the output terminal OUT and the inverter X102H and NAND circuit X103H, the inverter X102H and NAND circuit X103H, which have relatively low electrical resistance, can be effectively protected from the voltage of the output terminal OUT.

[0034] The connection point between the source of the N-channel DMOS transistor M105L and the resistor R101L is connected to the NAND circuit X103L via the inverter X102L. The output of the NAND circuit X103L is supplied to the gate of the P-channel MOS transistor M104L based on the voltage at the output terminal OUT from the source of the N-channel DMOS transistor M105L, which is always on, and the input signal Vin via the inverter X101L. The source of the P-channel MOS transistor M104L is connected to the positive voltage terminal of the low-side gate drive circuit power supply V103, and the drain is connected to the gate of the low-side N-channel DMOS power transistor M101L.

[0035] When the input signal Vin changes from high to low, the low-side gate drive circuit 103 generates a predetermined dead time DTL-1, as described above. During this dead time DTL-1, the potential Vout of the output terminal OUT suddenly transitions from high to low due to the inductor energy stored in the inductance L. When the voltage obtained by dividing the potential Vout of the output terminal OUT by the on-resistance of the N-channel DMOS transistor M105L and the resistor R101L reaches a predetermined voltage, the P-channel MOS transistor M104L instantaneously turns on the low-side N-channel DMOS power transistor M101L. As a result, the dead time becomes a shorter period DTL-2 than the original period DTL-1, as shown in FIG. 2. At this time, the P-channel MOS transistor M104L turns on faster than the N-channel MOS transistor M103L turns off due to the dead time set by the dead time generating circuit X104L, causing a through current to flow from the P-channel MOS transistor M104L through the N-channel MOS transistor M103L. Therefore, the path is blocked using N-channel MOS transistor M106L. The above operation causes the current generated by the inductor energy to flow through the channel of low-side N-channel DMOS power transistor M101L, suppressing undershoot in the output voltage Vout at output terminal OUT.

[0036] The P-channel MOS transistor M102L and N-channel MOS transistor M103L in the low-side gate drive circuit 103 are set to have on-resistances that take into consideration EMI (Electro Magnetic Interference) countermeasures for the output terminal and ground terminal caused by the on / off of the low-side N-channel DMOS power transistor M101L during normal operation. In contrast, in the low-side dead time cancellation circuit 105, it is preferable to set the on-resistance of the P-channel MOS transistor M104L to be smaller than the on-resistance of the P-channel MOS transistor M102L. This makes it possible to instantly turn on the low-side N-channel DMOS power transistor M101L in order to suppress undershoot in the output voltage Vout at the output terminal OUT.

[0037] Second Embodiment 3 is a circuit diagram showing a class-D amplifier circuit 101' according to the second embodiment. The class-D amplifier circuit 101' differs in that the high-side gate drive circuit 102 has a P-channel DMOS power transistor, whereas the class-D amplifier circuit 101 according to the first embodiment described above has an N-channel DMOS power transistor. Due to this difference, the configuration of the high-side dead time cancellation circuit is partially different. In the following description, components corresponding to those in the class-D amplifier circuit 101 according to the first embodiment will be assigned the same reference numerals, and duplicated descriptions will be omitted unless otherwise specified.

[0038] Generally, in a class-D amplifier circuit, the smaller the on-resistance of the power transistor used in the output stage, the higher the efficiency. Therefore, N-channel power transistors with low on-resistance are used, such as the high-side N-channel DMOS power transistor M101H and the low-side N-channel DMOS power transistor M101L of the class-D amplifier circuit 101 according to the first embodiment. On the other hand, when N-channel power transistors are used, the peripheral circuitry connected to the gate becomes complicated, and costs increase unless the proportion of the output power transistor portion in the chip area is large. The class-D amplifier circuit 101′ according to the second embodiment is designed to balance cost and performance by using a P-channel power transistor (high-side P-channel DMOS transistor M101H′) on the high side.

[0039] The class D amplifier circuit 101' includes a high-side P-channel DMOS power transistor M101H' as a high-side power transistor. The high-side P-channel DMOS power transistor M101H' has a source connected to the positive voltage terminal of the output power supply V101 and a drain connected to the output terminal OUT. In the high-side gate drive circuit 102', as in the first embodiment described above, when the input signal Vin goes high, the high-side P-channel DMOS power transistor M101H', which is off, turns on after a predetermined dead time set by the dead time generation circuit X104H has elapsed. On the other hand, when the input signal Vin goes low, the high-side P-channel DMOS power transistor M101H', which is on, turns off.

[0040] The class D amplifier circuit 101′ includes a high-side dead time cancellation circuit 104′. The high-side dead time cancellation circuit 104′ has a different circuit configuration from that of the first embodiment described above but is capable of similar operation. That is, when the input signal Vin goes high, causing a predetermined dead time period, the high-side dead time cancellation circuit 104′ is configured to turn on a high-side P-channel DMOS power transistor M101H′ to cancel the dead time when the voltage difference between the output power supply V101 and the output terminal OUT becomes smaller than a threshold value due to the increase in the voltage Vout at the output terminal OUT. To achieve this function, in this embodiment, the high-side dead time cancellation circuit 104′ includes a P-channel DMOS transistor M105H′, an AND circuit X103H, and an N-channel MOS transistor M104H′. Compared to the high-side dead time cancellation circuit 104 of the first embodiment, this high-side dead time cancellation circuit 104′ does not require at least the inverter X102H, and can achieve equivalent functionality with a simpler circuit configuration.

[0041] The high-side dead time cancel circuit 104' further comprises a resistor R101H' and a P-channel MOS transistor M106H'.

[0042] In the above embodiments, examples have been given of the case where both the high-side dead time cancellation circuit 104, 104' and the low-side dead time cancellation circuit 105 are provided, but in the case where only either the overshoot or the undershoot in the voltage Vout of the output terminal OUT is to be suppressed, only either the high-side dead time cancellation circuit 104, 104' or the low-side dead time cancellation circuit 105 may be provided.

[0043] Additionally, the components in the above-described embodiments may be replaced with known components as appropriate, and the above-described embodiments may be combined as appropriate, without departing from the spirit of the present disclosure. For example, in the first embodiment, the high-side N-channel DMOS power transistor M101H is turned on by the P-channel MOS transistor M104H to cancel the dead time during the dead time period. However, it is also possible to configure the high-side N-channel DMOS power transistor M101H to be turned on by an N-channel MOS transistor. In this case, the source of the N-channel MOS transistor is connected to the gate of the high-side N-channel DMOS power transistor M101H, and the drain is connected to the positive voltage terminal of the high-side gate drive circuit power supply V102. Then, a signal with the opposite logic to the signal supplied to the gate of the P-channel MOS transistor M104H is supplied to the gate. Similarly, when replacing the P-channel MOS transistor M104L with an N-channel MOS transistor, the source of the N-channel MOS transistor is connected to the gate of the low-side N-channel DMOS power transistor M101L, the drain is connected to the positive voltage terminal of the low-side gate drive circuit power supply V103, and a signal of the opposite logic to the signal supplied to the gate of the P-channel MOS transistor M104L is supplied to the gate. Similarly, when replacing the N-channel MOS transistor M104H' of the second embodiment with a P-channel MOS transistor, the source of the P-channel MOS transistor is connected to the gate of the high-side P-channel DMOS power transistor M101H', the drain is connected to the negative voltage terminal of the high-side gate drive circuit power supply V102, and a signal of the opposite logic to the signal supplied to the gate of the N-channel MOS transistor M104H' is supplied to the gate.

[0044] The contents described in each of the above embodiments can be understood, for example, as follows.

[0045] (1) A class D amplifier circuit according to one aspect includes: a high-side N-channel DMOS power transistor (e.g., the high-side N-channel DMOS power transistor M101H in the above-described embodiments) having a drain connected to an output power supply terminal (e.g., the positive voltage terminal of the output power supply V101 in the above-described embodiments) and a source connected to an output terminal (e.g., the output terminal OUT in the above-described embodiments); a low-side N-channel DMOS power transistor (for example, the low-side N-channel DMOS power transistor M101L in the above embodiment) having a source connected to a ground terminal (for example, the ground terminal GND in the above embodiment) and a drain connected to the output terminal; a high-side gate drive circuit (e.g., the high-side gate drive circuit 102 in the above embodiment) that turns on the high-side N-channel DMOS power transistor after a dead time has elapsed when an input signal (e.g., the input signal Vin in the above embodiment) becomes high level, and turns off the high-side N-channel DMOS power transistor when the input signal becomes low level, and that is operable by a high-side gate drive circuit power supply (e.g., the high-side gate drive circuit power supply V102 in the above embodiment) based on the output terminal; In a class D amplifier circuit having a low-side gate drive circuit (e.g., the low-side gate drive circuit 103 in the above embodiment) that can operate by a low-side gate drive circuit power supply (e.g., the low-side gate drive circuit power supply V103 in the above embodiment) based on the ground terminal, the low-side N-channel DMOS power transistor is turned on after a dead time has elapsed when the input signal becomes low level, and the low-side N-channel DMOS power transistor is turned off when the input signal becomes high level, a high-side dead time cancellation circuit (for example, the high-side dead time cancellation circuit 104 in the above embodiment) capable of canceling the dead time by turning on the high-side N-channel DMOS power transistor when the potential difference between the output power supply terminal and the output terminal becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit (for example, the low-side dead time cancellation circuit 105 in the above embodiment) capable of canceling the dead time by turning on the low-side N-channel DMOS power transistor when the potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the above is provided.

[0046] According to the aspect (1) above, by providing a high-side dead time cancellation circuit, if the potential difference between the output power supply terminal and the output terminal becomes smaller than the threshold during the dead time period when the input signal becomes high level, the high-side N-channel DMOS power transistor is turned on to cancel the dead time. This cuts off the current flowing through the body diode during the dead time period, thereby effectively preventing overshoot from occurring in the output from the output terminal. Furthermore, by providing a low-side dead time cancellation circuit, if the potential difference between the ground terminal and the output terminal becomes smaller than the threshold during the dead time period when the input signal becomes low level, the low-side N-channel DMOS power transistor is turned on to cancel the dead time. This cuts off the current flowing through the body diode during the dead time period, thereby effectively preventing undershoot from occurring in the output from the output terminal.

[0047] (2) In another embodiment, in the above embodiment (1), the high-side dead time cancellation circuit includes, at an input stage, an N-channel DMOS transistor (e.g., the N-channel DMOS transistor M105H in the above embodiment) in a normally-on state, the drain of which is connected to the output power supply terminal and the source of which is connected to the output terminal via a resistor (e.g., the resistor R101H in the above embodiment); The low-side dead time cancellation circuit includes, at its input stage, an N-channel DMOS transistor (e.g., the N-channel DMOS transistor M105L in the above embodiment) that is always on and has a drain connected to the output terminal and a source connected to the ground terminal via a resistor (e.g., the resistor R101L in the above embodiment).

[0048] According to the above aspect (2), by providing such an N-channel DMOS transistor in the input stage of the high-side dead time cancellation circuit or in the input stage of the low-side dead time cancellation circuit, it is possible to suitably protect the components of the high-side dead time cancellation circuit or the low-side dead time cancellation circuit, which have relatively low electrical resistance.

[0049] (3) In another embodiment, in the above embodiment (1) or (2), The high-side dead time cancellation circuit a first P-channel MOS transistor (e.g., the P-channel MOS transistor M104H in the above embodiment) having a source connected to the high-side gate drive circuit power supply and a drain connected to the gate of the high-side N-channel DMOS power transistor; a first N-channel MOS transistor (for example, the N-channel MOS transistor M106H in the above embodiment) having a source connected to the output terminal and a gate connected to the gate of the first P-channel MOS transistor; the first N-channel MOS transistor is turned off at the same time as the first P-channel MOS transistor is turned on; The low-side dead time cancellation circuit a third P-channel MOS transistor (e.g., the P-channel MOS transistor M104L in the above embodiment) having a source connected to the low-side gate drive circuit power supply and a drain connected to the gate of the low-side N-channel DMOS power transistor; a second N-channel MOS transistor (for example, the N-channel MOS transistor M106L in the above embodiment) having a source connected to the ground terminal and a gate connected to the third P-channel MOS transistor; The second N-channel MOS transistor is turned off at the same time as the third P-channel MOS transistor is turned on.

[0050] According to the above aspect (3), by providing a P-channel MOS transistor M104H in the high-side dead time cancel circuit, the high-side N-channel DMOS power transistor can be turned on during the dead time period, thereby canceling the dead time. Furthermore, by providing an N-channel MOS transistor M106H that turns off simultaneously with the P-channel MOS transistor M104H turning on, the path from the P-channel MOS transistor M104H through the N-channel MOS transistor M103H in the high-side gate drive circuit can be blocked to prevent a through current from flowing. Similarly, by providing a P-channel MOS transistor M104L in the low-side dead time cancel circuit, the low-side N-channel DMOS power transistor can be turned on during the dead time period, thereby canceling the dead time. Furthermore, by providing an N-channel MOS transistor M106L that turns off simultaneously with the P-channel MOS transistor M104L turning on, the path from the P-channel MOS transistor M104L through the N-channel MOS transistor M103L in the low-side gate drive circuit can be blocked to prevent a through current from flowing.

[0051] (4) In another embodiment, in the above embodiment (3), The high-side gate drive circuit a second P-channel MOS transistor (for example, the P-channel MOS transistor M102H in the above embodiment) having a source connected to the high-side gate drive circuit power supply, a drain connected to the drain of the first P-channel MOS transistor, and a gate to which the input signal can be input; an on-resistance of the first P-channel MOS transistor is smaller than an on-resistance of the second P-channel MOS transistor; The low-side gate drive circuit a fourth P-channel MOS transistor (for example, the P-channel MOS transistor M102L in the above embodiment) having a source connected to the low-side gate drive circuit power supply, a drain connected to the drain of the third P-channel MOS transistor, and a gate to which the input signal can be input; The on-resistance of the third P-channel MOS transistor is smaller than the on-resistance of the fourth P-channel MOS transistor.

[0052] According to the above aspect (4), the high-side N-channel DMOS power transistor or the low-side N-channel DMOS power transistor can be instantly turned on during the dead time period to cancel the dead time.

[0053] (5) A class D amplifier circuit according to one aspect (for example, the class D amplifier circuit 101′ in the above embodiment) a high-side P-channel DMOS power transistor (e.g., the high-side P-channel DMOS power transistor M101H′ in the above embodiment) having a source connected to an output power supply terminal (e.g., the positive voltage terminal of the output power supply V101 in the above embodiment) and a drain connected to an output terminal (e.g., the output terminal OUT in the above embodiment); a low-side N-channel DMOS power transistor (for example, the low-side N-channel DMOS power transistor M101L in the above embodiment) having a source connected to a ground terminal (for example, the ground terminal GND in the above embodiment) and a drain connected to the output terminal; a high-side gate drive circuit (e.g., the high-side gate drive circuit 102′ in the above embodiment) that turns on the high-side P-channel DMOS power transistor after a dead time has elapsed when an input signal (e.g., the input signal Vin in the above embodiment) becomes high level, and turns off the high-side P-channel DMOS power transistor when the input signal becomes low level, and that is operable by a high-side gate drive circuit power supply (e.g., the high-side gate drive circuit power supply V102 in the above embodiment) having a positive voltage terminal connected to the output power supply terminal; In a class D amplifier circuit having a low-side gate drive circuit (e.g., the low-side gate drive circuit 103 in the above embodiment) that can operate by a low-side gate drive circuit power supply (e.g., the low-side gate drive circuit power supply V103 in the above embodiment) based on the ground terminal, the low-side N-channel DMOS power transistor is turned on after a dead time has elapsed when the input signal becomes low level, and the low-side N-channel DMOS power transistor is turned off when the input signal becomes high level, a high-side dead time cancellation circuit (for example, the high-side dead time cancellation circuit 104′ in the above embodiment) capable of canceling the dead time by turning on the high-side P-channel DMOS power transistor when the potential difference between the output power supply terminal and the output terminal becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit (for example, the low-side dead time cancellation circuit 105 in the above embodiment) capable of canceling the dead time by turning on the low-side N-channel DMOS power transistor when the potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the above is provided.

[0054] According to the aspect (5) above, by providing a high-side dead time cancellation circuit, if the potential difference between the output power supply terminal and the output terminal becomes smaller than the threshold during the dead time period when the input signal becomes high level, the high-side P-channel DMOS power transistor is turned on to cancel the dead time. This cuts off the current flowing through the body diode during the dead time period, thereby effectively preventing overshoot from occurring in the output from the output terminal. Furthermore, by providing a low-side dead time cancellation circuit, if the potential difference between the ground terminal and the output terminal becomes smaller than the threshold during the dead time period when the input signal becomes low level, the low-side N-channel DMOS power transistor is turned on to cancel the dead time. This cuts off the current flowing through the body diode during the dead time period, thereby effectively preventing undershoot from occurring in the output from the output terminal. In addition, by using a P-channel power transistor on the high side, it is possible to achieve a design that balances cost and performance.

[0055] (6) In another embodiment, in the above embodiment (5), the high-side dead time cancellation circuit includes, at an input stage, a P-channel DMOS transistor (e.g., the P-channel DMOS transistor M105H′ in the above embodiment) in a normally-on state, the drain of which is connected to the output terminal and the source of which is connected to the output power supply terminal via a resistor (e.g., the resistor R101H in the above embodiment); The low-side dead time cancellation circuit includes, at its input stage, an N-channel DMOS transistor (e.g., the N-channel DMOS transistor M105L in the above embodiment) that is always on and has a drain connected to the output terminal and a source connected to the ground terminal via a resistor (e.g., the resistor R101L in the above embodiment).

[0056] According to the above aspect (6), by providing such a P-channel DMOS transistor or N-channel DMOS transistor in the input stage of the high-side dead time cancellation circuit or in the input stage of the low-side dead time cancellation circuit, it is possible to suitably protect the components of the high-side dead time cancellation circuit or low-side dead time cancellation circuit, which have relatively low electrical resistance.

[0057] (7) In another embodiment, in the above embodiment (5) or (6), The high-side dead time cancellation circuit a first N-channel MOS transistor (e.g., the N-channel MOS transistor M104H′ in the above embodiment) having a source connected to the negative voltage terminal of the high-side gate drive circuit power supply and a drain connected to the gate of the high-side P-channel DMOS power transistor; a third P-channel MOS transistor (for example, the P-channel MOS transistor M106H′ in the above embodiment) having a source connected to the output power supply terminal and a gate connected to the gate of the first N-channel MOS transistor; the third P-channel MOS transistor is turned off at the same time as the first N-channel MOS transistor is turned on; The low-side dead time cancellation circuit a first P-channel MOS transistor (e.g., the P-channel MOS transistor M104L in the above embodiment) having a source connected to the low-side gate drive circuit power supply and a drain connected to the gate of the low-side N-channel DMOS power transistor; a third N-channel MOS transistor (for example, the N-channel MOS transistor M106L in the above embodiment) having a source connected to the ground terminal and a gate connected to the gate of the first P-channel MOS transistor; The third N-channel MOS transistor is turned off at the same time as the first P-channel MOS transistor is turned on.

[0058] According to the aspect (7) above, by providing the N-channel MOS transistor M104H' in the high-side dead time cancel circuit, the high-side P-channel DMOS power transistor can be turned on during the dead time period to cancel the dead time. Furthermore, by providing the P-channel MOS transistor M106H' that turns off simultaneously with the N-channel MOS transistor M104H' turning on, it is possible to block the path from the P-channel MOS transistor M102H' in the high-side gate drive circuit through the N-channel MOS transistor M104H' so that no through current flows. Similarly, by providing the P-channel MOS transistor M104L in the low-side dead time cancel circuit, it is possible to turn on the low-side N-channel DMOS power transistor during the dead time period to cancel the dead time. Furthermore, by providing the N-channel MOS transistor M106L that turns off simultaneously with the P-channel MOS transistor M104L turning on, it is possible to block the path from the P-channel MOS transistor M104L through the N-channel MOS transistor M103L in the low-side gate drive circuit so that no through current flows.

[0059] (8) In another embodiment, in the above embodiment (7), The high-side gate drive circuit a second N-channel MOS transistor (for example, the N-channel MOS transistor M103H′ in the above embodiment) having a source connected to the source of the first N-channel MOS transistor, a drain connected to the drain of the first N-channel MOS transistor, and a gate to which the input signal can be input; an on-resistance of the first N-channel MOS transistor is smaller than an on-resistance of the second N-channel MOS transistor; The low-side gate drive circuit a second P-channel MOS transistor (for example, the P-channel MOS transistor M102L in the above embodiment) having a source connected to the low-side gate drive circuit power supply, a drain connected to the drain of the first P-channel MOS transistor, and a gate to which the input signal can be input; The on-resistance of the first P-channel MOS transistor is smaller than the on-resistance of the second P-channel MOS transistor.

[0060] According to the above aspect (8), the high-side P-channel DMOS power transistor or the low-side N-channel DMOS power transistor can be instantly turned on during the dead time period to cancel the dead time. [Explanation of symbols]

[0061] 101 Class D amplifier circuit 102 High-side gate drive circuit 103 Low-side gate drive circuit 104 High-side dead time cancellation circuit 105 Low-side dead time cancellation circuit V101 output power V102 High-side gate drive circuit power supply V103 Low-side gate drive circuit power supply X101H Level Shifter X101L, X102H, X102L, X105H, X105L inverter X103H, X103L NAND gates M101H, M101L, M105H, M105L N-channel DMOS transistors M103H, M103L, M106H, M106L N-channel MOS transistors M102H, M102L, M104H, M104L P-channel MOS transistors R101H, R101L resistor L101 inductor C101 capacitor X101 Signal Generator (Tri-level PWM Modulator) Q101: Parasitic NPN

Claims

1. a high-side N-channel DMOS power transistor having a drain connected to the positive voltage terminal of the output power supply and a source connected to the output terminal; a low-side N-channel DMOS power transistor having a source connected to a ground terminal and a drain connected to the output terminal; a high-side gate drive circuit that turns on the high-side N-channel DMOS power transistor after a high-side dead time generated by a high-side dead time generation circuit has elapsed when an input signal becomes high level, and turns off the high-side N-channel DMOS power transistor when the input signal becomes low level, and is operable by a high-side gate drive circuit power supply referenced to the output terminal; a class D amplifier circuit having a low-side gate drive circuit that can operate by a low-side gate drive circuit power supply referenced to the ground terminal, wherein when the input signal becomes low level, the low-side N-channel DMOS power transistor is turned on after a low-side dead time generated by a low-side dead time generation circuit has elapsed, and when the input signal becomes high level, the low-side N-channel DMOS power transistor is turned off; a high-side dead time cancellation circuit capable of canceling the high-side dead time by turning on the high-side N-channel DMOS power transistor when a potential difference between the positive voltage terminal and the output terminal of the output power supply becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit that can cancel the low-side dead time by turning on the low-side N-channel DMOS power transistor when a potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the following is provided: the high side dead time cancellation circuit includes, in an input stage, a high side N-channel DMOS transistor in a normally on state, the drain of which is connected to the positive voltage terminal of the output power supply and the source of which is connected to the output terminal via a first resistor; a first inverter having an input side connected to the source of the high side N-channel DMOS transistor; and a first NAND circuit having a first input side connected to the output side of the first inverter and a second input side connected to the output side of a level shifter whose input side receives the input signal, and having a source connected to the positive voltage terminal of the high side gate drive circuit power supply and an output side connected to the gate of a first P-channel MOS transistor, the first P-channel MOS transistor having a drain connected to the gate of the high side N-channel DMOS power transistor; the low-side dead time cancellation circuit is a class D amplifier circuit including, at its input stage, a low-side N-channel DMOS transistor in a normally-on state, the drain of which is connected to the output terminal and the source of which is connected to the ground terminal via a second resistor; a second inverter having an input side connected to the source of the low-side N-channel DMOS transistor; and a second NAND circuit having a first input side connected to the output side of the second inverter, a second input side connected to the output side of a fourth inverter to whose input side the input signal is input, and an output side connected to the gate of a third P-channel MOS transistor having a source connected to the positive voltage terminal of the low-side gate drive circuit power supply and a drain connected to the gate of the low-side N-channel DMOS power transistor.

2. the high-side dead time cancel circuit includes a first N-channel MOS transistor having a source connected to the output terminal and a gate connected to a gate of the first P-channel MOS transistor; when the potential of the output terminal reaches a predetermined value during the high side dead time and the high side N channel DMOS power transistor is turned on by the first P channel MOS transistor earlier than the high side dead time, a through current flowing through a path passing through the first P channel MOS transistor is cut off by turning off the first N channel MOS transistor; the low-side dead time cancellation circuit includes a second N-channel MOS transistor having a source connected to the ground terminal and a gate connected to a gate of the third P-channel MOS transistor; 2. The class-D amplifier circuit according to claim 1, wherein when the potential of said output terminal reaches a predetermined value during said low-side dead time, and said low-side N-channel DMOS power transistor is turned on by said third P-channel MOS transistor earlier than said low-side dead time, a through current flowing through a path passing through said third P-channel MOS transistor is cut off by turning off said second N-channel MOS transistor.

3. The high-side gate drive circuit a second P-channel MOS transistor having a source connected to a positive voltage terminal of the high-side gate drive circuit power supply and a drain connected to the drain of the first P-channel MOS transistor; a third N-channel MOS transistor having a drain connected to the drain of the second P-channel MOS transistor and a source connected to the drain of the first N-channel MOS transistor; a third inverter having an input connected to an output of the high-side dead time generation circuit and an output connected to the gates of the second P-channel MOS transistor and the third N-channel MOS transistor; Equipped with the level shifter level-shifts the input signal to a PWM signal having an amplitude of the high-side gate drive circuit power supply; the high-side dead time generating circuit has an input connected to the output of the level shifter; an on-resistance of the first P-channel MOS transistor is smaller than an on-resistance of the second P-channel MOS transistor; The low-side gate drive circuit a fourth P-channel MOS transistor having a source connected to the positive voltage terminal of the low-side gate drive circuit power supply and a drain connected to the drain of the third P-channel MOS transistor; a fourth N-channel MOS transistor having a drain connected to the drain of the fourth P-channel MOS transistor and a source connected to the drain of the second N-channel MOS transistor; a fifth inverter having an input connected to an output of the low-side dead time generation circuit and an output connected to gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor; Equipped with the fourth inverter inverts the input signal; the low-side dead time generation circuit has an input connected to the output of the fourth inverter; 3. The class D amplifier circuit according to claim 2, wherein an on-resistance of said third P-channel MOS transistor is smaller than an on-resistance of said fourth P-channel MOS transistor.

4. a high-side P-channel DMOS power transistor having a source connected to the positive voltage terminal of the output power supply and a drain connected to the output terminal; a low-side N-channel DMOS power transistor having a source connected to a ground terminal and a drain connected to the output terminal; a high-side gate drive circuit that turns on the high-side P-channel DMOS power transistor after a high-side dead time generated by a high-side dead time generation circuit has elapsed when an input signal becomes high level, and turns off the high-side P-channel DMOS power transistor when the input signal becomes low level, and that is operable by a high-side gate drive circuit power supply having a positive voltage terminal connected to a positive voltage terminal of the output power supply; a class D amplifier circuit having a low-side gate drive circuit that can operate by a low-side gate drive circuit power supply referenced to the ground terminal, wherein when the input signal becomes low level, the low-side N-channel DMOS power transistor is turned on after a low-side dead time generated by a low-side dead time generation circuit has elapsed, and when the input signal becomes high level, the low-side N-channel DMOS power transistor is turned off; a high-side dead time cancellation circuit capable of canceling the high-side dead time by turning on the high-side P-channel DMOS power transistor when a potential difference between the positive voltage terminal of the output power supply and the output terminal becomes smaller than a threshold value while the input signal is at a high level; a low-side dead time cancellation circuit that can cancel the low-side dead time by turning on the low-side N-channel DMOS power transistor when a potential difference between the ground terminal and the output terminal becomes smaller than a threshold value while the input signal is at a low level; At least one of the following is provided: the high side dead time cancellation circuit includes, in an input stage, a high side P channel DMOS transistor in a normally on state, the drain of which is connected to the output terminal and the source of which is connected via a first resistor to the positive voltage terminal of the output power supply, an AND circuit having a first input connected to the source of the high side P channel DMOS transistor, a second input connected to the output side of a level shifter to whose input side the input signal is input, a source connected to the negative voltage terminal of the high side gate drive circuit power supply, and a drain connected to the gate of the high side P channel DMOS power transistor, the low-side dead time cancellation circuit is a class D amplifier circuit including, at its input stage, a low-side N-channel DMOS transistor in a normally-on state, the drain of which is connected to the output terminal and the source of which is connected to the ground terminal via a second resistor; a second inverter having an input side connected to the source of the low-side N-channel DMOS transistor; and a NAND circuit having a first input side connected to the output side of the second inverter, a second input side connected to the output side of a fourth inverter to whose input side the input signal is input, and a source connected to the positive voltage terminal of the low-side gate drive circuit power supply and an output side connected to the gate of a first P-channel MOS transistor having a drain connected to the gate of the low-side N-channel DMOS power transistor.

5. the high side dead time cancellation circuit includes a third P-channel MOS transistor having a source connected to the positive voltage terminal of the output power supply and a gate connected to the gate of the first N-channel MOS transistor; when the potential of the output terminal reaches a predetermined value during the high side dead time and the high side P channel DMOS power transistor is turned on by the first N channel MOS transistor earlier than the high side dead time, a through current flowing through a path passing through the first N channel MOS transistor is cut off by turning off the third P channel MOS transistor; the low-side dead time cancellation circuit further includes a third N-channel MOS transistor having a source connected to the ground terminal and a gate connected to the gate of the first P-channel MOS transistor; 5. The class-D amplifier circuit according to claim 4, wherein when the potential of said output terminal reaches a predetermined value during said low-side dead time, and said low-side N-channel DMOS power transistor is turned on by said first P-channel MOS transistor earlier than said low-side dead time, a through current flowing through a path passing through said first P-channel MOS transistor is cut off by turning off said third N-channel MOS transistor.

6. The high-side gate drive circuit a second N-channel MOS transistor having a source connected to the source of the first N-channel MOS transistor and a drain connected to the drain of the first N-channel MOS transistor; a fourth P-channel MOS transistor having a drain connected to the drain of the second N-channel MOS transistor and a source connected to the drain of the third P-channel MOS transistor; Equipped with the level shifter level-shifts the input signal to a PWM signal having an amplitude of the high-side gate drive circuit power supply; the high-side dead time generation circuit has an input side connected to the output side of the level shifter and an output side connected to the gates of the second N-channel MOS transistor and the fourth P-channel MOS transistor; an on-resistance of the first N-channel MOS transistor is smaller than an on-resistance of the second N-channel MOS transistor; The low-side gate drive circuit a second P-channel MOS transistor having a source connected to a positive voltage terminal of the low-side gate drive circuit power supply and a drain connected to the drain of the first P-channel MOS transistor; a fourth N-channel MOS transistor having a drain connected to the drain of the second P-channel MOS transistor and a source connected to the drain of the third N-channel MOS transistor; a fifth inverter having an input connected to an output of the low-side dead time generation circuit and an output connected to the gates of the second P-channel MOS transistor and the fourth N-channel MOS transistor; Equipped with the fourth inverter inverts the input signal; the low-side dead time generation circuit has an input connected to the output of the fourth inverter; 6. The class D amplifier circuit according to claim 5, wherein an on-resistance of said first P-channel MOS transistor is smaller than an on-resistance of said second P-channel MOS transistor.

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