Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing electrostatic capacitance.SOLUTION: A semiconductor device comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first conductive part, a first gate electrode, and a second electrode. The first conductive part is provided in the first semiconductor region via a first insulation part, including impurities of the second conductivity type. The first gate electrode is provided on the first conductive part via a first interlayer insulation part. The first gate electrode faces the second semiconductor region via a first gate insulating layer. The first gate electrode includes impurities of the first conductivity type. An impurity concentration of the first conductivity type in the first interlayer insulation part is higher than that in the first insulation part. An impurity concentration of the second conductivity type in the first interlayer insulation part is higher than that in the first insulation part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, for example, and there is a demand for reducing the capacitance of such semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-181809 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing electrostatic capacitance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first conductive portion, a first gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region. The first conductive portion is provided in the first semiconductor region via a first insulating portion and contains impurities of the second conductivity type. The first gate electrode is provided on the first conductive portion via a first interlayer insulating portion. The first gate electrode faces the second semiconductor region via a first gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The first gate electrode contains impurities of the first conductivity type. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region, the third semiconductor region, and the first conductive portion. The first interlayer insulating part has a higher impurity concentration of the first conductivity type than the first insulating part, and the first interlayer insulating part has a higher impurity concentration of the second conductivity type than the first insulating part. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of a portion P1 of FIG. [Figure 3] 3 is a cross-sectional view taken along A1-A2 in FIG. 2. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 8]FIG. 8 is an enlarged view of a portion P2 of FIG. [Figure 9] 9 is a cross-sectional view taken along B1-B2 in FIG. 8. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when showing the same part, the dimensions and ratios may be expressed differently depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n and p + , p - The notation indicates the relative level of each impurity concentration. That is, a notation with a "+" indicates a relatively higher impurity concentration than a notation with neither a "+" nor a "-" and a notation with a "-" indicates a relatively lower impurity concentration than a notation with neither a "+" nor a "-". When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to a first embodiment, Fig. 2 is an enlarged view of a portion P1 of Fig. 1, and Fig. 3 is a cross-sectional view taken along the line A1-A2 of Fig. 2. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIGS. 1 to 3, the semiconductor device 100 according to the first embodiment has a p - n-type (first conductivity type) drift region 1 (first semiconductor region), n-type (second conductivity type) base region 2 (second semiconductor region), p + source region 3 (third semiconductor region), n + Shape contact area 4, p+ The semiconductor device includes a drain region 5, a first conductive portion 11, a first insulating portion 11a, a first interlayer insulating portion 11b, a first gate electrode 21, a first gate insulating layer 21a, a drain electrode 31 (first electrode), a source electrode 32 (second electrode), and a gate pad 33. In Fig. 2, the source electrode 32 is represented by a dashed line, and a part of the first gate insulating layer 21a is omitted.

[0009] The embodiment will be described using an XYZ orthogonal coordinate system. - The direction toward the drift region 1 is the Z direction (first direction). The direction perpendicular to the Z direction is the X direction (second direction). The direction perpendicular to the X and Z directions is the Y direction. - The direction toward the drift region 1 is called "up" and the opposite direction is called "down." - This is a direction based on the relative positional relationship with the shape drift region 1 and is unrelated to the direction of gravity.

[0010] 1, a source electrode 32 and a gate pad 33 are provided on the upper surface of the semiconductor device 100. The source electrode 32 and the gate pad 33 are spaced apart from each other and electrically isolated from each other.

[0011] 2, a plurality of first gate electrodes 21 are provided below the source electrode 32. The plurality of first gate electrodes 21 are aligned in the X direction and extend in the Y direction. Each of the first gate electrodes 21 is electrically connected to a gate pad 33.

[0012] As shown in FIG. 3, the drain electrode 31 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. - The drift region 1 is p + The p-type drain region 5 is provided on the p-type drain region 5. - The n-type impurity concentration in the drift region 1 is p + The concentration of n-type impurities in the n-type drain region 5 is lower than that in the p-type drain region 6.- The drift region 1 is p + The gate electrode 31 is electrically connected to the drain electrode 31 via the drain region 5 .

[0013] The n-type base region 2 is p - The semiconductor device is provided on the drift region 1. + The n-type source region 3 is provided on a part of the n-type base region 2. + The n-type contact region 4 is provided on another part of the n-type base region 2. + The p-type impurity concentration in the contact region 4 is higher than the p-type impurity concentration in the n-type base region 2.

[0014] The first conductive portion 11 is connected to the p - The first gate electrode 21 is provided in the n-type drift region 1. The first gate electrode 21 is provided on the first conductive portion 11 via a first interlayer insulating portion 11b. The first gate electrode 21 faces the n-type base region 2 in the X direction via a first gate insulating layer 21a. In the illustrated example, the first gate electrode 21 is - Part of the drift region 1 and p + It also faces a part of the source region 3.

[0015] The source electrode 32 is p + shaped source region 3 and n + The p-type contact region 4 is provided on the p-type contact region 4. + Shape source region 3, n + The n-type base region 2 is electrically connected to the n-type contact region 4 and the first conductive portion 11. + The first gate electrode 21 is electrically connected to the source electrode 32 via the contact region 4. The first gate electrode 21 is electrically isolated from the source electrode 32 by the first gate insulating layer 21a.

[0016] As shown in FIGS. 2 and 3, the n-type base region 2, p + Shape source region 3, n + Each of the p-type contact regions 4 and the first conductive portions 11 extends in the Y direction, and a plurality of p-type contact regions 4 and the first conductive portions 11 are provided in the X direction. +A plurality of pairs of p-type source regions 3 are provided on one of the n-type base regions 2. + The n-type source regions 3 are provided on the plurality of n-type base regions 2, respectively. The plurality of first conductive portions 11 are respectively connected to the p-type - The n-type base region 2 is provided in the n-type drift region 1. The Y-direction end of each first conductive portion 11 is pulled upward and electrically connected to the source electrode 32. A plurality of first gate electrodes 21 are provided on the plurality of first conductive portions 11 via a plurality of first interlayer insulating portions 11b. The plurality of first gate electrodes 21 face the plurality of n-type base regions 2 via a plurality of first gate insulating layers 21a.

[0017] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the source electrode 32 relative to the drain electrode 31, a negative voltage equal to or greater than the threshold is applied to the first gate electrode 21. This forms a channel (inversion layer) in the n-type base region 2, turning the semiconductor device 100 on. Holes flow through the channel from the source electrode 32 to the drain electrode 31. When the negative voltage applied to the first gate electrode 21 becomes lower than the threshold, the channel in the n-type base region 2 disappears, turning the semiconductor device 100 off.

[0018] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 31 with respect to the source electrode 32 increases. - From the interface with the drift region 1, - The depletion layer spreads toward the p-type drift region 1. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be maintained while the p-type drift region 1 is - The n-type impurity concentration in the n-type drift region 1 can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0019] An example of the material of each component of the semiconductor device 100 will be described. p - n-type drift region 1, n-type base region 2, p + Shape source region 3, n+ contact region 4, and p + The semiconductor material of the drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, the n-type impurity can be arsenic, phosphorus, or antimony. The p-type impurity can be boron.

[0020] The first insulating portion 11a, the first interlayer insulating portion 11b, and the first gate insulating layer 21a include an insulating material. For example, the first insulating portion 11a, the first interlayer insulating portion 11b, and the first gate insulating layer 21a include silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 31 and the source electrode 32 include a metal such as titanium, tungsten, or aluminum.

[0021] The first conductive portion 11 and the first gate electrode 21 contain a conductive material such as polysilicon. The first conductive portion 11 contains one of n-type and p-type impurities. The first gate electrode 21 contains the other of n-type and p-type impurities. That is, the first conductive portion 11 and the first gate electrode 21 contain impurities of different conductivity types. Preferably, the first conductive portion 11 contains n-type impurities, and the first gate electrode 21 contains p-type impurities.

[0022] The first conductive portion 11 and the first gate electrode 21 may contain both n-type impurities and p-type impurities. In this case, the concentration of one of the n-type and p-type impurities in the first conductive portion 11 is higher than the concentration of the other of the n-type and p-type impurities in the first gate electrode 21. The concentration of the other of the n-type and p-type impurities in the first conductive portion 11 is higher than the concentration of one of the n-type and p-type impurities in the first gate electrode 21. For example, the concentration of the n-type impurities in the first conductive portion 11 is higher than the concentration of the p-type impurities, and the concentration of the p-type impurities in the first gate electrode 21 is higher than the concentration of the n-type impurities.

[0023] 4 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. An example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. +A semiconductor substrate Sub including a semiconductor layer 5a is prepared. + Silicon is epitaxially grown on the semiconductor layer 5a to form a p - A semiconductor layer 1a is formed. - A plurality of trenches T are formed on the upper surface of the semiconductor layer 1a. As shown in FIG. 4(a), the p - An insulating layer 10a is formed along the upper surface of the semiconductor layer 1a and the inner surface of the trench T.

[0024] A conductive layer 10 is formed on the insulating layer 10a to fill the trenches T. The conductive layer 10 is formed by chemical vapor deposition (CVD) of a conductive material such as polysilicon. N-type impurities are ion-implanted into the conductive layer 10. The n-type impurities are diffused and activated in the conductive layer 10 by heat treatment. The upper surface of the conductive layer 10 is recessed by chemical dry etching (CDE) or the like. This results in multiple conductive layers 10 separated and provided in the multiple trenches T. As shown in FIG. 4(b), an insulating layer 10b is formed on the insulating layer 10a and the multiple conductive layers 10. The insulating layer 10b is formed by CVD of boron phosphorus silicate glass (BPSG). Therefore, the insulating layer 10b contains more n-type impurities and p-type impurities than the insulating layer 10a.

[0025] The upper surfaces of the insulating layers 10a and 10b are recessed by wet etching. - The upper surface of the semiconductor layer 1a and a part of the side surface of the trench T are exposed. - An insulating layer 20a is formed on the upper surface of the semiconductor layer 1a and on the side walls of the trenches T. The thickness of the insulating layer 20a is smaller than that of the insulating layer 10a. A conductive layer 20 is formed on the insulating layer 20a. P-type impurities are ion-implanted into the conductive layer 20. The p-type impurities are diffused and activated in the conductive layer 20 by heat treatment. As shown in FIG. 5(a), the upper surface of the conductive layer 20 is recessed by CDE or wet etching, and the conductive layer 20 is formed inside each trench T.

[0026] Between trenches T - The n-type impurity and the p-type impurity are ion-implanted successively into the upper portion of the n-type semiconductor layer 1a to form the n-type semiconductor region 2a and the p-type semiconductor region 2b. + 5(b), an insulating layer 20b is formed to cover the plurality of conductive layers 20.

[0027] Insulating layer 20b, insulating layer 20a, and p + An opening OP is formed through the n-type semiconductor region 3a to reach the n-type semiconductor region 2a. P-type impurities are ion-implanted into the n-type semiconductor region 2a through the opening OP, and as shown in FIG. + A semiconductor region 4a is formed.

[0028] A metal layer 32a is formed on the insulating layer 20b to fill the opening OP. + The lower surface of the semiconductor substrate Sub is ground until the shaped semiconductor layer 5a reaches a predetermined thickness. As shown in Figure 6(b), a metal layer 31a is formed on the ground lower surface. Through the above steps, the semiconductor device 100 shown in Figure 1 is manufactured.

[0029] p shown in Figure 6(b) - The semiconductor layer 1a is a p-type semiconductor layer shown in FIG. - The n-type semiconductor region 2a corresponds to the n-type drift region 1. The n-type semiconductor region 2a corresponds to the n-type base region 2. + The semiconductor region 3a is p + corresponds to the source region 3. + The semiconductor region 4a is n + It corresponds to the contact area 4. + The semiconductor layer 5a is p + The metal layer 31a corresponds to the drain region 5. The conductive layer 10 corresponds to the first conductive portion 11. The insulating layer 10a corresponds to the first insulating portion 11a. The insulating layer 10b corresponds to the first interlayer insulating portion 11b. The conductive layer 20 corresponds to the first gate electrode 21. The insulating layers 20a and 20b correspond to the first gate insulating layer 21a. The metal layer 31a corresponds to the drain electrode 31. The metal layer 32a corresponds to the source electrode 32.

[0030] The advantages of the embodiment will be described. p - The drift region 1 and the first conductive portion 11 face each other via the first insulating portion 11a. - A capacitance is generated between the drift region 1 and the first conductive portion 11. In the embodiment, - The drift region 1 and the first conductive portion 11 contain impurities of different conductivity types. With this structure, the work function of the first conductive portion 11 increases, and the potential of the first conductive portion 11 increases relative to the p - The first conductive portion 11 and the p - Due to the potential difference between the first insulating portion 11a and the drift region 1, - The depletion layer spreads toward the first insulating portion 11a and the holes near the first insulating portion 11a are repelled, and the p - The capacitance between the drift region 1 and the first conductive portion 11 decreases. That is, the capacitance Cds between the drain electrode 31 and the source electrode 32 decreases. The capacitance Cds is related to the output capacitance Coss of the semiconductor device 100. As the capacitance Cds increases, the output capacitance Coss also increases. The larger the output capacitance Coss is, the longer the time required to charge or discharge the output capacitance Coss when the semiconductor device 100 is switched. According to the embodiment, the output capacitance Coss of the semiconductor device 100 can be reduced, and the switching loss of the semiconductor device 100 can be reduced.

[0031] In addition, p between the first conductive parts 11 - In the drift region 1, the first insulating portion 11a and the p - As the depletion layer expands from the interface with the drift region 1, holes near the first gate insulating layer 21a are also repelled, and p -The capacitance between the drift region 1 and the first gate electrode 21 also decreases. That is, the capacitance Cgd between the drain electrode 31 and the first gate electrode 21 decreases. The capacitance Cgd corresponds to the feedback capacitance Crss of the semiconductor device 100. The decrease in capacitance Cgd also decreases the feedback capacitance Crss. The feedback capacitance Crss affects the length of the transition period until the semiconductor device 100 is fully turned on when the semiconductor device 100 is turned on. The larger the feedback capacitance Crss, the longer the transition period, and the greater the switching loss of the semiconductor device 100. According to the embodiment, in addition to the output capacitance Coss, the feedback capacitance Crss of the semiconductor device 100 can also be reduced, thereby further reducing the switching loss of the semiconductor device 100.

[0032] In addition, in the manufacturing process of the semiconductor device 100, p + The impurities contained in the p-type drain region 5 - The impurity concentration in the first conductive portion 11 increases, and the p - The capacitance Cds between the drift region 1 and the first conductive portion 11 increases, and the capacitance Cds also increases. - By making the drift region 1 thicker, it is possible to suppress the diffusion of impurities into the first conductive portion 11, but the on-resistance of the semiconductor device 100 increases. - When the drift region 1 and the first conductive portion 11 contain impurities of different conductivity types, even if the impurities diffuse into the first conductive portion 11, an increase in capacitance Cds can be suppressed, and an increase in switching loss of the semiconductor device 100 can be suppressed.

[0033] More preferably, the first conductive portion 11 and the first gate electrode 21 contain impurities of different conductivity types. -The drift region 1 and the first gate electrode 21 contain impurities of the same conductivity type, but contain impurities of a conductivity type different from that of the first conductive portion 11. With this configuration, the difference in work function between the first conductive portion 11 and the first gate electrode 21 decreases, and the capacitance between the first conductive portion 11 and the first gate electrode 21 increases, compared to when the first conductive portion 11 and the first gate electrode 21 contain impurities of the same conductivity type. Although the capacitance Cgs between the first gate electrode 21 and the source electrode 32 increases, the decrease in capacitance Cgd is greater, and as a result, the input capacitance Ciss of the semiconductor device 100 decreases.

[0034] Preferred impurity concentrations for each element are shown below. p - The p-type impurity concentration in the drift region 1 is 1.0×10 16 atom / cm 3 higher than 1.0×10 18 atom / cm 3 The n-type impurity concentration in the n-type base region 2 is lower than 1.0×10 16 atom / cm 3 higher than 1.0×10 18 atom / cm 3 Lower than p + The p-type impurity concentration in the source region 3 is 1.0×10 17 atom / cm 3 higher than 1.0×10 21 atom / cm 3 The n-type impurity concentration in the first conductive portion 11 is lower than 1.0×10 19 atom / cm 3 higher than 1.0×10 21 atom / cm 3 The p-type impurity concentration in the first gate electrode 21 is lower than 1.0×10 19 atom / cm 3 higher than 1.0×10 21 atom / cm 3 Lower than.

[0035] The impurity concentration in each of the first conductive portion 11 and the first gate electrode 21 is 1.0×10 19atom / cm 3 If the impurity concentration in each of the first conductive portion 11 and the first gate electrode 21 is lower than 1.0×10, they may not function as electrodes. As a result, a decrease in breakdown voltage, an increase in on-resistance, or a threshold fluctuation in the gate voltage for turn-on may occur. 21 atom / cm 3 If the temperature is higher than 1000 volts, impurities may diffuse into the semiconductor region, resulting in a decrease in breakdown voltage, an increase in on-resistance, or a shift in the threshold value of the gate voltage for turn-on.

[0036] Furthermore, in the semiconductor device 100, the first interlayer insulating portion 11b contains both n-type and p-type impurities. The n-type impurity concentration in the first interlayer insulating portion 11b is higher than the n-type impurity concentration in the first insulating portion 11a. The p-type impurity concentration in the first interlayer insulating portion 11b is higher than the p-type impurity concentration in the first insulating portion 11a. This configuration enhances the gettering effect of the first interlayer insulating portion 11b on mobile ions, n-type impurities, p-type impurities, and the like. For example, the first interlayer insulating portion 11b can capture mobile ions from outside the first insulating portion 11a and the first interlayer insulating portion 11b. Impurities that diffuse between the first conductive portion 11 and the first gate electrode 21 can be captured. As a result, fluctuations in the characteristics of the semiconductor device 100 due to the movement of mobile ions or impurities to the first conductive portion 11 or the first gate electrode 21 can be suppressed.

[0037] (Second embodiment) Fig. 7 is a plan view showing a semiconductor device according to a second embodiment, Fig. 8 is an enlarged view of a portion P2 of Fig. 7, and Fig. 9 is a cross-sectional view taken along B1-B2 of Fig. 8. 7 to 9, the semiconductor device 200 according to the second embodiment further includes a second conductive portion 12, a second insulating portion 12a, a second interlayer insulating portion 12b, a second gate electrode 22, and a second gate insulating layer 22a, compared to the semiconductor device 100. In Fig. 8, the source electrode 32 is represented by a dashed line, and part of the second gate insulating layer 22a is omitted.

[0038] As shown in FIG. 7, in the semiconductor device 200, p -The semiconductor device 200 includes a first region r1, a second region r2, a third region r3, and a third region r4. The second region r2 is provided around the first region r1 along the XY plane (first plane). The third region r3 is provided between the first region r1 and the second region r2 in the X direction. The first region r1 and the third region r3 correspond to an element region through which current flows when the semiconductor device 200 is in an on-state. The second region r2 corresponds to a termination region for improving the breakdown voltage of the semiconductor device 200. In the illustrated example, a pair of third regions r3 are provided spaced apart from each other in the X direction. The first region r1 is located between the pair of third regions r3.

[0039] 8, a second gate electrode 22 is provided below the source electrode 32. The second gate electrode 22 is located on the third region r3. The second gate electrode 22 extends in the Y direction along the first gate electrode 21. As shown in the figure, a plurality of second gate electrodes 22 may be provided in the X direction. The end of the second gate electrode 22 in the Y direction is electrically connected to the gate pad 33 via the gate wiring 33a.

[0040] As shown in FIG. 9, the second conductive portion 12 is connected to the p - The second conductive portion 12 is provided in the third region r3 of the n-type drift region 1. The second conductive portion 12 is electrically connected to the source electrode 32. The second gate electrode 22 is provided on the second conductive portion 12 via a second interlayer insulating portion 12b. The second gate electrode 22 faces the n-type base region 2 in the X direction via a second gate insulating layer 22a. In the illustrated example, the second gate electrode 22 is - Part of the drift region 1 and p + The second gate electrode 22 also faces a part of the source region 3. The second gate electrode 22 is electrically isolated from the source electrode 32 by the second gate insulating layer 22a.

[0041] The second conductive portion 12 and the second gate electrode 22 include a conductive material such as polysilicon. The second conductive portion 12 and the second gate electrode 22 include impurities of the same conductivity type. Preferably, p -The drift region 1, the second conductive portion 12, and the second gate electrode 22 contain p-type impurities. For example, the p-type impurity concentration in the second conductive portion 12 is higher than the n-type impurity concentration, and the p-type impurity concentration in the second gate electrode 22 is higher than the n-type impurity concentration.

[0042] The structure of the semiconductor device 200 in the portion P1 shown in FIG. 7 is similar to the structure of the semiconductor device 100 in the portion P1 shown in FIG. 2. The cross-sectional structure of the semiconductor device 200 in the portion P1 is similar to the cross-sectional structure of the semiconductor device 100 shown in FIG. 3. As shown in FIG. 8, the first gate electrode 21 is located on the first region r1. A third conductive portion 13 may be provided in the second region r2 via a third insulating portion 13a. The third conductive portion 13 is electrically connected to the source electrode 32 and contains n-type impurities. For example, in the third conductive portion 13, the n-type impurity concentration is higher than the p-type impurity concentration.

[0043] The conductivity type of the impurities contained in the second conductive portion 12 is p - If the conductivity type is the same as that of the drift region 1, p - The potential difference between the drift region 1 and the second conductive portion 12 becomes smaller. - Compared with the case where the conductivity type of the drift region 1 and the conductivity type of the impurities contained in the second conductive portion 12 are different, - The depletion layer extending toward the first drift region 1 is smaller. Therefore, the on-resistance per unit area in the third region r3 is lower than the on-resistance per unit area in the first region r1. By providing the third region r3 including the second conductive portion 12 and the second gate electrode 22, the on-resistance of the semiconductor device 200 can be reduced compared to the semiconductor device 100 according to the first embodiment.

[0044] In particular, holes spread and accumulate in the second region r2, which is the termination region, during the on-state. When the semiconductor device 200 is turned off, the holes accumulated in the second region r2 move in the direction of the voltage and are discharged from the semiconductor device 200. The time from when the semiconductor device 200 is turned off until the holes accumulated in the second region r2 are discharged affects the switching loss of the semiconductor device 200. Because the on-resistance in the third region r3 is lower than the on-resistance in the first region r1, holes are more easily discharged from the third region r3 than from the first region r1 in the on-state. By providing the third region r3, from which holes are more easily discharged, on the second region r2 side, the spreading and accumulation of holes in the second region r2 in the on-state can be suppressed. As a result, the time until holes are discharged at turn-off is shortened, and the switching loss of the semiconductor device 200 can be reduced.

[0045] In the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0046] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0047] 1:p - Shape drift region, 1a:p - 2: n-type base region; 2a: n-type semiconductor region; 3: p + Shape source area, 3a:p + Shape semiconductor area, 4:n + Shape contact area, 4a:n +Shape semiconductor area, 5:p + Shape drain region, 5a:p + semiconductor layer, 10: conductive layer, 10a, 10b: insulating layer, 11: first conductive portion, 11a: first insulating portion, 11b: first interlayer insulating portion, 12: second conductive portion, 12a: second insulating portion, 12b: second interlayer insulating portion, 13: third conductive portion, 13a: third insulating portion, 20: conductive layer, 20a, 20b: insulating layer, 21: first gate electrode, 21a: first gate insulating layer, 22: second gate electrode, 22a: second gate insulating layer, 31: drain electrode, 31a: metal layer, 32: source electrode, 32a: metal layer, 33: gate pad, 33a: gate wiring, 100, 200: semiconductor device, OP: opening, Sub: semiconductor substrate, T: trench, r1: first region, r2: 2nd area, r3: 3rd area

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode, A first region; a second region provided around the first region along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a third region provided between the first region and the second region in a second direction perpendicular to the first direction; the first semiconductor region including a second semiconductor region of a second conductivity type provided on the first region and the third region and provided in plurality in the second direction; a third semiconductor region of the first conductivity type provided on a portion of each of the second semiconductor regions; a first conductive portion provided in the first region via a first insulating portion and containing impurities of a second conductivity type; a first gate electrode that is provided on the first conductive portion via a first interlayer insulating portion, faces one of the plurality of second semiconductor regions in the second direction via a first gate insulating layer, and contains an impurity of the first conductivity type; a second conductive portion provided in the third region via a second insulating portion and containing impurities of the first conductivity type; a second gate electrode that is provided on the second conductive portion via a second interlayer insulating portion, faces another one of the plurality of second semiconductor regions in the second direction via a second gate insulating layer, and contains an impurity of the first conductivity type; a second electrode provided on the plurality of second semiconductor regions and the plurality of third semiconductor regions, and electrically connected to the plurality of second semiconductor regions, the plurality of third semiconductor regions, the first conductive portion, and the second conductive portion; Equipped with a concentration of impurities of the first conductivity type in the first interlayer insulating portion is higher than a concentration of impurities of the first conductivity type in the first insulating portion; a concentration of the second conductivity type impurity in the first interlayer insulating portion is higher than a concentration of the second conductivity type impurity in the first insulating portion.

2. A plurality of the first conductive portions are provided in the first region of the first semiconductor region via a plurality of the first insulating portions, 2. The semiconductor device according to claim 1, wherein a plurality of the first gate electrodes are provided on the plurality of first conductive portions, respectively, with a plurality of the first interlayer insulating portions interposed therebetween, and each face two or more of the plurality of second semiconductor regions in the second direction, with a plurality of the first gate insulating layers interposed therebetween.

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