Semiconductor element and semiconductor device

Abstract

This semiconductor element is provided with: first and second electrodes which are formed on an element main surface; an insulating layer which is formed on the element main surface; and first and second electrode terminals which are respectively in contact with the first and second electrodes. The insulating layer is provided with: first and second openings; and first and second overlapping parts which are respectively in contact with the first and second openings. The first and second electrodes are respectively exposed from the first and second openings. The first and second overlapping parts respectively overlap the first and second electrodes when viewed in the thickness direction. The first and second electrode terminals are respectively in contact with the first and second electrodes through the first and second openings, while respectively overlapping the first and second overlapping parts when viewed in the thickness direction. The first electrode terminal is provided in a region where the electrode terminal arrangement density is high, while the second electrode terminal is provided in a region where the electrode terminal arrangement density is low. The size of the first overlapping part in the thickness direction is larger than the size of the second overlapping part in the thickness direction.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor elements and semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices have been proposed in which multiple leads and a semiconductor element are bonded in a so-called flip-chip configuration. In such semiconductor devices, electrode terminals are formed on electrodes formed on the principal surface of the semiconductor element by electrolytic plating, and the electrode terminals are bonded to the leads. The electrode terminals may be unevenly distributed on the principal surface of the semiconductor element. For example, the principal surface may have regions where multiple electrode terminals are densely arranged and regions where multiple electrode terminals are isolated from each other. In such cases, the current density in the electrolytic plating differs between the densely arranged region and the sparsely arranged region. As a result, the height of the formed electrode terminals varies. Specifically, in the sparsely arranged region, current concentration is likely to occur, resulting in a high current density. Therefore, the height of the formed electrode terminals is higher in the sparsely arranged region than in the densely arranged region. Variation in the height of the electrode terminals deteriorates coplanarity (uniformity of the mounting surface of the electrode terminals). As a result, low electrode terminals may not be properly bonded to the leads, resulting in poor connection.

[0003] Patent Document 1 discloses a manufacturing method for suppressing variations in the height of electrode terminals in flip-chip bonded semiconductor elements by temporarily placing dummy electrode terminals during manufacturing, even in areas where electrode terminals are sparsely arranged, and then removing them later. However, this method requires forming a base layer including removable portions, temporarily forming dummy electrode terminals, and then removing the dummy electrode terminals in a later process, which complicates the manufacturing process. In addition, the material for the removed dummy electrode terminals is wasted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-189404 A Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above circumstances, one object of the present disclosure is to provide a semiconductor element in which variations in height of electrode terminals are suppressed by a simple method. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure comprises a main surface and a back surface of the device facing opposite each other in a thickness direction; a plurality of electrodes formed on the main surface; an insulating layer formed on the main surface; and a plurality of electrode terminals, each of which contacts one of the plurality of electrodes and partially overlaps the insulating layer when viewed in the thickness direction. The insulating layer has a plurality of openings and a plurality of overlapping portions respectively contacting the plurality of openings, the plurality of openings exposing the plurality of electrodes, and the plurality of overlapping portions respectively overlapping the plurality of electrodes when viewed in the thickness direction. The plurality of electrode terminals contact the plurality of electrodes through the plurality of openings and overlap the plurality of overlapping portions when viewed in the thickness direction. When viewed in the thickness direction, the plurality of electrode terminals include a plurality of first electrode terminals arranged closely together and a plurality of second electrode terminals arranged sparsely together. The thickness direction dimension of the overlapping portions overlapping each of the first electrode terminals is greater than the thickness direction dimension of the overlapping portions overlapping each of the second electrode terminals. [Effects of the Invention]

[0007] According to the present disclosure, the thickness of the overlapping portions overlapping the densely arranged electrode terminals (first electrode terminals) is greater than the thickness of the overlapping portions overlapping the sparsely arranged electrode terminals (second electrode terminals). Therefore, even if the height of each second electrode terminal from the insulating film becomes greater than the height of each first electrode terminal due to current concentration, the variation in height (height from the electrode) between the multiple electrode terminals is suppressed.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 2 is a plan view showing the semiconductor device of FIG. 1, seen through a sealing resin. FIG. [Figure 3] 2 is a plan view showing the semiconductor device of FIG. 1, further showing a semiconductor element in a see-through manner. FIG. [Figure 4] FIG. 2 is a bottom view showing the semiconductor device of FIG. [Figure 5] 1 is a plan view showing a semiconductor element according to a first embodiment of the present disclosure. [Figure 6] FIG. 2 is a front view showing the semiconductor device of FIG. [Figure 7] FIG. 2 is a rear view showing the semiconductor device of FIG. [Figure 8] FIG. 2 is a right side view showing the semiconductor device of FIG. [Figure 9] FIG. 2 is a left side view showing the semiconductor device of FIG. [Figure 10] FIG. 4 is a cross-sectional view taken along line XX in FIG. 3. [Figure 11] FIG. 4 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 4 is a cross-sectional view taken along line XII-XII in FIG. 3. [Figure 13] FIG. 4 is a cross-sectional view taken along line XIII-XIII in FIG. 3. [Figure 14]FIG. 11 is a partially enlarged view of FIG. [Figure 15] FIG. 15 is a partially enlarged cross-sectional view taken along line XV-XV in FIG. [Figure 16] FIG. 11 is a partially enlarged view of FIG. [Figure 17] 10A and 10B are diagrams for explaining differences in the dimensions of electrode terminals due to the density of their arrangement. [Figure 18] 10 is a schematic diagram showing a cross section of a semiconductor device in which variations in height of electrode terminals remain; FIG. [Figure 19] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure, with a sealing resin and a semiconductor element seen through. [Figure 20] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure, seen through a sealing resin. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. [Figure 22] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure, seen through a sealing resin. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 22. [Figure 25] FIG. 10 is a partial plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, seen through a sealing resin. [Figure 26] FIG. 10 is a partial plan view showing a semiconductor device according to a sixth embodiment of the present disclosure, seen through a sealing resin. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0012] First Embodiment 1 to 16 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a plurality of first leads 10A, 10B, and 10C, a plurality of second leads 21, a pair of third leads 22, a semiconductor element 30, and a sealing resin 40. The package format of the semiconductor device A10 is not particularly limited, and in this embodiment, it is a QFN (Quad Flat Non-leaded package) type, as shown in FIG. 1 . The applications and functions of the semiconductor device A10 are not limited in any way. Examples of applications of the semiconductor device A10 include electronic equipment, general industrial equipment, and automotive applications. Examples of functions of the semiconductor device A10 include a DC / DC converter and an AC / DC converter. In this embodiment, the semiconductor device A10 configured as an automotive DC / DC converter will be described as an example.

[0013] FIG. 1 is a perspective view showing a semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outer shape of the sealing resin 40 is shown by an imaginary line (two-dot chain line) through the sealing resin 40. FIG. 3 is a plan view showing the semiconductor device A10. In FIG. 3, for ease of understanding, the outer shapes of the sealing resin 40 and the semiconductor element 30 are shown by an imaginary line (two-dot chain line) through the sealing resin 40 and the semiconductor element 30. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a plan view showing the semiconductor element 30. In FIG. 5, the outer shapes of the multiple electrode terminals 36 are shown by an imaginary line (two-dot chain line) through the insulating layer 35 and the multiple electrode terminals 36. FIG. 6 is a front view showing the semiconductor device A10. FIG. 7 is a rear view showing the semiconductor device A10. FIG. 8 is a right side view showing the semiconductor device A10. FIG. 9 is a left side view showing the semiconductor device A10. FIG. 10 is a cross-sectional view taken along line XX in FIG. 3. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 3. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 3. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 3. Fig. 14 is a partially enlarged view of Fig. 10 (near an electrode terminal 36A, which will be described later). Fig. 15 is a partially enlarged view of Fig. 10 (near an electrode terminal 36B, which will be described later). Fig. 16 is a partially enlarged view of Fig. 10 (near an electrode terminal 36B, which will be described later).

[0014] As shown in Fig. 1, the semiconductor device A10 is plate-shaped. Specifically, the semiconductor device A10 is a hexahedron with a relatively low height (small dimension in the z direction) and has a rectangular shape when viewed in the thickness direction (plan view). For convenience of explanation, the thickness direction of the semiconductor device A10 is defined as the z direction, the direction along one side of the semiconductor device A10 perpendicular to the z direction (the up-down direction in Figs. 2 to 4) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the left-right direction in Figs. 2 to 4) is defined as the y direction. The shape and dimensions of the semiconductor device A10 are not limited.

[0015] As shown in Fig. 2, the multiple first leads 10A, 10B, 10C, the multiple second leads 21, and the pair of third leads 22 support the semiconductor element 30 and serve as terminals for mounting the semiconductor device A10 on a wiring board. As shown in Figs. 10 to 13, each of the multiple first leads 10A, 10B, 10C, the multiple second leads 21, and the pair of third leads 22 is partially covered with sealing resin 40. In Fig. 1 and Figs. 4 to 9, the portions of the multiple first leads 10A, 10B, 10C, the multiple second leads 21, and the pair of third leads 22 that are exposed from the sealing resin 40 are shaded with a plurality of discrete dots.

[0016] The multiple first leads 10A, 10B, and 10C, the multiple second leads 21, and the pair of third leads 22 are formed, for example, by etching a metal plate. Alternatively, the multiple first leads 10A, 10B, and 10C, the multiple second leads 21, and the pair of third leads 22 may be formed by punching or bending a metal plate. The multiple first leads 10A, 10B, and 10C, the multiple second leads 21, and the pair of third leads 22 are arranged spaced apart from each other. The multiple first leads 10A, 10B, and 10C, the multiple second leads 21, and the pair of third leads 22 are made of, for example, Cu or a Cu alloy, but the present disclosure is not limited thereto.

[0017] As shown in FIGS. 3 and 4, each of the multiple first leads 10A, 10B, and 10C has a strip shape extending in the x direction when viewed in the z direction. Each of the multiple first leads 10A, 10B, and 10C has a first main surface 101 and a first back surface 102 facing opposite sides in the z direction. The first main surface 101 faces one side in the z direction and faces the semiconductor element 30. The first main surface 101 is covered with the sealing resin 40. The first back surface 102 faces the other side in the z direction. The first back surface 102 is exposed from the sealing resin 40. In the first leads 10A, 10B, and 10C, the semiconductor element 30 is supported by the first main surface 101. 3 and 4, in the illustrated example, the area of the first main surface 101 of each of the first leads 10A, 10B, and 10C is larger than the area of the first rear surface 102. Each of the first leads 10A, 10B, and 10C has at least one portion (anchor portion) where the first main surface 101 does not overlap the first rear surface 102 when viewed in the z direction. Such an anchor portion can be formed, for example, by half-etching from the first rear surface 102 side. Each of the first leads 10A, 10B, and 10C has one or more anchor portions, which can prevent each lead from falling off the bottom surface 42 of the sealing resin 40 (this effect will be referred to as the "anchoring effect" below).

[0018] The first lead 10A and the first lead 10B receive DC power (voltage) to be converted by the semiconductor device A10. In this embodiment, the first lead 10A is a positive electrode (P terminal). The first lead 10B is a negative electrode (N terminal). The first lead 10C outputs AC power (voltage) converted by a switching circuit 321 of the semiconductor element 30 (described later). As shown in FIG. 3, the multiple first leads 10A, 10B, and 10C are arranged in the y direction from one side to the other in the order of the first lead 10A, the first lead 10C, and the first lead 10B. The first lead 10A is located between the multiple second leads 21 and the first lead 10C in the y direction. The first lead 10C is located between the first lead 10A and the first lead 10B in the y direction.

[0019] As shown in FIGS. 3 and 4 , each of the first leads 10A and 10C includes a main portion 11 and a pair of side portions 12. The main portion 11 extends in the x direction. The pair of side portions 12 are connected to both ends of the main portion 11 in the x direction and have a smaller dimension in the y direction than the main portion 11. Each of the pair of side portions 12 has a first end surface 121. As shown in FIG. 11 , the first end surface 121 is connected to both the first main surface 101 and the first back surface 102 and faces the x direction. The first end surface 121 is exposed from the sealing resin 40.

[0020] As shown in FIGS. 3 and 4, the first lead 10B includes a main portion 11, four side portions 12, and multiple protrusions 13. The main portion 11 extends in the x direction. Two of the side portions 12 are connected to one end of the main portion 11 in the x direction. The other two side portions 12 are connected to the other end of the main portion 11 in the x direction. Each of the four side portions 12 has a first end face 121. As shown in FIG. 12, the first end face 121 is connected to both the first main surface 101 and the first back surface 102 and faces the x direction. The first end face 121 is exposed from the sealing resin 40. The multiple protrusions 13 protrude from the other side of the main portion 11 in the y direction. The sealing resin 40 is filled between two adjacent protrusions 13. Each of the multiple protrusions 13 has a minor end face 131. As shown in FIG. 10, the minor end surface 131 is connected to both the first main surface 101 and the first back surface 102 and faces the other side in the y direction. The minor end surface 131 is exposed from the sealing resin 40. As shown in FIG. 8, the multiple minor end surfaces 131 are arranged at predetermined intervals along the x direction. Note that the first leads 10A, 10B, and 10C are not limited to a shape having a main portion 11 and a side portion 12.

[0021] In each of the first lead 10A, the first lead 10B, and the first lead 10C, the first rear surface 102, the pair of first end faces 121, and the plurality of sub-end faces 131 exposed from the sealing resin 40 may be plated with, for example, Sn. Note that instead of Sn plating, a plurality of metal platings, for example, Ni, Pd, and Au stacked in this order, may be used.

[0022] As shown in FIG. 3, the multiple second leads 21 are located on one side of the first lead 10 in the y direction. One of the multiple second leads 21 is a ground terminal of a control circuit 322 of the semiconductor element 30, which will be described later. To each of the other multiple second leads 21, power (voltage) for driving the control circuit 322 or an electrical signal to be transmitted to the control circuit 322 is input. As shown in FIGS. 3 and 4, each of the multiple second leads 21 has a second main surface 211, a second back surface 212, and a second end surface 213. The shape of the second leads 21 is not limited in any way.

[0023] The second main surface 211 faces the same side in the z direction as the first main surface 101 of the first lead 10 and faces the semiconductor element 30. The second main surface 211 is covered with the sealing resin 40. The semiconductor element 30 is supported by the second main surface 211. The second back surface 212 faces the side opposite the second main surface 211. The second back surface 212 is exposed from the sealing resin 40. The second end surface 213 is connected to both the second main surface 211 and the second back surface 212 and faces one side in the y direction. The second end surface 213 is exposed from the sealing resin 40. As shown in FIG. 9 , the multiple second end surfaces 213 are arranged at predetermined intervals along the x direction. In addition, the two second leads 21 arranged at both ends in the x direction further have fourth end surfaces 214. The fourth end surfaces 214 are surfaces facing the x direction and are exposed from the sealing resin 40. 3 and 4, in each of the multiple second leads 21, the area of the second main surface 211 is larger than the area of the second back surface 212. The portion of each second lead 21 where the second main surface 211 does not overlap the second back surface 212 as viewed in the z direction is formed by, for example, half-etching processing from the second back surface 212 side, and prevents each second lead 21 from falling off from the bottom surface 42 of the sealing resin 40 by an anchoring effect.

[0024] For example, Sn plating may be applied to the second rear surfaces 212, the second end surfaces 213, and the fourth end surfaces 214 of the second leads 21 exposed from the sealing resin 40. Note that instead of Sn plating, multiple metal platings, for example, Ni, Pd, and Au stacked in this order, may be used.

[0025] As shown in FIG. 3, the pair of third leads 22 are located between the first lead 10A and the plurality of second leads 21 in the y direction. The pair of third leads 22 are spaced apart from each other in the x direction. An electrical signal or the like is input to each of the pair of third leads 22 to be transmitted to a control circuit 322 configured in the semiconductor element 30. As shown in FIGS. 3 and 4, each of the pair of third leads 22 has a third main surface 221, a third back surface 222, and a third end surface 223. The shape of the third lead 22 is not limited in any way.

[0026] The third main surface 221 faces the same side in the z direction as the first main surface 101 of the first lead 10 and faces the semiconductor element 30. The third main surface 221 is covered with the sealing resin 40. The semiconductor element 30 is supported by the third main surface 221. The third back surface 222 faces the side opposite to the third main surface 221. The third back surface 222 is exposed from the sealing resin 40. The third end surface 223 is connected to both the third main surface 221 and the third back surface 222 and faces the x direction. The third end surface 223 is exposed from the sealing resin 40. The third end surface 223 is arranged along the y direction together with the first end surface 121 of each first lead 10. In the illustrated example, in each of a pair of third leads 22, the area of the third main surface 221 is larger than the area of the third back surface 222. The portion of each third lead 22 where the third main surface 221 does not overlap the third back surface 222 when viewed in the z direction is formed, for example, by half-etching processing from the third back surface 222 side, and prevents each third lead 22 from falling off from the bottom surface 42 of the sealing resin 40 by an anchoring effect.

[0027] For example, Sn plating may be applied to the third rear surfaces 222 and the third end surfaces 223 of the pair of third leads 22 exposed from the sealing resin 40. Note that instead of Sn plating, multiple metal platings, for example, Ni, Pd, and Au stacked in this order, may be used.

[0028] The first leads 10A, 10B, and 10C, the second leads 21, and the pair of third leads 22 may each have a plurality of recesses recessed in the z direction from the main surfaces 101, 211, and 221. The recesses can be formed, for example, by half-etching from the main surfaces 101, 211, and 221. The recesses have inner surfaces that adhere closely to the sealing resin 40, thereby improving adhesion between each lead and the sealing resin 40. The recesses can also be used for positioning the semiconductor element 30 as viewed in the z direction (positioning in the xy plane). The number, shape, and arrangement of the first leads 10A, 10B, and 10C, the second leads 21, and the third leads 22 are not limited.

[0029] As shown in FIG. 2, the semiconductor element 30 is disposed in the center of the semiconductor device A10 when viewed in the z direction. As shown in FIGS. 10 to 16, the semiconductor element 30 is supported by a plurality of first leads 10A, 10B, and 10C, a plurality of second leads 21, and a pair of third leads 22. The semiconductor element 30 is covered with a sealing resin 40. The semiconductor element 30 has a semiconductor substrate 31, a semiconductor layer 32, a passivation film 33, electrodes 34, an insulating layer 35, and a plurality of electrode terminals 36. The semiconductor element 30 is a flip-chip type LSI having a circuit configured therein.

[0030] The semiconductor element 30 has a rectangular shape when viewed in the z direction as shown in FIG. 2, and a plate shape as shown in FIGS. 10 to 13. The semiconductor element 30 has an element main surface 30a and an element back surface 30b. The element main surface 30a faces the first main surfaces 101 of the first leads 10A, 10B, and 10C, the second main surfaces 211 of the second leads 21, and the third main surfaces 221 of the pair of third leads 22 in the z direction. The element back surface 30b faces the opposite side of the element main surface 30a in the z direction. As shown by the dashed line in FIG. 2, the element main surface 30a includes a first region 301 and a second region 302. The first region 301 is a region of the element main surface 30a that includes portions facing the first main surfaces 101 of the first leads 10A, 10B, and 10C, and is located on the other end side in the y direction (the right side in FIG. 2). The second region 302 is a region of the element main surface 30a that includes portions that face the second main surfaces 211 of the multiple second leads 21 and the third main surfaces 221 of the pair of third leads 22, and is located on one end side in the y direction (the left side in Figure 2).

[0031] 14 to 16, a semiconductor layer 32, a passivation film 33, an electrode 34, an insulating layer 35, and a plurality of electrode terminals 36 are provided on the lower side of the semiconductor substrate 31 in the z direction. The semiconductor substrate 31 is made of, for example, silicon (Si) or silicon carbide (SiC). In this embodiment, one surface of the semiconductor substrate 31 constitutes the element back surface 30b.

[0032] As shown in FIGS. 10 to 13, the semiconductor layer 32 is stacked on the semiconductor substrate 31 on the side facing the first main surface 101 of the first lead 10 in the z direction. The semiconductor layer 32 includes multiple types of p-type and n-type semiconductors based on differences in the amounts of doped elements. The semiconductor layer 32 includes a switching circuit 321 and a control circuit 322 that is electrically connected to the switching circuit 321. The switching circuit 321 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the example shown in semiconductor device A10, the switching circuit 321 is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is configured with one n-channel MOSFET. The control circuit 322 includes a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 321, and the like, and performs control for normally driving the switching circuit 321. Note that a wiring layer (not shown) is further formed in the semiconductor layer 32. The wiring layer provides mutual conduction between the switching circuit 321 and the control circuit 322.

[0033] 14 to 16, the passivation film 33 covers the lower surface of the semiconductor layer 32. The passivation film 33 has electrical insulation properties. The passivation film 33 is composed of, for example, a silicon oxide film (SiO2) in contact with the lower surface of the semiconductor layer 32 and a silicon nitride film (Si3N4) laminated on the silicon oxide film. In this embodiment, one surface of the passivation film 33 constitutes the element main surface 30a.

[0034] As shown in FIG. 5, a plurality of electrodes 34 are formed on the element principal surface 30a. The shape of the plurality of electrodes 34 formed in the first region 301 as viewed in the z direction is, for example, triangular or rhomboidal, and is elongated in the y direction. In this embodiment, a plurality of isosceles triangular electrodes 34 with their apex angles facing one side in the y direction (left side in FIG. 5) are arranged side by side at equal intervals in the x direction near an end of the first region 301 on the other side in the y direction (right side in FIG. 5). Another plurality of isosceles triangular electrodes 34 are arranged side by side in the x direction near an end of the first region 301 on one side in the y direction with their apex angles facing the other side in the y direction. The electrode 34 arranged on the other side in the y direction and the electrode 34 arranged on one side in the y direction are arranged with their apex angles facing each other. A rhomboid-shaped electrode 34 is arranged in each gap between the plurality of electrodes 34 arranged on the other side in the y direction and the plurality of electrodes 34 arranged on one side in the y direction. The electrodes 34 arranged on the other side in the y direction are electrically connected to the first lead 10B via the respective electrode terminals 36. The electrodes 34 arranged on one side in the y direction are electrically connected to the first lead 10A via the respective electrode terminals 36. The electrodes 34 arranged in each gap are electrically connected to the first lead 10C via the respective electrode terminals 36. The shape of the multiple electrodes 34 formed in the second region 302 as viewed in the z direction is, for example, rectangular. In the second region 302, the multiple electrodes 34 are each arranged in isolation. Some of the electrodes 34 arranged in the second region 302 are electrically connected to the second lead 21 or the third lead 22 via the respective electrode terminals 36. Note that the shape and arrangement of each of the multiple electrodes 34 as viewed in the z direction are not limited. Slits (gaps) are provided between adjacent electrodes 34. FIG. 5 shows a slit having a line-segment planar shape. The planar shape of the slit is not limited to a line-segment shape. The planar shape of the slit may be a wavy line, a zigzag line, or the like.

[0035] As shown in FIGS. 14 to 16, each electrode 34 is connected to a wiring layer formed on the semiconductor layer 32 through an opening (not shown) provided in the passivation film 33. As a result, the electrode 34 is electrically connected to either the switching circuit 321 or the control circuit 322 of the semiconductor layer 32. In this embodiment, the electrode 34 is formed of a plurality of metal layers stacked downward from the passivation film 33, and includes a first layer 34a, a second layer 34b, and a third layer 34c. The first layer 34a is in contact with the passivation film 33 and is made of Cu. The second layer 34b is in contact with the first layer 34a and is made of Ni. The third layer 34c is in contact with the second layer 34b and is made of Pd. The configuration of the electrodes 34 is not limited.

[0036] As shown in FIGS. 14 to 16 , the insulating layer 35 is formed on the element principal surface 30 a and covers the passivation film 33 and a portion of the electrode 34. The insulating layer 35 has electrical insulation properties. In this embodiment, the insulating layer 35 is made of a phenolic resin. However, the insulating layer 35 may be made of any other insulating material, such as a polyimide resin. The insulating layer 35 has a plurality of openings 35 a. One of the electrodes 34 is exposed through each of the openings 35 a. The insulating layer 35 also has a plurality of overlapping portions 35 b. Each of the overlapping portions 35 b contacts one of the openings 35 a and overlaps a portion of the electrode 34 exposed through the opening 35 a when viewed in the z direction. The insulating layer 35 is formed, for example, by applying photolithography to a photosensitive resin material applied by a spin coater.

[0037] As shown in Figures 10 to 13, the multiple electrode terminals 36 are provided on the element main surface 30a side in the z direction, and protrude toward the first main surface 101, the second main surface 211, and the third main surface 221. Also, as shown in Figures 14 to 16, each of the multiple electrode terminals 36 contacts one of the electrodes 34 through an opening 35a in the insulating layer 35, and partially overlaps the overlapping portion 35b of the insulating layer 35 as viewed in the z direction. Each electrode terminal 36 contacts the electrode 34 at its center as viewed in the z direction, and overlaps the overlapping portion 35b at its peripheral edge. The multiple electrode terminals 36 are conductive.

[0038] As shown in FIGS. 14 to 16 , the plurality of electrode terminals 36 include pillar portions 361 and solder portions 362. The pillar portions 361 include a seed layer 361a, a first plating layer 361b, and a second plating layer 361c. The seed layer 361a is in contact with the electrode 34 and the insulating layer 35 and contains Cu. The seed layer 361a is formed, for example, by electroless plating. Note that the constituent material and formation method of the seed layer 361a are not limited. For example, the seed layer 361a may be formed by sputtering. The first plating layer 361b is laminated on the seed layer 361a and is made of, for example, Cu or a Cu alloy. The first plating layer 361b is formed by electrolytic plating. Note that the constituent material of the first plating layer 361b is not limited. The second plating layer 361c is laminated on the first plating layer 361b. The second plating layer 361c is interposed between the first plating layer 361b and the solder portion 362 and functions to suppress a chemical reaction between the first plating layer 361b and the solder portion 362. The constituent material of the second plating layer 361c is not particularly limited, and a metal capable of suppressing the chemical reaction is appropriately selected, such as Ni or Fe. In this embodiment, the first plating layer 361b contains Cu and the solder portion 362 contains Sn, so the second plating layer 361c is made of, for example, Ni. In this embodiment, the second plating layer 361c is formed by electrolytic plating. The constituent material and formation method of the second plating layer 361c are not limited. Furthermore, the second plating layer 361c is not necessarily required. A recess 361d is formed in the tip surface of the pillar portion 361 (the surface facing away from the electrode 34 and facing the first main surface 101, the second main surface 211, and the third main surface 221), with the center portion recessed from the periphery.

[0039] The solder portion 362 is conductive and is interposed between the pillar portion 361 and any one of the first main surfaces 101 of the multiple first leads 10A, 10B, and 10C, the second main surfaces 211 of the multiple second leads 21, and the third main surface 221 of the third lead 22, thereby electrically connecting them to one another. In this embodiment, the solder portion 362 is made of, for example, a solder containing Sn (such as SnAg). In this embodiment, a solder layer in contact with the pillar portion 361 is formed in advance by electrolytic plating (see FIG. 17 , which will be described later). When the semiconductor element 30 is mounted on the first leads 10A, 10B, and 10C, the second lead 21, and the third lead 22, the solder layer goes through a molten state and becomes the solder portion 362. The constituent material and the method for forming the solder portion 362 are not limited.

[0040] The plurality of electrode terminals 36 includes a plurality of electrode terminals 36A and a plurality of electrode terminals 36B.

[0041] The electrode terminals 36A are electrically connected to the switching circuit 321 of the semiconductor layer 32. The electrode terminals 36A are connected to the first main surfaces 101 of the first leads 10A, 10B, and 10C. This electrically connects the first leads 10A, 10B, and 10C to the switching circuit 321. The shape (planar shape) of the electrode terminals 36A as viewed in the z direction is not limited, and a circular shape, an elliptical shape (oval shape), a rectangular shape, a polygonal shape, or the like may be selected as appropriate. In the illustrated example, the electrode terminals 36A have the same elliptical shape as viewed in the z direction. As shown in FIG. 5, the electrode terminals 36A are formed so that their longitudinal direction (direction of the major axis) is parallel to the longitudinal direction of the electrodes 34. In this embodiment, the longitudinal direction of the electrode terminals 36A is perpendicular to the extension direction of the first leads 10A, 10C, and 10B. The relationship between the longitudinal direction of the electrode terminal 36A and the direction in which the first leads 10A, 10C, and 10B extend is not limited to this. The dimensions of the electrode terminal 36A are not limited in any way, and for example, the major axis (dimension in the y direction) is 300 μm, and the minor axis (dimension in the x direction) is 100 μm.

[0042] As indicated by dashed lines in FIG. 2, the plurality of electrode terminals 36A are arranged in a first region 301 of the element principal surface 30a. In the first region 301, the plurality of electrode terminals 36A are densely arranged, and the ratio of the area of the electrode terminals 36 (36A) to the area of the region is relatively high. For example, as a non-limiting example, in the first region 301, the maximum dimension in a plan view (e.g., the dimension in the y direction) of each electrode terminal 36 is greater than the separation distance between the electrode terminal and the adjacent electrode terminal 36. In other words, the first region 301 is a region in which the plurality of electrode terminals 36 are densely arranged. In this way, since the electrode terminals 36 are formed to be densely arranged in the first region 301, the current density during electrolytic plating is relatively low. Therefore, the height dimension (dimension in the z direction) Ya of the pillar portion 361 from the insulating layer 35 (see FIGS. 14, 15, and 17) is relatively small.

[0043] In this embodiment, the insulating layer 35 formed in the first region 301 is formed to be relatively thick. Therefore, as shown in Figures 14, 15, and 17, the thickness dimension (dimension in the z direction) Xa of the overlapping portion 35b that overlaps the electrode terminal 36A when viewed in the z direction is relatively large.

[0044] As indicated by dashed lines in FIG. 2 , the electrode terminals 36B are arranged in the second region 302 of the element principal surface 30a. The electrode terminals 36B are electrically connected to the control circuit 322 of the semiconductor layer 32. Most of the electrode terminals 36B are connected to the second principal surfaces 211 of the second leads 21. The remaining electrode terminals 36B are connected to the third principal surfaces 221 of the pair of third leads 22. This electrically connects the second leads 21 and the pair of third leads 22 to the control circuit 322. The shape (planar shape) of the electrode terminals 36B as viewed in the z direction is not limited in any way, and may be a circle, an oval, a rectangle, a polygon, or the like, as appropriate. In the illustrated example, the electrode terminal 36B is circular as viewed in the z direction. The dimensions of the electrode terminal 36B are not limited in any way, and the diameter is, for example, 100 μm.

[0045] The area (planar area) of each electrode terminal 36 in a plan view will be described. The planar area of each electrode terminal 36A arranged in the first region 301 is set to be larger than the planar area of each electrode terminal 36B arranged in the second region 302. The planar area of each electrode terminal 36 corresponds to the fact that the value of the current flowing through one electrode terminal 36A is larger than the value of the current flowing through one electrode terminal 36B. Generally, a plurality of electrode terminals 36A are formed in the first region 301 where power system elements, for example, power transistors, are arranged. Generally, a plurality of electrode terminals 36B are formed in the second region 302 where logic system elements are arranged.

[0046] The shape (planar shape) of each electrode terminal when viewed from above will be described. The planar shape of the electrode terminal 36A arranged in the first region 301 is preferably an elongated rectangle or the like, in addition to the ellipse described above. The planar shape of the electrode terminal 36B arranged in the second region 302 is preferably a square or a rectangle close to a square, in addition to the circle described above. By setting the shape of each electrode terminal 36 in this manner, the ratio of the total area of the electrode terminals 36A formed per unit area to the total area of the electrode terminals 36B can be increased. Therefore, the ratio of the sum of the current values flowing through the multiple electrode terminals 36A to the sum of the current values flowing through the multiple electrode terminals 36B can be increased. The value of the current flowing through the multiple electrode terminals 36B per unit area can be increased.

[0047] In the second region 302, the plurality of electrode terminals 36B are arranged in isolation from one another, and the ratio of the area of the electrode terminals 36 (36B) to the area of the region is relatively low. That is, the second region 302 is a region in which the plurality of electrode terminals 36 are sparsely arranged. For example, as a non-limiting example, in the second region 302, the maximum dimension (e.g., diameter) in a plan view of each electrode terminal 36 is smaller than the distance between the electrode terminal 36 and the adjacent electrode terminal 36. In this way, since the electrode terminals 36 are sparsely arranged in the second region 302, the current density during electrolytic plating is relatively high. Therefore, the height dimension (dimension in the z direction) Yb of the pillar portion 361 from the insulating layer 35 (see FIGS. 16 and 17) is relatively large.

[0048] In this embodiment, the insulating layer 35 formed in the second region 302 is formed to be relatively thin. Therefore, as shown in Figures 16 and 17, the thickness dimension (dimension in the z direction) Xb of the overlapping portion 35b that overlaps the electrode terminal 36B as viewed in the z direction is relatively small.

[0049] A region where a plurality of electrode terminals 36 are densely arranged has an aspect in which a plurality of electrode terminals 36 having the same planar shape and the same planar area are densely arranged. Additionally, a region where a plurality of electrode terminals 36 are densely arranged has an aspect in which, in a region where a plurality of electrode terminals 36 having different planar shapes and different planar areas are arranged, the ratio of the total area of the plurality of electrode terminals 36 to the total area of the region is relatively large. Conversely, a region where a plurality of electrode terminals 36 are sparsely arranged has an aspect in which a plurality of electrode terminals 36 having the same planar shape and the same planar area are sparsely arranged. Additionally, a region where a plurality of electrode terminals 36 are sparsely arranged has an aspect in which, in a region where a plurality of electrode terminals 36 having different planar shapes and different planar areas are arranged, the ratio of the total area of the plurality of electrode terminals 36 to the total area of the region is relatively small.

[0050] Fig. 17 is a diagram for explaining differences in the dimensions of the electrode terminals 36 due to the density of their arrangement. Fig. 17 shows a partially enlarged cross-sectional view of the semiconductor element 30 before it is mounted. The upper left is a partially enlarged cross-sectional view of the vicinity of electrode terminals 36A that are densely arranged in the first region 301, and corresponds to Fig. 15. The upper right is a partially enlarged cross-sectional view of the vicinity of electrode terminals 36B that are sparsely arranged in the second region 302, and corresponds to Fig. 16.

[0051] The height dimension Ya of the pillar portion 361 of the electrode terminal 36A from the insulating layer 35 is smaller than the height dimension Yb of the pillar portion 361 of the electrode terminal 36B from the insulating layer 35 (Ya < Yb). Also, since the solder layer 363 in contact with the pillar portion 361 is formed by electrolytic plating in the same manner as the pillar portion 361, the height dimension Za of the electrode terminal 36A including the solder layer 363 from the insulating layer 35 is smaller than the height dimension Zb of the electrode terminal 36B including the solder layer 363 from the insulating layer 35 (Za < Zb). On the other hand, in the present embodiment, the thickness dimension Xa of the overlapping portion 35b overlapping the electrode terminal 36A is set to be larger than the thickness dimension Xb of the overlapping portion 35b overlapping the electrode terminal 36B (Xa > Xb). Therefore, the height dimension (Xa + Za) of the electrode terminal 36A from the electrode 34 approaches the height dimension (Xb + Zb) of the electrode terminal 36B from the electrode 34. The thickness dimensions Xa and Xb are set to cancel out the difference between the height dimension Za and the height dimension Zb so that the height dimension (Xa + Za) becomes approximately the same as the height dimension (Xb + Zb).

[0052] As shown in FIGS. 14 to 16, the plating layer 60 is interposed between any one of the first main surfaces 101 of the plurality of first leads 10A, 10B, 10C, the second main surfaces 211 of the plurality of second leads 21, and the third main surface 221 of the third lead 22 and the solder portion 362 of the electrode terminal 36, and electrically connects them to each other. The plating layer 60 functions to suppress the chemical reaction between the first leads 10A, 10B, 10C, the second leads 21, the third lead 22, and the solder portion 362. The constituent material of the plating layer 60 is not particularly limited, and a metal capable of suppressing the chemical reaction is appropriately selected, for example, Ni, Fe, etc. In the illustrated example, the plating layer 60 is provided so as to cover a part of the first main surface 101, the second main surface 211, and the third main surface 221, and is not configured to cover the entire first main surface 101, the second main surface 211, and the third main surface 221.

[0053] In this embodiment, the plating layer 60 has a first layer 61, a second layer 62, and a third layer 63. The first layer 61 is laminated on any one of the first main surfaces 101 of the first leads 10A, 10B, and 10C, the second main surfaces 211 of the second leads 21, and the third main surface 221 of the third lead 22. In this embodiment, the first leads 10A, 10B, and 10C, the second leads 21, and the third lead 22 contain Cu, and the solder portion 362 contains Sn. Therefore, the first layer 61 is made of, for example, Ni. The second layer 62 is laminated on the first layer 61. The constituent material of the second layer 62 is not particularly limited and may include, for example, Pd. The third layer 63 is laminated on the second layer 62. The constituent material of the third layer 63 is not particularly limited and may include, for example, Au. The method for forming the plating layer 60 is not particularly limited. Furthermore, the plating layer 60 is not necessarily required.

[0054] The shape (planar shape) of the plating layer 60 as viewed in the z direction is not limited in any way. As shown in FIGS. 2, 3, 14, and 15, in the illustrated example, the plating layer 60 corresponding to the electrode terminal 36A all has an oval shape as viewed in the z direction (planar shape). On the other hand, as shown in FIGS. 2, 3, and 16, the plating layer 60 corresponding to the electrode terminal 36B all has a circular shape as viewed along the z direction. Also, as shown in FIGS. 14 to 16, in this embodiment, the electrode terminal 36 is enclosed within the plating layer 60 as viewed in the z direction. In the illustrated example, the plating layer 60 has a third layer 63, and the third layer 63 has relatively good wettability with solder. In this case, the solder portion 362 has a shape in which the area of a cross section perpendicular to the z direction increases from the pillar portion 361 toward the plating layer 60 in the z direction. The solder portion 362 has a solder fillet. This ensures a reliable connection between the electrode terminal 36 and the plating layer 60.

[0055] The sealing resin 40 covers the entire semiconductor element 30, the multiple first leads 10A, 10B, and 10C, the multiple second leads 21, and a portion of each of the pair of third leads 22. The sealing resin 40 is made of a material containing, for example, black epoxy resin. The material of the sealing resin 40 is not limited. The sealing resin 40 has a rectangular shape when viewed in the z direction, and has a top surface 41, a bottom surface 42, a pair of first side surfaces 431, and a pair of second side surfaces 432, as shown in FIGS. 6 to 9 .

[0056] 10 to 13, the top surface 41 faces the same side in the z direction as the first main surfaces 101 of the multiple first leads 10A, 10B, and 10C. As shown in FIGS. 6 to 9, the bottom surface 42 faces the opposite side to the top surface 41. As shown in FIG. 4, the first rear surfaces 102 of the multiple first leads 10A, 10B, and 10C, the second rear surfaces 212 of the multiple second leads 21, and the third rear surfaces 222 of the pair of third leads 22 are exposed from the bottom surface 42.

[0057] 8 and 9, the pair of first side surfaces 431 are connected to both the top surface 41 and the bottom surface 42 and face in the x direction. The pair of first side surfaces 431 are spaced apart in the x direction. As shown in FIGS. 6, 7, and 11 to 13, the first end surfaces 121 of the plurality of first leads 10A, 10B, and 10C, the fourth end surface 214 of the second lead 21, and the third end surface 223 of the third lead 22 are exposed from each of the pair of first side surfaces 431 so as to be flush with the first side surfaces 431.

[0058] As shown in FIGS. 6 and 7 , the pair of second side surfaces 432 are connected to all of the top surface 41, the bottom surface 42, and the pair of first side surfaces 431 and face in the y direction. The pair of second side surfaces 432 are spaced apart in the y direction. As shown in FIG. 10 , the second end surfaces 213 of the multiple second leads 21 are exposed from the second side surface 432 located on one side in the y direction so as to be flush with the second side surface 432. The multiple minor end surfaces 131 of the first lead 10B are exposed from the second side surface 432 located on the other side in the y direction so as to be flush with the second side surface 432.

[0059] Next, the effects of the semiconductor device A10 will be described.

[0060] According to this embodiment, the thickness Xa of the overlapping portions 35b that overlap the densely arranged electrode terminals 36A in the first region 301 is relatively large and is larger than the thickness Xb of the overlapping portions 35b that overlap the sparsely arranged electrode terminals 36B in the second region 302. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density in electrolytic plating, the difference between the height (Xa+Za) of the electrode terminal 36A from the electrode 34 and the height (Xb+Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0061] When the dimensions of the electrode terminals 36A and 36B were measured in an actual semiconductor element 30, the average height Za of the electrode terminals 36A from the insulating layer 35 was 68.0 μm, and the average height Zb of the electrode terminals 36B from the insulating layer 35 was 74.0 μm, a difference of 6.0 (74.0-68.0) μm. Meanwhile, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A was 10.2 μm, and the thickness Xb of the overlapping portion 35b overlapping the electrode terminal 36B was 6.5 μm. Therefore, the height dimension (Xa+Za) of electrode terminal 36A from insulating layer 35 was 78.2 (68.0+10.2) μm, and the height dimension (Xb+Zb) of electrode terminal 36B from insulating layer 35 was 80.5 (74.0+6.5) μm, with a difference of 2.3 (80.5-78.2) μm. In other words, the variation in height due to differences in current density in electrolytic plating was canceled out by the difference in thickness of overlapping portion 35b, and the variation in height of electrode terminal 36 from electrode 34 was suppressed.

[0062] As described above, variations in height of the electrode terminals 36 are suppressed, but variations in height may still remain. According to this embodiment, as shown in FIG. 2, the electrode terminal 36A is formed in the first region 301, and the electrode terminal 36B is formed in the second region 302. The first region 301 is disposed on the other end side of the element main surface 30a in the y direction (the right side in FIG. 2), and the second region 302 is disposed on one end side of the element main surface 30a in the y direction (the left side in FIG. 2). Therefore, the arrangement of the first region 301 and the second region 302 is asymmetric in the y direction. As a result, even if one of the electrode terminals 36A and 36B is higher than the other, the semiconductor element 30 is joined in a state inclined with respect to a plane perpendicular to the z direction, thereby suppressing the occurrence of connection defects.

[0063] FIG. 18 is a schematic diagram showing a cross section of a semiconductor device A10 in the case where there is still variation in the height of the electrode terminals 36. FIG. 18 shows a state in which, for example, the insulating layer 35 formed in the first region 301 is insufficiently thick, causing the height of the electrode terminal 36A to be lower than the height of the electrode terminal 36B. Even in this state, by bonding the semiconductor element 30 in an inclined state, each electrode terminal 36A is bonded to the first leads 10A, 10B, and 10C, respectively, thereby suppressing the occurrence of connection defects. Note that in FIG. 18, the difference in height of the electrode terminals 36 and the inclination of the semiconductor element 30 are made extremely large in order to explain the above-mentioned effect.

[0064] According to this embodiment, the pillar portion 361 includes a second plating layer 361c made of Ni at a position where the pillar portion 361 contacts the solder portion 362. Therefore, a chemical reaction between the first plating layer 361b containing Cu and the solder portion 362 containing Sn is suppressed. This suppresses the formation of voids at the bonding interface between the pillar portion 361 and the solder portion 362, thereby reducing the occurrence of cracks. Furthermore, according to this embodiment, the plating layer 60 containing Ni is interposed between the first main surfaces 101 of the multiple first leads 10A, 10B, and 10C, the second main surfaces 211 of the multiple second leads 21, and the third main surface 221 of the third lead 22 and the solder portion 362 of the electrode terminal 36. Therefore, a chemical reaction between the first leads 10A, 10B, and 10C, the second lead 21, and the third lead 22 containing Cu and the solder portion 362 containing Sn is suppressed. This prevents voids from being generated at the bonding interfaces between the first leads 10A, 10B, 10C, the second lead 21, and the third lead 22 and the solder portion 362, thereby reducing the occurrence of cracks.

[0065] According to this embodiment, the semiconductor element 30 is mounted on the plurality of first leads 10A, 10B, and 10C, the plurality of second leads 21, and the pair of third leads 22 by so-called flip-chip bonding. Therefore, compared to a semiconductor device in which each electrode 34 and each lead are electrically connected by wires, the resistance of the conductive path can be reduced and a thinner device can be achieved. Furthermore, when viewed in plan, if the outer size of the sealing resin 40 is the same, a larger semiconductor element 30 can be mounted, and if the same semiconductor element 30 is mounted, the outer size of the sealing resin 40 can be made smaller.

[0066] 19 to 26 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0067] Second Embodiment Fig. 19 is a diagram illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. Fig. 19 is a plan view showing the semiconductor device A20, and corresponds to Fig. 3. In Fig. 19, for ease of understanding, the outer shapes of the sealing resin 40 and the semiconductor element 30 are shown by imaginary lines (two-dot chain lines) through the sealing resin 40 and the semiconductor element 30. The semiconductor device A20 of this embodiment differs from the first embodiment in that the semiconductor element 30 further includes a plurality of electrode terminals 36C.

[0068] In this embodiment, the semiconductor element 30 further includes a plurality of electrode terminals 36C. The electrode terminals 36C have the same structure as the electrode terminals 36A and 36B. The electrode terminals 36C are arranged in the second region 302 of the element main surface 30a. However, the electrode terminals 36C are "dummy electrode terminals" that are not connected to any of the first leads 10A, 10B, and 10C, the second lead 21, and the third lead 22. In contrast, each of the electrode terminals 36A and 36B is a "functional electrode terminal" that is connected to one of the leads. The shape (planar shape) of the electrode terminals 36C as viewed in the z direction is not limited, but a larger area is preferable, and in this embodiment, the electrode terminals 36C are oval. The electrode terminals 36C are provided to increase the area of the electrode terminals 36 arranged in the second region 302, thereby suppressing the current density during electrolytic plating. This allows the height dimension Zb of the electrode terminal 36B from the insulating layer 35 (the height dimension Yb of the pillar portion 361 from the insulating layer 35) to be smaller than when the electrode terminal 36C is not provided.

[0069] In this embodiment, too, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A is greater than the thickness Xb of the overlapping portion 35b overlapping the electrode terminals 36B and 36C. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density during electrolytic plating, the difference between the height (Xa + Za) of the electrode terminal 36A from the electrode 34 and the height (Xb + Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0070] According to this embodiment, since the electrode terminal 36C is provided in the second region 302, the total area of the electrode terminals 36 arranged in the second region 302 is increased, and the current density during electrolytic plating is reduced. As a result, the height dimension Zb of the electrode terminal 36B from the insulating layer 35 is smaller than when the electrode terminal 36C is not provided. Therefore, variation in the height of the electrode terminals 36 can be reduced.

[0071] Third Embodiment 20 and 21 are diagrams illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 20 is a plan view showing the semiconductor device A30 and corresponds to FIG. 2. In FIG. 20, for ease of understanding, the outline of the sealing resin 40 is shown by an imaginary line (two-dot chain line) through the sealing resin 40. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20 and corresponds to FIG. 10. The semiconductor device A30 of this embodiment differs from the first embodiment in the arrangement of the electrode terminals 36 on the semiconductor element 30.

[0072] The semiconductor device A30 does not include a first lead 10B, but instead includes a plurality of second leads 21 and a pair of third leads 22. As indicated by the dashed lines in FIG. 20 , the element main surface 30a further includes a third region 303. The first region 301 is disposed at the center in the y direction, the second region 302 is disposed at one end in the y direction, and the third region 303 is disposed at the other end in the y direction. Similar to the second region 302, the third region 303 is also provided with a plurality of electrode terminals 36B connected to the second lead 21 or the third lead 22. In the third region 303, the plurality of electrode terminals 36B are disposed in isolation from one another, and the ratio of the area of the electrode terminals 36 (36B) to the area of the region is relatively low. In other words, the third region 303 is a region in which the plurality of electrode terminals 36 are sparsely disposed. In this embodiment, the second region 302 and the third region 303, in which the plurality of electrode terminals 36 are sparsely arranged, are arranged on opposite sides of the first region 301, in which the plurality of electrode terminals 36 are densely arranged, in the y direction. In other words, the arrangement of the region in which the plurality of electrode terminals 36 are sparsely arranged and the region in which they are densely arranged is symmetrical in the y direction.

[0073] In this embodiment, too, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A is greater than the thickness Xb of the overlapping portion 35b overlapping the electrode terminal 36B. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density in electrolytic plating, the difference between the height (Xa + Za) of the electrode terminal 36A from the electrode 34 and the height (Xb + Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0074] In this embodiment, the regions where the electrode terminals 36 are sparsely arranged and the regions where they are densely arranged are symmetrical in the y direction, which is preferable from the viewpoint of stress compared to a case where the regions where the electrode terminals 36 are sparsely arranged and the regions where they are densely arranged are asymmetrical.

[0075] <Fourth embodiment> 22 to 24 are diagrams illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 22 is a plan view showing the semiconductor device A40 and corresponds to FIG. 2. In FIG. 22, for ease of understanding, the outline of the sealing resin 40 is shown by an imaginary line (two-dot chain line) through the sealing resin 40. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22 and corresponds to FIG. 10. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 22 and corresponds to FIG. 11. The semiconductor device A40 of this embodiment differs from the first embodiment in the arrangement of the electrode terminals 36 on the semiconductor element 30.

[0076] The semiconductor device A30 does not include a first lead 10B, and instead further includes a plurality of second leads 21 and a pair of third leads 22. As indicated by the dashed lines in Fig. 22, a first region 301 in which a plurality of electrode terminals 36 are densely arranged is disposed at the center of the element main surface 30a, and a second region 302 in which a plurality of electrode terminals 36 are sparsely arranged is disposed so as to surround the periphery of the first region 301. In other words, the arrangement of the region in which a plurality of electrode terminals 36 are sparsely arranged and the region in which they are densely arranged is symmetrical in the y direction and also symmetrical in the x direction.

[0077] In this embodiment, too, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A is greater than the thickness Xb of the overlapping portion 35b overlapping the electrode terminal 36B. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density in electrolytic plating, the difference between the height (Xa + Za) of the electrode terminal 36A from the electrode 34 and the height (Xb + Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0078] In this embodiment, the arrangement of the region where the electrode terminals 36 are sparsely arranged and the region where they are densely arranged are symmetrical in the x and y directions, which is preferable from the viewpoint of stress compared to a case where the arrangement of the region where the electrode terminals 36 are sparsely arranged and the region where they are densely arranged are asymmetrical.

[0079] As shown in the third and fourth embodiments, by adjusting the thickness dimension of the overlapping portion 35b of the insulating layer 35, it is possible to suppress variations in the height of the electrode terminals 36, so there is no need to asymmetrically arrange the regions where the electrode terminals 36 are sparsely arranged and the regions where they are densely arranged. Therefore, the arrangement of the regions where the electrode terminals 36 are sparsely arranged and the regions where they are densely arranged can be freely designed, which increases the degree of freedom in designing the semiconductor element 30.

[0080] Fifth Embodiment Fig. 25 is a diagram illustrating a semiconductor device A50 according to a fifth embodiment of the present disclosure. Fig. 25 is a partial plan view showing the semiconductor device A50, and corresponds to Fig. 2. For ease of understanding, Fig. 25 shows the sealing resin 40 transparently. The semiconductor device A50 of this embodiment differs from the first embodiment in that the semiconductor element 30 is mounted on a substrate rather than on leads.

[0081] In the first to fourth embodiments, the semiconductor element 30 is mounted on a plurality of first leads 10A, 10B, and 10C, a plurality of second leads 21, and a pair of third leads 22, and the electrode terminals 36 are joined to these leads. However, the semiconductor element 30 may be joined to a conductive member other than the leads. In the fifth embodiment, a semiconductor device A50 will be described in which the semiconductor element 30 is mounted on a wiring board and the electrode terminals 36 are joined to the wiring of the wiring board.

[0082] The semiconductor device A50 does not include first leads 10A, 10B, 10C, second lead 21, or third lead 22, but instead includes a wiring board 80. The wiring board 80 includes a base material 81 and a plurality of wirings 82. The base material 81 is a rectangular plate made of, for example, glass epoxy resin or ceramic. The material and shape of the base material 81 are not limited. The wirings 82 are made of, for example, Cu, and are formed on the base material 81. The material and shape of the wirings 82 are not limited.

[0083] The semiconductor element 30 is flip-chip mounted with the element main surface 30a facing the wiring board 80. Each electrode terminal 36 is bonded to one of the multiple wires 82 of the wiring board 80. The entire semiconductor element 30 and at least a part of the wiring board 80 are covered with a sealing resin 40 (omitted in FIG. 25). Other electronic components may be mounted on the wiring board 80, and leads for mounting the semiconductor device A50 on the wiring board may be bonded thereto.

[0084] In this embodiment, too, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A is greater than the thickness Xb of the overlapping portion 35b overlapping the electrode terminal 36B. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density in electrolytic plating, the difference between the height (Xa + Za) of the electrode terminal 36A from the electrode 34 and the height (Xb + Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0085] Sixth Embodiment Fig. 26 is a diagram illustrating a semiconductor device A60 according to a sixth embodiment of the present disclosure. Fig. 26 is a partial plan view showing the semiconductor device A60, and corresponds to Fig. 25. For ease of understanding, Fig. 26 shows the sealing resin 40 in a transparent manner. The semiconductor device A60 of this embodiment differs from the fifth embodiment in that the semiconductor element 30 includes a dummy electrode terminal 36C.

[0086] The semiconductor element 30 according to this embodiment is similar to the semiconductor element 30 according to the second embodiment, and includes a plurality of electrode terminals 36C arranged in a second region 302 of the element main surface 30a. No wiring 82 is formed in the wiring substrate 80 at positions facing the plurality of electrode terminals 36C. Therefore, the plurality of electrode terminals 36C are not connected to any of the wiring 82 and are not electrically connected.

[0087] In this embodiment, too, the thickness Xa of the overlapping portion 35b overlapping the electrode terminal 36A is greater than the thickness Xb of the overlapping portion 35b overlapping the electrode terminals 36B and 36C. Therefore, even if the height Za of the electrode terminal 36A becomes smaller than the height Zb of the electrode terminal 36B due to differences in current density during electrolytic plating, the difference between the height (Xa + Za) of the electrode terminal 36A from the electrode 34 and the height (Xb + Zb) of the electrode terminal 36B from the electrode 34 can be reduced. This makes it possible to suppress variations in the height of the electrode terminals 36A from the electrode 34.

[0088] According to this embodiment, since the electrode terminal 36C is provided in the second region 302, the total area of the electrode terminals 36 arranged in the second region 302 is increased, and the current density during electrolytic plating is reduced. As a result, the height dimension Zb of the electrode terminal 36B from the insulating layer 35 is smaller than when the electrode terminal 36C is not provided. Therefore, variation in the height of the electrode terminals 36 can be reduced.

[0089] The semiconductor element and semiconductor device according to the present disclosure are not limited to the above-described embodiments, and the specific configurations of the respective parts of the semiconductor element and semiconductor device according to the present disclosure can be freely modified in various ways.

[0090] Appendix 1. a main surface and a rear surface of the element facing opposite directions in a thickness direction; a plurality of electrodes formed on the main surface of the element; an insulating layer formed on the main surface of the element; a plurality of electrode terminals, each of which is in contact with one of the plurality of electrodes and partially overlaps the insulating layer when viewed in the thickness direction; the insulating layer includes a plurality of openings and a plurality of overlapping portions in contact with the plurality of openings, the plurality of openings exposing the plurality of electrodes, and the plurality of overlapping portions overlap the plurality of electrodes as viewed in the thickness direction; the plurality of electrode terminals are in contact with the plurality of electrodes through the plurality of openings, respectively, and overlap the plurality of overlapping portions as viewed in the thickness direction; When viewed in the thickness direction, the plurality of electrode terminals include a plurality of first electrode terminals that are densely arranged and a plurality of second electrode terminals that are sparsely arranged, a dimension in the thickness direction of the overlapping portion overlapping each of the first electrode terminals is greater than a dimension in the thickness direction of the overlapping portion overlapping each of the second electrode terminals; Appendix 2. 2. The semiconductor element according to claim 1, wherein each of the plurality of electrode terminals has a pillar portion that contacts a corresponding one of the plurality of electrodes and contains Cu. Appendix 3. 3. The semiconductor element of claim 2, wherein the pillar portion has a tip surface opposite the corresponding electrode, the tip surface having a peripheral portion and a central portion recessed from the peripheral portion. Appendix 4. The semiconductor element according to claim 2 or 3, wherein the pillar portion includes a seed layer in contact with the corresponding one of the electrodes, and a plating layer stacked on the seed layer. Appendix 5. 5. The semiconductor element according to claim 4, wherein the plating layer includes a first plating layer made of Cu and a second plating layer made of Ni. Appendix 6. 6. The semiconductor element according to claim 2, wherein each of the electrode terminals includes a solder portion that contacts the pillar portion. Appendix 7. 7. The semiconductor element according to claim 1, wherein the insulating layer contains a phenolic resin. Appendix 8. the element main surface includes a first region in which the plurality of first electrode terminals are arranged and a second region in which the plurality of second electrode terminals are arranged, and has a first end and a second end spaced apart from each other in a first direction perpendicular to the thickness direction; the first region is disposed on the first end side of the element main surface, 8. The semiconductor element according to claim 1, wherein the second region is disposed on the second end side of the element main surface. Appendix 9. the element main surface includes a first region in which the plurality of first electrode terminals are arranged and a second region in which the plurality of second electrode terminals are arranged; the first region is disposed at the center of the element main surface, 8. The semiconductor element according to claim 1, wherein the second region is disposed so as to surround the first region. Appendix 10. the element main surface includes a first region in which the plurality of first electrode terminals are arranged, and a second region and a third region in which the plurality of second electrode terminals are arranged, A semiconductor element described in any one of appendixes 1 to 7, wherein the second region and the third region are arranged on opposite sides of each other with respect to the first region in a first direction perpendicular to the thickness direction. Appendix 11. each of the plurality of first electrode terminals has an elliptical shape when viewed in the thickness direction; 11. The semiconductor element according to any one of claims 1 to 10, wherein each of the second electrode terminals has a circular shape when viewed in the thickness direction. Appendix 12. 12. The semiconductor element according to claim 1, wherein each of the plurality of electrodes contains Cu. Appendix 13. 13. The semiconductor device according to any one of claims 1 to 12, wherein each of the plurality of electrodes comprises a first layer made of Cu, a second layer made of Ni, and a third layer made of Pd. Appendix 14. A semiconductor element according to any one of Supplementary Notes 1 to 13; a sealing resin that covers the semiconductor element; A semiconductor device comprising: Appendix 15. It further comprises multiple leads, 15. The semiconductor device according to claim 14, wherein the plurality of electrode terminals include a dummy electrode terminal that is not joined to any of the plurality of leads, and a plurality of other functional electrode terminals, and each of the plurality of functional electrode terminals is joined to a corresponding one of the plurality of leads. Appendix 16. 16. The semiconductor device according to claim 15, further comprising a lead plating layer containing Ni, interposed between each functional electrode terminal and the corresponding one lead. Appendix 17. Further comprising a substrate and a plurality of wirings formed on the substrate, each of the plurality of wirings is connected to one of the plurality of electrode terminals; 15. The semiconductor device according to claim 14, wherein the plurality of electrode terminals includes a dummy electrode terminal that is not joined to any of the plurality of wirings. [Explanation of symbols]

[0091] A10, A20, A30, A40, A50, A60: Semiconductor device 10, 10A, 10B, 10C: 1st lead 11: Main part 12: Side part 13: Protruding part 101: First main surface 102: First back surface 121: First end face 131: Secondary end face 21: Second lead 211: Second main surface 212: Second rear surface 213: Second end surface 214: 4th end face 22: 3rd lead 221: Third main surface 222: Third back surface 223: Third end face 30: Semiconductor element 30a: element main surface 301: first region 302: 2nd area 303: 3rd area 30b: Back surface of element 31: Semiconductor substrate 32: Semiconductor layer 321: Switching circuit 322: Control circuit 33: Passivation film 34: Electrode 34a: First layer 34b: Second layer 34c: Third layer 35: Insulating layer 35a: Opening 35b: Overlapping portion 36,36A,36B,36C: Electrode terminal 361: Pillar portion 361a: Seed layer 361b: First plating layer 361c: Second plating layer 361d: recess 362: soldering part 363: Solder layer 40: Sealing resin 41: Top surface 42: Bottom surface 431: First side 432: Second side surface 60: Plating layer 61: 1st layer 62: 2nd layer 63: 3rd layer 80: wiring board 81: base material 82: wiring

Claims

1. a main surface and a rear surface of the element facing opposite directions in a thickness direction; a plurality of electrodes formed on the main surface of the element; an insulating layer formed on the main surface of the element; a plurality of electrode terminals, each of which is in contact with one of the plurality of electrodes and partially overlaps the insulating layer when viewed in the thickness direction; the insulating layer includes a plurality of openings and a plurality of overlapping portions in contact with the plurality of openings, the plurality of openings exposing the plurality of electrodes, and the plurality of overlapping portions overlap the plurality of electrodes as viewed in the thickness direction; the plurality of electrode terminals are in contact with the plurality of electrodes through the plurality of openings, respectively, and overlap the plurality of overlapping portions as viewed in the thickness direction; When viewed in the thickness direction, the plurality of electrode terminals include a plurality of first electrode terminals that are densely arranged and a plurality of second electrode terminals that are sparsely arranged, a dimension in the thickness direction of each overlapping portion overlapping each first electrode terminal is larger than a dimension in the thickness direction of each overlapping portion overlapping each second electrode terminal; the element main surface includes a first region in which the plurality of first electrode terminals are arranged and a second region in which the plurality of second electrode terminals are arranged, and has a first end and a second end spaced apart from each other in a first direction perpendicular to the thickness direction; the first region is disposed on the first end side of the element main surface, The second region is disposed on the second end side of the main surface of the semiconductor element.

2. a main surface and a rear surface of the element facing opposite directions in a thickness direction; a plurality of electrodes formed on the main surface of the element; an insulating layer formed on the main surface of the element; a plurality of electrode terminals, each of which is in contact with one of the plurality of electrodes and partially overlaps the insulating layer when viewed in the thickness direction; the insulating layer includes a plurality of openings and a plurality of overlapping portions in contact with the plurality of openings, the plurality of openings exposing the plurality of electrodes, and the plurality of overlapping portions overlap the plurality of electrodes as viewed in the thickness direction; the plurality of electrode terminals are in contact with the plurality of electrodes through the plurality of openings, respectively, and overlap the plurality of overlapping portions as viewed in the thickness direction; When viewed in the thickness direction, the plurality of electrode terminals include a plurality of first electrode terminals that are densely arranged and a plurality of second electrode terminals that are sparsely arranged, a dimension in the thickness direction of each overlapping portion overlapping each first electrode terminal is larger than a dimension in the thickness direction of each overlapping portion overlapping each second electrode terminal; the element main surface includes a first region in which the plurality of first electrode terminals are arranged and a second region in which the plurality of second electrode terminals are arranged; the first region is disposed at the center of the element main surface, The second region is disposed so as to surround the first region.

3. a main surface and a rear surface of the element facing opposite directions in a thickness direction; a plurality of electrodes formed on the main surface of the element; an insulating layer formed on the main surface of the element; a plurality of electrode terminals, each of which is in contact with one of the plurality of electrodes and partially overlaps the insulating layer when viewed in the thickness direction; the insulating layer includes a plurality of openings and a plurality of overlapping portions in contact with the plurality of openings, the plurality of openings exposing the plurality of electrodes, and the plurality of overlapping portions overlap the plurality of electrodes as viewed in the thickness direction; the plurality of electrode terminals are in contact with the plurality of electrodes through the plurality of openings, respectively, and overlap the plurality of overlapping portions as viewed in the thickness direction; When viewed in the thickness direction, the plurality of electrode terminals include a plurality of first electrode terminals that are densely arranged and a plurality of second electrode terminals that are sparsely arranged, a dimension in the thickness direction of each overlapping portion overlapping each first electrode terminal is larger than a dimension in the thickness direction of each overlapping portion overlapping each second electrode terminal; the element main surface includes a first region in which the plurality of first electrode terminals are arranged, and a second region and a third region in which the plurality of second electrode terminals are arranged, A semiconductor element, wherein the second region and the third region are arranged on opposite sides of the first region in a first direction perpendicular to the thickness direction.

4. 4. The semiconductor device according to claim 1, wherein each of the plurality of electrode terminals includes a pillar portion that is in contact with a corresponding one of the plurality of electrodes and that contains Cu.

5. The semiconductor element according to claim 4 , wherein the pillar portion has a tip surface on the opposite side to the corresponding one electrode, the tip surface having a peripheral edge portion and a central portion recessed from the peripheral edge portion.

6. The semiconductor element according to claim 4 , wherein the pillar portion includes a seed layer in contact with the corresponding one of the electrodes, and a plating layer stacked on the seed layer.

7. The semiconductor element according to claim 6 , wherein the plating layer includes a first plating layer made of Cu and a second plating layer made of Ni.

8. 8. The semiconductor device according to claim 4, wherein each of said electrode terminals has a solder portion in contact with said pillar portion.

9. 9. The semiconductor device according to claim 1, wherein the insulating layer contains a phenolic resin.

10. each of the plurality of first electrode terminals has an elliptical shape when viewed in the thickness direction; The semiconductor element according to claim 1 , wherein each of the second electrode terminals has a circular shape when viewed in the thickness direction.

11. 11. The semiconductor device according to claim 1, wherein each of the plurality of electrodes contains Cu.

12. 12. The semiconductor device according to claim 1, wherein each of the plurality of electrodes comprises a first layer made of Cu, a second layer made of Ni, and a third layer made of Pd.

13. A semiconductor element according to any one of claims 1 to 12; a sealing resin that covers the semiconductor element; A semiconductor device comprising:

14. It further comprises multiple leads, 14. The semiconductor device according to claim 13, wherein the plurality of electrode terminals include a dummy electrode terminal that is not joined to any of the plurality of leads, and a plurality of other functional electrode terminals, and each of the plurality of functional electrode terminals is joined to a corresponding one of the plurality of leads.

15. 15. The semiconductor device according to claim 14, further comprising a lead plating layer containing Ni, interposed between each of said functional electrode terminals and said corresponding one of said leads.

16. Further comprising a substrate and a plurality of wirings formed on the substrate, each of the plurality of wirings is connected to one of the plurality of electrode terminals; 14. The semiconductor device according to claim 13, wherein said plurality of electrode terminals includes a dummy electrode terminal that is not joined to any of said plurality of wirings.

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