Signal generating device and signal generating method

Abstract

To provide a signal generation device capable of reducing the time required for phase matching while remarkably increasing a maximum phase difference, with which phases can be matched, between signals outputted from a plurality of transceivers and a signal generation method.SOLUTION: In a signal generation device, a phase synchronization control section 31 executes first phase move processing for moving a phase of a toggle pattern from an initial value just by a first initial phase difference PC1 and second phase move processing for moving the phase of the toggle pattern, which is moved by the first phase move processing, just by a second initial phase difference PC2. The second phase move processing is repeatedly executed while decreasing a frequency division ratio step by step by a frequency division ratio setting section 33. After the first phase move processing or the second phase move processing is executed when the frequency division ratio is equal to or less than a predetermined value, a clock selection section selects an external clock in place of a frequency divided clock.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a signal generating device and a signal generating method, and more particularly to a signal generating device and a signal generating method that include a transceiver that converts parallel data into high-speed serial data and outputs the converted data. [Background technology]

[0002] As communication standards such as Ethernet® 800GbE (Gigabit Ethernet) and PCIe® (Peripheral Component Interconnect Express) Gen (Generation) 6 become faster, signal transmission methods are no longer simple binary digital signals such as NRZ (Non Return to Zero), but are now typified by PAM (Pulse Amplitude Modulation) 4. It is expected that transmission methods such as PAM8 and PAM16 will be standardized in the future. When developing or testing products that use these signals, a test signal source is required.

[0003] Such signal sources should naturally be able to generate signals such as PAM4 and PAM8, but it is also desirable that they be able to generate signals that have passed through a specific transmission path, or signals that have been subjected to emphasis or filtering. Therefore, there is a demand for an arbitrary waveform generator (AWG) that can generate arbitrary waveforms in an analog manner and has a high speed of over 100 Gsps (G Symbol / s).

[0004] An AWG must allow the user to freely set the analog waveform to be output. Naturally, since it is required to generate any desired signal, it must also be possible to set the waveform using numerical data. Therefore, an AWG must have a mechanism inside it to convert the digital data output from an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) into analog data. This conversion can be achieved using a Digital-to-Analog Converter (DAC).

[0005] However, when the required analog data output rate is high, not only does it become necessary to input signals multiplexed by a multiplexer (MUX) at higher speeds to the DAC, but the effects of phase differences between the multiple input signals input to the DAC and the MUX in the preceding stage cannot be ignored.For example, if the FPGA output rate is 32 Gbps and the DAC bit resolution is 8 bits, it is desirable that the maximum phase difference between all signals input to the MUX be less than 0.1 UI (Unit Interval) (3.125 ps).

[0006] Here, by using the technique described in Patent Document 1, it is possible to adjust the maximum phase difference between all signals input to the MUX to a value less than or close to 0.1 UI. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6346212 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the technology described in Patent Document 1 may adjust the phase between signals input to the MUX at a position that is shifted by one clock (1 UI), which occurs when there is a large phase shift between the signals before the adjustment.

[0009] Specifically, the technology described in Patent Document 1 cannot handle cases where a phase difference between pre-adjusted signals exceeds 1 UI. Furthermore, even if the phase difference between pre-adjusted signals is suppressed to within 1 UI by other means, there are technical and cost challenges, such as the need for an additional mechanism to adjust the clock phase provided to the FPGA transceiver, etc., and the need to measure the phase adjustment amount, which varies depending on the frequency. In the case of an FPGA, the phase difference between transceivers may change every time the FPGA is powered up or reset, requiring re-measurement of the phase adjustment amount. Furthermore, depending on the FPGA used, it may not be possible to suppress the phase difference between output signals to within 1 UI, even if the connection route within the FPGA is fixed.

[0010] In this case, when signals are multiplexed using a MUX, unintended data is generated. For example, if this data is used as a test signal for a Bit Error Rate Tester (BERT), the test signal itself will contain errors, making it impossible to measure the correct error rate.

[0011] The applicant attempted to solve these problems in Japanese Patent Application No. 2023-160154 (hereinafter referred to as the "prior application"). By using the technology of the prior application, it is possible to align the phase difference of the signals input to the DAC and the MUX in the preceding stage, but this technology requires a time of approximately 10 ms to several hundred ms in some cases to align the phases.

[0012] Therefore, when the signal generator performs the phase acquisition process, phase difference calculation process, and phase movement process according to the technology of the prior application multiple times, or due to multiple factors including delays caused by using this technology, there is a risk of a significant delay occurring between the time a user operates the signal generator to start signal transmission and the time the signal is actually transmitted.If the delay becomes too long, it will impair the availability of the signal generator itself.

[0013] The present invention has been made to solve the above-mentioned problems of the related art, and has as its object to provide a signal generating device and a signal generating method that can significantly increase the maximum phase difference that can be phase-matched between signals output from multiple transceivers while reducing the time required for phase matching. [Means for solving the problem]

[0014] In order to achieve the above object, a signal generating device according to the present invention includes a parallel data output unit (11) that outputs parallel data of multiple bits, a FIFO (21) that stores N-bit parallel data of the parallel data of multiple bits output from the parallel data output unit, and a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data, a phase synchronization control unit (31) that controls the phase of the 1-bit serial data converted by each of the transceivers, a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock, a division ratio setting unit (33) that sets a division ratio of the frequency-divided clock in the frequency-divided clock output unit, a clock selection unit (17) that selects either the external clock or the frequency-divided clock, a rate control unit (34) that controls each of the transceivers to output, as the 1-bit serial data, a toggle pattern of the frequency-divided clock or the external clock selected by the clock selection unit, and a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the external clock and the toggle pattern, and the phase synchronization control unit includes a phase acquisition processing unit (31b) that executes phase acquisition processing to acquire an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value, and a phase synchronization control unit that executes phase acquisition processing to acquire an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value, the phase synchronization control unit includes a phase acquisition processing unit (31b) that executes phase acquisition processing to acquire an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value, the maximum value, and the minimum value of the detection voltage acquired by the phase acquisition processing unit, and a phase difference calculation processing unit (31d) that executes a first phase difference calculation process to calculate a first initial phase difference between the phase of the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern, the first initial phase difference being within a predetermined range; a phase shift processing unit (31e) that shifts the phase of the toggle pattern so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; and an initial voltage acquisition processing unit (31c) that executes an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern has been shifted by the phase shift processing unit,The phase difference calculation processing unit further executes a second phase difference calculation process to calculate a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing unit, based on the maximum and minimum values of the detected voltage acquired by the phase acquisition processing unit and the initial voltage acquired by the initial voltage acquisition processing unit; the phase shift processing unit executes a first phase shift process to shift the phase of the toggle pattern from the initial value by the first initial phase difference, and a second phase shift process to shift the phase of the toggle pattern shifted by the first phase shift process by the second initial phase difference; the phase synchronization control unit repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio using the division ratio setting unit; and the clock selection unit selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process has been executed when the division ratio is equal to or less than a predetermined value. ,

[0015] With this configuration, the signal generating device according to the present invention can reduce the maximum phase difference between the serial data output from the plurality of transceivers to 0.1 UI or less relative to the external clock.

[0016] Furthermore, the signal generating device of the present invention reduces the number of phase acquisition processes to one, thereby shortening the time required for phase matching between lanes compared to the prior art technology in which the phase acquisition process is repeated every time the division ratio changes.

[0017] Furthermore, the signal generating device according to the present invention can significantly increase the maximum phase difference that can be matched between the serial data output from the plurality of transceivers after startup or resetting.

[0018] Furthermore, the signal generator according to the present invention does not require an additional mechanism, such as a delay circuit external to the FPGA, to limit the phase difference between pre-adjusted serial data to within 1 UI in advance, eliminating the need to investigate the parameters to be given to the additional mechanism after the product has been manufactured.

[0019] Furthermore, the signal generating device according to the present invention may be configured such that the clock selection unit selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

[0020] Furthermore, in a signal generating device according to the present invention, each of the transceivers includes a PISO (22) that converts the N-bit parallel data read from the FIFO in response to a read clock signal into the 1-bit serial data, a usage determination unit (23) that executes first and second usage determination processes to determine whether the usage of the FIFO is equal to or greater than a usage threshold, and a phase adjustment unit (24) that executes a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount, and the phase synchronization control unit further includes a usage control processing unit (31 a) that executes a usage control process to control the usage of the FIFO before the phase acquisition processing unit executes the phase acquisition process, and the usage control processing of the usage control processing unit is a process of causing the usage determination unit to execute the first usage determination process on condition that output of the serial data from each of the transceivers has started. a process of causing the phase adjustment unit to execute the first phase adjustment process on condition that the first usage determination process determines that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold; a process of causing the usage determination unit to execute the second usage determination process on condition that the number of consecutive times that the first usage determination process determines that the usage of the FIFO of each of the transceivers is less than the usage threshold reaches a first determination count; a process of causing the phase adjustment unit to execute the second phase adjustment process on condition that the second usage determination process determines that the usage of the FIFO of each of the transceivers is less than the usage threshold; and a process of causing the phase adjustment unit to terminate adjustment of the phase of the read clock signal on condition that the number of consecutive times that the second usage determination process determines that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold reaches a second determination count.

[0021] Furthermore, the signal generating device according to the present invention is configured to execute a usage control process to halve the FIFO usage of all lanes before starting a full-area phase measurement process using a divided clock, including a phase acquisition process. As a result, when the FIFO usage corresponds to 2 UI of a divided clock with the maximum division ratio, the signal generating device according to the present invention can shift the phase of the toggle pattern in both positive and negative directions within a range of up to -1 UI to +1 UI during the phase acquisition process.

[0022] Further, a signal generating method according to the present invention is a signal generating method for controlling the phase of the 1-bit serial data converted by each of the transceivers using a signal generating device (1) including: a parallel data output unit (11) that outputs parallel data of multiple bits; a FIFO (21) that stores N-bit parallel data of the parallel data of multiple bits output from the parallel data output unit; a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data; a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the external clock or the frequency-divided clock; and a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, the signal generating method comprising: a frequency-dividing ratio setting step (S14, S18) of setting a frequency-dividing ratio of the frequency-divided clock in the frequency-divided clock output unit; a rate control step (S31, S37) of causing each of the transceivers to output a toggle pattern having a frequency that is half the frequency of the frequency-divided clock or the external clock selected by the clock selection unit as serial data of a bit; a phase acquisition processing step (S32, S35) of executing a phase acquisition processing of acquiring an initial value, a maximum value, and a minimum value of the detected voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S33, S36, S39) of executing a first phase difference calculation processing of calculating a first initial phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the initial value, the maximum value, and the minimum value of the detected voltage acquired by the phase acquisition processing step; and a phase movement processing step (S16, S17) of moving the phase of the toggle pattern so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern becomes a value within a predetermined range.and an initial voltage acquisition processing step (S38) of executing an initial voltage acquisition processing of acquiring the detected voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern has been shifted by the phase shift processing step, wherein the phase difference calculation processing step further executes a second phase difference calculation processing of calculating a second initial phase difference between the frequency-divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing step, based on the maximum and minimum values of the detected voltage acquired by the phase acquisition processing step and the initial voltage acquired by the initial voltage acquisition processing step, and the phase shift processing step A first phase shift process is executed to shift the phase of the toggle pattern shifted by the first phase shift process from the initial value by the first initial phase difference, and a second phase shift process is executed to shift the phase of the toggle pattern shifted by the first phase shift process by the second initial phase difference, and the signal generation method further includes steps (S16 to S19) of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process while gradually decreasing the division ratio by the division ratio setting step, and an external clock selection step (S20) of selecting the external clock instead of the divided clock by the clock selection unit after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value.

[0023] Furthermore, the signal generation method according to the present invention may be configured such that the external clock selection step selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less. [Effects of the Invention]

[0024] The present invention provides a signal generating device and a signal generating method that can significantly increase the maximum phase difference that can be phase-matched between signals output from multiple transceivers while reducing the time required for phase matching. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a block diagram showing a configuration of a signal generating device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing a part of the configuration of a data output unit included in the signal generating device of FIG. 1. FIG. [Figure 3] 2 is a schematic diagram of a phase detection unit included in the signal generating device of FIG. 1. [Figure 4] FIG. 2 is a block diagram showing the configuration of one lane of the transceiver section. [Figure 5] 2 is a state transition diagram for explaining a usage amount control process performed by the signal generating device of FIG. 1. FIG. [Figure 6] 10 is a block diagram showing the configuration of an FPGA control unit included in the data output unit. FIG. [Figure 7] FIG. 10 is a diagram showing the relationship between a toggle pattern output from one lane of a data output unit and a clock. [Figure 8] 10 is a graph showing the relationship between a detection voltage according to a duty ratio of a phase detection signal output from a phase detection unit and the amount of change in the phase of a toggle pattern from an initial value. [Figure 9] This figure explains the phase shift processing of the toggle patterns of each lane by the phase synchronization control unit provided in the FPGA control unit, where (a) shows a case where the initial phase differences of the toggle patterns of all lanes are distributed in positive directions, (b) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, and (c) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, with the positive distribution and negative distribution separated by 0.5 UI or more. [Figure 10] 10 is a diagram showing the amount of phase shift of the toggle pattern by the phase synchronization control unit for each division ratio. FIG. [Figure 11] 2 is a flowchart showing the process of a signal generation method using the signal generation device of FIG. 1. [Figure 12]12(a) is a flowchart showing details of the global phase measurement process using a frequency-divided clock in the flowchart of FIG. 11, (b) is a flowchart showing details of the global phase measurement process using an external clock in the flowchart of FIG. 11, and (c) is a flowchart showing details of the current phase measurement process in the flowchart of FIG. 11. [Figure 13] FIG. 10 is a diagram showing the phase relationship of the toggle patterns of each lane after the usage control process. [Figure 14] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 64, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 15] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 4, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 16] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when an external clock is selected by the clock selection unit, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. DETAILED DESCRIPTION OF THE INVENTION

[0026] DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a signal generating device and a signal generating method according to the present invention will be described with reference to the drawings.

[0027] 1 includes a data output unit 10, a clock selection unit 17, a phase detection unit 40, a MUX 50, an amplifier 52, an ADC 55, a DAC 60, an operation unit 65, and a control unit 70. The data output unit 10 is configured on, for example, an FPGA or an ASIC, but the following description will be given assuming that these are configured on an FPGA.

[0028] The data output unit 10 includes a parallel data output unit 11, a plurality of transceiver units 12-1 to 12-p, a clock generation unit 13, a frequency-divided clock output unit 14, and an FPGA control unit 15.

[0029] The parallel data output unit 11 has an internal memory (not shown) that stores a series of data strings of a predetermined pattern in advance, or an arithmetic circuit (not shown) that generates the data strings. For example, in the example shown in Fig. 2, the parallel data output unit 11 is configured to output 32 x N-bit parallel data.

[0030] The parallel data output unit 11 is configured to output, for example, a PAM signal pattern consisting of a multi-value K (K is an integer equal to or greater than 2) of two or more as 32×N-bit parallel data based on pattern information input from the operation unit 65. The parallel data output unit 11 generates a PAM signal pattern consisting of any multi-value K, such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), or a PAM8 signal (K=8). Here, the pattern information refers to information on the PAM signal pattern, such as the value of K and the type of pattern (for example, a Pseudo Random Binary Sequence (PRBS) pattern, a Short Stress Pattern Random Quaternary (SSPRQ) pattern, or any pattern).

[0031] The data output unit 10 includes p transceiver units 12-1 to 12-p. Although Figures 1 and 2 show an example where p=8, in the present invention, the number of transceiver units 12 is not limited to eight and may be any number.

[0032] As shown in FIG. 2, the clock signal generated by the clock generating unit 13 is distributed to each transceiver unit 12.

[0033] Each transceiver unit 12 includes, for example, four transceivers 20-0 to 20-3. Each transceiver 20 is an output unit of an FPGA and outputs a digital signal of 0 or 1. Each transceiver 20 converts, in synchronization with the clock signal generated by the clock generation unit 13, N-bit parallel data stored in a FIFO 21 (described later) out of the 32×N-bit parallel data output from the parallel data output unit 11, into 1-bit serial data. Here, N is an integer equal to or greater than 2.

[0034] That is, each transceiver unit 12 converts the 4×N-bit parallel data output from the parallel data output unit 11 into 4-bit parallel data and outputs it. That is, the data output unit 10 outputs 8 channels of 4-bit parallel data, in other words, 32 lanes of serial data.

[0035] The divided clock output unit 14 outputs a divided clock obtained by dividing the frequency of the external clock. The maximum frequency of the divided clock is half the frequency of the external clock. For example, the divided clock output unit 14 may be implemented by a transceiver having a similar configuration to each of the transceivers 20.

[0036] The clock selector 17 selects either the external clock or the divided clock in response to a clock selection signal output from a clock selection signal output unit 35 (described later). In this specification, the divided clock and the external clock are collectively referred to simply as the "clock." The external clock is, for example, a 32 GHz pulse signal.

[0037] The phase detector 40 outputs a detection voltage corresponding to the phase difference between the divided clock or external clock selected by the clock selector 17 and the toggle pattern output from each transceiver 20. The toggle pattern is 1-bit serial data in which "0" and "1" are alternately repeated, and is output from each transceiver 20 when a phase acquisition process or an initial voltage acquisition process, which will be described later, is executed. One phase detector 40 is disposed downstream of each transceiver 20. Since the phase detector 40 is used to check the phase of the toggle pattern output from each transceiver 20, it may be incorporated into the MUX 50 or may be disposed independently upstream of the MUX 50.

[0038] A schematic diagram of the phase detection unit 40 for one lane is shown in Fig. 3. As shown in the figure, the phase detection unit 40 includes, for example, a D flip-flop 41, an EXOR circuit 42, and an averaging circuit 43.

[0039] The D flip-flop 41 has two input terminals, a D terminal and a CLK terminal, and one output terminal, a Q terminal. A toggle pattern from the corresponding transceiver 20 is input to the D terminal, and a clock selected by the clock selection unit 17 is input to the CLK terminal.

[0040] The EXOR circuit 42 outputs a phase detection signal by taking the exclusive OR of the toggle pattern from the corresponding transceiver 20 and the output signal from the Q terminal of the D flip-flop 41. When a toggle pattern with a period twice that of the clock is input to the D terminal, the phase detection signal becomes a pulse-like signal with a duty ratio corresponding to the phase of the toggle pattern input to the D terminal.

[0041] The averaging circuit 43 is configured, for example, by a low-pass filter, and is configured to average the phase detection signal. When a toggle pattern with a period twice that of the clock is input to the D terminal, the averaging circuit 43 outputs a detection voltage signal according to the duty ratio of the phase detection signal. This makes it possible to obtain the phase of the toggle pattern from the corresponding transceiver 20 as a detection voltage.

[0042] The amplifier 52 amplifies the detected voltage signal from the phase detector 40 to a voltage level suitable for the ADC 55 at the subsequent stage, as required.

[0043] The ADC 55 samples the detection voltage signal amplified by the amplifier 52 at a predetermined sampling rate and converts it into digital data. That is, the ADC 55 outputs digital data of the detection voltage corresponding to the phase difference between the toggle pattern and the divided clock or external clock selected by the clock selection unit 17. Here, the predetermined sampling rate may be a value of several hundred ksps to several Msps, such as 500 ksps or 1 Msps. For this reason, an ADC with multiple input channels, such as a four-channel ADC, can also be used as the ADC 55.

[0044] The MUX 50 latches the m-bit parallel data output from each transceiver unit 12, selects n bits at a time in a predetermined order in synchronization with the external clock selected by the clock selection unit 17, and outputs n-bit data corresponding to the frequency of the external clock selected by the clock selection unit 17. Here, n is an integer greater than or equal to 1 and less than or equal to m-1. In the example shown in FIG. 1, n=1 and m=4. That is, the MUX 50 can multiplex the m-bit data from each transceiver unit 12 into n-bit data.

[0045] DAC 60 is an n×p-bit DAC that outputs an n×p-bit analog signal, i.e., a multi-value K PAM signal, corresponding to the n×p-bit data output from all MUXes 50. In the example shown in FIG. 1, n=1 and p=8.

[0046] The operation unit 65 is for accepting operation inputs by the user, and is configured, for example, as a touch panel equipped with a touch sensor for detecting a contact position by a touch operation on an input surface corresponding to a display screen of a display device (not shown). Alternatively, the operation unit 65 may be configured to include an input device such as a keyboard or a mouse. Operation inputs to the operation unit 65 are detected by the control unit 70.

[0047] The control unit 70 is composed of a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA, a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive), and controls the operation of each of the above-mentioned components that make up the signal generating device 1.

[0048] 4 is a diagram showing the configuration of one lane of the data output unit 10. Each transceiver 20 has a FIFO (First-In First-Out) 21 that stores N-bit parallel data out of the 32×N-bit parallel data output from the parallel data output unit 11, a PISO (Parallel-In Serial-Out) 22 that converts the N-bit parallel data read from the FIFO 21 into 1-bit serial data in response to a read clock signal, a usage determination unit 23 that executes first and second usage determination processes to determine whether the usage of the FIFO 21 is equal to or greater than a usage threshold, a phase adjustment unit 24 that adjusts the phase of the read clock signal of the FIFO 21 so as to decrease or increase it, frequency dividers 25 and 26, and a subtractor 27.

[0049] That is, the transceiver 20 reads out the stored N-bit parallel data from the FIFO 21, performs parallel / serial conversion on the read parallel data in the PISO 22, and outputs the serial data.

[0050] In the signal generating device 1 of this embodiment, each transceiver unit 12 can be configured with a transceiver equipped with a function for adjusting the phase of a read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TXPI") provided by Xilinx, Inc. Furthermore, for example, an FPGA that configures the data output unit 10 can suitably be an UltraScale+ equipped with a GTY transceiver manufactured by Xilinx, Inc.

[0051] Generally, the timing at which multiple transceivers configured on an FPGA actually output data after they are started or reset does not necessarily match. Therefore, the usage amount of the FIFO 21 of each transceiver 20 is usually different when the data output starts. Furthermore, even when focusing on a single transceiver 20, the usage amount when the data output starts may differ each time the transceiver is started or reset.

[0052] The basic operation of TXPI will be described below with reference to FIG.

[0053] The FIFO 21 functions as a buffer for the parallel data output from the parallel data output unit 11 and is capable of storing up to M words of N-bit parallel data. The FIFO 21 writes or reads N-bit parallel data at the rising edge of an input write clock signal or read clock signal. The write clock signal and read clock signal are signals based on the clock signal generated by the clock generation unit 13, for example.

[0054] The frequency divider 25 divides the read clock signal by the maximum number of words M of the FIFO 21 to obtain a read address of the FIFO 21. On the other hand, the frequency divider 26 divides the write clock signal by the maximum number of words M of the FIFO 21 to obtain a write address of the FIFO 21.

[0055] The subtractor 27 outputs the difference between the read address and the write address output from the frequency dividers 25 and 26. The difference output from the subtractor 27 reflects the amount of usage of the FIFO 21.

[0056] The usage determination unit 23 executes first and second usage determination processes for determining, for each clock of the operation clock of the FPGA that constitutes the data output unit 10, whether the difference output from the subtractor 27 is equal to or greater than a usage threshold. The usage determination unit 23 constantly monitors the difference between the read address and write address of the FIFO 21 as the usage of the FIFO 21, and outputs 0 if this usage is less than the usage threshold, and 1 if it is equal to or greater than the usage threshold. For example, the usage threshold is M / 2, i.e., half the maximum number of words M of the FIFO 21. The usage of the FIFO 21 changes as the phase of the read clock signal changes.

[0057] The phase adjustment unit 24 executes a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount in a usage control process described later. The first phase adjustment process is a process to decrease the usage of the FIFO 21, and the second phase adjustment process is a process to increase the usage of the FIFO 21.

[0058] The phase adjustment unit 24 can shift the read address value of the FIFO 21 by adjusting the phase of the read clock signal of the FIFO 21. This shifts the phase of the parallel data output from the FIFO 21. However, the phase adjustment unit 24 cannot adjust the phase of the parallel data output from the FIFO 21 to an arbitrary value, and the phase adjustment width and maximum adjustment amount that can be adjusted at one time are also limited. For example, when the output data rate of the transceiver 20 is 32 Gbps, the phase adjustment width that the phase adjustment unit 24 can adjust is 1 / 64 UI step width, and the maximum adjustment amount that the phase adjustment unit 24 can adjust is 64 UI.

[0059] The following describes the usage control process executed by the usage control processor 31a of the phase synchronization controller 31 (see FIG. 6) included in the FPGA controller 15, with reference to the state transition diagram in FIG. 5. The usage control process of the usage control processor 31a controls the usage of the FIFO 21 of each transceiver 20, and is executed independently for each lane, i.e., for each transceiver 20.

[0060] 5, the usage control processor 31a includes eight states S1 to S7, namely, an initial state, a PRESET state, a BUFCHK1 state, a TXPI_DEC state, a TXPI_INC state, a BUFCHK2 state, and a PHASEADJ state. Arrows between states indicate transitions and their directions.

[0061] First, the usage control processor 31a transitions from the initial state S1 to the PRESET state S2. The PRESET state S2 is a standby state until each transceiver 20 starts outputting serial data. Here, each transceiver 20 starts generating a clock in a clock generation circuit (not shown) when it is ready to start outputting serial data after startup or reset. The usage control processor 31a can detect the rising edge of this clock to determine when each transceiver 20 starts outputting serial data.

[0062] When the usage control processing unit 31a detects that each transceiver 20 has started outputting serial data, it transitions from the PRESET state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the first usage determination process.

[0063] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 on the condition that the first usage determination process determines that the usage of the FIFO 21 of each transceiver 20 is equal to or greater than the usage threshold. The TXPI_DEC state S4 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the first phase adjustment process.

[0064] The usage control processor 31a transitions from the TXPI_DEC state S4 back to the BUFCHK1 state S3 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been decreased by a predetermined amount by the first phase adjustment process.

[0065] The usage control processor 31a transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 when the number of consecutive times that the usage of the FIFO 21 of each transceiver 20 is determined to be less than the usage threshold by the first usage determination process reaches the first determination count. The TXPI_INC state S5 is a state in which the usage control processor 31a causes the phase adjuster 24 to execute the second phase adjustment process.

[0066] The usage control processor 31a transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been increased by a predetermined amount by the second phase adjustment process. The BUFCHK2 state S6 is a state in which the usage control processor 31a causes the usage determiner 23 to execute the second usage determination process.

[0067] The usage control processing unit 31a transitions from the BUFCHK2 state S6 back to the TXPI_INC state S5 on the condition that it is determined in the second usage determination process that the usage of the FIFO 21 of each transceiver 20 is less than the usage threshold.

[0068] The usage control processor 31a transitions from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of consecutive times that the usage of the FIFO 21 of each transceiver 20 is determined to be equal to or greater than the usage threshold value in the second usage determination process reaches the second determination count. The PHASEADJ state S7 is a state in which the usage control processor 31a causes the phase adjuster 24 to finish adjusting the phase of the read clock signal and waits until a reset signal is input to each transceiver 20.

[0069] 5 for all transceivers 20, the usage control processing unit 31a can halve the usage of the FIFO 21 of all lanes, thereby aligning the data latency of all lanes. Since the phase of the 32×N-bit parallel data output from the parallel data output unit 11 is the same for all lanes, the phase of the serial data output from all transceivers 20 will also be approximately the same.

[0070] 5, when the phase adjustment width by phase adjustment unit 24 is 1 / 64 UI, the phase of the serial data output from transceiver 20 can be adjusted with a calculated accuracy of ±0.008 UI (theoretical limit value). Note that the first and second determination counts may be equal or different from each other.

[0071] 5, if the transitions from BUFCHK1 state S3 to TXPI_DEC state S4, from BUFCHK2 state S6 to TXPI_INC state S5, from BUFCHK1 state S3 to TXPI_INC state S5, and from BUFCHK2 state S6 to PHASEADJ state S7 are executed if the respective conditions for their transitions are satisfied once, the maximum phase difference between the serial data output from all transceivers 20 after phase adjustment is complete will be greater than the theoretical limit value. This is thought to be because the usage of FIFO 21 constantly fluctuates due to jitter components in the write clock signal and read clock signal, which causes fluctuations in the results of the first and second usage determination processes performed by usage determiner 23.

[0072] Therefore, in the processing of the usage control processing unit 31a shown in Figure 5, the signal generating device 1 of this embodiment specifies the first and second number of judgments that must be made consecutively to satisfy the transition conditions for the transition from the BUFCHK1 state S3 to the TXPI_INC state S5 and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7, and executes the transition only if the transition conditions are met for those number of consecutive judgments.

[0073] As shown in FIG. 6, the FPGA control unit 15 includes a phase synchronization control unit 31, a frequency division ratio setting unit 33, a rate control unit , and a clock selection signal output unit .

[0074] The phase synchronization control section 31 controls the phase of the toggle pattern, which is 1-bit serial data converted by each transceiver 20.

[0075] The phase synchronization control unit 31 includes a usage control processing unit 31a, a phase acquisition processing unit 31b, an initial voltage acquisition processing unit 31c, a phase difference calculation processing unit 31d, and a phase movement processing unit 31e.

[0076] As already described, the usage control processing of the usage control processing unit 31a includes processing for causing the usage determination unit 23 to execute a first usage determination processing, processing for causing the phase adjustment unit 24 to execute a first phase adjustment processing, processing for causing the usage determination unit 23 to execute a second usage determination processing, processing for causing the phase adjustment unit 24 to execute a second phase adjustment processing, and processing for causing the phase adjustment unit 24 to end adjustment of the phase of the read clock signal. The usage control processing unit 31a executes the above-described usage control processing before the phase acquisition processing, which will be described later, is executed by the phase acquisition processing unit 31b.

[0077] The phase acquisition processing unit 31b controls the phase adjustment unit 24 of each transceiver 20 to change the phase of the toggle pattern output from each transceiver 20 from the initial value, and obtains the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40. H , and the minimum value V L Here, the digital data of the detected voltage is input from the ADC 55 to the phase acquisition processing unit 31b.

[0078] A specific example of the phase acquisition process by the phase acquisition processor 31b will be described below. The phase acquisition processor 31b performs the phase acquisition process on all toggle patterns for 32 lanes simultaneously or sequentially. Figure 7 shows the relationship between the toggle pattern and the clock output from the transceiver 20 of one lane of the data output unit 10.

[0079] First, the phase acquisition processing unit 31b acquires the detected voltage output from the phase detection unit 40 at the start of the phase acquisition process. Here, the phase of the toggle pattern at the start is set to 0 UI. Furthermore, the phase synchronization control unit 31 acquires the detected voltage output from the phase detection unit 40 while moving the phase of the toggle pattern within a range of -0.75 UI to +0.75 UI, with one clock cycle at that time being set to 1 UI. For example, as shown by the arrows in FIG. 7, the phase synchronization control unit 31 moves the phase of the toggle pattern from 0 UI, which is the initial value at the start of the phase acquisition process, to -0.75 UI, then from -0.75 UI to +0.75 UI, and finally from +0.75 UI to 0 UI at the start.

[0080] This means, for example, repeating the operation of measuring the detected voltage output from the phase detection unit 40 every time the phase of the toggle pattern is shifted by approximately 0.1 UI. This allows the results shown in Figure 8 to be obtained. In the graph of Figure 8, the horizontal axis represents the amount of change [UI] in the phase of the toggle pattern from its initial value, and the vertical axis represents the detected voltage [V] output from the phase detection unit 40.

[0081] In the phase acquisition process, for example, eight ADC55s with four-channel input and 500 ksps are used, and digital data of the detected voltage is acquired 10 times per channel per measurement point for averaging. In this case, a measurement time of about 80 μs is required per measurement point. If the toggle pattern phase is shifted and measured at 32 measurement points, the measurement time required is approximately 3 ms.

[0082] Since TXPI adjusts the phase of the serial data from each transceiver 20 based on the usage of the FIFO 21, if the usage is uneven in the initial state, it may not be possible to ensure an adjustment range of ±0.75 UI. For this reason, the phase synchronization control unit 31 performs the usage control process described above, so that the phase of the toggle pattern can be moved within a range of ±0.75 UI.

[0083] In the above description, the range of phase change of the toggle pattern is -0.75 UI to +0.75 UI, but the present invention is not limited to this. The range of phase change of the toggle pattern needs to be at least 1 UI, and the phase of the toggle pattern may be changed within the range of -0.5 UI to +0.5 UI, for example.

[0084] Furthermore, the phase acquisition processing unit 31b calculates an initial value V0, which is the detected voltage at the start of the phase acquisition process, and a maximum value V H , the minimum value of the detection voltage V L Get.

[0085] 8, the relationship between the detected voltage and the toggle pattern phase is linear in units of 1 UI. Therefore, the phase acquisition processing unit 31b uses the linear least squares method to find an approximation line of the relationship between the detected voltage and the toggle pattern phase, rather than the output value itself from the phase detection unit 40, and obtains the initial value V0 and the maximum value V H , minimum value V L Calculate.

[0086] This reduces the influence of disturbances such as noise on the measurement result of the phase difference between the clock and the toggle pattern by the phase detection unit 40, and the initial value V0 and the maximum value V H , minimum value V L The accuracy of each value of can be improved.

[0087] The initial voltage acquisition processing unit 31c is configured to perform an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit 40 as an initial voltage V0' after the phase of the toggle pattern output from each transceiver 20 is shifted by the phase shift processing unit 31e described later.

[0088] That is, the initial voltage acquisition process by the initial voltage acquisition processor 31c is premised on the fact that the phase acquisition process by the phase acquisition processor 31b has already been performed. The initial voltage acquisition process does not move the phase of the toggle pattern, but only acquires the initial voltage V0', which is the detected voltage at the time the initial voltage acquisition process is performed. The initial voltage acquisition processor 31c performs the initial voltage acquisition process simultaneously or sequentially for all toggle patterns for 32 lanes.

[0089] The phase difference calculation processing unit 31d calculates the initial value V0 and the maximum value V1 of the detected voltage acquired by the phase acquisition processing unit 31b. H , and the minimum value V L Based on this, a first initial phase difference P between the divided clock or the external clock selected by the clock selection unit 17 and the initial value of the phase of the toggle pattern is calculated. C1 The first phase difference calculation process is executed to calculate the following.

[0090] Furthermore, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage acquired by the phase acquisition processing of the phase acquisition processing unit 31b. H and minimum value V L and the initial voltage V0′ acquired by the initial voltage acquisition processing of the initial voltage acquisition processing unit 31c, a second initial phase difference P between the frequency-divided clock selected by the clock selection unit 17 and the phase of the toggle pattern shifted by the phase shift processing unit 31e described later is calculated. C2 In this specification, the first phase difference calculation process and the second phase difference calculation process are collectively referred to simply as "phase difference calculation process."

[0091] The phase difference calculation processing unit 31d calculates the initial value V0 and maximum value V of the detected voltage acquired by the phase acquisition processing. H , and the minimum value V L By substituting into the following equation (1), the first initial phase difference P of the toggle pattern at the start of the phase acquisition process is obtained. C1 Furthermore, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage obtained by the phase acquisition processing. H and minimum value VL and the initial voltage V0′ acquired by the initial voltage acquisition process into the following equation (2), the second initial phase difference P C2 In this specification, the first initial phase difference P C1 and the second initial phase difference P C2 are summed up and simply referred to as "initial phase difference P C " is also called.

[0092]

number

[0093]

number

[0094] That is, the second phase difference calculation process is performed by calculating the maximum value V of the detected voltage acquired by the phase acquisition process. H and minimum value V L Since the initial phase difference P C For example, if the measurement conditions are the same as those exemplified for the phase acquisition process, the measurement time required for the initial voltage acquisition process is about 80 μs.

[0095] The phase synchronization control unit 31 performs the same phase difference calculation process for all toggle patterns for 32 lanes simultaneously or sequentially. As a result, for example, the lane numbers and initial phase differences P C The correspondence is obtained.

[0096] Here, lane numbers 1 to 4 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-1, respectively. Lane numbers 5 to 8 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-2, respectively. Lane numbers 9 to 12 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-3, respectively. Lane numbers 13 to 16 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-4, respectively. Lane numbers 17 to 20 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-5, respectively. Lane numbers 21 to 24 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-6, respectively. Lane numbers 25 to 28 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-7, respectively. Lane numbers 29 to 32 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-8, respectively.

[0097] The phase shift processing unit 31e controls the phase adjustment unit 24 of each transceiver 20 so that the phase difference between the toggle pattern and the divided clock or external clock selected by the clock selection unit 17 falls within a predetermined range, thereby shifting the phase of the toggle pattern output from each transceiver 20. Here, the value (phase difference) within the predetermined range is the value closest to 0 within the precision of the phase adjustment width that the phase adjustment unit 24 can adjust.

[0098] The phase shift processing unit 31e shifts the phase of the toggle pattern output from each transceiver 20 from the initial value at the start of the phase acquisition process by a first initial phase difference P C1 The first phase shift process shifts the toggle pattern phase by the second initial phase difference P C2 In this specification, the first phase shift process and the second phase shift process are collectively referred to simply as "phase shift process."

[0099] Hereinafter, the phase shift processing of the toggle pattern of each lane performed by the phase shift processing unit 31e will be described with reference to FIGS. 9(a) to 9(c).

[0100] FIG. 9(a) shows the initial phase difference P C In this case, the phase shift processing unit 31e shifts the phase of the toggle pattern of all lanes toward 0 by -P C The initial phase difference P C The same is true if is negatively distributed.

[0101] FIG. 9(b) shows the initial phase difference P C is distributed either positively or negatively, and the distribution width is less than 0.5 UI. In this case, the phase shift processing unit 31e shifts the phase of the toggle pattern that is distributed positively toward 0 by -P C The phase of the toggle pattern shifts negatively towards 0. C Move only.

[0102] FIG. 9(c) shows the initial phase difference P C is distributed in either positive or negative directions, and the positive distribution and the negative distribution are separated by 0.5 UI or more. In this case, the initial phase difference P C It is considered that a part of the distribution of 1+P appears to be shifted by 1 UI. For this reason, the phase shift processing unit 31e shifts the phase of the toggle pattern that is positively distributed in the positive direction toward 0 by, for example, 1+P C and shifts the phase of the negatively distributed toggle pattern towards 0 in the positive direction -P C Move only.

[0103] As can be seen from FIGS. 9(a) to 9(c), the four transceivers 20 included in the same transceiver unit 12 have the same initial phase difference P CIn such a case, the phase acquisition process, the initial voltage acquisition process, and the phase difference calculation process are performed for only one transceiver 20 included in each transceiver unit 12, and the obtained initial phase difference P C may be regarded as an initial phase difference common to the four transceivers 20 included in each transceiver unit 12.

[0104] The division ratio setting unit 33 is configured to set the division ratio of the divided clock based on the external clock to the divided clock output unit 14. The phase synchronization control unit 31 repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while the division ratio setting unit 33 gradually decreases the division ratio.

[0105] In the prior art, the division ratio was an integer power of 2, and was repeatedly halved to change, for example, 64, 32, 16, 8, 4, and 2 in that order.

[0106] In the signal generating device 1 of this embodiment, the division ratio is, for example, an integer that is a power of 2 or 4, and the minimum value is 4 or less. The division ratio setting unit 33 repeatedly reduces the division ratio to 1 / 4. For example, if the maximum division ratio is 64, the division ratio setting unit 33 changes the division ratio in the order of 64, 16, and 4. Furthermore, if the maximum division ratio is 32, for example, the division ratio setting unit 33 changes the division ratio in the order of 32, 8, and 2.

[0107] Compared to the prior art technology in which the division ratio is reduced by 1 / 2, the signal generating device 1 of this embodiment reduces the division ratio by 1 / 4, thereby speeding up the process of matching the maximum phase difference between the toggle patterns of each lane with an accuracy of 0.1 UI or less based on the divided clock, and reducing the time required for phase matching between lanes.

[0108] Furthermore, if the maximum phase difference between the toggle patterns of each lane can be adjusted to an accuracy of 0.1 UI or less based on the divided clock, the division ratio is not limited to 1 / 4 and may be the reciprocal of an integer that is a power of 2, such as 1 / 8 or 1 / 16.

[0109] 10 is a diagram showing the amount of phase shift of the toggle pattern by the phase acquisition process for each division ratio when the toggle pattern phase is shifted within a range of -0.75 UI to +0.75 UI relative to 1 UI of the divided clock, as a percentage of the capacity of FIFO 21. For example, the capacity of FIFO 21 is equivalent to 128 UI when 1 clock of the external clock is 1 UI, and is equivalent to 2 UI (±1 UI) for a divided clock obtained by dividing the external clock by a maximum of 64.

[0110] When the division ratio is 64, 75% of the capacity of FIFO 21 is used to shift the phase of the toggle pattern. Thereafter, the amount of shift is reduced to 1 / 4 every time the division ratio becomes 1 / 4, and when the division ratio is 1, the amount of shift is equivalent to 1.17% of the capacity of FIFO 21.

[0111] The rate control unit 34 controls each transceiver 20 to output, as 1-bit serial data from each transceiver 20, a toggle pattern having a frequency that is half the frequency of the divided clock or external clock selected by the clock selection unit 17. For example, the rate control unit 34 controls the parallel data output unit 11 to output N-bit parallel data such that the frequency of the toggle pattern output from each transceiver 20 is half the frequency of the divided clock or external clock.

[0112] The clock selection signal output unit 35 outputs a clock selection signal for selecting either the external clock or the divided clock to the clock selection unit 17. Specifically, when the division ratio set by the division ratio setting unit 33 is equal to or less than a predetermined value, the clock selection signal output unit 35 outputs a clock selection signal for causing the clock selection unit 17 to select the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed. The minimum value of the division ratio is, for example, an integer equal to or less than 4.

[0113] An example of the signal generation method using the signal generating device 1 of this embodiment will be described below with reference to the flowcharts of Figures 11, 12(a), 12(b), and 12(c). Note that descriptions that overlap with the description of the configuration of the signal generating device 1 described above will be omitted as appropriate. The processing shown in this flowchart is performed for each of the 32 lanes of output.

[0114] When each transceiver unit 12 is started or reset (step S11: YES), the phase synchronization control unit 31 executes a usage control process (step S12). For example, when the bit rate of the PAM signal output from the signal generating device 1 is changed by a user's operation input to the operation unit 65, each transceiver unit 12 is reset. By the usage control process, the usage of the FIFO 21 of each transceiver 20 is halved.

[0115] FIG. 13 is a simplified diagram showing an example of the phase relationship of the toggle patterns output from the transceiver 20 of each lane after the usage control process. The vertical dashed lines in the diagram indicate the rising edges of the external clock. Each transceiver unit 12 has four lanes, Lane 0 to Lane 3. "Ch1 Lane 0," "Ch1 Lane 2," "Ch4 Lane 0," and "Ch7 Lane 3" in the diagram represent Lane 0 of the transceiver unit 12-1, Lane 2 of the transceiver unit 12-1, Lane 0 of the transceiver unit 12-4, and Lane 3 of the transceiver unit 12-7, respectively. Data indicated by "0" in the toggle pattern of each lane is data that should be in phase across all lanes. This notation is used in subsequent figures. After the usage control process, the phases of the toggle patterns of each lane are usually shifted by more than one clock of the external clock.

[0116] Next, the clock selection unit 17 selects a divided clock (divided clock selection step S13).

[0117] Next, the frequency division ratio setting unit 33 sets the value of the frequency division ratio of the frequency-divided clock in the frequency-divided clock output unit 14 to 64 (frequency division ratio setting step S14). At this time, there is a phase difference between the frequency-divided clock and the external clock, but this does not need to be taken into consideration at this point.

[0118] Next, the FPGA control unit 15 executes a full-range phase measurement process using the frequency-divided clock (step S15). As shown in Fig. 12(a), the process of step S15 includes the processes of steps S31 to S33.

[0119] In step S31, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency half the frequency of the divided clock whose division ratio has been set to 64 in the division ratio setting step S14 (rate control step S31).

[0120] Next, the phase acquisition processing unit 31b calculates the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40 while changing the phase of the toggle pattern output from each transceiver 20 from the initial value in the range of −0.75 UI to +0.75 UI, with one cycle of the frequency-divided clock having a frequency division ratio of 64 being 1 UI. H , and the minimum value V L (phase acquisition processing step S32).

[0121] Next, the phase difference calculation processing unit 31d calculates the initial value V0 and the maximum value V of the detected voltage acquired in the phase acquisition processing step S32. H , and the minimum value V L Based on this, a first initial phase difference P between the divided clock with a division ratio of 64 and the initial value of the phase of the toggle pattern output from each transceiver 20 is calculated. C1 A first phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S33).

[0122] FIG. 14(a) shows the first initial phase difference P C11 is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the calculation of . At this time, if the maximum phase difference between the toggle patterns of each lane is 32 UI or less based on the external clock, the subsequent phase shift process can be executed without error.

[0123] Next, the phase shift processing unit 31e shifts the phase of the toggle pattern from the initial value to the first initial phase difference P so that the phase difference between the frequency-divided clock, whose frequency division ratio is set to 64 in the frequency division ratio setting step S14, and the toggle pattern output from each transceiver 20 falls within a predetermined range. C1 Then, a first phase shift process is executed to shift the phase by the amount of (phase shift process step S16).

[0124] 14(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the first phase shift process when the division ratio of the divided clock is 64. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 6.4 UI or less (0.1 UI × 64 division) based on the external clock.

[0125] If the current division ratio is greater than 4 (step S17: NO), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to 1 / 4 of the current value (division ratio setting step S18).

[0126] Next, the FPGA control unit 15 executes a current phase measurement process (step S19). As shown in Fig. 12(c), the process of step S19 includes the processes of steps S37 to S39.

[0127] In step S37, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the divided clock having the division ratio set in the division ratio setting step S18 (rate control step S37).

[0128] Next, the initial voltage acquisition processing unit 31c executes an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit 40 as an initial voltage V0' (initial voltage acquisition process step S38).

[0129] Next, the phase difference calculation processing unit 31d calculates the maximum value V of the detected voltage acquired in the phase acquisition processing step S32. H and minimum value V L and a second initial phase difference P between the phase of the toggle pattern output from each transceiver 20 and the divided clock selected by the clock selector 17 based on the initial voltage V0′ acquired in the initial voltage acquisition process step S38. C2 Then, a second phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S39).

[0130] Next, in step S16, the phase shift processing unit 31e shifts the phase of the toggle pattern from the current value to the second initial phase difference P so that the phase difference between the divided clock having the division ratio set in the division ratio setting step S18 and the toggle pattern output from each transceiver 20 falls within a predetermined range. C2 Then, a second phase shift process is executed to shift the phase by the amount of (phase shift process step S16). Then, the processes from step S17 onwards are executed again.

[0131] That is, steps S16 to S19 are steps for repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while gradually decreasing the frequency division ratio in the frequency division ratio setting step S18.

[0132] 15A shows the second initial phase difference P C2 FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0133] 15(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the second phase shift process when the division ratio of the divided clock is 4. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 0.4 UI or less (0.1 UI × 4 division) based on the external clock.

[0134] On the other hand, if the current division ratio is 4 or less (step S17: YES), the clock selector 17 selects the external clock instead of the divided clock (external clock selection step S20). The external clock corresponds to a divided clock with a division ratio of 1, but its phase does not match that of the normal divided clock.

[0135] Next, the FPGA control unit 15 executes a full-range phase measurement process using the external clock (step S21). As shown in FIG. 12(b), the process of step S21 includes processes of steps S34 to S36.

[0136] In step S34, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the external clock (rate control step S34).

[0137] Next, the phase acquisition processing unit 31b calculates the initial value V0 and maximum value V1 of the detected voltage output from the phase detection unit 40 while changing the phase of the toggle pattern output from each transceiver 20 from the initial value within the range of −0.75 UI to +0.75 UI, with one cycle of the external clock being 1 UI. H , and the minimum value V L (phase acquisition processing step S35).

[0138] Next, the phase difference calculation processing unit 31d calculates the initial value V0 and the maximum value V of the detected voltage acquired in the phase acquisition processing step S35. H , and the minimum value V L Based on this, a first initial phase difference P between the external clock and the initial value of the phase of the toggle pattern output from each transceiver 20 is calculated. C1Then, a first phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S36).

[0139] FIG. 16(a) shows the first initial phase difference P C1 FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0140] Next, the phase shift processing unit 31e shifts the phase of the toggle pattern from the initial value to a first initial phase difference P so that the phase difference between the external clock selected in the external clock selection step S20 and the toggle pattern output from each transceiver 20 falls within a predetermined range. C1 Then, a first phase shift process is executed to shift the phase by the amount of (phase shift process step S22).

[0141] 16(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the first phase shift process when the external clock is selected by the clock selection unit 17. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI (0.1 UI × 1 division) or less based on the external clock.

[0142] Then, the phase synchronization control unit 31 goes into a standby state until each transceiver unit 12 is activated or reset again (step S11).

[0143] In step S11, the transceiver units 12 are started or reset, so that the processes from step S12 onward are automatically executed, but the present invention is not limited to this. For example, in step S11, the user may press an execute button provided on an operation screen (not shown) of the signal generating device 1 via the operation unit 65, so that the user can execute the processes from step S12 onward at any timing.

[0144] When the phase adjustment of the toggle pattern output from each transceiver 20 is completed in step S22, the FPGA control unit 15 automatically transitions to a mode for generating a PAM signal during normal operation, and causes the parallel data output unit 11 to output N-bit parallel data for normal operation according to the frequency of the external clock.

[0145] In this way, the signal generation method using the signal generating device 1 of this embodiment initially uses a divided clock with a large division ratio to roughly adjust the phase of the toggle pattern of each lane with a large amount of movement, and finally uses an external clock with a division ratio equivalent to 1 to finely adjust the phase of the toggle pattern of each lane with a small amount of movement.

[0146] In steps S16 to S19, in which the initial voltage acquisition process, the second phase difference calculation process, and the second phase shift process are repeatedly performed while the division ratio is gradually decreased, the maximum value V of the detected voltage increases as the frequencies of the clock and the toggle pattern increase. H and minimum value V L Therefore, in the signal generation method using the signal generator 1 of this embodiment, the relationship between the phase of the detection voltage and the toggle pattern is measured again by the full-range phase measurement process using the external clock in step S21, and the maximum value V of the detection voltage that matches the frequency of the external clock is calculated. H and minimum value V L It is designed to obtain the following.

[0147] As described above, the signal generating device 1 according to this embodiment is configured to repeatedly execute the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while gradually decreasing the division ratio of the divided clock by the division ratio setting unit 33.

[0148] With this configuration, the signal generating device 1 according to this embodiment can reduce the maximum phase difference between the serial data output from the plurality of transceivers 20 to 0.1 UI or less relative to the external clock.

[0149] Furthermore, the signal generating device 1 according to this embodiment detects the maximum value V of the detected voltage acquired by one phase acquisition process. H and minimum value V L and the current initial voltage V0′ acquired by the initial voltage acquisition process, a second initial phase difference P between the frequency-divided clock selected by the clock selection unit 17 and the phase of the toggle pattern shifted by the phase shift processing unit 31e is calculated. C2 The following formula is calculated:

[0150] As a result, the signal generating device 1 of this embodiment reduces the number of phase acquisition processes to one, thereby reducing the time required for phase matching between lanes compared to the prior art technology in which the phase acquisition process is repeated every time the division ratio changes.

[0151] Specifically, the signal generating device 1 according to this embodiment reduces the number of phase acquisition processes to one, thereby reducing the total measurement time required for the ADC 55 to generate digital data of the detected voltage during the phase acquisition process and the initial voltage acquisition process by approximately 70% compared to the prior art.

[0152] On the other hand, the total time required for phase shifting to shift the phase of the toggle pattern in the phase acquisition process and the phase shift process is about 1 / 100 of the total time required for measurement, and the measurement time dominates the total time required. Therefore, the signal generating device 1 according to this embodiment can be expected to reduce the total time required by about 70%.

[0153] Furthermore, the signal generating device 1 according to this embodiment can significantly increase the maximum phase difference that allows phase matching between the serial data output from the plurality of transceivers 20 after startup or resetting.

[0154] For example, the signal generating device 1 according to this embodiment can set the maximum phase difference that can be matched between the serial data from each transceiver 20 to 32 UI relative to the external clock. This value corresponds to 1000 ps at 32 Gbps, for example. For example, the phase error listed in the data sheet for Xilinx UltraScale+ GTY transceivers is 500 ps, and the signal generating device 1 according to this embodiment can converge this phase error.

[0155] Furthermore, the signal generating device 1 according to this embodiment does not require an additional mechanism such as a delay circuit external to the FPGA to limit the phase difference between pre-adjusted serial data to within 1 UI in advance, so there is no need to investigate the parameters to be given to the additional mechanism after the product is manufactured.

[0156] Although the signal generating device 1 according to this embodiment requires an ADC 55 for each lane, the required speed performance is low (several hundred ksps to several Msps), so an ADC with multiple input channels can be used, and the ADC peripheral circuitry can be made smaller. Furthermore, the signal generating device 1 according to this embodiment does not require an external delay circuit, so the circuit scale and board size can also be reduced.

[0157] Furthermore, the signal generating device 1 according to this embodiment is configured to execute a usage control process to halve the usage of the FIFO 21 of all lanes before starting the full-area phase measurement process using the divided clock, including the phase acquisition process. As a result, the signal generating device 1 according to this embodiment can shift the phase of the toggle pattern in both positive and negative directions within a range of up to -1 UI to +1 UI during the phase acquisition process, for example, when the usage of the FIFO 21 corresponds to 2 UI of the divided clock with the maximum division ratio. [Explanation of symbols]

[0158] 1. Signal Generator 10 Data output section 11 Parallel data output section 12, 12-1 to 12-8 Transceiver section 14-divided clock output section 15 FPGA control unit 17 Clock selection section 20,20-0~20-3 Transceiver 21 FIFO 22 PISO 23 Usage amount determination section 24 Phase adjustment section 31 Phase synchronization control section 31a Usage control processing unit 31b Phase acquisition processing unit 31c Initial voltage acquisition processing section 31d Phase difference calculation processing unit 31e Phase shift processing unit 33 Division ratio setting section 34 Rate control section 40 Phase detection section

Claims

1. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of transceivers (20) each having a FIFO (21) for storing N-bit parallel data among the plurality of bits of parallel data output from the parallel data output unit, and for converting the N-bit parallel data stored in the FIFO into 1-bit serial data; a phase synchronization control unit (31) for controlling the phase of the 1-bit serial data converted by each of the transceivers; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a division ratio setting unit (33) that sets the division ratio of the divided clock to the divided clock output unit; a clock selection unit (17) that selects either the external clock or the divided clock; a rate control unit (34) that controls each of the transceivers to output, as the 1-bit serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit; a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern, The phase synchronization control unit a phase acquisition processing unit (31b) that executes a phase acquisition process to acquire an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing unit (31d) that executes a first phase difference calculation process to calculate a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern, based on the initial value, the maximum value, and the minimum value of the detection voltage acquired by the phase acquisition processing unit; a phase shift processing unit (31e) that shifts the phase of the toggle pattern so that a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; an initial voltage acquisition processing unit (31c) that executes an initial voltage acquisition process to acquire the detected voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern is shifted by the phase shift processing unit, the phase difference calculation processing unit further executes a second phase difference calculation process to calculate a second initial phase difference between the divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing unit, based on the maximum and minimum values of the detected voltage acquired by the phase acquisition processing unit and the initial voltage acquired by the initial voltage acquisition processing unit; the phase shift processing unit executes a first phase shift process of shifting the phase of the toggle pattern from the initial value by the first initial phase difference, and a second phase shift process of shifting the phase of the toggle pattern shifted by the first phase shift process by the second initial phase difference, the phase synchronization control unit repeatedly executes the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while the division ratio setting unit gradually decreases the division ratio; a clock selector for selecting the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value;

2. 2. The signal generating device according to claim 1, wherein the clock selection unit selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

3. Each of the transceivers comprises: a PISO (22) that converts the N-bit parallel data read from the FIFO into the 1-bit serial data in response to a read clock signal; a usage determination unit (23) that executes first and second usage determination processes to determine whether the usage of the FIFO is equal to or greater than a usage threshold; a phase adjustment unit (24) that executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, the phase synchronization control unit further includes a usage control processing unit (31 a) that executes a usage control processing for controlling a usage amount of the FIFO before the phase acquisition processing unit executes the phase acquisition processing, The usage control processing of the usage control processing unit includes: a process of causing the usage amount determiner to execute the first usage amount determination process on the condition that output of the serial data from each of the transceivers has started; a process of causing the phase adjustment unit to execute the first phase adjustment process on condition that it is determined by the first usage amount determination process that the usage amount of the FIFO of each of the transceivers is equal to or greater than the usage amount threshold; a process of causing the usage determination unit to execute the second usage determination process on condition that the number of consecutive times that it has been determined in the first usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold has reached a first determination number; a process of causing the phase adjustment unit to execute the second phase adjustment process on condition that it is determined in the second usage amount determination process that the usage amount of the FIFO of each of the transceivers is less than the usage amount threshold; and a process of causing the phase adjustment unit to terminate adjustment of the phase of the read clock signal on condition that the number of consecutive times that the usage of the FIFO of each transceiver is determined to be equal to or greater than the usage threshold value by the second usage determination process reaches a second determination number.

4. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of transceivers (20) each having a FIFO (21) for storing N-bit parallel data among the plurality of bits of parallel data output from the parallel data output unit, and for converting the N-bit parallel data stored in the FIFO into 1-bit serial data; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the external clock or the divided clock; a phase detection unit (40) that outputs a detection voltage corresponding to a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, the signal generation method controlling the phase of the 1-bit serial data converted by each of the transceivers, comprising: a division ratio setting step (S14, S18) of setting the division ratio of the divided clock to the divided clock output unit; a rate control step (S31, S37) of causing each of the transceivers to output, as the 1-bit serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit; a phase acquisition processing step (S32, S35) of executing a phase acquisition process to acquire an initial value, a maximum value, and a minimum value of the detection voltage output from the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S33, S36, S39) of executing a first phase difference calculation processing to calculate a first initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern, based on the initial value, the maximum value, and the minimum value of the detection voltage acquired in the phase acquisition processing step; a phase shift processing step (S16, S22) of shifting the phase of the toggle pattern so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; an initial voltage acquisition processing step (S38) of executing an initial voltage acquisition processing to acquire the detected voltage output from the phase detection unit as an initial voltage after the phase of the toggle pattern is shifted by the phase shift processing step, the phase difference calculation processing step further executes a second phase difference calculation processing to calculate a second initial phase difference between the frequency-divided clock selected by the clock selection unit and the phase of the toggle pattern shifted by the phase shift processing step, based on the maximum and minimum values of the detection voltage acquired by the phase acquisition processing step and the initial voltage acquired by the initial voltage acquisition processing step; the phase shift processing step executes a first phase shift processing of shifting the phase of the toggle pattern from the initial value by the first initial phase difference, and a second phase shift processing of shifting the phase of the toggle pattern shifted by the first phase shift processing by the second initial phase difference, The signal generating method includes: a step (S16 to S19) of repeatedly executing the initial voltage acquisition process, the second phase difference calculation process, and the second phase movement process while gradually decreasing the frequency division ratio in the frequency division ratio setting step; an external clock selection step (S20) of selecting the external clock instead of the divided clock by the clock selection unit after the first phase shift process or the second phase shift process is executed when the division ratio is equal to or less than a predetermined value.

5. 5. The signal generating method according to claim 4, wherein the external clock selecting step selects the external clock instead of the divided clock after the first phase shift process or the second phase shift process is executed when the division ratio is 4 or less.

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