Air conditioning system, receiving device, and communication method

Abstract

To provide an air conditioning system with improved data transmission efficiency.SOLUTION: An air conditioning system (1) includes a plurality of devices (for example, an indoor device 4, an outdoor device 6). A first device (for example, the outdoor device 6) of the plurality of devices includes a decoding unit (12) that decodes a data signal, which is received from a second device (for example, the indoor device 4) of the plurality of devices via a communication line (L10), and in which data having a preamble is encoded, and outputs the decoded signal, a clock extraction unit (18) that outputs a clock signal (VCO_Out) in phase synchronization with a reference signal, where a portion of the decoded signal corresponding to the preamble is set as the reference signal (Sig_IN), and a recognition unit (16) that recognizes received data from the decoded signal input after the end of the preamble, based on the clock signal that is continuously output by the clock extraction unit (18).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an air conditioning system, and more particularly to an air conditioning system, a receiving device, and a communication method for performing communication between devices via a communication line. [Background technology]

[0002] Air conditioning systems that implement serial data communication in accordance with the Home Bus System (HBS) are known. This serial data communication is carried out using a start-stop synchronization circuit such as a Universal Asynchronous Receiver Transmitter (UART) built into the microprocessor in both the outdoor and indoor units. This serial data communication transmits 8 bits of information over a total of 11 bits, including a start bit, parity, and stop bit. Therefore, the data transmission efficiency η, calculated by dividing the data to be transmitted by the total size including additional data, is 8 / 11 = 72.7%.

[0003] There is a demand for faster and more multi-functional communication in air conditioning systems, and there is also a demand for faster control communication speeds.As the amount of communication data increases, there is a demand not only for faster physical communication speeds, but also for improvements in the data transmission efficiency mentioned above.

[0004] In addition, Japanese Patent Application Laid-Open No. 2022-056052 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2019-004216 (Patent Document 2) are known with respect to data communication in air conditioning systems.

[0005] Patent Document 1 discloses a configuration in an air conditioning system in which multiple air conditioning devices belonging to the same refrigerant system are connected via communication lines within the system, and multiple air conditioning devices belonging to different refrigerant systems are connected via communication lines outside the system, in which recognition processing can be performed while air conditioning control processing is being performed for multiple air conditioning devices belonging to the same refrigerant system by transmission via at least the communication lines within the system.

[0006] Furthermore, Patent Document 2 discloses a communication control device that includes a communication unit that can communicate by switching between a first communication method and a second communication method of a time division multiple access method, and a first communication detection period generation instruction unit that instructs the generation of a channel usage detection period for the first communication method when communicating using the second communication method, and the communication unit transmits a signal including the channel usage detection period onto a transmission path based on the instruction to generate the channel usage detection period from the first communication detection period generation instruction unit.

[0007] However, the conventional techniques of Patent Documents 1 and 2 do not disclose any improved techniques from the viewpoint of improving data transmission efficiency. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2022-056052 [Patent Document 2] Japanese Patent Application Publication No. 2019-004216 Summary of the Invention [Problem to be solved by the invention]

[0009] The present disclosure has been made in consideration of the above-mentioned conventional technology, and aims to provide an air conditioning system, a receiving device, and a communication method that can improve the data transmission efficiency of data communication between devices in an air conditioning system. [Means for solving the problem]

[0010] The present disclosure provides an air conditioning system including a plurality of devices having the following characteristics. In this air conditioning system, a first device of the plurality of devices includes a decoding unit that decodes a data signal, in which data having a preamble is encoded, received from a second device of the plurality of devices via a communication line, and outputs a decoded signal. The first device also includes a clock extraction unit that uses a portion of the decoded signal corresponding to the preamble as a reference signal and outputs a clock signal in phase synchronization with the reference signal. The first device further includes a recognition unit that recognizes received data from the input decoded signal based on the clock signal that is continuously output by the clock extraction unit after the end of the preamble. [Effects of the Invention]

[0011] With the above configuration, it is possible to improve the data transmission efficiency of data communication between devices in an air conditioning system.

[0012] The present disclosure also provides a receiving device and a communication method having the above-mentioned functions. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram illustrating an air conditioning system including one or more indoor units and outdoor units according to one or more embodiments of the present disclosure. [Figure 2] FIG. 2 is a circuit block diagram illustrating communication-related components of an outdoor unit in an air conditioning system according to a first embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating serial data communication in the air conditioning system according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a data frame format used in serial data communication in an air conditioning system according to one or more embodiments of the present disclosure. [Figure 5] FIG. 5 is a timing chart showing a clock extraction operation during reception in the communication circuit of the outdoor unit according to the first embodiment of the present disclosure. [Figure 6]FIG. 6 is a diagram showing a switch connection state before lock-in of a clock extraction unit in a communication circuit of an outdoor unit according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram showing switch connections after lock-in of a clock extraction unit in a communication circuit of an outdoor unit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing an environment in which a high-speed indoor unit 4 and a high-speed outdoor unit 6 according to the second embodiment of the present disclosure are mixed with an existing indoor unit 5 and an existing outdoor unit 7. In FIG. [Figure 9] FIG. 9 is a diagram illustrating serial data communication in an air conditioning system according to a second embodiment of the present disclosure. [Figure 10] FIG. 10 is a timing chart of serial data communication between a high-speed outdoor unit and a high-speed indoor unit in an environment where existing devices exist in the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating serial data communication in a conventional air conditioning system. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings, but the embodiments of the present disclosure are not limited to the specific embodiments described below. In the drawings, the same reference numerals indicate the same or corresponding parts.

[0015] The present disclosure relates to an air conditioning system, a receiving device, and a communication method. An air conditioning system includes a plurality of devices (for example, an indoor unit, an outdoor unit, a remote controller, a central control device, etc.).

[0016] Focusing on a receiving device among the multiple devices, the device includes a decoder (e.g., transceiver 12) that decodes a data signal (e.g., a serial data signal) in which data having a preamble is encoded and that is received via a communication line from another transmitting device, and outputs a decoded signal. The device also includes a clock extractor (e.g., clock extractor 18) that uses a portion of the decoded signal corresponding to the preamble as a reference signal and outputs a clock signal in phase synchronization with the reference signal. The device further includes a recognition unit (e.g., SCI 16) that recognizes received data from the input decoded signal based on the clock signal that is continuously output by the clock extractor after the end of the preamble.

[0017] In the above configuration, the clock signal, which is phase-synchronized with the portion of the decoded signal corresponding to the preamble, maintains its phase for a certain period of time even after the end of the preamble. Therefore, the recognition unit can recognize the received data from the input decoded signal based on the clock signal continuously output by the clock extraction unit. This reduces the ratio of additional data to the data to be transmitted, thereby improving the data transmission efficiency of data communication between devices in the air conditioning system.

[0018] In a preferred embodiment, the device further includes a sample-and-hold circuit that fixes an adjustable parameter of the oscillator circuit of the clock extraction unit in response to the end of the preamble, thereby fixing the parameter after the end of the preamble when phase synchronization is complete, thereby maintaining the phase of the clock signal for a fixed period of time.

[0019] In a specific embodiment, the device includes a voltage-controlled oscillator (VCO) that generates a clock signal. The device also includes a frequency divider (e.g., a divide-by-2 frequency divider) that divides the clock signal generated by the VCO to generate a comparison signal. The device further includes a phase comparator (PC) that detects a phase difference between a reference signal (Sig_IN) and a comparison signal (Cmp_IN). In this specific embodiment, the adjustable parameter of the oscillator circuit is an input value of the tuning voltage (VT) of the VCO. Before the end of the preamble, an output (PC_Out) corresponding to the phase difference detected by the PC is input to the tuning voltage (VT) of the VCO, and the sample-and-hold circuit holds the output corresponding to the phase difference detected by the PC. Meanwhile, in response to the end of the preamble, the output of the sample-and-hold circuit is input to the tuning voltage (VT) of the VCO.

[0020] In a preferred embodiment, the division ratio of the comparison signal input to the clock extraction unit for phase synchronization with respect to the clock signal is 2. In this preferred embodiment, the preamble corresponds to a bit string (e.g., "1010101...") in which one logical "1" and one logical "0" are alternately arranged. This maximizes time efficiency and ultimately improves data transmission efficiency.

[0021] In a preferred embodiment, the encoded data signal is data encoded using a clock-imperfect coding scheme that does not include a data communication clock component in the code. Here, the clock-imperfect coding scheme refers to a coding scheme that does not guarantee a clock by itself, but rather, by combining with the properties of the data, can include clock information at a rate of one for every several bits. In a specific embodiment, the clock-imperfect coding scheme is an AMI (Alternate Mark Inversion) coding scheme. The AMI coding scheme distinguishes between a logic "1" and a logic "0" in data by the presence or absence of a pulse. For example, if a logic "0" is present, clock information is present when the data is a logic "0," and clock information is present when the data is a logic "0," but is absent when the data is a logic "1."

[0022] In a preferred embodiment, the fundamental frequency of the encoded data signal generated on the communication line is F1 [Hz], the frequency of the clock signal extracted by the clock extraction unit is F2 [Hz], and F2 = F1 × 2 holds. For example, in the above-mentioned AMI encoding method, the fundamental frequency F1 [Hz] of the encoded data signal is the frequency of the frequency component of data "10" (when there is a succession of pulses with and without pulses), and in this case, one cycle is made up of two pulses, so for example, if the minimum pulse width (1 bit) is 10 μsec, F1 is 50 kHz and the frequency F2 of the clock signal is 100 kHz.

[0023] In a preferred embodiment, where F3 is the frequency of the frequency component of the decoded signal corresponding to the preamble and F4 (bps) is the data communication rate of the encoded data signal, the following equation holds: F4 [bps] = F3 [Hz] × 2. For example, if the preamble is a bit string in which one logical "1" and one logical "0" are alternately arranged, one period is made up of two bits of data "10." Therefore, when the data communication rate F4 is 100 kbps, the frequency F3 [Hz] of the frequency component of the decoded signal corresponding to the preamble is 50 kHz.

[0024] In a preferred embodiment, a data frame of the encoded data signal includes data length information. In this preferred embodiment, the device includes a control unit that calculates the end point of the payload in the data frame based on the data length information, and, in response to the end of the payload, releases the fixed parameters of the sample-and-hold circuit and controls the clock extraction unit to resume waiting for phase synchronization between the clock signal and the reference signal. This completes preparations to accept the next frame (first preamble).

[0025] In another preferred embodiment, the control unit calculates the end point of the payload in the data frame based on the data length information, and after the end of the payload, in response to receiving a post-word, releases the parameters fixed by the sample-and-hold circuit and resumes waiting for the clock signal and reference signal to be synchronized by the clock extraction unit. This makes the device ready to accept the next frame (first preamble). In addition, the control unit captures the received data if the post-word matches a predefined value, but requests retransmission if the post-word does not match the predefined value. In the event of a mismatch, the received data may be discarded. In this way, a mismatch in the post-word is assumed to indicate a phase shift, so requesting retransmission ensures accurate reception of the received data. According to an embodiment of the present disclosure, the received data is recognized based on the clock signal continuously output by the clock extraction unit, and by checking the match of the post-word, correct reception of the data can be more reliably achieved.

[0026] In a preferred embodiment, the device includes a serial communication interface including a recognition unit within a processor and an asynchronous circuit for asynchronous communication. Furthermore, another device among the plurality of devices communicates in asynchronous communication. The device transmits data using the asynchronous circuit to acquire the right to transmit prior to communication via the serial communication interface. When a new device is introduced into an existing air conditioning system, it typically coexists with existing devices. The above configuration enables communication in a mixed environment with an existing device (third device) that communicates in asynchronous communication. In a specific embodiment, the existing device (third device) communicates using carrier sense multiple access (CSMA).

[0027] In one or more embodiments, the preamble corresponds to a bit string in which logical "1"s and logical "0"s are alternately arranged, for example, one by one ("1010101..."). In one or more embodiments, the data frame may include a preamble, a synchronization word, a header, and a payload. The header may include information about the length of the data described above.

[0028] In another embodiment, a receiving device is provided, further comprising the following features: The receiving device includes a decoding unit that decodes a data signal, received from the transmitting device via a communication line, in which data having a preamble is encoded, and outputs a decoded signal; The receiving device also includes a clock extraction unit that uses a portion of the decoded signal corresponding to the preamble as a reference signal and outputs a clock signal in phase synchronization with the reference signal; The receiving device further includes a recognition unit that recognizes received data from the input decoded signal after the end of the preamble, based on the clock signal that is continuously output by the clock extraction unit.

[0029] The above configuration makes it possible to improve the data transmission efficiency of data communication between the receiving device and the transmitting device.

[0030] In yet another embodiment, there is provided a communication method having the following features. The communication method includes a step of receiving, via a communication line, a data signal in which data having a preamble is encoded from a transmitting device, by a receiving unit of the receiving device. The communication method also includes a step of decoding, by a decoding unit of the receiving device, the encoded data signal to generate a decoded signal. The communication method further includes a step of generating, by a clock extraction unit of the receiving device, a clock signal in phase synchronization with a reference signal, using a portion of the decoded signal corresponding to the preamble as a reference signal. The communication method still further includes a step of recognizing, by a recognition unit of the receiving device, the received data based on the clock signal continuously generated from the decoded signal input after the end of the preamble.

[0031] In a particular embodiment, a communication method includes encoding data with a preamble by an encoding unit of a transmitting device, and further includes transmitting the encoded data signal over a communication line by a transmitting unit of the transmitting device.

[0032] The above configuration makes it possible to improve the data transmission efficiency of data communication between devices.

[0033] Below, serial data communication in an air conditioning system 1 according to one or more embodiments of the present disclosure will be explained with reference to Figures 1 to 7, but first, the overall configuration of the air conditioning system 1 according to an embodiment of the present disclosure will be explained with reference to Figure 1.

[0034] FIG. 1 is a schematic diagram showing an air conditioning system 1 including one or more indoor units 4 and an outdoor unit 6 according to an embodiment of the present disclosure. The air conditioning system 1 is a device that conditions air by circulating a refrigerant in a refrigeration cycle. As shown in FIG. 1, the air conditioning system 1 includes one or more indoor units 4 (4a, 4b, etc.) that are installed indoors (spaces to be air-conditioned), and an outdoor unit 6 that is installed outdoors. The one or more indoor units 4a, 4b, etc. and the outdoor unit 6 are connected via refrigerant piping (not shown). For example, a hydrofluorocarbon such as R410a or R32 is used as the refrigerant.

[0035] During operation, the indoor unit 4 takes in indoor air, exchanges heat between the taken-in air and a refrigerant supplied from the outdoor unit 6, and blows out cooled or heated air to cool or heat the room to a set temperature. The outdoor unit 6 starts up upon receiving instructions from the control device, and controls the operation of the compressor and outdoor fan according to the operation mode set by an operating device such as a remote controller or central control device.

[0036] 1 shows two indoor units 4a and 4b as the indoor units 4, the number of indoor units 4 is not particularly limited and may be one, or three or more. Also, the number of outdoor units 6 is shown as one, but is not limited to one.

[0037] In the air conditioning system 1, the indoor unit 4 and the outdoor unit 6 are connected via a communication line 2. In addition, an operating device such as a remote controller for operating the indoor unit 4 may be connected to the indoor unit 4 in the room where the indoor unit 4 is installed via the communication line 2 or another communication line. Furthermore, a centralized controller that centrally controls one or more indoor units 4a, 4b and the outdoor unit 6 may be connected via the communication line 2 or another communication line.

[0038] 1, the air conditioning system 1 is shown as an embodiment of a multi-air conditioner for a building equipped with an up-blowing type outdoor unit 6. However, in the embodiment of the present disclosure, the form of the air conditioning system 1 is not particularly limited, and may be a packaged air conditioner.

[0039] In the air conditioning system 1 described above, serial data communication is carried out between devices, such as between the indoor unit 4 and the outdoor unit 6, and between the central control device and the indoor unit 4 or the outdoor unit 6. Serial data communication in a conventional air conditioning system will now be described with reference to FIG.

[0040] FIG. 11 is a diagram illustrating serial data communication in a conventional air conditioning system. The following description will be given using an example of a serial data communication method that uses the AMI (Alternate Mark Inversion) coding method. As shown in FIG. 11, a conventional air conditioning system 100 includes an outdoor unit 110 and an indoor unit 150. The outdoor unit 110 and the indoor unit 150 are connected via a communication line L10', such as a non-polarized two-core crossover wire. The outdoor unit 110 includes an AMI transceiver 112 and a microprocessor 114. The microprocessor 114 incorporates an asynchronous circuit 116, such as a UART. The indoor unit 150 also has a similar configuration to the outdoor unit 110; however, for ease of explanation, only the AMI transceiver 152 in the indoor unit 150 is shown in FIG. 11. The communication speed of the AMI transceivers 112, 152 is, for example, 9.6 kbps.

[0041] Let us consider a case where data is transmitted from the indoor unit 150 to the outdoor unit 110 using the AMI encoding method. The AMI encoding method has an encoding rule where, for example, a logical "0" is encoded and a logical "1" is no signal. For example, when data whose bit assignment is shown in S1' is transmitted via the communication line L10' using the AMI encoding method, the AMI waveform on the communication line becomes a waveform shown in S2'. In S2', ST+D0, which is the combination of the first start bit and the first data bit, contains a double-width pulse, and the subsequent data (D1 to D7+parity (PR)+stop bit (SP)) each has a single-width pulse. Assuming a transmission speed of 9.6 kbps, the pulse width P' is 104 μsec.

[0042] In the receiving outdoor unit 110, the waveform of the decoded output DOUT' received and decoded by the AMI transceiver 112 is as shown by S3'. Even in S3', assuming a transmission speed of 9.6 kbps, the pulse width P' is 104 μsec. The start-stop synchronization circuit 116 of the microprocessor 114 receives the decoded output DOUT' from the AMI transceiver 112, triggers on the falling edge (↓) corresponding to the start bit, performs oversampling at a predetermined sampling rate (e.g., 9.6 kHz) (at the timing indicated by the circle in the figure), and recognizes the received data.

[0043] As described above, in the conventional air conditioning system 100, serial data communication transmits 8 bits of information using a total of 11 bits (ST, SP, PR) of time, as shown by S1' in Figure 11. Therefore, the data transmission efficiency η is η = 8 / (1 + 8 + 2) = 72.7%.

[0044] In order to cope with the increase in communication traffic required by a wide variety of air conditioning applications, faster data speeds are required. Not only is it necessary to increase the physical communication speed, but it is also necessary to further improve throughput by increasing the data transmission efficiency η.

[0045] (First embodiment) Serial data communication in the air conditioning system 1 according to the first embodiment of the present disclosure will be described in more detail below with reference to Figures 2 to 7. Figure 2 is a circuit block diagram showing communication-related aspects of the outdoor unit 6 in the air conditioning system 1 according to the first embodiment of the present disclosure.

[0046] 2, the outdoor unit 6 in the air conditioning system 1 according to the embodiment of the present disclosure includes a communication circuit 10, which includes a transceiver (TRX) 12, a microprocessor unit (MPU) 14, and a clock extraction unit 18. The communication circuit 10 includes an external terminal T to which a communication line for communicating with an external device is connected, and the transmission inputs (TxN, TxP) and reception inputs (RxN, RxP) of the transceiver 12 are connected to the external terminal T. A communication line such as a non-polarized two-core jumper wire is connected to the external terminal T.

[0047] The transceiver 12 is compatible with a predetermined encoding (decoding) method. Here, a clock-imperfect encoding method, which does not include a data communication clock component in the code, is preferably used as the encoding method. Here, the clock-imperfect encoding method is not a clock-perfect encoding method in which clock information is included in every bit, but rather an encoding method in which clock information is not guaranteed by itself and is included at a rate of one in several bits by combining with the properties of the data. Examples of clock-imperfect encoding methods include, but are not limited to, alternate mark inversion (AMI), non-return to zero (NRZ), return to zero (RZ), bipolar, and non-return to zero inversion (NRZI). In a specific embodiment, the alternate mark inversion (AMI) encoding method is preferably used as the clock-imperfect encoding method. The AMI encoding method distinguishes between a logic "1" and a logic "0" in data by the presence or absence of a pulse, with a logic "0" representing the presence of a pulse and a logic "1" representing the presence of a pulse. The following description assumes that the AMI encoding method is used.

[0048] The MPU 14 includes a serial communication interface (SCI) 16. The transmit data terminal TD of the SCI 16 of the MPU 14 is input to the data encoding input DIN of the transceiver 12. The data decoding output DOUT of the transceiver 12 is input to the receive data terminal RD of the SCI 16.

[0049] The clock extraction unit 18 includes a phase comparator (PC) 20 and a voltage controlled oscillator (VCO) 22, which is an oscillation circuit, and is implemented as a phase locked loop (PLL). In a specific embodiment, the clock extraction unit 18 may be implemented as an LSI PLL circuit incorporating the phase comparator 20 and VCO 22. The peripheral components of the clock extraction unit 18 include a frequency divider 24, a clock extraction input switch 26, an adjustment voltage switch 28, and a sample and hold circuit (S / H) 30.

[0050] The clock extraction unit 18 has a reference signal input Sig_IN, a phase comparison signal input Comp_IN, and an oscillation output VCO_Out. The oscillation output VCO_Out of the clock extraction unit 18 outputs a clock signal of a predetermined frequency generated by an internal VCO 22. This clock signal is input to the serial clock input terminal SCLK of the SCI 16 of the MPU 14 via signal line L4. The oscillation output VCO_Out of the clock extraction unit 18 is also branched and looped through a frequency divider 24 to the phase comparison signal input Comp_IN of the clock extraction unit 18 via signal line L5. A clock signal divided by N is input to the phase comparison signal input Comp_IN of the clock extraction unit 18. In a preferred embodiment, the frequency division ratio of the frequency divider 24 is 2. The following description will be given assuming a frequency division ratio of 2.

[0051] The decoded data output DOUT of the transceiver 12 is connected to the clock extraction input switch 26 described above. One output of the clock extraction input switch 26 is the reference signal input Sig_IN of the clock extraction unit 18, and the other is non-connected (NC: Con Connection). The clock extraction input switch 26 switches the output destination in response to an external selection signal. In the state shown in FIG. 2, the decoded output DOUT signal of the transceiver 12 is input to the reference signal input Sig_IN of the clock extraction unit 18 via signal line L2.

[0052] The clock extraction unit 18 further has an adjustment voltage input VT, a phase comparison output PC_Out, and a source follower output SF. The adjustment voltage input VT is a terminal to which an adjustment voltage for changing the oscillation frequency of the internal VCO 22 is input. The source follower output SF is a terminal that buffers the adjustment voltage input VT within the LSI and outputs it. The phase comparison output PC_Out is the output of a phase comparator 20 within the LSI (for example, a charge pump output or, more simply, the output of an exclusive logic circuit (XOR)), and is an output corresponding to the phase difference. Note that, although a charge pump type PLL will be described as an example in the described embodiment, any type of PLL can be used.

[0053] The source follower output SF is connected to S / H 30 via signal line L8. S / H 30 is a circuit that holds the adjustment voltage input VT of the clock extraction unit 18 to fix it. S / H 30 has a switch, and in the state shown in FIG. 2, it is connected to the source follower output SF to charge an internal capacitor. The phase comparison output PC_Out is connected to adjustment voltage switch 28. In the state shown in FIG. 2, the phase comparison output PC_Out is smoothed by a low-pass filter (LPF) outside the LSI via signal line L7 and applied to adjustment voltage input VT. On the other hand, when S / H 30 and adjustment voltage switch 28 are in the opposite state to that shown in FIG. 2, the output (charged voltage) of S / H 30 is applied to adjustment voltage input VT, and the adjustment voltage is switched to a fixed value (fixed to the value at lock-in).

[0054] Fig. 3 is a diagram illustrating serial data communication in the air conditioning system 1 according to the first embodiment of the present disclosure. Fig. 4(A) and Fig. 4(B) show the format of a data frame used in serial data communication in the air conditioning system according to the first embodiment of the present disclosure. Below, the basic operation of serial data communication from the indoor unit 4 to the outdoor unit 6 will be described with reference to Fig. 3 and Figs. 4(A) and (B).

[0055] The outdoor unit 6 and the indoor unit 4 have similar configurations, but Figure 3 shows the communication circuit 10 on the outdoor unit 6 side shown in Figure 2 and the communication circuit 50 on the indoor unit 4, and a transceiver 52 is shown as a component of the communication circuit 50 on the indoor unit 4.

[0056] The communication circuit 50 of the indoor unit 4 transmits control data (such as a set temperature) to the outdoor unit 6 using the AMI encoding method at a predetermined communication speed Fbps (for example, 100 kbps; for ease of explanation, the following explanation will be given assuming a communication speed Fbps of 100 kbps, a frequency FHz of 100 kHz, and a pulse width P of 10 μsec, which are easy to calculate.) At this time, the waveform on the communication line L10 is a waveform in which positive and negative pulses alternate from a midpoint potential, as shown in S1. The waveform shown by S1 in Figure 3 is an example of 8 bits of data "10101010".

[0057] The transceiver 12 of the outdoor unit 6 receives an AMI-encoded serial data signal received from (the transceiver 52 of the communication circuit 50 of) the indoor unit 4 via the communication line L10, decodes the encoded serial data signal, and outputs the decoded signal from the decoded output DOUT. The transceiver 12 of the outdoor unit 6 constitutes the receiving unit and decoding unit in this embodiment, and the transceiver 52 of the indoor unit 4 constitutes the transmitting unit and encoding unit in this embodiment.

[0058] At the start of data reception, the clock extraction unit 18 synchronizes the phase of the decoded output DOUT decoded by the transceiver 12 with the oscillation output VCO_Out (=SCLK) of the VCO 22, and extracts a clock signal.

[0059] In the embodiment to be described, a data frame format shown in Fig. 4A is used to extract a clock signal of a predetermined frequency F (for example, 100 kHz). As shown in Fig. 4A, a data frame 70 includes a fixed-length preamble 72, a fixed-length sync word 74, a fixed-length header 76, and an arbitrary-length payload 78. The preamble 72 can be a bit string in which logical "1"s and logical "0"s are alternately arranged, more specifically, a bit string in which logical "1"s and logical "0"s are alternately arranged one by one.

[0060] In the following explanation, it is assumed that the 8-bit string "10101010" described above is used as the preamble 72. Therefore, the waveform of the decoded signal output from the decoded output DOUT is as shown in S3. As shown in S3, the preamble 72 alternates between logic "1" and logic "0" for each bit. Therefore, if the preamble is viewed as a clock waveform, one clock cycle consists of logic "10." Therefore, a 100 kbps preamble 72 is the same as a clock signal with a frequency F3 (e.g., 50 kHz), which is half the frequency F4 (e.g., 100 kHz). In other words, if the frequency component of the decoded signal corresponding to the preamble is F3 [Hz] and the data communication speed of the encoded serial data signal is F4 [bps], then F4 = F3 × 2 holds.

[0061] The clock extraction unit 18 receives the decoded output DOUT at its reference signal input Sig_IN, and receives a signal obtained by dividing the oscillation output VCO_Out of the VCO 22 by two at its phase comparison signal input Comp_IN. The clock extraction unit 18 uses a portion of the decoded signal from the decoded output DOUT corresponding to the preamble as a reference signal, compares the phase of the reference signal (Sig_IN) with the comparison signal (Comp_IN), performs lock-in, and outputs a clock signal phase-synchronized with the reference signal. The frequency F2 of the clock signal output from the VCO is twice the frequency F3 (=½ F Hz) of the frequency component of the decoded signal and the frequency of the comparison signal. The frequency F2 of this clock signal is preferably such that F2 = F1 × 2, where F1 is the fundamental frequency of the encoded serial data signal generated on the communication line. Here, the fundamental frequency F1 of the serial data signal refers to the frequency when pulses alternate between continuous and continuous.

[0062] Since the portion of the decoded signal corresponding to the preamble is the 8-bit bit string "10101010" described above, lock-in is completed during this period, and the MPU 14 switches the clock extraction input switch 26, the adjustment voltage switch 28, and the switch of S / H 30. This switching switches the decoded output DOUT to NC, the adjustment voltage input VT from the phase comparison output PC_Out to the output of S / H 30, and S / H 30 from the source follower output SF to the adjustment voltage input VT.

[0063] After the preamble ends, the SCI 16 of the MPU 14 samples the decoded signal input to the receive data terminal RD based on the fixed-frequency clock signal continuously input to the serial clock input terminal SCLK by the clock extraction unit 18, and recognizes the receive data (after the preamble). The SCI 16 constitutes the recognition unit in this embodiment, and the MPU 14 constitutes the control unit in this embodiment.

[0064] The operation of the circuit during and after preamble reception will be described in more detail below with reference to Figures 5 to 7. Figure 5 shows a timing chart of the clock extraction operation during reception in the communication circuit 10 of the outdoor unit 6 according to the first embodiment of the present disclosure. Figure 6 shows the switch connection state before lock-in of the clock extraction unit 18 in the communication circuit 10 of the outdoor unit 6 according to the embodiment of the present disclosure (during reception standby and preamble reception). Figure 7 shows the switch connection after lock-in of the clock extraction unit 18 in the communication circuit 10 of the outdoor unit 6 according to the embodiment of the present disclosure (during header and payload reception).

[0065] 6 and 7 will be described focusing on the differences between FIGS. 2 and 3. The clock extraction unit 18 is provided with a lock-in detector (LD) 32, and the LD 32 outputs a lock-in detection signal Lock_Det indicating that the clock extraction unit 18 has locked in to the MPU 14. Whether the clock extraction unit 18 has locked in can be determined by the LD 32 based on the phase comparison output PC_Out of the phase comparator 20 and the phase pulse signal output Ph_Pulse, which is also an output of the phase comparator 20. The MPU 14 outputs a switch control signal output Lock_IN that switches three locations: the S / H 30, the adjustment voltage switch 28, and the clock extraction input switch 26, based on the lock-in detection signal Lock_Det.

[0066] The operation of extracting a clock signal of a corresponding predetermined frequency FHz (for example, 100 kHz) from the decoded output DOUT of a predetermined communication speed Fbps (for example, 100 kbps) will be described in more detail below with reference to FIGS.

[0067] While waiting to receive data from other outdoor or indoor units, the MPU 14 fixes the switch control signal output Lock_IN, which switches three switches 26, 28, and 30, to high (H) as shown in Figure 6. When the switch control signal output Lock_IN is high (H), it assumes the state shown in Figure 6, and when it is low (L), it assumes the state shown in Figure 7. At this time, the clock extraction input switch 26 connects the reference signal input Sig_IN to the decoded output DOUT, the adjustment voltage switch 28 connects the adjustment voltage input VT to the phase comparison output PC_Out, and the S / H 30 connects to the source follower output SF to charge the internal capacitor. Furthermore, the VCO 22 inside the clock extraction unit 18 oscillates in a free-running state, centered on a predetermined frequency F (e.g., 100 kHz). The frequency divider 24 has a division ratio of 2.

[0068] Data is transmitted from another outdoor unit or indoor unit, and an 8-bit preamble of "10101010" at F bps (for example, 100 kbps) is input to the reference signal input Sig_IN. If this signal is used as a clock, the clock frequency will be 1 / 2 F Hz (for example, 50 kHz) as described above. On the other hand, the phase comparison signal input Comp_IN, which is obtained by dividing the oscillation frequency F Hz (for example, 100 kHz) of the VCO 22 by 2, is also 1 / 2 F Hz (for example, 50 kHz), and is subjected to phase comparison with the reference signal input Sig_IN.

[0069] Initially, as shown at point A in the flowchart in Figure 5, the phase comparison signal input Comp_IN is initially out of phase with the reference signal input Sig_IN. When the preamble is input sequentially from the first bit, the clock extraction unit 18 compares the phase of the reference signal of the reference signal input Sig_IN with the comparison signal of the phase comparison signal input Comp_IN, and eventually locks in at the timing of the seventh bit, as shown at point B in Figure 5. When lock-in occurs, the lock-in detection signal Lock_Det of the clock extraction unit 18 changes from low (L) to high (H).

[0070] When the lock-in detection signal Lock_Det changes to a high (H) level, the MPU 14 changes the switch control signal output Lock_IN from high (H) to low (L). As a result, as shown in Fig. 7, the clock extraction input switch 26 is connected from the reference signal input Sig_IN of the clock extraction unit 18 to the non-connection (NC) side, the adjusted voltage switch 28 connects the adjusted voltage input VT from the phase comparison output PC_Out to S / H 30, and S / H 30 is switched from the source follower output SF to the adjusted voltage switch 28. As a result, the oscillation output VCO_Out has a fixed frequency of FHz (e.g., 100kHz) that is phase-synchronized with the portion (reference signal) corresponding to the preamble in the decoded output DOUT (=Sig_IN), and the SCI 16 of the MPU 14 samples the decoded output DOUT input to the receive data terminal RD of a predetermined frequency of FHz, as shown at point C in the flowchart of Figure 5, and receives the receive data RxData (in the example of Figure 5, sampling is performed on the falling edge, but this is not limited to this and sampling can also be performed on the rising edge). This makes it possible to recognize data in units of bits, and after receiving the synchronization word 74, it becomes possible to recognize data in units of bytes, so that the header and preamble can be sampled based on the clock signal as shown at point D in Figure 5.

[0071] The above explains the flow of operations from the reception standby state to clock extraction and data recognition. Below, we will explain how to return to the reception standby state after data reception is complete, with reference to Figure 4(B).

[0072] FIG. 4(B) shows a more detailed format of the header in the air conditioning system 1 according to the first embodiment of the present disclosure, and explains how to return to a reception standby state after completing reception processing of received data.

[0073] Fig. 4(B) shows the timing at which the MPU 14 changes the switch control signal output Lock_IN back from low (L) to high (H). In the data frame 70 shown in Fig. 4(A), the internal configuration of the header 76 includes an outdoor unit address 76a, an indoor unit address 76b, and a payload length 76c. The payload length 76c is information indicating the length (number of bytes) of the payload 78 following the header 76, and constitutes data length information in this embodiment.

[0074] The MPU 14 calculates the end point of the payload 78 in the data frame based on the payload length 76c. The MPU 14 counts the length from the start of reception while receiving, and switches the switch control signal output Lock_IN from low (L) to high (H) in response to reaching the end point of the payload indicated by the payload length 76c. As a result, after reception of the received data is completed, the MPU 14 transitions again to a preamble reception standby state. In other words, the MPU 14 releases the fixation of the adjustment voltage input VT by the S / H 30 and resumes waiting for phase synchronization between the clock signal and the reference signal by the clock extraction unit 18.

[0075] Hereinafter, with reference to Fig. 4(C), a method for returning to a reception standby state after completing reception processing of received data in an air conditioning system according to an embodiment of a modified example of the present disclosure will be described. Fig. 4(C) shows a more detailed format around the payload in the air conditioning system 1 according to an embodiment of a modified example of the present disclosure, and also describes a method for returning to a reception standby state after completing reception processing of received data.

[0076] Fig. 4(C) shows the timing when the MPU 14 returns the switch control signal output Lock_IN from low (L) to high (H). The internal structure of the header 76 in the data frame 70 shown in Fig. 4(C) is the same as that in Fig. 4(B), but in the format of Fig. 4(C), a post-word 80 is added following the payload 78 that follows the header 76.

[0077] In the embodiment shown in FIG. 4B, the MPU 14 calculates the end point of the payload from the payload length 76c at the point corresponding to point P in FIG. 4C and returns the switch control signal output Lock_IN to high (H). In contrast, in the modified embodiment, a postword 80 with a predetermined value (e.g., 0x55) is added after the payload 78, and the MPU 14 determines whether the received data from point Q in FIG. 4C matches the predetermined value defined as the postword. If the value corresponding to the postword matches the predefined value, the MPU 14 determines that the received data is normal and imports it. Then, at point R in FIG. 4C, the MPU 14 returns the switch control signal output Lock_IN from low (L) to high (H). On the other hand, if the value corresponding to the postword does not match the predefined value, the MPU 14 discards the received data and causes the SCI 16 to transmit a retransmission request to the other party from the transmit data terminal TD. If there is a mismatch with the predefined value, it indicates that some error has occurred, such as a sampling error caused by a phase shift while the clock extraction unit 18 continues to output the clock signal. By checking the postword match, it is possible to more reliably recognize the correct received data.

[0078] Referring again to FIG. 4A, the data transmission efficiency in serial data communication according to an embodiment of the present disclosure will be described. As shown in FIG. 4A, typically, the preamble 72 can be 1 byte (8 bits), the synchronization word 74 can be 1 byte, and the header can be 3 bytes. If the payload is 11 bytes, the information to be transmitted, which is the combination of the header and payload, is 14 bytes in total. Meanwhile, the total data volume is 16 bytes (1 + 1 + 3 + 11), and the data transmission efficiency η is 87.5% (= 14 / 16). Furthermore, in an embodiment using a postword, assuming the same payload length, the total data volume is 17 bytes (1 + 1 + 3 + 11 + 1) for a total of 14 bytes, resulting in a data transmission efficiency η of 82.5% (= 14 / 17).

[0079] This exceeds the 72.7% achieved in conventional asynchronous technology, when 11 bits (including parity) are used to transmit 8 bits. Even with parity, the data transmission efficiency η is 80%, so this data transmission efficiency is even higher. Assuming the specifications of a typical VCO22, this clock extraction method is thought to be able to maintain a synchronized state of 15 bytes or more in a free-running state after phase synchronization. By making the payload longer than 11 bytes, the data transmission efficiency η can be further improved, achieving high throughput that can handle the high traffic demands of air conditioning applications.

[0080] In the above embodiment, only a preamble is provided in the frame for phase synchronization, but in other embodiments, a midamble can be provided at a predetermined location in the payload to extend the time during which phase synchronization can be maintained. In this case, the number of bits is counted, and the switch control signal output Lock_IN is transitioned to high (H) for the period corresponding to the midamble, just as during the preamble period.

[0081] In order to oscillate VCO 22 as stably as possible in a free-running state after phase synchronization, it is preferable to narrow the range of oscillation frequencies by adjusting the parameters of clock extraction unit 18 (resistance and capacitance for VCO adjustment).

[0082] In the above-described embodiment, the preamble is described as a bit string ("1010...") in which two logical "1s" and two logical "0s" are alternately arranged, and the division ratio is 2. However, the division ratio may be other integers, and a corresponding preamble may be used. For example, it is logically possible to use a bit string ("110011...") in which two logical "1s" and two logical "0s" are alternately arranged, and a division ratio of 4. However, such a configuration reduces the number of edges that appear within a given time, which may affect the lock-in pull-in time. Therefore, from the perspective of time efficiency, it is preferable to use a bit string in which two logical "1s" and two logical "0s" are alternately arranged and a division ratio of 2. Furthermore, the bit string in which two logical "1s" and two logical "0s" are alternately arranged is not limited to the bit string starting with a logical "1" as described above, and may also be a bit string starting with a logical 0 ("010101...").

[0083] Although the communication circuit in the outdoor unit 6 has been described above, the indoor unit 4 also has a similar configuration. Furthermore, if the communication partner is a remote controller or a central control device, the remote controller or the central control device has a communication circuit such as that shown in FIG.

[0084] With the above configuration, it is possible to realize communication with high data efficiency by using a receiving device including a transceiver 12 (decoding unit), SCI 16 (recognition unit), clock extraction unit 18, and S / H 30 according to an embodiment of the present disclosure, without relying on an asynchronous circuit, and by using a data frame including a preamble from the transmitting side.

[0085] In serial data communications for air conditioning systems, clock recovery is performed to transmit and receive data, reducing overhead and increasing data transmission efficiency to, for example, 87.5%. This exceeds the data transmission efficiency η of conventional asynchronous circuits, which was 72.7% (with parity) / 80% (without parity), making it possible to achieve high throughput even with increased communications traffic.

[0086] (Second embodiment) The above description has been given on the assumption that both the transmitting and receiving sides are devices compatible with serial data communication according to the embodiment of the present disclosure. This is effective when building a completely new air conditioning system. However, in reality, it is often the case that only partial replacement is performed, such as introducing new indoor and outdoor units into an air conditioning system that already has existing indoor and outdoor units that perform existing serial data communication.

[0087] Hereinafter, a second embodiment of an air conditioning system that is compatible with an environment in which it coexists with devices that only use existing serial data communication methods will be described with reference to FIGS.

[0088] FIG. 8 shows an environment in which indoor units 4 and outdoor units 6 (hereinafter referred to as high-speed indoor units 4 and high-speed outdoor units 6) with a relatively high communication speed using a clock extraction unit 18 according to an embodiment of the present disclosure coexist with existing indoor units 5 and outdoor units 7 (hereinafter referred to as existing indoor units 5 and existing outdoor units 7) with a relatively low communication speed (e.g., 9.6 kbps). This is an environment in which, during a customer replacement, some high-speed indoor units 4 and high-speed outdoor units 6 that support high-speed communication using a clock extraction unit 18 were installed, while the rest of the existing equipment was left operating as is. In the existing air conditioning system 1 before replacement, the existing indoor units 5 and existing outdoor units 7 communicate using carrier sense multiple access (CSMA).

[0089] In Figure 8, the high-speed indoor unit 4 / high-speed outdoor unit 6 is equipped with a clock extraction unit 18 / 58, a first transceiver (TX1) 12 / 52 connected to the clock extraction unit 18 / 58, and a second transceiver (TX2) 13 / 53 with the same functions as the existing indoor unit 5 and existing outdoor unit 7. The MPU 14 / 54 of the high-speed indoor unit 4 / high-speed outdoor unit 6 incorporates a UART 17 / 57 in addition to an SCI 16 / 56. Meanwhile, the existing indoor unit 5 / outdoor unit 7 is equipped with a second transceiver (TX2) 13 / 53 and an MPU 15 incorporating a UART 17 / 57. This shows that existing low-speed serial data communication and high-speed serial data communication are communicated on the same communication line 2 using time division multiplexing.

[0090] 9 illustrates serial data communication in an air conditioning system according to a second embodiment of the present disclosure. The first transceiver 12 of the high-speed outdoor unit 6 inputs and outputs data to and from the SCI 16 of the MPU 14, and the second transceiver 13, which is the same as the existing one, inputs and outputs data to and from the asynchronous read / write circuit (UART) 17 of the MPU 14. Meanwhile, in the existing indoor unit 5, the second transceiver 53 only inputs and outputs data to and from the asynchronous read / write circuit (UART) 57 of the MPU 15.

[0091] 10 shows a timing chart of serial data communication between the high-speed indoor unit 4 and the high-speed outdoor unit 6 in an environment where existing devices exist in the second embodiment. Prior to high-speed serial data communication by the SCI 16, the high-speed outdoor unit 6 obtains the right to transmit by CSMA by transmitting low-speed serial communication data from the transmission terminal TxD of the asynchronous communication circuit (UART) 17 at point X in FIG.

[0092] The data sent from this transmission terminal TxD begins with an identification code and includes a type code, data length, system address, local address + destination address, and data rate. Because the data rate is included, other high-speed indoor units 4 and the like can detect that high-speed communication is taking place by reading this. Existing indoor units 5 also receive low-speed serial communication data, detect the carrier, recognize that other nodes have the right to transmit, and suppress their own transmission.

[0093] Next, at point Y in Figure 11, the high-speed outdoor unit 6 transmits a preamble for high-speed serial communication from the transmit data terminal TD of the SCI 16. The clock extraction unit 58 of the receiving high-speed indoor unit 4 detects the preamble and phase-synchronizes the VCO oscillation output VCO_Out to the received data at point Z in Figure 11. The receive data terminal RD of the SCI 16 samples the data after the synchronization word with a high-speed clock and recognizes the received data. This operation enables mixed operation of the high-speed indoor unit 4 / outdoor unit 6 according to the embodiment of the present disclosure and the existing indoor unit 5 / existing outdoor unit 7. Note that in an environment where existing indoor units 5 / existing outdoor units 7 do not coexist, the right to transmit can be acquired by transmitting the preamble, eliminating the need for communication to acquire the right to transmit via low-speed communication using a start-stop synchronization circuit (UART).

[0094] As described above, according to the present disclosure, it is possible to provide an air conditioning system, a receiving device, and a communication method that can improve the data transmission efficiency of data communication between devices in an air conditioning system.

[0095] In the above configuration, the clock signal from the oscillator output VCO_Out, which is phase-synchronized with the reference signal from the reference signal input Sig_IN corresponding to the preamble in the decoded signal, maintains its phase for a certain period of time even after the preamble ends. Therefore, the SCI 16 can recognize the received data from the decoded signal input from the DOUT terminal of the transceiver 12 based on the clock signal continuously output by the clock extraction unit 18. This reduces the ratio of additional data to the data to be transmitted, thereby improving the data transmission efficiency of data communication between devices in the air conditioning system.

[0096] Patent Documents 1 and 2 are cited, but although they describe the AMI encoding method as a serial data transmission method for air conditioning control, they do not describe extracting a clock by phase-synchronizing a VCO oscillation signal with a PLL to the decoded output of a transceiver. They also do not describe control for switching the VCO adjustment voltage to a fixed value when preamble reception is complete.

[0097] It should be noted that the embodiments of the present invention are not limited to the above-described embodiments and may include various modifications. For example, the above-described embodiments have been described in detail for ease of understanding, and are not necessarily limited to those including all of the described features. Furthermore, some of the features of one embodiment may be replaced with features of another embodiment, or features of one embodiment may be added to features of another embodiment. Furthermore, some of the features of each embodiment may be added to, deleted from, or replaced with other features. [Explanation of symbols]

[0098] 1...air conditioning system, 2...communication line, 4...indoor unit, 6...air conditioner, 10, 50...communication circuit, 12, 13, 52, 53...transceiver, 14, 15, 54, 55...MPU, 16, 56...SCI, 17, 57...UART, 18, 58...clock extraction unit, 20...phase comparator, 22...VCO, 24...frequency divider, 26...clock extraction input switch, 28...adjustment voltage switch, 30...sample and hold circuit (S / H), 32...lock detector, 70...data frame, 72...preamble, 74...synchronization word, 76...header, 78...payload, 80...postword

Claims

1. An air conditioning system including a plurality of devices, A first device of the plurality of devices includes: a decoding unit that decodes a data signal, which is received via a communication line from a second device among the plurality of devices and in which data having a preamble is encoded, and outputs a decoded signal; a clock extraction unit that uses a portion of the decoded signal corresponding to the preamble as a reference signal and outputs a clock signal in phase synchronization with the reference signal; a recognition unit that recognizes received data from the input decoded signal after the preamble ends, based on the clock signal that is continuously output by the clock extraction unit; an air conditioning system, including

2. a sample-and-hold circuit for holding an adjustable parameter of an oscillator circuit of the clock extraction unit to fix it in response to the end of the preamble; The air conditioning system of claim 1 further comprising:

3. a voltage variable frequency oscillator for generating the clock signal; a frequency divider that divides the frequency of the clock signal generated by the voltage variable frequency oscillator to generate a comparison signal; a phase comparator that detects a phase difference between the reference signal and the comparison signal; the parameter is an input value of an adjustment voltage of the voltage variable frequency oscillator, and before the end of the preamble, an output according to the phase difference detected by the phase comparator is input to the adjustment voltage of the voltage variable frequency oscillator, and the sample-and-hold circuit holds an output according to the phase difference detected by the phase comparator, and in response to the end of the preamble, the output of the sample-and-hold circuit is input to the adjustment voltage of the voltage variable frequency oscillator.

4. The air conditioning system according to claim 1 , wherein a division ratio of the comparison signal input to the clock extraction unit for phase synchronization with respect to the clock signal is 2.

5. 2. The air conditioning system according to claim 1, wherein the encoded data signal is data encoded using a clock incomplete encoding method that does not include a data communication clock component in the code.

6. The air conditioning system according to claim 5 , wherein the clock imperfect coding method is an AMI coding method.

7. The air conditioning system according to claim 1, characterized in that, when the fundamental frequency of the encoded data signal generated on the communication line is F1 [Hz] and the frequency of the clock signal extracted by the clock extraction unit is F2 [Hz], F2 = F1 x 2 holds.

8. The air conditioning system of claim 1, characterized in that the frequency of the frequency component of the decoded signal of the decoding unit corresponding to the preamble is F3 [Hz], the data communication speed of the encoded data signal is F4 [bps], and F4 = F3 x 2 holds.

9. The data frame of the encoded data signal has data length information, and the first device further 3. The air conditioning system according to claim 2, further comprising a control unit that calculates an end point of a payload in the data frame based on the length information of the data, and in response to the end of the payload, releases the fixation of the parameters by the sample-and-hold circuit and controls the clock extraction unit to resume waiting for phase synchronization between the clock signal and the reference signal.

10. The data frame of the encoded data signal has data length information, and the first device further 3. The air conditioning system according to claim 2, further comprising a control unit that calculates an end point of a payload in the data frame based on length information of the data, and, in response to receiving a post-word after the end of the payload, releases the parameter fixation by the sample-and-hold circuit and resumes waiting for phase synchronization between the clock signal and the reference signal by the clock extraction unit, and takes in the received data when the post-word matches a predefined value, while requesting retransmission when the post-word does not match the predefined value.

11. the first device includes a serial communication interface including the recognition unit in a processor and an asynchronous circuit for communicating in an asynchronous manner, and a third device among the plurality of devices communicates in the asynchronous manner; The air conditioning system according to claim 1 , wherein the first device transmits data using the asynchronous circuit to acquire a transmission right prior to communication using the serial communication interface.

12. 12. The air conditioning system of claim 11, wherein the third device communicates by Carrier Sense Multiple Access (CSMA).

13. The air conditioning system according to claim 1 , wherein the preamble corresponds to a bit string in which logical "1"s and logical "0"s are alternately arranged.

14. A receiving device, a decoding unit that decodes a data signal in which data having a preamble is encoded and that is received from a transmitting device via a communication line, and outputs a decoded signal; a clock extraction unit that uses a portion of the decoded signal corresponding to the preamble as a reference signal and outputs a clock signal in phase synchronization with the reference signal; a recognition unit that recognizes received data from the input decoded signal after the preamble ends, based on the clock signal that is continuously output by the clock extraction unit; a receiving device including:

15. 1. A communication method comprising: receiving, by a receiving unit of the receiving device, a data signal in which data having a preamble is encoded from the transmitting device via a communication line; decoding the received encoded data signal by a decoding unit of the receiving device to generate a decoded signal; generating a clock signal in phase synchronization with a portion of the decoded signal corresponding to the preamble as a reference signal by a clock extraction unit of the receiving device; a step of recognizing received data from the decoded signal input after the end of the preamble by a recognition unit of the receiving device based on the clock signal continuously generated by the clock extraction unit; A communication method, including:

16. encoding data having a preamble by an encoding unit of the transmitting device; transmitting the encoded data signal via the communication line by a transmitting unit of the transmitting device; 16. The communication method of claim 15, comprising:

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