SiC complementary field-effect transistors

Abstract

To provide a SiC complementary field effect transistor that can operate stably over a wide temperature range.SOLUTION: In a SiC complementary field effect transistor in which a normally-off type n-channel field effect transistor 1a and a p-channel field effect transistor 1b are formed on a SiC substrate 10, the p-type impurity doped in the channel region of the p-channel field effect transistor is Al (aluminum) or B (boron), the first n-type impurity doped into the channel region 13 of the n-channel field effect transistor is S (sulfur), and a second n-type impurity having a shallower energy level than S (sulfur) is codoped into the first n-type impurity.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide (SiC) complementary field effect transistor formed using a SiC substrate. [Background technology]

[0002] Current semiconductor integrated circuits are mainly made of silicon (Si), but in the industrial field, there is a strong demand for integrated circuits that can operate at temperatures above 200°C, which is not possible with Si, for applications such as engine control in automobiles and aircraft, automobile tire monitors, and space electronics.

[0003] SiC has a band gap approximately three times higher than that of Si, making it possible to fabricate integrated circuits that operate in high-temperature environments of 500°C or higher.

[0004] As an example of an integrated circuit fabricated using a SiC substrate, Non-Patent Document 1 discloses an integrated circuit configured with complementary MOSFETs. Patent Document 1 also discloses a complementary JFET in which an n-channel JFET and a p-channel JFET are insulated and separated by a semi-insulating SiC layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-166025 [Non-patent literature]

[0006] [Non-Patent Document 1] SH Ryu et al., IEEE Trans. Electron Devices, vol.45 (1998), p.45. Summary of the Invention [Problem to be solved by the invention]

[0007] The complementary MOSFET disclosed in Non-Patent Document 1 has the problem that the threshold voltage varies greatly with temperature due to the presence of high density defects and charges at the interface between the SiC substrate and the gate oxide film, making it unable to operate stably. Another problem is that the gate oxide film deteriorates at high temperatures.

[0008] The complementary JFET disclosed in Patent Document 1 has a structure in which an n-channel JFET and a p-channel JFET are isolated by an intrinsic SiC layer formed by hot-wall CVD. This requires repeated steps of fine trench formation, embedding growth, and surface planarization polishing, which results in a very complicated fabrication process.

[0009] To date, several studies have been reported on complementary field-effect transistors using SiC substrates, but only high-temperature operation has been confirmed, and a complementary field-effect transistor capable of stable operation over a wide temperature range has not yet been realized.

[0010] The present invention has been made in view of the above-mentioned problems, and a main object of the present invention is to provide a SiC complementary field effect transistor capable of stable operation over a wide temperature range. [Means for solving the problem]

[0011] The SiC complementary field effect transistor according to the present invention is a SiC complementary field effect transistor in which a normally-off n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate, in which the p-type impurity doped into the channel region of the p-channel field effect transistor is Al (aluminum) or B (boron), the first n-type impurity doped into the channel region of the n-channel field effect transistor is S (sulfur), and the first n-type impurity is co-doped with a second n-type impurity having an energy level shallower than that of S (sulfur). [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a SiC complementary field effect transistor capable of stable operation over a wide temperature range. [Brief explanation of the drawings]

[0013] [Figure 1] 1A to 1C are diagrams showing the structure of a SiC JFET disclosed in the specification of the previous application. [Figure 2] FIG. 1 is a circuit diagram showing an inverter circuit made up of complementary JFETs. [Figure 3] 1 is a graph showing temperature characteristics of input / output characteristics of an inverter circuit. [Figure 4] 1 is a graph showing the temperature dependence of carrier density. [Figure 5] 1 is a graph showing the temperature dependence of carrier density. [Figure 6] 1 is a graph showing temperature characteristics of input / output characteristics of an inverter circuit. [Figure 7] 1A and 1B are diagrams showing the structure of a Hall effect measuring element. [Figure 8] 1 is a graph showing the temperature dependence of carrier density. [Figure 9] 1 is a graph showing the temperature dependency of the maximum operating frequency in an inverter circuit. [Figure 10] 1 is a graph showing the temperature dependence of carrier density. [Figure 11] FIG. 1 is a diagram showing an energy band structure when S and N are co-doped in a channel region. [Figure 12] 1 is a graph showing the temperature dependence of carrier density. [Figure 13] 1 is a graph showing the temperature dependency of the maximum operating frequency in an inverter circuit. [Figure 14] 10 is a graph showing the temperature dependence of a logical threshold voltage of an inverter circuit. [Figure 15] 1A to 1C are diagrams illustrating a process for forming an n-type co-doped layer. [Figure 16]1 is a graph showing the distribution of impurity density in the depth direction in an n-type co-doped layer. [Figure 17] 1 is a graph showing the temperature dependence of carrier density. [Figure 18] 1 is a graph showing the temperature dependence of carrier density. DETAILED DESCRIPTION OF THE INVENTION

[0014] The applicant of the present application has disclosed the structure of a SiC junction field effect transistor (hereinafter referred to as "SiC JFET") that facilitates normally-off operation in the specification of a previous application (JP 2019-091873).

[0015] 1(A) to 1(C) are diagrams showing the structure of the SiC JFET disclosed in the specification, where FIG. 1(A) is a plan view of an n-channel JFET, FIG. 1(B) is a cross-sectional view taken along line BB in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along line CC in FIG. 1(A).

[0016] As shown in FIGS. 1A to 1C, the n-channel JFET 1 includes an n-type buried channel region 13 formed in a SiC substrate 10 and n-type junctions 14 formed opposite to each other with the buried channel region 13 interposed therebetween. + A pair of p-type source and drain regions 11 and 12 are formed in a direction perpendicular to the direction in which the source and drain regions 11 and 12 face each other. + The p-channel JFET has a similar structure.

[0017] In the n-channel JFET 1, the width L of the pair of gate regions 14a and 14b is the channel length, the distance D between the pair of gate regions 14a and 14b is the channel thickness, and the distance W in the depth direction of the buried channel region 13 is the channel width.

[0018] The expansion of the depletion layer in the buried channel region 13 is controlled by the gate voltage applied to a pair of gate regions 14a and 14b formed on both sides of the buried channel region 13. By adjusting the impurity concentration N of the buried channel region 13 and the channel thickness D, a normally-off SiC JFET can be realized. Specifically, the impurity concentration N (cm -3 ), and the channel thickness D (cm) is N(D / 2) 2 <3×10 7 cm -1 It is sufficient to set it so as to satisfy the following.

[0019] In the n-channel JFET 1 shown in FIGS. 1(A) to 1(C), the channel region is the buried channel region 13, but the channel region may extend to the surface of the SiC substrate .

[0020] Figure 2 shows an inverter circuit consisting of complementary JFETs, a normally-off n-channel JFET 1a and a normally-off p-channel JFET 1b. The gate electrodes of the n-channel JFET 1a and the p-channel JFET 1b are connected to the input terminal V in The drain electrodes D of the n-channel JFET 1a and p-channel JFET 1b are connected to the output terminal V of the inverter circuit. out The source electrode S of the n-channel JFET 1a is connected to ground, and the source electrode S of the p-channel JFET 1b is connected to the power supply (V DD )

[0021] Typically, an inverter circuit has a logic threshold voltage V th is the power supply voltage V DD In this case, the saturation current I of the n-channel JFET1a and p-channel JFET1b is Dn , I Dp is equal to where I Dn , I Dp are expressed by the following equations (1) and (2).

[0022]

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[0023]

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[0024] In the above formulas (1) and (2), V G is the gate voltage, V Tn , V Tp are the threshold voltages of n-channel JFET1a and p-channel JFET1b, β n , β p are the beta values (gain) of n-channel JFET 1a and p-channel JFET 1b.

[0025] The gate electrode of n-channel JFET 1a is connected to V in , and the gate electrode of p-channel JFET1b is V in -V DD Since a voltage of I is applied, using the above equations (1) and (2), Dn =I Dp From this, the following equation (3) is obtained.

[0026]

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[0027] From the above equation (3), the logical threshold voltage V of the inverter circuit th is expressed by the following equation (4).

[0028]

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[0029] Also, β R is calculated by the following formula (5) using the physical property values and structural dimensions of the JFET having the structure shown in FIGS. 1(A) to 1(C).

[0030]

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[0031] In the above formula (5), the parameters are as follows: Note that the subscripts n and p indicate the parameters of the n-channel JFET and the p-channel JFET.

[0032] μ n , μ p : Mobility of electrons and holes n n , p p : electron density, hole density W n , W p :Channel width L n , L p :Channel length D n , D p : Channel thickness N D , N A : impurity concentration of the channel region 13 Figure 3 is a graph showing the temperature characteristics of the input / output characteristics of the inverter circuit shown in Figure 2, calculated using the above formula (4). Here, the input / output characteristics of the inverter circuit were calculated using a well-known formula for current-voltage characteristics.

[0033] As shown in Figure 3, the logic threshold voltage V th As the temperature increases, the value of β shifts significantly from 1 V. This is mainly due to the parameter β R This is due to the large temperature dependence of

[0034] Figure 4 shows the temperature dependence of electron and hole carrier density in a SiC JFET. n , the graph shown in B is the hole density p p The n-type impurity (donor) is P (phosphorus) and the p-type impurity (acceptor) is Al (aluminum). n and p p The calculation was performed using the following equations (6) and (7).

[0035]

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[0036]

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[0037] In the above formulas (6) and (7), i represents two sites in 4H—SiC (i=h, k sites), and the parameters in the formulas are as follows:

[0038] g i : Degeneracy of donor (acceptor) levels N di , N ai : Donor density, acceptor density N c , N v :Effective density of states in the conduction band, effective density of states in the valence band n n , p p : electron density, hole density ΔE i :Ionization energy As shown in Figure 4, the electron density n n is almost constant over a wide temperature range, whereas the hole density p p changes significantly from room temperature to high temperatures. This is because the energy level of the n-type impurity is shallower than the conduction band edge (ΔE i : about 60 meV), the ionization rate is large, while the energy level of the p-type impurity is deep from the valence band edge (ΔE i : about 200 meV), the ionization rate is small. Therefore, the hole density p p Only the temperature change is large, and as shown in equation (5), β R (∝n n / p p ) changes with temperature as a function of the hole density p p The temperature change becomes dominant.

[0039] The applicant of the present invention has discovered that by using an n-type impurity having a deep energy level similar to a p-type impurity, the logic threshold voltage V thA method for suppressing temperature changes is disclosed in the specification of a previous application (JP 2021-197517).

[0040] Figure 5 shows a graph of the calculated temperature dependence of electron and hole densities when a hypothetical donor with a deep energy level is assumed as the n-type impurity and Al is used as the p-type impurity. The energy level of the hypothetical donor is assumed to be approximately 260 meV from the conduction band edge. Here, the graph indicated by A shows the hole density p p , the graph shown in B is the electron density n n As shown in Figure 5, the electron density n n , and hole density p p changes almost the same over a wide temperature range from room temperature to high temperatures.

[0041] Figure 6 is a graph showing the temperature characteristics of the input / output characteristics of an inverter circuit when the above-mentioned hypothetical donor is used as the n-type impurity and Al is used as the p-type impurity, calculated using the well-known current-voltage characteristic equation. As shown in Figure 6, the logic threshold voltage V th is approximately 1 V over a wide temperature range.

[0042] In this way, by using n-type impurities with deep energy levels similar to p-type impurities, the logic threshold voltage V th The fluctuations in the temperature can be significantly suppressed.

[0043] (Experimental search for n-type impurities with deep energy levels) The energy levels of impurities other than N (nitrogen) and P (phosphorus), which have traditionally been used as n-type impurities, such as S (sulfur), As (arsenic), and Sb (antimony), were determined using the well-known Hall effect measurement.

[0044] 7(A) and (B) are diagrams showing the structure of a Hall effect measuring element, with FIG. 7(A) being a plan view and FIG. 7(B) being a cross-sectional view.

[0045] As shown in Figures 7(A) and (B), a p-type epitaxial layer 20 was formed on an n-type 4H-SiC (0001) substrate 10, and then S, As, and Sb ions were implanted into the p-type epitaxial layer 20. The resulting n-type doped layer 30 was then patterned into a cloverleaf shape, and four electrodes 40 were formed at each of the four corners of the pattern.

[0046] FIG. 8 is a graph showing the temperature dependence of carrier density of SiC doped with S, As, and Sb impurities, respectively, determined by Hall effect measurement.

[0047] As shown in Figure 8, the carrier density of As and Sb had almost no temperature dependence, whereas the carrier density of S had a large temperature dependence. This demonstrates that As and Sb, like N and P, have shallow energy levels, whereas S has a deep energy level.

[0048] Next, the measured data for S was fitted to the temperature dependence equation of carrier density to determine the ionization energy of S. Note that since S in group 16 has two energy levels per site, the temperature dependence equation of carrier density was calculated using the following equation (8).

[0049]

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[0050] where f i,m is expressed by the following equation (9) considering two sites (i = h, k sites) and two energy levels (m = 1, 2) in 4H—SiC.

[0051]

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[0052] where g' i,m are the following values for the two energy levels:

[0053]

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[0054] Table 1 shows the ionization energy (ΔE di,m ) where i=h and k respectively represent the two sites of 4H-SiC. Table 1 demonstrates that S has a deep energy level of 340 meV or more.

[0055] [Table 1]

[0056] (Maximum operating frequency of inverter circuit) As mentioned above, by using deep energy level S as the n-type impurity doped into the channel region of the n-channel JFET, the logical threshold voltage V th However, the inventors of the present invention have discovered a new problem in that the maximum operating frequency of the inverter circuit drops significantly at temperatures near room temperature.

[0057] FIG. 9 shows the maximum operating frequency f in the inverter circuit using the following equation (10). max Graph A shows the temperature dependence when N, which has a shallow energy level, is used as the n-type impurity doped into the channel region, and graph B shows the temperature dependence when S, which has a deep energy level, is used as the n-type impurity doped into the channel region.

[0058]

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[0059] where t r is the rise time, t f represents the fall time, and tr and t f are calculated by the following equations (11).

[0060]

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[0061] Here, C is the load capacitance, and in the above calculations, C is assumed to be 550 fF.

[0062] As shown in Figure 9, the maximum operating frequency f max It can be seen that is significantly reduced near room temperature compared to when N is used.

[0063] This is thought to be because, as shown in Figure 10, in N, which has a shallow energy level (low ionization energy), there is almost no change in carrier density with temperature, whereas in S, which has a deep energy level (high ionization energy), the carrier density decreases significantly around room temperature.

[0064] That is, as shown in the above formula (5), β n The temperature change of depends greatly on the temperature change of the carrier density n. Therefore, as shown in the above formula (11), the fall time t f increases significantly near room temperature, which leads to the maximum operating frequency f max is thought to have decreased significantly.

[0065] The inventors of the present application have noticed that when S, which has a deep energy level, is used as an n-type impurity, the carrier density at around room temperature is significantly reduced. By co-doping an n-type impurity with a shallow energy level as an n-type impurity to compensate for the carrier density at around room temperature, the maximum operating frequency f max The present inventors have conceived the present invention based on the idea that it is possible to suppress the decrease in the amount of carbon dioxide at temperatures around room temperature.

[0066] FIG. 11 shows the energy level E d1The deep n-type impurity (first n-type impurity) S and the energy level E d2 1 is a diagram showing an energy band structure when N is co-doped as a shallow n-type impurity (second n-type impurity) in a semiconductor layer of a semiconductor substrate. The impurity densities of N and S are not particularly limited, but typically, the impurity density of N is set to be lower than the impurity density of S.

[0067] As shown in Figure 11, the conduction band contains ionized S + Carriers due to ionized N + There are carriers (electrons) due to N + Therefore, the carrier density at room temperature is + The carrier density due to

[0068] FIG. 12 shows the energy level E d1 Deep S and energy level E d2 10 is a graph showing the calculated temperature dependence of carrier density when shallow N is co-doped.

[0069] Here, the graph indicated by A1 shows the temperature dependence of the carrier density n1 of S calculated using the above formula (8), the graph indicated by A2 shows the temperature dependence of the carrier density n2 of N calculated using the above formula (6), and the graph indicated by A shows the temperature dependence of the carrier density n (n = n1 + n2) when co-doped with S and N. Furthermore, the graph indicated by B shows the temperature dependence of the carrier density p when doped with Al (p-type impurity) calculated using the above formula (7).

[0070] In the above formulas (8), (6) and (7), the impurity concentration N ds is 5.0 x 10 16 cm -3 and the impurity concentration of N is N dN is 3.0 x 10 15 cm -3 and the impurity concentration of N is N dNis 5.0 x 10 16 cm -3 The compensation defect density, which will be described later, was calculated as 0 cm -3 It was assumed that:

[0071] As shown in FIG. 12, the carrier density when co-doped with S and N is higher than that when only S is doped at room temperature, which means that the effective ionization energy when co-doped with S and N is lower.

[0072] Figure 13 is a graph showing the calculated temperature dependence of the maximum operating frequency when the channel region is co-doped with deep-energy S and shallow-energy N as n-type impurities. Here, graph A shows the temperature dependence when only S is doped, and graph B shows the temperature dependence when both S and N are co-doped.

[0073] As shown in Figure 13, by co-doping a channel region doped with S, which has a deep energy level, with N, which has a shallower energy level than S, the maximum operating frequency near room temperature can be increased. This makes it possible to realize a circuit that can operate stably at high speeds over a wide temperature range.

[0074] The impurity density of co-doped N may be set so that the carrier density supplied by ionized N is greater than the carrier density supplied by ionized S at room temperature.

[0075] FIG. 14 shows the logic threshold voltage V when the channel region is co-doped with S, which has a deep energy level, and N, which has a shallow energy level, as n-type impurities. th Graph A shows the temperature dependence of S doping alone, and graph B shows the temperature dependence of S and N co-doping.

[0076] As shown in Figure 14, by co-doping N, which has a shallower energy level than S, into the channel region doped with S, the logic threshold voltage V th The fluctuations can be further suppressed.

[0077] (Measurement of carrier density when co-doped with S and N) 15, S and N ions were implanted into a p-type epitaxial layer 20 formed on the surface of an n-type 4H—SiC (0001) substrate 10, to form an n-type co-doped layer 30 of S and N on the surface of the p-type epitaxial layer 20. Here, the impurity concentration of the p-type epitaxial layer 20 was 5×10 14 cm -3 The implantation dose of S is 3.51 × 10 12 cm -2 The implantation dose of N is 3.52 × 10 11 cm -2 The ion implantation energy of S was set to 10 to 350 keV, and the ion implantation energy of N was set to 10 to 200 keV.

[0078] 16 is a graph showing the results of measuring the depth distribution of the impurity densities of S and N in the n-type co-doped layer 30 using secondary ion mass spectrometry (SIMS). Graph A shows the depth distribution of the impurity density of S, and graph B shows the depth distribution of the impurity density of N. As shown in FIG. 16, the impurity density of S in the n-type co-doped layer 30 is 1.0×10 17 cm -3 The impurity density of N is 1.0×10 16 cm -3 It was.

[0079] 17 is a graph showing the results of measuring the temperature dependence of carrier density in the n-type co-doped layer 30 using the Hall effect measurement element shown in FIGS. 7A and 7B. Here, graph A shows the temperature dependence when only S is doped, and graph B shows the temperature dependence when S and N are co-doped. As shown in FIG. 17, it was demonstrated that the carrier density of the co-doped layer 30 co-doped with S and N increases near room temperature.

[0080] (Dependence of carrier density on compensation defect density) When forming SiC complementary field-effect transistors on a SiC substrate, a p-type epitaxial layer may be formed on the SiC substrate to avoid the influence of recombination in the SiC substrate, and the SiC complementary field-effect transistors may be formed on the p-type epitaxial layer. In this case, the channel region of the n-channel JFET is formed by ion implanting n-type impurities into the p-type epitaxial layer.

[0081] In this case, the p-type impurities doped into the p-type epitaxial layer are present in the channel region, and these p-type impurities become levels (compensation defects) that capture carriers (electrons) in the channel region, thereby reducing the carrier density (electron density) in the channel region.

[0082] FIG. 18 shows the impurity densities of S and N co-doped into the channel region, respectively, at 5.0×10 16 cm -3 , 3.0×10 15 cm -3 The impurity density (compensation defect density) of p-type impurities in the channel region is set to 0 to 1 × 10 16 cm -3 The graphs A0 to A4 show the temperature dependence of the carrier density when the compensation defect density is changed in the range of 0, 1 × 10 15 cm -3 , 3×10 15 cm -3 , 5×10 16 cm -3 , 1×10 16 cm-3 This shows the case.

[0083] As shown in Figure 18, the carrier density in the channel region at room temperature decreases as the compensation defect density increases. Therefore, the impurity density of N co-doped into the channel region must be determined taking into account the compensation defect density present in the channel region.

[0084] Although the above example illustrates the case where a SiC complementary field-effect transistor is formed on a p-type epitaxial layer, even when a SiC complementary field-effect transistor is formed on an n-type epitaxial layer or a semi-insulating substrate, the impurity density of N co-doped into the channel region must be determined in consideration of the density of compensation defects present in the channel region.

[0085] Although the present invention has been described above with reference to preferred embodiments, such description is not intended to be limiting and various modifications are possible.

[0086] For example, in the above embodiment, an example has been described in which a channel region doped with S (sulfur) as an n-type impurity (first n-type impurity) with a deep energy level is co-doped with N (nitrogen) as an n-type impurity (second n-type impurity) with an energy level shallower than that of S, but the present invention is not limited to this, and the channel region may be co-doped with, for example, P (phosphorus), As (arsenic), Sb (antimony), etc. Furthermore, at least one n-type impurity selected from N, P, As, and Sb may be co-doped.

[0087] In the present invention, the n-type impurities to be co-doped are intentionally doped at a controlled appropriate dose, and do not include n-type impurities that are inevitably present in SiC substrates, etc.

[0088] Furthermore, in the above embodiment, Al (aluminum) is used as an example of a p-type impurity, but the effects of the present invention can also be achieved by using B (boron), which has a deep energy level.

[0089] In the above embodiment, the SiC complementary JFET is applied to an inverter circuit, but it can also be applied to other logic gates, such as a NAND circuit or a NOR circuit. Furthermore, it can also be applied to analog circuits in addition to digital circuits based on the logic gates.

[0090] Furthermore, in the above embodiment, SiC complementary JFETs have been described as examples of SiC complementary field effect transistors, but the present invention can also be applied to SiC complementary MOSFETs.

[0091] In addition, in the above embodiment, the SiC JFET having the structure shown in FIG. 1 has been described as an example of a transistor constituting the SiC complementary field effect transistor, but the present invention can of course be applied to SiC JFETs or SiC MOSFETs having other structures. [Explanation of symbols]

[0092] 1. JFET 1a n-channel JFET 1b p-channel JFET 10 SiC substrate 11 Source Area 12 Drain region 13 Buried channel region 14a, 14b Gate region

Claims

1. A SiC complementary field effect transistor in which a normally-off n-channel field effect transistor and a p-channel field effect transistor are formed on a SiC substrate, The p-type impurity doped into the channel region of the p-channel field effect transistor is Al (aluminum) or B (boron), the first n-type impurity doped into the channel region of the n-channel field effect transistor is S (sulfur), The first n-type impurity is co-doped with a second n-type impurity having an energy level shallower than that of S (sulfur).

2. 2. The SiC complementary field effect transistor according to claim 1, wherein the second n-type impurity includes at least one impurity selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), and Sb (antimony).

3. 3. The SiC complementary field effect transistor according to claim 1, wherein an impurity density of the second n-type impurity is set so that a carrier density due to the second n-type impurity is higher than a carrier density due to the first n-type impurity at room temperature.

4. 4. The SiC complementary field effect transistor according to claim 3, wherein an impurity density of the second n-type impurity is lower than an impurity density of the first n-type impurity.

5. 2. The SiC complementary field effect transistor according to claim 1, wherein the n-channel field effect transistor and the p-channel field effect transistor are composed of an n-channel junction field effect transistor and a p-channel junction field effect transistor, respectively.

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