Semiconductor Devices

Abstract

To provide a semiconductor device improved in switching characteristics.SOLUTION: A semiconductor device includes a first electrode, a second electrode, a semiconductor part, a conductive body, and a control electrode. The second electrode is provided apart from the first electrode in a first direction. The semiconductor part includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type which is provided on the first semiconductor layer, the semiconductor part being located between the first electrode and the second electrode. The conductive body is provided within the semiconductor part, electrically insulated by a first insulating film from the semiconductor part, and facing the first semiconductor layer via the first insulating film. The control electrode includes a first portion provided between the second semiconductor layer and the first electrode via a second insulating film, and a second portion facing the second semiconductor layer via the second insulating film in a second direction orthogonal to the first direction, the first portion and the second portion being connected to each other and apart from the conductive body.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Semiconductor devices used for power control are required to have reduced on-resistance and improved switching characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-165182 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device with improved switching characteristics. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a second electrode, a semiconductor portion, a conductor, and a control electrode. The second electrode is spaced apart from the first electrode in a first direction. The semiconductor portion includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and is located between the first electrode and the second electrode. The conductor is provided within the semiconductor portion, electrically insulated from the semiconductor portion by a first insulating film, and faces the first semiconductor layer via the first insulating film. The control electrode has a first portion provided between the second semiconductor layer and the first electrode via a second insulating film, and a second portion facing the second semiconductor layer via the second insulating film in a second direction perpendicular to the first direction, the first portion and the second portion being connected to each other and spaced apart from the conductor. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 1 is a partial cross-sectional view schematically illustrating a semiconductor device according to an embodiment. [Figure 3] 1 is a graph showing characteristics of a semiconductor device according to an embodiment. [Figure 4] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views showing the manufacturing process following FIG. 4. [Figure 6] 6A to 6C are schematic cross-sectional views showing the manufacturing process following FIG. 5. [Figure 7] 7A to 7C are schematic cross-sectional views showing the manufacturing process following FIG. 6. [Figure 8] 8A to 8C are schematic cross-sectional views showing the manufacturing process following FIG. 7. [Figure 9] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a power MOSFET. The semiconductor device 1 includes, for example, a semiconductor portion 10, a first electrode 20, and a second electrode 30.

[0010] The semiconductor portion 10 is made of, for example, silicon. The semiconductor portion 10 is provided between a first electrode 20 and a second electrode 30. The first electrode 20 is, for example, a source electrode. The second electrode 30 is, for example, a drain electrode.

[0011] The semiconductor section 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, a fourth semiconductor layer 17 of the second conductivity type, and a fifth semiconductor layer 19 of the first conductivity type. In the following description, the first conductivity type will be referred to as n-type and the second conductivity type as p-type, but this is not intended to be limiting.

[0012] The first semiconductor layer 11 is, for example, an n-type drift layer. The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30.

[0013] The second semiconductor layer 13 is, for example, a p-type base layer. The second semiconductor layer 13 is provided on the first semiconductor layer 11. The second semiconductor layer 13 has a surface located within the upper surface 10F of the semiconductor portion 10.

[0014] The third semiconductor layer 15 is, for example, an n-type source layer. The third semiconductor layer 15 is partially provided on the second semiconductor layer 13. The third semiconductor layer 15 is electrically connected to the first electrode 20.

[0015] The fourth semiconductor layer 17 is, for example, a p-type contact layer. The fourth semiconductor layer 17 is partially provided on the second semiconductor layer 13. The fourth semiconductor layer 17 contains a higher concentration of second conductivity type impurities than the second conductivity type impurities of the second semiconductor layer 13. The first electrode 20 is in contact with and electrically connected to the fourth semiconductor layer 17. The second semiconductor layer 13 is electrically connected to the first electrode 20 via the fourth semiconductor layer 17.

[0016] The fifth semiconductor layer 19 is provided between the first semiconductor layer 11 and the second electrode 30. The fifth semiconductor layer 19 is, for example, an n-type buffer layer. The fifth semiconductor layer 19 is electrically connected to the second electrode 30. The fifth semiconductor layer 19 contains a higher concentration of first conductivity type impurities than the first conductivity type impurities of the first semiconductor layer 11.

[0017] The semiconductor device 1 further includes a conductor 40 and a control electrode 50. The semiconductor portion 10 has a trench TR having a depth that reaches from the surface of the second semiconductor layer 13 into the first semiconductor layer 11. The conductor 40 is, for example, a field plate electrode and is provided inside the trench TR. The conductor 40 is electrically insulated from the semiconductor portion 10 by a first insulating film 43. The conductor 40 faces the first semiconductor layer 11 via the first insulating film 43. The first insulating film 43 is, for example, a field plate insulating film.

[0018] The control electrode 50 includes, for example, a first portion 50a and a second portion 50b. The first portion 50a is provided on the surface 10F of the semiconductor portion 10. The second portion 50b is provided inside the trench TR. The second portion 50b is provided in the trench TR and spaced apart from the conductor 40. The second portion 50b is also provided on the inner wall of the trench TR and connected to the first portion 50a. The first portion 50a and the second portion 50b are provided integrally.

[0019] The second portion 50b of the control electrode 50 is provided on, for example, the first insulating film 43. The control electrode 50 has an end portion that extends in a direction intersecting the inner wall of the trench TR, for example, in the X direction, along the upper end of the first insulating film 43. This cross-sectional shape of the control electrode 50 is merely an example, and the control electrode 50 may have a cross-sectional shape that does not have an end portion extending in the X direction.

[0020] The control electrode 50 is electrically insulated from the semiconductor portion 10 by a second insulating film 53. The second insulating film 53 is, for example, a gate insulating film. The first portion 50a and the second portion 50b of the control electrode 50 face the second semiconductor layer 13 via the second insulating film 53.

[0021] A surface of the second semiconductor layer 13 located within the upper surface of the semiconductor portion 10 faces the first portion 50a of the control electrode 50. Another surface of the second semiconductor layer 13 included in the inner wall of the trench TR faces the second portion 50b of the control electrode 50. Furthermore, on the upper surface 10F of the semiconductor portion 10, the third semiconductor layer 15 includes a region facing the first portion 50a of the control electrode 50, with the second insulating film 53 interposed therebetween.

[0022] The first electrode 20 is provided on the front surface 10F side of the semiconductor portion 10 so as to cover the third semiconductor layer 15, the fourth semiconductor layer 17, the conductor 40, and the control electrode 50. A third insulating film 55 is provided between the first electrode 20 and the conductor 40, and between the first electrode 20 and the control electrode 50. The conductor 40 and the control electrode 50 are electrically insulated from the first electrode 20 by the third insulating film 55. The third insulating film 55 is, for example, an interlayer insulating film.

[0023] The first electrode 20 is electrically connected to the third semiconductor layer 15 and the fourth semiconductor layer 17 via a contact trench CT provided in the third insulating film 55. The contact trench CT has a depth that extends from the upper surface of the third insulating film 55 into the second semiconductor layer 13, for example. The fourth semiconductor layer 17 is provided on the bottom surface of the contact trench CT. The first electrode 20 is in contact with and electrically connected to the third semiconductor layer 15 included in the inner wall of the contact trench CT.

[0024] Fig. 2(a) is a partial cross-sectional view schematically showing a semiconductor device 1 according to an embodiment. Fig. 2(b) is a partial cross-sectional view schematically showing a semiconductor device 2 according to a comparative example. Figs. 2(a) and 2(b) each show an opening of a trench TR.

[0025] 2(a), the second semiconductor layer 13 has a first surface 13f located within the upper surface 10F of the semiconductor portion 10 and a second surface 13g included in the inner wall of the trench TR. The first surface 13f of the second semiconductor layer 13 faces the first portion 50a of the control electrode 50 via the second insulating film 53. The second surface 13g faces the second portion 50b of the control electrode 50 via the second insulating film 53. The gate length of the control electrode 50 is the creepage distance from the third semiconductor layer 15 to the first semiconductor layer 11 via the first surface 13f and the second surface 13g.

[0026] 2(a), 13c denotes a first distance in the Z direction from the first surface 13f along the second surface 13g to the boundary between the first semiconductor layer 11 and the second semiconductor layer 13. Also, 13d denotes a second distance in the Z direction from the upper surface 10F of the semiconductor portion 10 to the boundary between the first semiconductor layer 11 and the second semiconductor layer 13 in a region away from the trench TR. That is, the second distance is the distance in the Z direction between the boundary between the second insulating film 53 and the third semiconductor layer 15 and the boundary between the first semiconductor layer 11 and the second semiconductor layer 13. In the semiconductor device 1, the first distance 13c is shorter than the second distance 13d. In other words, the first semiconductor layer 11 has an extension 11ex that extends along the inner wall of the trench TR between the second semiconductor layer 13 and the second portion 50b of the control electrode 50.

[0027] The extension portion 11ex is depleted by, for example, a built-in potential between the first semiconductor layer 11 and the second semiconductor layer 13. This makes it possible to reduce the parasitic capacitance Cgd between the gate and the drain.

[0028] The third semiconductor layer 15 also has an overlapping region that faces the first portion 50a of the control electrode 50, with the second insulating film 53 interposed therebetween. An overlapping width 15d of the third semiconductor layer 15 facing the control electrode 50 is, for example, the diffusion distance of the first conductivity type impurity in the third semiconductor layer 15. That is, the overlapping width 15d is controlled by the formation conditions of the third semiconductor layer 15, for example, the heat treatment temperature after ion implantation and the dose of the first impurity.

[0029] 2(b), the semiconductor device 2 has a control electrode 60 provided inside the trench TR. The control electrode 60 faces the surfaces of the second semiconductor layer 13 and the third semiconductor layer 15 included in the inner wall of the trench TR, via a second insulating film 63.

[0030] In this example, the distance from the upper surface 10F of the semiconductor portion 10 to the boundary between the first semiconductor layer 11 and the second semiconductor layer 13 is uniform. That is, the first semiconductor layer 11 does not have an extension 11ex that extends between the second semiconductor layer 13 and the control electrode 60. Therefore, the parasitic capacitance Cgd between the gate and source in the semiconductor device 2 is larger than the parasitic capacitance Cgd of the semiconductor device 1.

[0031] Furthermore, the overlap width 15d in the Z direction of the overlap region of the third semiconductor layer 15 that overlaps the control electrode 60 via the second insulating film 63 depends, for example, on the recess depth ΔR of the control electrode 60 relative to the upper surface 10F of the semiconductor portion 10. The control electrode 60 is formed to have a predetermined length in the Z direction by, for example, dry etching. Therefore, the recess depth ΔR includes non-uniformity of the etching. For example, if the recess depth ΔR becomes large and the overlap region of the third semiconductor layer 15 disappears, the semiconductor device 2 will not turn on. To avoid this, it is preferable to reduce the recess depth ΔR and increase the overlap width 15d, but this would increase the gate-source parasitic capacitance Cgs. In contrast, in the semiconductor device 1, the overlap width 15d is easily controlled and can be reduced. That is, the gate-source parasitic capacitance Cgs can be reduced.

[0032] In this way, the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd can be reduced in the semiconductor device 1. This makes it possible to improve the switching characteristics.

[0033] Furthermore, the semiconductor device 1 can have a thin control electrode 50, which facilitates the manufacturing process. For example, it is possible to eliminate structural defects such as voids that occur in the control electrode 60 when the control electrode 60 is embedded inside the trench TR.

[0034] FIG. 3 is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. The horizontal axis represents the drain voltage, and the vertical axis represents the drain current. "MG" in the figure indicates the characteristics of the semiconductor device 1. "TG" represents the characteristics of a trench gate transistor, and "PG" represents the characteristics of a planar gate transistor. The channel lengths of the transistors are the same.

[0035] As shown in Figure 3, the drain current of a planar-gate transistor is half or less of the drain current of a trench-gate transistor, meaning that the on-resistance of a planar transistor is greater than the on-resistance of a trench-gate transistor.

[0036] In contrast, the drain current of the semiconductor device 1 is approximately the same as the drain current of a trench gate transistor. In the semiconductor device 1, the control electrode 50 has a planar gate portion (first portion 50a) and a trench gate portion (second portion 50b), which improves the controllability of the overlap width 15d where the gate electrode faces the third semiconductor layer 13 via the second insulating film 53. In other words, it is possible to improve the controllability of the width of the overlap region where the gate electrode faces the source layer via the gate insulating film, thereby reducing parasitic capacitance. Meanwhile, despite the control electrode 50 having a planar gate portion, the on-resistance of the semiconductor device 1 can be made approximately the same as the on-resistance of a trench gate transistor.

[0037] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 4(a) to 8(b). Figures 4(a) to 8(b) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0038] The semiconductor device 1 uses, for example, a silicon wafer 100. The silicon wafer 100 includes an n-type silicon substrate 101 and an n-type silicon layer 103. The n-type silicon layer 103 is epitaxially grown on the n-type silicon substrate 101. The n-type impurity concentration of the n-type silicon layer 103 is lower than the n-type impurity concentration of the n-type silicon substrate 101.

[0039] 4(a), a trench TR is formed on the upper surface side of the n-type silicon layer 103. The trench TR is formed by selectively etching the n-type silicon layer 103 using, for example, RIE (Reactive Ion Etching).

[0040] As shown in FIG. 4(b), a first insulating film 43 is formed to cover the inner surface of the trench TR. The first insulating film 43 is, for example, a silicon oxide film. The first insulating film 43 includes, for example, a silicon oxide film formed by thermally oxidizing the n-type silicon layer 103 and a silicon oxide film deposited by CVD (Chemical Vapor Deposition). The first insulating film 43 is formed so as to leave a space inside the trench TR.

[0041] Subsequently, a conductive layer 105 is formed on the first insulating film 43. The conductive layer 105 is formed so as to fill the internal space of the trench TR. The conductive layer 105 is, for example, polysilicon having conductivity. The conductive layer 105 is formed by, for example, CVD.

[0042] 4(c), a conductor 40 is formed inside the trench TR. The conductor 40 is formed by partially removing the conductive layer 105 by, for example, dry etching or wet etching.

[0043] 5(a), the first insulating film 43 is partially etched to expose the inner wall at the top of the trench TR. The first insulating film 43 is partially removed by, for example, dry etching. The etching amount of the first insulating film 43 is controlled so that the recess amount ΔR1 with respect to the upper surface 103F of the n-type silicon layer 103 becomes a predetermined value.

[0044] As shown in FIG. 5(b), a second insulating film 53 is formed on the surface of the n-type silicon layer 103. The second insulating film 53 covers the inner wall of the upper part of the trench TR. The second insulating film 53 is formed by, for example, thermal oxidation. At this time, an insulating film 45 is also formed on the upper end of the conductor 40. The second insulating film 53 and the insulating film 45 are, for example, silicon oxide films.

[0045] 5(c), a conductive layer 107 is formed so as to cover the first insulating film 43 and the second insulating film 53. The conductive layer 107 is made of, for example, conductive polysilicon. The conductive layer 107 is formed by, for example, CVD.

[0046] 6(a), an etching mask 109 is formed on the conductive layer 107. The etching mask 109 is, for example, a photoresist. The etching mask 109 is formed using, for example, photolithography so as to cover a part of the upper surface 103F of the n-type silicon layer 103 and the inner wall of the trench TR.

[0047] 6(b), the conductive layer 107 is selectively etched using the etching mask 109 to form the control electrode 50. The conductive layer 107 is removed by, for example, dry etching.

[0048] 6(c), the second semiconductor layer 13 is formed on the upper surface side of the n-type silicon layer 103. The n-type silicon layer 103 located between the second semiconductor layer 13 and the n-type silicon substrate 101 becomes the first semiconductor layer 11.

[0049] The second semiconductor layer 13 is formed by selectively ion-implanting p-type impurities, such as boron (B), into the upper surface of the n-type silicon layer 103. The control electrode 50 functions as an ion-implantation mask. The ion-implanted p-type impurities are activated and diffused by heat treatment.

[0050] The second semiconductor layer 13 has a surface 13g in contact with the second insulating film 53 on the inner wall of the trench TR, and its width in the Z direction is a first distance 13c (see FIG. 2(a)). The recess amount ΔR1 (see FIG. 5(a)) of the first insulating film 43 is controlled to be larger than the first distance 13c. That is, the lower surface of the second portion 50b (see FIG. 2(a)) of the control electrode 50 is located lower in the Z direction than the lower end of the surface of the second semiconductor layer 13 in contact with the second insulating film 53.

[0051] 7(a), the third semiconductor layer 15 is formed on the second semiconductor layer 13. The third semiconductor layer 15 is formed by selectively ion-implanting n-type impurities, such as arsenic (As), into the upper surface side of the second semiconductor layer 13 and performing a heat treatment. The control electrode 50 functions as an ion-implantation mask.

[0052] The third semiconductor layer 15 has an overlapping region that overlaps with the first portion 50a of the control electrode 50 in the Z direction. An overlapping width 15d (see FIG. 2(a)) of the overlapping region of the third semiconductor layer 15 is controlled, for example, by the heat treatment temperature after ion implantation or the dose of n-type impurities ion-implanted. Therefore, the overlapping region is formed uniformly within the wafer surface. Also, the overlapping width 15d is easily controlled.

[0053] As shown in FIG. 7(b), a third insulating film 55 is formed to cover the control electrode 50 and the conductor 40. The third insulating film 55 is, for example, a silicon oxide film. The third insulating film 55 is formed by using, for example, CVD. The third insulating film 55 is formed to also cover the third semiconductor layer 15.

[0054] As shown in FIG. 8(a), a contact trench CT is formed in the third insulating film 55. The contact trench CT is formed to a depth that reaches from the upper surface of the third insulating film 55 to the second semiconductor layer 13. Furthermore, a fourth semiconductor layer 17 is formed on the bottom surface of the contact trench CT. The fourth semiconductor layer 17 is formed by ion-implanting a p-type impurity, for example, boron (B), into the second semiconductor layer 13 through the contact trench CT and performing heat treatment.

[0055] 8(b), a first electrode 20 is formed on the third insulating film 55. The first electrode 20 is formed to extend inside the contact trench CT and to be in contact with the third semiconductor layer 15 and the fourth semiconductor layer 17. The first electrode 20 includes, for example, tungsten (W) and aluminum (Al).

[0056] Next, the rear surface side of the n-type silicon substrate 101 is thinned by grinding or etching. This forms a fifth semiconductor layer 19 (see FIG. 1). Furthermore, a second electrode 30 is formed on the rear surface of the fifth semiconductor layer 19. The second electrode 30 includes, for example, nickel (Ni), aluminum (Al), silver (Ag), or the like.

[0057] 9(a) and 9(b) are schematic cross-sectional views showing semiconductor devices 3 and 4 according to modifications of the embodiment, each of which is a partial cross-sectional view showing the opening of a trench TR.

[0058] 9(a), the second semiconductor layer 13 has rounded corners in the region where the upper surface 10F of the semiconductor portion 10 is connected to the inner wall of the trench TR. The corners of the second semiconductor layer 13 are formed to have a radius of curvature Rc that is larger than the thickness 53T of the second insulating film 53 in the Z direction, for example.

[0059] The corners of the second semiconductor layer 13 are rounded, for example, by dry etching when forming the trench TR or by thermal oxidation when forming the second insulating film 53. In other words, the inner surface of the trench TR is formed so as to be connected to the upper surface of the second semiconductor layer 13 via a curved surface. Furthermore, the first portion 50a and the second portion 50b (see FIG. 2) of the control electrode 50 cover the rounded corners of the second semiconductor layer 13 and are connected to each other via a curved portion having a curvature radius Rc. As such, since the second semiconductor layer 13 has rounded corners, the second insulating film 53 has a uniform film thickness. This can suppress variations in the threshold voltage of the control electrode 50. Furthermore, electric field concentration in the second insulating film 53 at the corners of the second semiconductor layer 13 can be suppressed, thereby improving the reliability of the second insulating film 53.

[0060] In the semiconductor device 4 shown in FIG. 9(b), the first portion 50a and the second portion 50b of the control electrode 50 are formed in different processes. The second portion 50b is embedded in a recess formed in the first insulating film 43, for example. Meanwhile, the first portion 50a is formed by patterning a conductive layer formed on the first insulating film 43, the second portion 50b, and the second insulating film 53. The first portion 50a is formed to cover the upper surface of the second semiconductor layer 13. The first portion 50a also includes a portion extending from the upper end of the second portion 50b toward the trench TR. In other words, the first portion 50a extends over the second semiconductor layer 13, the second portion 50b, and the first insulating film in the X direction, for example, and is connected to the upper end of the second portion 50b.

[0061] In this example, the gate resistance of the control electrode 50 can be reduced by increasing the cross-sectional area of the second portion 50b of the control electrode 50. Furthermore, when forming the second portion 50b, there is no need to control the overlap width 15d (see FIG. 2(b)) of the region overlapping with the third semiconductor layer 15, and the allowable range of the recess amount ΔR (see FIG. 2(a)) is widened. This makes it easier to form the second portion 50b.

[0062] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0063] 1, 2, 3, 4...semiconductor device, 10...semiconductor portion, 10F, 103F...upper surface, 11...first semiconductor layer, 11ex...extension portion, 13...second semiconductor layer, 13c...first distance, 13d...second distance, 13f, 13g...surface, 15...third semiconductor layer, 15T, 53T...thickness, 15d...overlap width, 17...fourth semiconductor layer, 19...fifth semiconductor layer, 20...first electrode, 30...second electrode, 40...conductor, 43...first insulating film, 45...insulating film, 50, 60...control electrode, 50a...first portion, 50b...second portion, 53, 63...second insulating film, 55...third insulating film, ΔR, ΔR1...recess amount, 100...silicon wafer, 101...n-type silicon substrate, 103...n-type silicon layer, 105, 107...conductive layer, 109...etching mask, CT...contact trench, Rc...radius of curvature, TR...trench

Claims

1. A first electrode; a second electrode spaced apart from the first electrode in a first direction; a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and positioned between the first electrode and the second electrode; a first insulating film; A second insulating film; a conductor provided in the semiconductor portion, electrically insulated from the semiconductor portion by the first insulating film, and facing the first semiconductor layer via the first insulating film; a first portion provided between the second semiconductor layer and the first electrode with the second insulating film interposed therebetween; a second portion facing the second semiconductor layer via the second insulating film in a second direction perpendicular to the first direction; a control electrode, the first portion and the second portion being connected to each other and spaced apart from the conductor; Equipped with a portion of the first insulating film is located above an upper end of the conductor; an end portion of the control electrode is continuous with the second portion and is located on the part of the first insulating film; The width of the end portion of the control electrode is greater than the width of the second portion.

2. the semiconductor portion further includes a third semiconductor layer of the first conductivity type partially provided on the second semiconductor layer, 2. The semiconductor device according to claim 1, wherein the third semiconductor layer includes a region facing the first portion of the control electrode via the second insulating film.

3. the first electrode is electrically connected to the second semiconductor layer and the third semiconductor layer; 3. The semiconductor device according to claim 2, wherein the control electrode and the conductor are electrically insulated from the first electrode by a third insulating film.

4. 4. The semiconductor device according to claim 2, wherein in the first direction, a first width of the second semiconductor layer along the second insulating film is smaller than a second distance from a boundary between the first semiconductor layer and the second semiconductor layer to a boundary between the second insulating film and the third semiconductor layer.

5. 5. The semiconductor device according to claim 4, wherein the first semiconductor layer includes an extension portion that extends along the second insulating film between the control electrode and the second semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the first portion and the second portion of the control electrode are connected via a curved portion.

7. 7. The semiconductor device according to claim 6, wherein the curved portion of the control electrode has a radius of curvature larger than the thickness of the second insulating film in the first direction, and is larger than the thickness of the second insulating film.

8. 6. The semiconductor device according to claim 1, wherein the first portion of the control electrode extends in the second direction on the first insulating film, on the second portion, and on the second semiconductor layer, and is connected to an upper end of the second portion extending in the first direction.

Images