Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing ON-resistance and improving withstanding voltage.SOLUTION: A semiconductor device comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a second electrode, and a third electrode. The gate electrode is opposed to the second semiconductor region via a gate insulating layer in a second direction. An upper part of the gate electrode includes: a first electrode portion opposed to the third semiconductor region via the gate insulating layer in the second direction; and a second electrode portion arranged side by side with the first electrode portion in a third direction. A length in the second direction of the second electrode portion is longer than that of the first electrode portion and longer than that of a lower part of the gate electrode. The second electrode is provided on the second semiconductor region and the third semiconductor region. The third electrode includes a wiring part provided on the second electrode portion and is separated from the second electrode.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are used for applications such as power conversion, etc. It is desirable for semiconductor devices to have a low on-resistance and a high breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6848317 Summary of the Invention [Problem to be solved by the invention]

[0004] The invention according to the embodiment aims to provide a semiconductor device capable of reducing the on-resistance or improving the breakdown voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a second electrode, and a third electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. An upper portion of the gate electrode includes a first electrode portion facing the third semiconductor region via the gate insulating layer in the second direction, and a second electrode portion aligned with the first electrode portion in a third direction perpendicular to the first and second directions. The length of the second electrode portion in the second direction is longer than the length of the first electrode portion in the second direction and longer than the length of a lower portion of the gate electrode in the second direction. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region. The third electrode includes a wiring portion provided on the second electrode portion and electrically connected to the second electrode portion, and is spaced apart from the second electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged plan view of a portion II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2. [Figure 5] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 1 is a cross-sectional view showing a semiconductor device according to a first reference example. [Figure 9] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second reference example. [Figure 10] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is a plan view showing a portion XI in FIG. [Figure 12] FIG. 12 is a plan view showing a portion XII of FIG. [Figure 13] 13 is a cross-sectional view taken along the line XIII-XIII in FIG. 11. [Figure 14] 14 is a cross-sectional view taken along the line XIV-XIV in FIG. 11. [Figure 15] 13 is a cross-sectional view taken along the line XV-XV in FIG. 12. [Figure 16] 16 is a cross-sectional view taken along the line XVI-XVI of FIG. 12. [Figure 17] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third reference example. [Figure 18] FIG. 10 is a cross-sectional view showing a semiconductor device according to a first modified example of the second embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a semiconductor device according to a first modified example of the second embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second modification of the second embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second modification of the second embodiment. [Figure 22] FIG. 10 is a plan view showing a semiconductor device according to a third modification of the second embodiment. [Figure 23] 23 is a cross-sectional view taken along the line XXIII-XXIII in FIG. 22. [Figure 24] FIG. 10 is a plan view showing a semiconductor device according to a fourth modification of the second embodiment. [Figure 25] 25 is a cross-sectional view taken along the line XXV-XXV of FIG. 24. [Figure 26] 26 is a cross-sectional view taken along line XXVI-XXVI of FIG. 24. [Figure 27] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 28]FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) Fig. 1 is a plan view showing a semiconductor device according to a first embodiment. Fig. 2 is an enlarged plan view of a portion II in Fig. 1. Figs. 3 and 4 are cross-sectional views taken along lines III-III and IV-IV in Fig. 2, respectively. The semiconductor device 100 according to the first embodiment shown in FIGS. 1 to 4 is a MOSFET. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p +Shape contact area 4, n + The semiconductor device includes a drain region 5, a gate electrode 10, a gate insulating layer 15, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), a gate pad 23 (third electrode), and an insulating layer 25.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (third direction) and the Y direction (second direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] 1, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are spaced apart from each other and electrically isolated from each other.

[0011] The gate pad 23 includes a pad portion 23a and a wiring portion 23b. A wiring such as a bonding wire is connected to the pad portion 23a. The wiring portion 23b is connected to the pad portion 23a and extends in the X direction or the Y direction. In the illustrated example, parts of the source electrodes 22 and the wiring portions 23b are alternately provided in the X direction. A plurality of source electrodes 22 may be provided in the X direction, and the wiring portions 23b may be provided between the source electrodes 22.

[0012] 2, the gate electrode 10 extends in the X direction below the source electrode 22 and the gate pad 23. A plurality of gate electrodes 10 are provided in the Y direction. Note that in FIG. 2, the insulating layer 25 is omitted, and the source electrode 22 and the gate pad 23 are indicated by dashed lines.

[0013] As shown in FIG. 3, a drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The drift region 1 is n + The n-type drain region 5 is electrically connected to the drain electrode 21. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 5 is lower than that of the n-type impurity of the n-type drain region 5 .

[0014] The p-type base region 2 is - The n-type drift region 1 is provided on the n-type drift region 1. + Shape source region 3 and p + The p-type contact region 4 is selectively provided on the p-type base region 2. + The p-type impurity concentration of the p-type contact region 4 is higher than the p-type impurity concentration of the p-type base region 2. The gate electrode 10 faces the p-type base region 2 in the Y direction, with the gate insulating layer 15 interposed therebetween.

[0015] As shown in FIGS. 2 to 4, the gate electrode 10 includes an upper portion 11 and a lower portion 12. The upper portion 11 is located above the lower portion 12. The width of a part of the upper portion 11 is wider than the width of the lower portion 12. The "width" corresponds to the length in the Y direction.

[0016] More specifically, the upper portion 11 includes a first electrode portion 11a and a second electrode portion 11b. The first electrode portion 11a is connected to the n-type electrode 11b via the gate insulating layer 15 in the Y direction. +The second electrode portion 11b faces the p-type source region 3. The second electrode portion 11b is aligned with the first electrode portion 11a in the X direction. The second electrode portion 11b is aligned with the p-type base region 2 in the Y direction, with the gate insulating layer 15 interposed therebetween. The width Wg2 of the second electrode portion 11b is wider than the width Wg1 of the first electrode portion 11a and wider than the width Wg0 of the lower portion 12. For example, a step exists between the second electrode portion 11b and the lower portion 12. As shown in FIG. 2, the first electrode portions 11a and the second electrode portions 11b are alternately arranged in the X direction.

[0017] 2 to 4, depending on the relationship between the widths Wg0 to Wg2, the distance Dg2 is shorter than the distance Dg0 and shorter than the distance Dg1. The distance Dg0 is the distance in the Y direction between a pair of lower parts 12 adjacent in the Y direction. The distance Dg1 is the distance in the Y direction between a pair of first electrode portions 11a adjacent in the Y direction. The distance Dg2 is the distance in the Y direction between a pair of second electrode portions 11b adjacent in the Y direction.

[0018] As shown in FIGS. 2 and 4, the wiring portion 23b is located on the second electrode portion 11b. An insulating layer 25 is provided between the p-type base region 2 and the wiring portion 23b and between the gate electrode 10 and the wiring portion 23b. The wiring portion 23b includes a connecting portion 23c. The connecting portion 23c penetrates the insulating layer 25 in the Z direction and contacts the second electrode portion 11b. The second electrode portion 11b is electrically connected to the wiring portion 23b by the connecting portion 23c. In other words, the gate electrode 10 and the gate pad 23 are electrically connected.

[0019] 3, the source electrode 22 may include a connection portion 22a. The connection portion 22a extends in the Z direction and penetrates the insulating layer 25. The connection portion 22a is connected to a part of the p-type base region 2 and the n-type base region 3 in the Y direction. + Shape source region 3 aligned. n + The source region 3 is located between the connection portion 22a and the first electrode portion 11a in the Y direction. + The p-type contact region 4 is located between the p-type base region 2 and the lower end of the connection portion 22a.

[0020] With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 22 to the drain electrode 21. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0021] An example of the material of each component will be described. n - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + contact region 4, and n + The semiconductor material of the drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, the n-type impurity can be arsenic, phosphorus, or antimony. The p-type impurity can be boron.

[0022] The gate electrode 10 includes a conductive material such as polysilicon. The polysilicon may be doped with n-type impurities or p-type impurities. The gate electrode 10 may include one or more metal materials selected from titanium, tungsten, and aluminum. The gate electrode 10 may include a nitride of the one or more metal materials (e.g., titanium nitride). The gate insulating layer 15 and the insulating layer 25 include an insulating material such as silicon oxide. The drain electrode 21, the source electrode 22, and the gate pad 23 include a metal such as titanium, tungsten, or aluminum.

[0023] 5(a) to 7(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. An example of a manufacturing method will be described with reference to Figures 5(a) to 7(b). In Figures 5(a) to 7(b), the left-hand figures show the manufacturing process for the cross-sectional structure shown in Figure 3. The right-hand figures show the manufacturing process for the cross-sectional structure shown in Figure 4. First, n +Semiconductor layer 5a and n - A semiconductor substrate including a semiconductor layer 1a is prepared. - The semiconductor layer 1a is + It is provided on the semiconductor layer 5a. - A mask M is formed on the semiconductor layer 1a. The mask M has an opening at a position corresponding to the gate electrode 10. As shown in FIG. 5(a), the mask M is used to form a n-type silicon nitride film by reactive ion etching (RIE). - An opening OP1 is formed in the semiconductor layer 1a.

[0024] The opening of a part of the mask M is widened by photolithography and RIE. Using the mask M with the widened opening, n - A part of the semiconductor layer 1a is removed. - The etching depth of the semiconductor layer 1a is the n-type in the first RIE. - As a result, as shown in FIG. 5(b), the width Wt2 of a portion of the upper part of the opening OP1 is wider than the width Wt1 of the other portion of the upper part of the opening OP1 and the width Wt0 of the lower part of the opening OP1.

[0025] The inner surface of the opening OP1 and the n - An insulating layer 15a is formed along the upper surface of the semiconductor layer 1a. A conductive layer is formed on the insulating layer 15a to fill the opening OP1. The upper surface of the conductive layer is recessed by chemical mechanical polishing (CMP) and chemical dry etching (CDE). As a result, a gate electrode 10 is formed inside the opening OP1, as shown in FIG. 6(a).

[0026] The portion of the gate electrode 10 provided in the part above the opening OP1 corresponds to the second electrode portion 11b. The portion of the gate electrode 10 provided in the other part above the opening OP1 corresponds to the first electrode portion 11a. The portion of the gate electrode 10 provided below the opening OP1 corresponds to the lower portion 12.

[0027] n -The upper surface of the semiconductor layer 1a is ion-implanted with p-type impurity concentration and n-type impurity concentration in sequence. At this time, the n-type impurity is implanted only around the first electrode portion 11a, and not around the second electrode portion 11b. As shown in FIG. 6(b), the impurities are activated by heat treatment, and the p-type semiconductor region 2a and the n-type impurity region 2b are formed. + A semiconductor region 3a is formed.

[0028] An insulating layer 25a is formed on the gate electrode 10 by chemical vapor deposition (CVD). A part of the insulating layer 25a, n + A part of the p-type semiconductor region 3a and a part of the p-type semiconductor region 2a are removed to form an opening OP2. P-type impurities are ion-implanted into the exposed p-type semiconductor region 2a through the opening OP2. The impurities are activated by heat treatment, and p + 7(a), another part of the insulating layer 25a is removed by RIE to form an opening OP3. The second electrode portion 11b of the gate electrode 10 is exposed through the opening OP3.

[0029] A metal layer is formed on the insulating layer 25a by sputtering. The metal layer is patterned to form the source electrode 22 and the gate pad 23. + The n-type semiconductor layer 5a is then grown to a predetermined thickness. + The lower surface of the semiconductor layer 5a is ground. As shown in FIG. 7(b), the n + A drain electrode 21 is formed on the lower surface of the shaped semiconductor layer 5a. In this way, the semiconductor device 100 according to the first embodiment is manufactured.

[0030] n shown in Figure 7(b) - The semiconductor layer 1a is a n-type semiconductor layer shown in FIGS. - The p-type semiconductor region 2a corresponds to the p-type drift region 1. The p-type semiconductor region 2a corresponds to the p-type base region 2. + The semiconductor region 3a is n + corresponds to the source region 3. + The semiconductor layer 5a is an n-type +A portion of the insulating layer 15a corresponds to the gate insulating layer 15. The other portion of the insulating layer 15a and the insulating layer 25a correspond to the insulating layer 25.

[0031] Fig. 8 is a cross-sectional view showing a semiconductor device according to a first reference example, and Fig. 9(a) and Fig. 9(b) are cross-sectional views showing a semiconductor device according to a second reference example. In a semiconductor device r1 according to a first reference example shown in FIG. 8, the overall width of an upper portion 11 of a gate electrode 10 is wider than the width of a lower portion 12. In a semiconductor device r2 according to a second reference example shown in FIGS. 9(a) and 9(b), a gate electrode 10 includes a narrow portion 13 and a wide portion 14. The width of the narrow portion 13 is wider than the width of the wide portion 14. Narrow The width of the narrow portion 13 is constant from its upper end to its lower end. The width of the wide portion 14 is constant from its upper end to its lower end.

[0032] The advantages of the embodiment will be described. When the gate electrode 10 is electrically connected to the wiring portion 23b, the connection portion 23c must be formed to match the position of the gate electrode 10. If the position of the connection portion 23c is misaligned with the position of the gate electrode 10, a connection failure occurs between the gate electrode 10 and the gate pad 23. In addition, the p-type base region 2, n + Shape source region 3, and p + When a semiconductor region such as the contact region 4 is electrically connected to the source electrode 22, a connection portion 22a needs to be formed between the gate electrodes 10. If the position of the connection portion 22a is misaligned with the position of the semiconductor region, a connection failure occurs between the semiconductor region and the source electrode 22.

[0033] To prevent these connection failures and improve the reliability of the semiconductor device, it is preferable that each connection portion can be easily connected to its corresponding target. For example, by widening the width of the portion of gate electrode 10 that is connected to connection portion 23c, connection portion 23c can be easily connected to gate electrode 10. By widening the spacing between gate electrodes 10, the width of the semiconductor region that is connected to connection portion 22a can be widened, and connection portion 22a can be easily connected to the semiconductor region.

[0034] In the semiconductor device r1 shown in FIG. 8, the width of the upper portion 11 is wide, so that the gate electrode 10 can be easily connected to the gate pad 23. On the other hand, the width of the upper portion 11 is uniformly wide, so that the distance between the gate electrodes 10 is narrow. In order to connect the connection portion 22a to the semiconductor region, the pitch of the gate electrodes 10 needs to be increased. The pitch corresponds to the distance between the centers of adjacent gate electrodes 10 in the Y direction. However, if the pitch of the gate electrodes 10 is increased, the area of the channel region formed per unit area (channel density) decreases, and the on-resistance of the semiconductor device r1 increases.

[0035] In the semiconductor device r2, as shown in FIG. 9(b), the wide portion 14 is provided below the wiring portion 23b, which facilitates connection between the gate electrode 10 and the wiring portion 23b. Furthermore, in the region other than below the wiring portion 23b, the narrow portion 13, which is narrower than the wide portion 14, is provided. Therefore, compared to the semiconductor device r1, the semiconductor region connected to the connection portion 22a can be widened, and the pitch of the gate electrode 10 can be made smaller. However, since the overall width of the wide portion 14 from the top to the bottom is uniformly wide, - The area of the pn junction between the p-type drift region 1 and the p-type base region 2 is smaller than that of the semiconductor device r1, resulting in a lower breakdown voltage of the semiconductor device r2 than that of the semiconductor device r1.

[0036] That is, according to the first or second reference example, although the reliability of the semiconductor device can be improved, an increase in on-resistance or a decrease in breakdown voltage occurs. Regarding this problem, in the semiconductor device 100 according to the first embodiment, the upper portion 11 of the gate electrode 10 includes a first electrode portion 11a and a second electrode portion 11b. The width Wg2 of the second electrode portion 11b provided below the pad portion 23a is wider than the width Wg1 of the first electrode portion 11a. This facilitates connection between the gate electrode 10 and the gate pad 23. Furthermore, the width Wg1 of the first electrode portion 11a is narrower than the width Wg2 of the second electrode portion 11b. Therefore, even if the pitch of the gate electrode 10 is reduced, the source electrode 22 can be easily connected to the p-type base region 2, n + Shape source region 3, and p + This allows for easy connection to semiconductor regions such as the contact region 4.

[0037] Furthermore, the width Wg2 of the second electrode portion 11b is wider than the width Wg0 of the lower portion 12. That is, the width Wg0 of the lower portion 12 is narrower than the width of the second electrode portion 11b. - The narrow width of the lower portion 12 aligned with the pn junction between the p-type drift region 1 and the p-type base region 2 allows the area of the pn junction to be larger than that of the semiconductor device r2, thereby improving the breakdown voltage of the semiconductor device 100.

[0038] According to the first embodiment, it is possible to reduce the on-resistance or improve the breakdown voltage of the semiconductor device 100 while suppressing a decrease in the reliability of the semiconductor device 100.

[0039] To more easily connect the second electrode portion 11b and the connection portion 23c and increase the area of the pn junction, it is preferable that the difference between the widths Wg2 and Wg1 and the difference between the widths Wg2 and Wg0 be larger. Specifically, it is preferable that the width Wg2 be at least 1.1 times the width Wg0 or the width Wg1. However, if the difference between these widths is too large, the potential is likely to rise in the semiconductor region between the second electrode portions 11b when the semiconductor device 100 is in the off state. This makes it easier for the gate insulating layer 15 to break down between the second electrode portion 11b and the semiconductor region. For this reason, it is preferable that the difference between the widths Wg2 and Wg1 and the difference between the widths Wg2 and Wg0 be no more than 0.9 times the width Ws of the p-type base region 2 located between the lower portions 12.

[0040] A portion of the lower portion 12 is located under the first electrode portion 11a. Another portion of the lower portion 12 is located under the second electrode portion 11b. The width Wg0 of the other portion of the lower portion 12 is different from the width Wg0 of the other portion of the lower portion 12 and may be wider than the width Wg0 of the other portion of the lower portion 12. More preferably, the width Wg0 of the other portion of the lower portion 12 is substantially the same as the width Wg0 of the other portion of the lower portion 12. For example, the sum of the width Wg0 of the lower portion 12 located under the second electrode portion 11b and the thickness T1 of the gate insulating layer 15 is greater than 0.90 and less than 1.1 times the sum of the width Wg0 of the lower portion 12 located under the first electrode portion 11a and the thickness T1. In other words, the difference between the width Ws of the p-type base region 2 aligned in the Y direction with the other portion of the lower portion 12 and the width Ws of the p-type base region 2 aligned in the Y direction with the portion of the lower portion 12 is preferably 0.1 times or less than the sum of the width Wg0 and thickness T1 of any portion of the lower portion 12. The thickness T1 corresponds to the thickness of the gate insulating layer 15 in the X direction between the gate electrode 10 and the p-type base region 2. With this configuration, the area of the pn junction can be increased, and the breakdown voltage of the semiconductor device 100 can be further improved.

[0041] (Second embodiment) Fig. 10 is a plan view showing a semiconductor device according to a second embodiment. Figs. 11 and 12 are plan views showing portions XI and XII of Fig. 10, respectively. Figs. 13 to 16 are cross-sectional views taken along lines XIII-XIII, XIV-XIV, XV-XV, and XVI-XVI of Fig. 12, respectively. The semiconductor device 200 according to the second embodiment shown in FIGS. 10 to 16 further includes a conductive portion 30 and an insulating portion 40 in addition to the semiconductor device 100. In the semiconductor device 200 shown in FIGS.

[0042] As shown in FIGS. 13 and 14, the insulating portion 40 has n - a part of the p-type drift region 1, a p-type base region 2, and an n + The insulating portion 40 is aligned with the source region 3 in the Y direction. The insulating portion 40 includes a first insulating portion 41, a second insulating portion 42, and a third insulating portion 43.

[0043] The first insulating portion 41 has a length of n -Lined up with part of the drift region 1. - The intermediate region 1m of the p-type drift region 1 is located between the first insulating portions 41 in the Y direction. The second insulating portion 42 and the third insulating portion 43 are provided on the first insulating portion 41. The second insulating portion 42 is located between the p-type base region 2 and the n-type + The third insulating portion 43 is aligned with the p-type source region 3 in the Y direction. The third insulating portion 43 is aligned with the p-type base region 2 in the Y direction. As shown in FIG. 11 , the third insulating portion 43 is aligned with the second insulating portion 42 in the X direction. The second insulating portion 42 and the third insulating portion 43 are provided alternately in the X direction.

[0044] As shown in FIGS. 13 and 14 , the conductive portion 30 is provided in the first insulating portion 41. The gate electrode 10 is provided in the second insulating portion 42 and the third insulating portion 43. The gate electrode 10 is separated from the conductive portion 30 and is electrically isolated from the conductive portion 30. As shown in FIGS. 15 and 16 , a portion of the conductive portion 30 is pulled upward and electrically connected to the source electrode 22 by a connection portion 22 b. Alternatively, the gate electrode 10 may be in contact with the conductive portion 30. In this case, the conductive portion 30 is electrically isolated from the source electrode 22. Alternatively, the conductive portion 30 may be electrically isolated from both the gate electrode 10 and the source electrode 22. In this case, the potential of the conductive portion 30 is controlled separately from the potential of the gate electrode 10 and the potential of the source electrode 22.

[0045] 11 to 14, the gate electrode 10 includes a first electrode portion 11a and a second electrode portion 11b. In the semiconductor device 200, the first electrode portion 11a and the second electrode portion 11b are provided not only on the top but also on the bottom of the gate electrode 10. As in the semiconductor device 100, the first electrode portion 11a is connected in the Y direction to the p-type base region 2 and the n-type base region 3 via the second insulating portion 42. +The second electrode portion 11b faces the p-type source region 3. The second insulating portion 42 functions as a gate insulating layer. The second electrode portion 11b is aligned with the first electrode portion 11a in the X direction. The second electrode portion 11b faces the p-type base region 2 in the Y direction via the third insulating portion 43. The width Wg2 of the second electrode portion 11b is wider than the width Wg1 of the first electrode portion 11a, the width Wc0 of the conductive portion 30, and the width Wi1 of the first insulating portion 41.

[0046] 11 to 14, the width Ws2 is shorter than the width Ws0 and shorter than the width Ws1 depending on the relationship between the widths of the first electrode portion 11a, the second electrode portion 11b, the conductive portion 30, and the first insulating portion 41. The width Ws0 is the width of the n electrode portions 11a, 11b ... - The width Ws1 is the width of the p-type drift region 1. The width Ws1 is the width of the p-type base region 2 located between a pair of first electrode portions 11a adjacent to each other in the Y direction. The width Ws2 is the width of the p-type base region 2 located between a pair of second electrode portions 11b adjacent to each other in the Y direction.

[0047] The conductive portion 30 includes a conductive material such as polysilicon. The polysilicon may be doped with n-type impurities or p-type impurities. The conductive portion 30 may include one or more metal materials selected from titanium, tungsten, and aluminum. The conductive portion 30 may include nitrides of the one or more metal materials. The insulating portion 40 includes an insulating material such as silicon oxide.

[0048] The semiconductor device 200 can operate as a MOSFET, similar to the semiconductor device 100. Furthermore, in the semiconductor device 200, when switched to the off state, n - In response to an increase in the potential difference between the drift region 1 and the conductive portion 30, n - The n-type drift region 1 is formed by the interface between the drift region 1 and the insulating portion 40. - The depletion layer expands toward the n-type drift region 1. This expansion of the depletion layer can increase the breakdown voltage of the semiconductor device 200. Alternatively, the n-type impurity concentration in the intermediate region 1m can be increased while maintaining the breakdown voltage of the semiconductor device 200, thereby reducing the on-resistance of the semiconductor device 200.

[0049] 17(a) and 17(b) are cross-sectional views showing a semiconductor device according to a third reference example. 17(a) and 17(b), the insulating portion 40 includes a narrow portion 45a and a wide portion 45b. The upper portion of the narrow portion 45a is in contact with the p-type base region 2 and the n-type base region 3 in the Y direction. + The wide portion 45b is aligned with the narrow portion 45a in the X direction. The gate electrode 10 and the conductive portion 30 are provided in the narrow portion 45a and the wide portion 45b. The width of the wide portion 45b is wider than the width of the narrow portion 45a.

[0050] The advantages of the second embodiment will be described. In the semiconductor device r3, the wide portion 45b is provided below the connection portion 23c. This allows the connection portion 23c to be easily connected to the gate electrode 10 provided within the wide portion 45b. The narrow portion 45a widens the width of the semiconductor region connected to the connection portion 22a, allowing the connection portion 22a to be easily connected to the semiconductor region. Meanwhile, the width of the wide portion 45b, where the gate electrode 10 is provided, is approximately the same as the width of the conductive portion 30. This means that the width of the intermediate region 1m located between the wide portions 45b is narrower than the width of the intermediate region 1m located between the narrow portions 45a. Narrowing the width of the intermediate region 1m reduces the area over which the depletion layer expands, thereby reducing the breakdown voltage of the semiconductor device r3.

[0051] To address this issue, in the semiconductor device 200 according to the second embodiment, the insulating portion 40 includes a first insulating portion 41, a second insulating portion 42, and a third insulating portion 43. The third insulating portion 43 is located below the wiring portion 23b, and the width Wi3 of the third insulating portion 43 is wider than the width Wi2 of the second insulating portion 42. This allows for easy connection of the wiring portion 23b to the gate electrode 10 provided within the third insulating portion 43. Furthermore, the width Wi2 of the second insulating portion 42 is narrower than the width Wi3 of the third insulating portion 43. This allows for a wide spacing between the second insulating portions 42, allowing for easy connection of the connection portion 22a to the semiconductor region. Furthermore, the width Wi1 of the first insulating portion 41 is narrower than the width Wi3 of the third insulating portion 43. This allows for a wider width of the intermediate region 1m than the semiconductor device r3, thereby improving the breakdown voltage of the semiconductor device 200.

[0052] According to the second embodiment, the breakdown voltage of the semiconductor device 200 can be improved while suppressing a decrease in the reliability of the semiconductor device 200.

[0053] A portion of the conductive portion 30 is located below the first electrode portion 11a. Another portion of the conductive portion 30 is located below the second electrode portion 11b. The width Wc0 of the other portion of the conductive portion 30 is different from the width Wc0 of the other portion of the conductive portion 30 and may be wider than the width Wc0 of the other portion of the conductive portion 30. More preferably, the width Wc0 of the other portion of the conductive portion 30 is substantially the same as the width Wc0 of the other portion of the conductive portion 30. For example, the sum of the width Wc0 of the other portion of the conductive portion 30 and the thickness T2 of the insulating portion 40 is greater than 0.90 times and less than 1.1 times the sum of the width Wc0 and thickness T2 of the other portion of the conductive portion 30. In other words, the width Wc0 of the other portion of the conductive portion 30 aligned in the Y direction with the other portion of the conductive portion 30 is greater than 0.90 times and less than 1.1 times the sum of the width Wc0 and thickness T2 of the other portion of the conductive portion 30. - The width Ws0 of the drift region 1 and the n - The difference between the width Ws0 of the shaped drift region 1 and the width Wc0 of any part of the conductive portion 30 and the thickness T2 is preferably 0.1 times or less. - The width Wc0 corresponds to the thickness of the insulating part 40 in the X direction between the first insulating part 41 and the drift region 1. The sum of the width Wc0 and the thickness T2 is the width Wi1 of the first insulating part 41. With this configuration, the volume of the intermediate region 1m can be increased, and the breakdown voltage of the semiconductor device 200 can be further improved.

[0054] 12 and 15, the insulating unit 40 may further include a fourth insulating portion 44. The fourth insulating portion 44 is aligned with the second insulating portion 42 in the X direction. The second insulating portion 42 is located between the third insulating portion 43 and the fourth insulating portion 44 in the X direction. The width Wi4a of the upper portion of the fourth insulating portion 44 is greater than the width Wi1 of the first insulating portion 41, the width Wi2 of the second insulating portion 42, and the width Wi4b of the lower portion of the fourth insulating portion 44. The width Wi4a of the upper portion of the fourth insulating portion 44 may be the same as or different from the width Wi3 of the third insulating portion 43.

[0055] A part of the conductive portion 30 is provided in the fourth insulating portion 44. The conductive portion 30 includes a first conductive portion 31 and a second conductive portion 32. The first conductive portion 31 is connected to the n-th conductive portion 32 via the first insulating portion 41 in the X direction. - The second conductive portion 32 faces the gate electrode 10 in the X direction via the fourth insulating portion 44. The width Wc2a of the upper portion of the second conductive portion 32 is wider than the width Wc2b of the lower portion of the second conductive portion 32 and is wider than the width Wc1 of the first conductive portion 31.

[0056] The connection portion 22b of the source electrode 22 extends in the Z direction and penetrates the insulating layer 25. The connection portion 22b is in contact with the upper surface of the second conductive portion 32. When the insulating portion 40 includes the fourth insulating portion 44, the source electrode 22 can be easily connected to the second conductive portion 32. This can further improve the reliability of the semiconductor device 200.

[0057] (First Modification) 18 and 19 are cross-sectional views showing a semiconductor device according to a first modification of the second embodiment, which correspond to the XIII-XIII and XIV-XIV cross-sectional views of FIG. In the semiconductor device 210 according to the first modification shown in FIGS. 18 and 19, the gate electrode 10 includes an upper portion 11 and a lower portion 12, similar to the semiconductor device 100. The lower portion 12 is provided in the first insulating portion 41. The upper portion 11 is a first electrode portion 11a. and The second electrode portion 11b has a width Wg2 that is greater than the width Wg1 of the first electrode portion 11a and is greater than the width Wg0 of the lower portion 12.

[0058] The upper portion 11 of the gate electrode 10 includes the first electrode portion 11a and the second electrode portion 11b, so that the semiconductor device 200 has n - This increases the area of the pn junction between the p-type drift region 1 and the p-type base region 2. According to the first modification, the breakdown voltage of the semiconductor device 210 can be improved.

[0059] (Second Modification) 20 and 21 are cross-sectional views showing a semiconductor device according to a second modification of the second embodiment, which correspond to the XIII-XIII and XIV-XIV cross-sectional views of FIG. In the semiconductor device 220 according to the second modification, the YZ cross-sectional shape of a part of the gate electrode 10 is different from the YZ cross-sectional shape of the gate electrode 10 in the semiconductor device 210.

[0060] 21, the lower portion 12 includes a portion 12a located below the first electrode portion 11a and a portion 12b located below the second electrode portion 11b. As shown in FIG. 19, the width of the gate electrode 10 of the semiconductor device 200 increases stepwise from the lower portion 12 toward the second electrode portion 11b. In contrast, the width of the gate electrode 10 of the semiconductor device 220 increases gradually from the portion 12b toward the second electrode portion 11b.

[0061] The side surfaces of second electrode portion 11b and portion 12b are inclined with respect to the Z direction. Meanwhile, as shown in Fig. 20, the width is constant from portion 12a to first electrode portion 11a. The inclination of the side surfaces of first electrode portion 11a and portion 12a with respect to the Z direction is smaller than the inclination of the side surfaces of second electrode portion 11b and portion 12b with respect to the Z direction.

[0062] According to the second modification, the area of the pn junction can be increased as in the first modification, and the breakdown voltage of the semiconductor device 220 can be improved.

[0063] (Third Modification) Fig. 22 is a plan view showing a semiconductor device according to a third modification of the second embodiment, and Fig. 23 is a cross-sectional view taken along line XXIII-XXIII of Fig. 22. As shown in FIGS. 22 and 23, the semiconductor device 230 according to the third modification has a p + The semiconductor device further includes a contact region 6 (fifth semiconductor region).

[0064] As shown in Figure 22, p + The contact region 6 is provided around the third insulating portion 43 in the XY plane and is in contact with the third insulating portion 43. + The contact region 6 is located under the wiring portion 23b. + The p-type contact region 6 is located on the p-type base region 2. + The p-type impurity concentration of the p-type contact region 6 is higher than the p-type impurity concentration of the p-type base region 2.

[0065] When a semiconductor device is switched off, the voltage applied to the semiconductor device increases temporarily, and avalanche breakdown can occur. At this time, a large number of carriers (electrons and holes) are generated. The electrons are + The holes pass through the p-type drain region 5 and are discharged from the drain electrode 21. + The electrons pass through the contact region 4 and are discharged from the source electrode 22 .

[0066] The semiconductor device is- a p-type drift region 1, a p-type base region 2, and an n + The p-type base region 2 and the p-type source region 3 form an npn bipolar transistor (parasitic transistor). When holes are discharged, it is desirable that the electrical resistance to the holes is small. + If the potential of the contact region 4 rises, a parasitic transistor may be activated. If the parasitic transistor is activated, a large current flows through the semiconductor device, destroying the semiconductor device.

[0067] In the region below the source electrode 22, p + The holes are efficiently discharged by the contact region 4 and the connection portion 22a. In other words, the electrical resistance to the holes is sufficiently small. On the other hand, in the region below the wiring portion 23b, + Therefore, the holes generated below the wiring portion 23b are not p + The p-type base region 2 moves to the region where the contact region 4 and the connection portion 22b are provided. Therefore, holes tend to accumulate in the region below the wiring portion 23b, and the potential of the p-type base region 2 tends to rise.

[0068] Regarding this problem, in the semiconductor device 230 according to the third modification, a p + The p-type contact region 6 is provided. The holes that flow into the p-type base region 2 are + The potential of the p-type base region 2 can be prevented from rising during avalanche breakdown, and therefore the parasitic transistor is less likely to operate. According to the third modification, the possibility of destruction of the semiconductor device 230 can be reduced, and the reliability of the semiconductor device 230 can be further improved.

[0069] (Fourth Modification) Fig. 24 is a plan view showing a semiconductor device according to a fourth modification of the second embodiment, Fig. 25 and Fig. 26 are cross-sectional views taken along lines XXV-XXV and XXVI-XXVI of Fig. 24, respectively. In the semiconductor device 240 according to the fourth modification, the YZ cross-sectional shape of a part of the gate electrode 10 is different from the YZ cross-sectional shape of a part of the gate electrode 10 in the semiconductor device 200.

[0070] 24 and 25, a pair of first electrode portions 11a are provided in the second insulating portion 42. The pair of first electrode portions 11a are spaced apart from each other in the Y direction. Each of the first electrode portions 11a extends along the X direction. A portion of the conductive portion 30 may extend further upward and be located between the pair of first electrode portions 11a.

[0071] 26, the shape of the second electrode portion 11b of the gate electrode 10 in the semiconductor device 240 is the same as the shape of the second electrode portion 11b of the gate electrode 10 in the semiconductor device 200. The end portion in the X direction of the first electrode portion 11a is in contact with the second electrode portion 11b.

[0072] As in the fourth modification, the divided first electrode portion 11a may be provided in the second insulating portion 42. In either case, the width Wi3 of the third insulating portion 43 is wider than the width Wi2 of the second insulating portion 42. This allows the gate pad 23 to be easily connected to the second electrode portion 11b provided in the third insulating portion 43.

[0073] Furthermore, according to the fourth modification, the opposing area between the gate electrode 10 and the conductive portion 30 in the Z direction can be reduced. Direction The smaller the area, the smaller the gate-source capacitance Cgs between the gate electrode 10 and the conductive portion 30. For example, the transition period when turning on the semiconductor device 240 can be shortened, and the switching loss of the semiconductor device 240 can be reduced.

[0074] (Third embodiment) 27 and 28 are cross-sectional views showing a semiconductor device according to the third embodiment. 27 and 28 is an IGBT. Compared to the semiconductor device 100, the semiconductor device 300 includes a p+ type collector region 7 and an n-type buffer region 8 instead of the n+ type drain region 5. The semiconductor device 300 also includes a collector electrode 21C instead of the drain electrode 21 and the source electrode 22. and An emitter electrode 22E is provided.

[0075] The collector electrode 21C and the emitter electrode 22E are provided on the bottom surface and the top surface of the semiconductor device 300, respectively. + The n-type collector region 7 is provided on the collector electrode 21C and is electrically connected to the collector electrode 21C. The n-type buffer region 8 is + The collector region 7 is provided on the n - The n-type drift region 1 is provided on the n-type buffer region 8. - The n-type impurity concentration of the n-type drift region 1 is lower than the n-type impurity concentration of the n-type buffer region 8.

[0076] Similar to the semiconductor device 100, the gate electrode 10 includes an upper portion 11 and a lower portion 12. The upper portion 11 includes a first electrode portion 11a and a second electrode portion 11b. The width Wg2 of the second electrode portion 11b is wider than the width Wg1 of the first electrode portion 11a and wider than the width Wg0 of the lower portion 12.

[0077] The operation of the semiconductor device 300 will now be described. With a positive voltage applied to the collector electrode 21C relative to the emitter electrode 22E, a voltage equal to or higher than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 2. Electrons pass through the channel from the emitter electrode 22E to form the n - In response to the injection of electrons, holes are injected into the n-type drift region 1, and the semiconductor device 300 is turned on. - The injected electrons and holes cause conductivity modulation, resulting in n -The electrical resistance of the p-type drift region 1 decreases. When a potential lower than the threshold is then applied to the gate electrode 10, the channel in the p-type base region 2 disappears, and the semiconductor device 300 enters an off state.

[0078] In the semiconductor device 300, the gate electrode 10 includes the first electrode portion 11a and the second electrode portion 11b, as in the first embodiment. Therefore, according to the third embodiment, it is possible to reduce the on-resistance or improve the breakdown voltage of the semiconductor device 300 while suppressing a decrease in the reliability of the semiconductor device 300.

[0079] The above-described embodiments can be combined as appropriate. For example, the YZ cross-sectional shape of the gate electrode 10 in the semiconductor device 220 may be applied to the gate electrode 10 in the semiconductor device 100. In the semiconductor device 100, p + A contact region 6 may be provided. In the semiconductor device 100, a plurality of gate electrodes 10 may be provided in one gate insulating layer 15, as in the semiconductor device 240.

[0080] Embodiments may include the following features. (Configuration 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, wherein an upper portion of the gate electrode is a first electrode portion facing the third semiconductor region in the second direction via the gate insulating layer; a second electrode portion aligned with the first electrode portion in a third direction perpendicular to the first direction and the second direction; the gate electrode, wherein a length of the second electrode portion in the second direction is longer than a length of the first electrode portion in the second direction and longer than a length of a lower portion of the gate electrode in the second direction; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode provided on the second electrode portion and including a wiring portion electrically connected to the second electrode portion, the third electrode being spaced from the second electrode; A semiconductor device comprising: (Configuration 2) the second electrode includes a connection portion in contact with a part of the second semiconductor region and the third semiconductor region, 2. The semiconductor device according to claim 1, wherein the third semiconductor region is located between the first electrode portion and the connection portion in the second direction. (Configuration 3) a conductive portion provided in the first semiconductor region via an insulating portion; 3. The semiconductor device according to claim 1, wherein the second electrode is electrically connected to the conductive portion. (Configuration 4) The conductive portion is a first conductive portion facing the first semiconductor region via the insulating portion in the second direction; a second conductive portion provided on the first conductive portion and aligned with the gate electrode in a third direction perpendicular to the first direction and the second direction; Including, a length of the second conductive portion in the second direction is longer than a length of the first conductive portion in the second direction; 4. The semiconductor device of claim 3, wherein the second electrode contacts the second conductive portion. (Configuration 5) a plurality of the gate electrodes are provided in the second direction; 5. The semiconductor device according to any one of configurations 1 to 4, wherein the wiring portion is located above a plurality of the second electrode portions and is in contact with the plurality of second electrode portions. (Configuration 6) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first insulating portion aligned with the first semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second insulating portion provided on the first insulating portion and aligned with the second semiconductor region and the third semiconductor region in the second direction; a third insulating portion aligned with the second insulating portion in a third direction perpendicular to the first direction and the second direction; an insulating portion including: a conductive portion provided in the first insulating portion; a gate electrode at least partially disposed within the second insulating portion and the third insulating portion; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode including a wiring portion provided on the third insulating portion, the third electrode being spaced apart from the second electrode and electrically connected to the gate electrode; A semiconductor device comprising: (Configuration 7) a lower portion of the gate electrode is provided in the first insulating portion; 7. The semiconductor device of claim 6, wherein an upper portion of the gate electrode is disposed within the second insulating portion and the third insulating portion. (Configuration 8) The upper portion of the gate electrode is a first electrode portion disposed within the second insulating portion; a second electrode portion disposed within the third insulating portion; Including, 8. The semiconductor device of claim 7, wherein the length of the second electrode portion in the second direction is longer than the length of the first electrode portion in the second direction and longer than the length of the lower portion of the gate electrode in the second direction. (Configuration 9) a fifth semiconductor region of the second conductivity type provided around the third insulating portion and positioned on the second semiconductor region; 9. The semiconductor device according to any one of configurations 6 to 8, wherein the fifth semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region. (Configuration 10) a portion of the first insulating portion is located below the second insulating portion; another part of the first insulating portion is located under the third insulating portion; A semiconductor device according to any one of configurations 6 to 9, wherein the length of the other part of the first insulating part in the second direction is more than 0.9 times and less than 1.1 times the length of the part of the first insulating part in the second direction. (Configuration 11) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a pair of insulating portions aligned with the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, and spaced apart from each other in the second direction; a pair of conductive portions respectively provided in the pair of insulating portions, each of the pair of conductive portions facing the first semiconductor region in the second direction; A pair of gate electrodes respectively provided in the pair of insulating portions, each of the pair of gate electrodes a first electrode portion facing the third semiconductor region in the second direction; a second electrode portion that is aligned with the first electrode portion in a third direction perpendicular to the first direction and the second direction, faces the second semiconductor region in the second direction, and has a length in the second direction longer than that of the first electrode portion; the plurality of gate electrodes, wherein a length in the second direction of the second semiconductor region between a pair of the second electrode portions is longer than a length in the second direction of the second semiconductor region between a pair of the first electrode portions and longer than a length in the second direction of the first semiconductor region between the pair of conductive portions; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode including a wiring portion provided on the pair of second electrode portions, the third electrode being spaced from the second electrode and electrically connected to the plurality of second electrode portions; A semiconductor device comprising:

[0081] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0082] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0083] 1:n - Shape drift region, 1a:n - p-type semiconductor layer, 1m: intermediate region, 2: p-type base region, 2a: p-type semiconductor region, 3: n + Shape source area, 3a:n + Shape semiconductor area, 4:p + Shape contact area, 5:n + Shaped drain region, 5a:n + Semiconductor layer, 6:p + Shape contact area, 7:p + n-type collector region, 8: n-type buffer region, 10: gate electrode, 11: upper portion, 11a: first electrode portion, 11b: second electrode portion, 12: lower portion, 12a, 12b: portions, 13: narrow portion, 14: wide portion, 15: gate insulating layer, 15a: insulating layer, 21: drain electrode, 21C: collector electrode, 22: source electrode, 22E: emitter electrode, 22a, 22b: connecting portion, 23: gate pad, 23a: pad portion, 23b: wiring portion, 23c: connecting portion, 25, 25a: insulating layer, 30: conductive portion, 31: first conductive portion, 32: second conductive portion, 40: insulating portion, 41: first insulating portion, 42: second insulating portion, 43: third insulating portion, 44: fourth insulating portion; 45a: narrow portion; 45b: wide portion; 100, 200-240, 300, r1-r3: semiconductor device; M: mask; OP1-OP3: openings

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, wherein an upper portion of the gate electrode is a first electrode portion facing the third semiconductor region in the second direction via the gate insulating layer; a second electrode portion aligned with the first electrode portion in a third direction perpendicular to the first direction and the second direction; the gate electrode, wherein a length of the second electrode portion in the second direction is longer than a length of the first electrode portion in the second direction and longer than a length of a lower portion of the gate electrode in the second direction; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode provided on the second electrode portion and including a wiring portion electrically connected to the second electrode portion, the third electrode being spaced from the second electrode; A semiconductor device comprising:

2. the second electrode includes a connection portion in contact with a part of the second semiconductor region and the third semiconductor region, The semiconductor device according to claim 1 , wherein said third semiconductor region is located between said first electrode portion and said connection portion in said second direction.

3. a conductive portion provided in the first semiconductor region via an insulating portion; The semiconductor device according to claim 1 , wherein the second electrode is electrically connected to the conductive portion.

4. The conductive portion is a first conductive portion facing the first semiconductor region via the insulating portion in the second direction; a second conductive portion provided on the first conductive portion and aligned with the gate electrode in a third direction perpendicular to the first direction and the second direction; Including, a length of the second conductive portion in the second direction is longer than a length of the first conductive portion in the second direction; The semiconductor device according to claim 3 , wherein said second electrode is in contact with said second conductive portion.

5. a plurality of the gate electrodes are provided in the second direction; The semiconductor device according to claim 1 , wherein the wiring portion is located on a plurality of the second electrode portions and is in contact with the plurality of second electrode portions.

6. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a first insulating portion aligned with the first semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region; a second insulating portion provided on the first insulating portion and aligned with the second semiconductor region and the third semiconductor region in the second direction; a third insulating portion aligned with the second insulating portion in a third direction perpendicular to the first direction and the second direction; an insulating portion including: a conductive portion provided in the first insulating portion; a gate electrode at least partially disposed within the second insulating portion and the third insulating portion; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode including a wiring portion provided on the third insulating portion, the third electrode being spaced apart from the second electrode and electrically connected to the gate electrode; A semiconductor device comprising:

7. a lower portion of the gate electrode is provided in the first insulating portion; 7. The semiconductor device according to claim 6, wherein an upper portion of said gate electrode is provided in said second insulating portion and said third insulating portion.

8. The upper portion of the gate electrode is a first electrode portion disposed within the second insulating portion; a second electrode portion disposed within the third insulating portion; Including, 8. The semiconductor device according to claim 7, wherein the length of said second electrode portion in said second direction is longer than the length of said first electrode portion in said second direction and longer than the length of said lower portion of said gate electrode in said second direction.

9. a fifth semiconductor region of the second conductivity type provided around the third insulating portion and positioned above the second semiconductor region; 9. The semiconductor device according to claim 6, wherein the fifth semiconductor region has a higher impurity concentration of the second conductivity type than the second semiconductor region.

10. a portion of the first insulating portion is located below the second insulating portion; another part of the first insulating portion is located under the third insulating portion; The semiconductor device according to any one of claims 6 to 8, wherein the length of the other part of the first insulating part in the second direction is longer than 0.9 times and shorter than 1.1 times the length of the part of the first insulating part in the second direction.

11. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a pair of insulating portions aligned with the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, and spaced apart from each other in the second direction; a pair of conductive portions provided in the pair of insulating portions, respectively, each of the pair of conductive portions facing the first semiconductor region in the second direction; A pair of gate electrodes respectively provided in the pair of insulating portions, each of the pair of gate electrodes a first electrode portion facing the third semiconductor region in the second direction; a second electrode portion aligned with the first electrode portion in a third direction perpendicular to the first direction and the second direction, facing the second semiconductor region in the second direction, and having a length in the second direction longer than that of the first electrode portion; the pair of gate electrodes, wherein a length in the second direction of the second semiconductor region between the pair of second electrode portions is shorter than a length in the second direction of the second semiconductor region between the pair of first electrode portions and shorter than a length in the second direction of the first semiconductor region between the pair of conductive portions; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a third electrode including a wiring portion provided on the pair of second electrode portions, the third electrode being spaced from the second electrode and electrically connected to the pair of second electrode portions; A semiconductor device comprising:

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