Transistor device and method of manufacturing the same

Abstract

A transistor device and a method for manufacturing the transistor device are disclosed. The transistor device includes a gate, a gate insulator, and a body region and a drift region stacked along a first direction. The gate includes opposing top and bottom surfaces and a side surface interposed between the top and bottom surfaces, the bottom surface being in the first direction of the top surface, the gate insulator surrounding at least a portion of the bottom and side surfaces of the gate, the gate insulator including a sidewall and a bottom, the body region surrounding a portion of the sidewall of the gate insulator, and the gate insulator extending along the first direction from a surface of the drift region facing the body region into the drift region. The body region includes a first subregion, a second subregion, and a third subregion arranged in sequence along a second direction, the second direction being perpendicular to the first direction and pointing away from the gate insulator, and the average carrier concentration of the first subregion and the average carrier concentration of the third subregion are both higher than the average carrier concentration of the second subregion.

Description

[Technical Field]

[0001] TECHNICAL FIELD This application relates to the field of semiconductor devices, and more particularly to transistor devices and methods for fabricating transistor devices. [Background technology]

[0002] Semiconductor transistors, particularly field-effect controlled switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are used in a variety of applications such as power supplies, power converters, etc. Many of these applications are high-power applications, requiring the transistor to be able to withstand large amounts of current and / or voltage.

[0003] Power transistors can be implemented as vertical trench MOS transistors, which can have blocking voltage capabilities of up to several hundred volts and current ratings exceeding one ampere. In vertical transistors, the gate can be disposed in a trench extending vertically in the semiconductor body. The gate is electrically isolated from the transistor's source, body, and drift regions, for example, through a gate insulator, and the gate and body regions are disposed laterally (the lateral direction is perpendicular to the vertical direction). The drain can be connected to the drift region. Under forward conduction conditions, the device trench is inverted along the vertical direction from the body region near the gate oxide.

[0004] Silicon carbide (SiC) offers certain excellent properties as a substrate material for power transistors. Certain attributes of silicon carbide enable higher blocking voltage capability at a given on-resistance than semiconductor devices using other substrate materials, such as silicon-based semiconductor devices. For example, silicon carbide has a higher critical electric field, i.e., the electric field at which avalanche breakdown occurs. Therefore, silicon carbide-based transistors have higher breakdown voltages. Silicon carbide devices can be significantly thinner and have lower on-resistance. This allows transistor devices to have lower capacitance and gate charge, further improving the switching characteristics of the device. Silicon carbide-based transistors also have superior high-temperature operation capabilities, allowing them to operate under high-temperature conditions (e.g., operating temperatures above 175°C) while also experiencing a smaller increase in on-resistance at high temperatures.

[0005] However, related silicon carbide-based transistor devices face several challenges. For example, due to process limitations, defects may exist at the interface between the silicon carbide body and the gate insulator (e.g., silicon dioxide, SiO2) in silicon carbide-based transistor devices, resulting in poor quality vertical trenches. This results in reduced electron mobility and increased on-resistance. To fully utilize the advantages of silicon carbide, the trench defect problem must be overcome. Summary of the Invention [Problem to be solved by the invention]

[0006] According to one aspect of the present application, there is provided a transistor device including a gate, a gate insulator, and a body region and a drift region stacked along a first direction. The gate includes opposing top and bottom surfaces and side surfaces interposed between the top and bottom surfaces, the bottom surface being in the first direction of the top surface. The gate insulator surrounds at least a portion of the bottom and side surfaces of the gate, the gate insulator including sidewalls and a bottom. The body region surrounds a portion of the sidewalls of the gate insulator, and the gate insulator extends along the first direction from a surface of the drift region facing the body region into the drift region. The body region includes a first subregion, a second subregion, and a third subregion arranged in sequence along a second direction, the second direction being perpendicular to the first direction and pointing away from the gate insulator. An average carrier concentration of the first subregion and an average carrier concentration of the third subregion are all higher than an average carrier concentration of the second subregion.

[0007] In some embodiments, the average carrier concentration of the second sub-region is between 60% and 80% of the average carrier concentration of the third sub-region.

[0008] In some embodiments, the average carrier concentration of the first sub-region is between 90% and 100% of the average carrier concentration of the third sub-region.

[0009] In some embodiments, the first sub-region and the third sub-region both contain dopants of a first conductivity type, the drift region contains dopants of a second conductivity type, the second sub-region contains dopants of the first conductivity type and dopants of the second conductivity type, and in the second sub-region, an average dopant concentration of the dopants of the second conductivity type is 20% to 40% of an average dopant concentration of the dopants of the first conductivity type.

[0010] In some embodiments, the distance between a centerline of the second subregion in the first direction and a sidewall of the gate insulator is in the range of 5 nm to 10 nm.

[0011] In some embodiments, the width of the second subregion in the second direction is 60% to 100% of the distance between a centerline of the second subregion in the first direction and a sidewall of the gate insulator.

[0012] In some embodiments, a dopant concentration increase region is present in the drift region at a position aligned with the second sub-region along the first direction, wherein an average dopant concentration of the second conductivity type dopant in the dopant concentration increase region is higher than an average dopant concentration of the second conductivity type dopant in the drift region.

[0013] In some embodiments, the substrate material of the body and drift regions is silicon carbide.

[0014] In some embodiments, the dimension of the gate insulator in the second direction is 2 to 5 times the dimension of the gate insulator in the first direction.

[0015] According to another aspect of the present application, there is provided a method for manufacturing a transistor device, the method including: providing an initial body region and a drift region stacked along a first direction; forming a gate trench in the initial body region and the drift region, the gate trench extending along the first direction from a surface of the initial body region away from the drift region, through the initial body region, and into the drift region; Injecting dopants into the initial body region by an ion implantation process to obtain a trench-buried body region, the trench-buried body region including a first sub-region, a second sub-region, and a third sub-region, the first sub-region, the second sub-region, and the third sub-region being sequentially arranged along a second direction, the second direction being perpendicular to the first direction and pointing away from the gate trench, and an average carrier concentration of the first sub-region and an average carrier concentration of the third sub-region being higher than an average carrier concentration of the second sub-region.

[0016] In some embodiments, implanting dopants into the initial body region by an ion implantation process to obtain a trench-filled body region includes implanting an ion beam including the dopant through the gate trench and into the initial body region in a direction that forms a non-zero angle with respect to the second direction.

[0017] In some embodiments, implanting the ion beam including the dopant through the gate trench and into the initial body region in a direction that forms a non-zero angle with respect to the second direction includes implanting the ion beam into the initial body region at different angles during at least two ion implantations.

[0018] In some embodiments, the angle between the ion beam and the second direction ranges from 30° to 60°.

[0019] In some embodiments, the temperature range for the ion implantation process is 500°C to 700°C.

[0020] In some embodiments, the substrate material of the initial body region and the drift region is silicon carbide; The method further includes performing a thermal oxidation process on the gate trench to form a silicon dioxide gate oxide on an inner wall of the gate trench.

[0021] In some embodiments, the method further includes annealing the trench-recessed body region at a temperature in the range of 1500° C. to 1700° C. after implanting dopants into the initial body region by an ion implantation process to obtain a trench-recessed body region. [Brief explanation of the drawings]

[0022] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly describes the drawings that need to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can further obtain other drawings based on these drawings without any creative efforts. [Figure 1] 1A and 1B illustrate schematic cross-sectional views of transistor devices according to embodiments of the present application; [Figure 2] 1A and 1B show schematic diagrams of input characteristic curves of a transistor device according to an embodiment of the present application and input characteristic curves of a related transistor device; [Figure 3] 3A and 3B illustrate schematic diagrams of carrier concentration distributions at various locations within a body region of a transistor device according to an embodiment of the present application. [Figure 4] 1A and 1B schematically illustrate enlarged partial cross-sectional views of transistor devices according to embodiments of the present application. [Figure 5] 1 illustrates a flow chart of a method for manufacturing a transistor device according to an embodiment of the present application. [Figure 6A] 1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; [Figure 6B] 1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; [Figure 6C] 1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; [Figure 6D]1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; [Figure 6E] 1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; [Figure 6F] 1A-1C show schematic diagrams of a transistor device at various stages in a method for fabricating the transistor device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0023] The technical solutions in the embodiments of the present application will be described below clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative efforts fall within the scope of protection of the present application.

[0024] In the drawings, specific embodiments of semiconductor devices and methods for manufacturing semiconductor devices are shown by way of example. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. For example, features illustrated or described in one embodiment may be used in or in conjunction with other embodiments to create yet further embodiments. The scope of the present application includes such modifications and variations.

[0025] It should be understood that the drawings are not to scale and are for illustrative purposes only and not for limitation.

[0026] Terms such as "have," "include," and "comprise" are open-ended. They indicate the presence of certain structures, elements, or features, but do not exclude the presence of other, additional structures, elements, or features. The article "a" does not exclude a plurality unless the context clearly indicates otherwise.

[0027] The gate insulator of a silicon carbide-based trench transistor can be obtained by thermally oxidizing the silicon carbide substrate material near the gate trench to silicon dioxide. The inventors discovered that residual carbon atoms during the thermal oxidation process create interface defects and interface states. Interface states are electrons trapped near the interface between silicon carbide and silicon dioxide. This causes strong interface scattering, particularly ionized impurity scattering, of trench carriers when the transistor device is in forward conduction. Ionized impurity scattering occurs when donor impurities ionize to positively charged ions and acceptor impurities ionize to negatively charged ions, creating a Coulomb potential field around the ionized donor or ionized acceptor. This Coulomb potential field locally disrupts the periodic potential field near the impurities. When carriers move near the ionized impurities, their speed and direction of movement change. As a result, the trench resistance of the transistor device becomes excessively large. For the same gate-source voltage, the resulting drain current is smaller.

[0028] According to one aspect of the present application, a transistor device is provided. FIG. 1 schematically illustrates a cross-sectional view of a transistor device according to one embodiment of the present application. As shown in FIG. 1 , the transistor device 100 includes a gate 105, a gate insulator 110, a body region 120, and a drift region 115 stacked along a first direction. The gate 105 includes opposing top and bottom surfaces 106 and 107, and a side surface 108 interposed between the top surface 106 and the bottom surface 107. The bottom surface 107 is in the first direction relative to the top surface 106. The gate insulator 110 surrounds at least a portion of the bottom surface 107 and the side surface 108 of the gate 105. The gate insulator 110 includes a sidewall 111 and a bottom 112. The body region 120 surrounds a portion of the sidewall 111 of the gate insulator 110. The gate insulator 110 extends along the first direction from a side of the drift region 115 facing the body region 120 into the drift region 115. The body region 120 includes a first sub-region 121, a second sub-region 122, and a third sub-region 123 arranged along a second direction. The second direction is perpendicular to the first direction and points away from the gate insulator 110. The average carrier concentration of the first sub-region 121 and the average carrier concentration of the third sub-region 123 are both higher than the average carrier concentration of the second sub-region 122.

[0029] The above configuration will be described in detail below. In a transistor device according to one embodiment of the present application, the body region 120 and the drift region 115 are stacked and arranged along a first direction. That is, the specific direction of the first direction is determined by the relative positions of the body region 120 and the drift region 115 within the transistor device 100. Both the body region 120 and the drift region 115 are part of the body of the transistor device, and both may be formed by doping a substrate material with different types and concentrations of impurities. In some embodiments, the substrate material may be silicon carbide. The impurity in the drift region 115 may be a group V element, such as nitrogen, at a concentration of 10 14 cm -3 From 10 16 cm-3 For example, the range is about 10 15 cm -3 The thickness of the drift region 115, i.e., the dimension of the drift region 115 in the first direction, is related to the voltage level. Generally, the higher the voltage level, the thicker the drift region 115. For example, if the voltage level of the transistor structure is 1200 V, the thickness of the drift region 115 may be 12 μm, and if the voltage level of the transistor structure is 1700 V, the thickness of the drift region 115 may be 17 μm. The transistor structure of the present application is intended for use in application scenarios of 650 V or higher, and therefore the thickness of the drift region 115 may be 6.5 μm or greater, at least 6.0 μm. The impurities in the body region 120 may include a group III element, such as aluminum, at a concentration of 3.5×10 16 cm -3 From 3.5 x 10 18 cm -3 The thickness of the body region 120 may range from 0.3 μm to 0.9 μm. The thickness of the body region 120 is independent of the thickness of the drift region 115. In some embodiments, the thickness of the body region 120 may range from 0.3 μm to 0.9 μm. For example, the thickness of the body region 120 may be approximately 0.6 μm.

[0030] The gate 105 includes a top surface 106, a bottom surface 107, and a side surface 108 sandwiched between the top surface and the bottom surface. A gate insulator 110 surrounds at least a portion of the bottom surface 107 and the side surface 108 of the gate 105, i.e., the top surface 106 of the gate 105 is exposed. Thus, the top surface 106 of the gate 105 can be used to connect to wiring (e.g., a gate line) of a control circuit and receive control signals. In some embodiments, the material of the gate 105 can be polysilicon.

[0031] The body region 120 surrounds a portion of the sidewall 111 of the gate insulator 110, and the gate insulator 110 extends along a first direction from the side of the drift region 115 facing the body region 120 into the drift region 115. Taking the viewing angle and orientation shown in FIG. 1 as an example, the above-mentioned feature can be understood as the gate insulator 110 (and the gate surrounded by it) traversing the entire body region 120 from top to bottom, and then continuing to extend downward into the drift region 115 after traversing the body region 120. The dimension of the gate insulator 110 along the first direction may be in the range of 0.7 μm to 1.3 μm. If the thickness of the body region 120 is 0.6 μm, the depth of the gate insulator 110 within the drift region 115 may be in the range of 0.1 μm to 0.7 μm.

[0032] When a control signal is applied to the gate 105, the body region near the gate insulator 110 undergoes inversion, forming trenches of the opposite conductivity type to the body region. For example, if the body region is P-type, applying a forward bias voltage to the gate forms N-type trenches in the body region on either side of the gate insulator 110, making the device conductive. The trenches are formed along the sidewalls of the gate insulator 110. The gate insulator 110 extends into the drift region 115, and the trenches also extend from the body region 120 into the drift region 115.

[0033] The body region 120 includes a first sub-region 121, a second sub-region 122, and a third sub-region 123 arranged in this order along a second direction. The second direction is perpendicular to the first direction. Taking the viewing angle and direction shown in FIG. 1 as an example, the first direction is the vertical direction, and the second direction is the horizontal direction. The second direction is away from the gate insulator 110. This can be understood as referring to a direction starting from the gate insulator 110 and moving away from the gate insulator 110. As shown in FIG. 1, any direction outward from the center line of the gate insulator 110 along the first direction (including leftward and rightward from the center line) is the second direction. The first sub-region 121, the second sub-region 122, and the third sub-region 123 are arranged along the second direction, i.e., horizontally, and of these three sub-regions, the first sub-region 121 is closest to the gate insulator 110, the second sub-region 122 is the next closest, and the third sub-region 123 is farthest from the gate insulator 110.

[0034] The average carrier concentration of the first sub-region 121 and the average carrier concentration of the third sub-region 123 are both higher than the average carrier concentration of the second sub-region 122. First, note that the "average carrier concentration" here refers to the average value of the carrier concentration in each sub-region in the body region when the transistor device is not powered. The above feature indicates that the concentration of carriers in the body region 120 first decreases and then increases along the second direction. By setting the carrier concentration in the body region in this way, a trench is formed in the second sub-region 122 after applying a control signal to the gate.

[0035] In the prior art, the carrier concentration in the body region of a transistor device is generally uniform throughout. When such a transistor device is in a forward conduction state, a trench is formed at the interface between the gate oxide (e.g., a material such as silicon dioxide) and the body region (e.g., a material such as silicon carbide). As described above, interface defects exist at the interface, causing interface states. When the transistor device is in a forward conduction state, trench carriers experience severe interface scattering. As a result, the trench resistance of the transistor device becomes excessively large.

[0036] In contrast, in the present application, the carrier concentration in the body region 120 first decreases and then increases in the direction away from the gate insulator, thereby shifting the location of the trench from the interface between the gate oxide 110 and the body region 120 to this region of reduced carrier concentration, i.e., the second sub-region 122. This avoids the problem of carrier interface scattering in the conductive state of the transistor device, thereby reducing the trench resistance and ultimately improving the performance of the silicon carbide MOSFET device.

[0037] FIG. 2 is a schematic diagram showing the input characteristic curve of a transistor device according to an embodiment of the present application and the input characteristic curve of a related transistor device. In FIG. 2, the dashed line shows the input characteristic curve of the related transistor device, and the solid line shows the input characteristic curve of the transistor device according to the embodiment of the present application. From FIG. 2, it can be seen that the transistor device according to the embodiment of the present application is an enhanced transistor device. Also, as shown in FIG. 2, the slope of the input characteristic curve of the transistor device according to the embodiment of the present application becomes larger after reaching the on-voltage. For the same gate-source voltage V GS In this case, the transistor device according to the present application has a higher drain current I D , which means it has a smaller trench resistance.

[0038] The average carrier concentration of each subregion can be determined and verified by spreading resistance measurements (SRP). FIG. 3 schematically illustrates the distribution of carrier concentration at various locations within the body region of a transistor device according to an embodiment of the present application. In FIG. 3, the horizontal axis represents the distance between the internal position of the body region 120, specifically the interface between the gate oxide 110 and the body region 120, and the corresponding location within the body region. The vertical axis represents carrier concentration. Reference numeral 221 can be understood as the range of the first subregion 121 in the second direction, reference numeral 222 can be understood as the range of the second subregion 122 in the second direction, and reference numeral 223 can be understood as the range of the third subregion 123 in the second direction. As can be seen from FIG. 3, the carrier concentration at various locations within the second subregion 122 is lower than both the carrier concentration at various locations within the first subregion 121 and the carrier concentration at various locations within the third subregion 123. Therefore, the average carrier concentration of the first sub-region 121 and the average carrier concentration of the third sub-region 123 are both higher than the average carrier concentration of the second sub-region 122 .

[0039] In some embodiments, the average carrier concentration of the second sub-region 122 is 60% to 80% of the average carrier concentration of the third sub-region 123. When the difference in average carrier concentration between the second sub-region 122 and the third sub-region 123 reaches this range, the trench can be effectively moved into the body region, avoiding the problem of a relatively large trench resistance caused by defects at the interface between the gate oxide and the body region.

[0040] To achieve the aforementioned average carrier concentration distribution within each subregion, in some embodiments, both the first subregion 121 and the third subregion 123 include dopants of a first conductivity type. The drift region 115 includes dopants of a second conductivity type. The second conductivity type is the opposite conductivity type to the first conductivity type. The second subregion 122 includes dopants of the first conductivity type and dopants of the second conductivity type. In a transistor device, the drift region and the body region are typically doped with dopants of different conductivity types. For example, in an N-trench vertical transistor device, the body region may be doped with P-type impurities and the drift region may be doped with N-type impurities. The first subregion 121, the second subregion 122, and the third subregion 123 all include dopants of the first conductivity type, and the second subregion 122 further includes dopants of the second conductivity type. The first-type carriers of the first-conductivity dopant and the second-type carriers of the second-conductivity dopant can combine to neutralize both carriers. For example, the first-conductivity dopant can be a Group III element whose carriers are holes, and the second-conductivity dopant can be a Group IV element whose carriers are electrons. When the second subregion is doped with both the first-conductivity dopant and the second-conductivity dopant, the electrons of the first-conductivity dopant and the holes of the second-conductivity dopant can form electron-hole pairs and enter a stable state in which they do not function as carriers. Therefore, the average carrier concentration in the second subregion decreases. That is, in the present application, the configuration of the average carrier concentration of each subregion according to the embodiments of the present application is achieved by implanting two types of conductivity dopants into the second subregion to neutralize each other.

[0041] In a more specific embodiment, the average dopant concentration of the second conductivity type dopant in the second sub-region is 20% to 40% of the average dopant concentration of the first conductivity type dopant, which can be understood as meaning that 20% to 40% of the carriers of the first conductivity type dopant are neutralized, resulting in an average carrier concentration in the second sub-region being reduced by 20% to 40% compared to the average carrier concentration in the unneutralized third sub-region, i.e., the average carrier concentration in the second sub-region is 60% to 80% of the average carrier concentration in the third sub-region.

[0042] In the embodiments of the present application, the reduction in the average carrier concentration occurs only in the second subregion, while the average carrier concentrations of the first and third subregions are preferably essentially unaffected. For example, in some embodiments, the average carrier concentration of the first subregion 121 is 90% to 100% of the average carrier concentration of the third subregion 123. This can be achieved using an ion implantation process. After implanting the second conductivity type dopant into the body region 120 using the ion implantation process, the concentration distribution of the second conductivity type dopant in the body region 120 exhibits a Gaussian distribution. That is, starting from the gate insulator 110, the concentration of the second conductivity type dopant first increases, reaches a peak, and then decreases. To achieve that the average carrier concentration of the first subregion and the average carrier concentration of the third subregion are both higher than the average carrier concentration of the second subregion, the concentration peak of the second conductivity type dopant must appear in the second subregion.

[0043] In some embodiments, the distance between the centerline of the second subregion 122 along the first direction and the sidewall of the gate insulator 110 is in the range of 5 nm to 10 nm. FIG. 4 schematically illustrates a magnified view of a portion of the transistor device of FIG. 1 . Specifically, FIG. 4 illustrates an enlarged view of the portion enclosed by the dashed line in FIG. 1 . The distance from the centerline of the second subregion 122 to the sidewall of the gate insulator 110 is indicated by an auxiliary line. By setting this distance in the range of 5 nm to 10 nm, the trench is appropriately shifted to avoid defects at the interface between the gate oxide and the body region and to maintain the trench within the effective control range of the electric field of the gate 105.

[0044] In some embodiments, the width of the second subregion 122 along the second direction is 60% to 100% of the distance from the centerline of the second subregion to the sidewall of the gate insulator 110. The term "width" can be understood to refer to the dimension of the second subregion in the second direction depending on the viewing angle of FIG. 1 . In embodiments of the present application, the width of the second subregion can be set based on the distance of its centerline to the gate insulator. For example, if the distance from the centerline of the second subregion to the sidewall of the gate insulator is a first distance, the extent of the second subregion in the second direction can extend from the centerline of the second subregion to both sides by 30% to 50% of the first distance. In a more specific embodiment, the extent of the second subregion can extend from the centerline of the second subregion to both sides by 40% of the first distance. For example, as described above, the distance from the centerline of the second subregion 122 to the sidewall of the gate insulator 110 can be 5 nm. In this example, the extent of the second subregion 122 can extend from the centerline to both sides by 2 nm. In this case, the width of the second sub-region 122 is 4 nm.

[0045] In some embodiments, a dopant concentration increase region 116 is present in the drift region 115 at a position aligned with the second sub-region 122 along the first direction. The average dopant concentration of the dopant of the second conductivity type in the dopant concentration increase region 116 is higher than the average dopant concentration of the dopant of the second conductivity type in the drift region 115. In transistor device 100, during forward conduction, a trench is not only present in the second sub-region of body region 120 but also extends into drift region 115, allowing current to flow along the trench from body region 120 into drift region 115. When dopants of the second conductivity type are implanted into second sub-region 122 by an ion implantation process, some of the dopants of the second conductivity type extend into drift region 115 and are aligned with second sub-region 122. The term "aligned" should be understood to mean that the orthogonal projection of the second sub-region 122 on the drain 140 at least partially overlaps with the orthogonal projection of the dopant concentration increased region 116 on the drain 140. As this portion of dopants of the second conductivity type is added into the drift region 115, the dopant concentration of the region where the newly added dopant of the second conductivity type is located increases, forming said dopant concentration increased region 116. The extent to which the dopant concentration increased region 116 extends into the drift region 115 is not limited by the present application.

[0046] In some embodiments, the dimension of the gate insulator 110 in the second direction is two to five times the dimension of the gate insulator 110 in the first direction. In a process for fabricating a transistor device according to embodiments of the present application, a gate trench is first formed in a stack of body region material and drift region material, and then an ion implantation process is performed to pass an ion beam through the gate trench and impinge on the sidewalls of the gate trench at an oblique angle to form the body region material in the first subregion, the second subregion, and the third subregion. The thickness of the gate insulator 110 is 1 nm to 100 nm, and the dimension of the gate insulator 110 in the first direction may reach 1 μm. That is, the thickness of the gate insulator 110 has very little effect on the dimension. Therefore, the feature "the thickness of the gate insulator 110 is two to five times the dimension of the gate insulator 110 in the second direction" can be understood to mean that the dimension of the gate trench in the second direction is two to five times the dimension of the gate insulator 110 in the first direction. Such dimensioning of the gate trench provides a larger adjustment space for the ion beam tilt angle of the aforementioned ion implantation process, which is advantageous for better control over the average carrier concentrations of the first sub-region, the second sub-region, and the third sub-region.

[0047] 1, the transistor device further includes a source 130, a drain 140, and a heavily doped source region 135 located on the side of the body region 120 away from the drift region 115. The body region 120 may include a thin region relatively close to the gate 105 and a thick region further away from the gate 105. The heavily doped source region 135 is located on the thin region. The dopant of the heavily doped source region 135 is the same as the dopant of the second conductivity type implanted in the second sub-region 122 of the body region 120, and may be, for example, a group V element such as nitrogen. The dopant concentration should be at least one order of magnitude higher than the dopant of the second conductivity type in the second sub-region 122, for example, 10 19 cm -3 From 1020 cm -3 1, the source 130 covers both the body region 120 and the heavily doped source region 135. The source 130 may be a stack of multiple metal materials. For example, the source electrode may include a titanium layer, a nickel layer, and an aluminum layer in a direction opposite the first direction. The nickel and titanium elements may enhance the ohmic contact between the aluminum layer and the silicon carbide semiconductor body and reduce the work function. The thickness of the source may range from 4 μm to 8 μm. In some embodiments, the thickness of the source electrode may be 5 μm. The drift region 115, the body region 120, and the heavily doped source region 135 together comprise the semiconductor body of the transistor structure.

[0048] As described above, in the transistor device according to the embodiment of the present application, the carrier concentration in the body region first decreases and then increases in the direction away from the gate, so that when the transistor device is conducting in the forward direction, the trench is spaced a certain distance from the interface between the gate insulator and the body region, thereby avoiding the interface scattering problem faced by trench carriers, reducing the trench resistance, and improving the performance of the transistor device.

[0049] According to another aspect of the present application, there is also provided a method for manufacturing a transistor device. By this method, a transistor device according to any of the embodiments of the present application can be obtained. The method for manufacturing the transistor device will now be described.

[0050] Figure 5 is a flow chart illustrating a method for manufacturing a transistor device according to an embodiment of the present application. Figures 6A to 6F are schematic diagrams illustrating the configuration of a transistor device at each stage of a method for manufacturing a transistor device according to an embodiment of the present application.

[0051] As shown in FIG. 5, the method includes:

[0052] In step S505, an initial body region and a drift region are prepared, stacked along a first direction.

[0053] In step S510, a gate trench is formed in the initial body region and the drift region, wherein the gate trench extends along a first direction from a surface of the initial body region away from the drift region, through the initial body region, and into the drift region.

[0054] In step S515, dopants are implanted into the initial body region by an ion implantation process to obtain a trench-filled body region, where the trench-filled body region includes a first sub-region, a second sub-region, and a third sub-region, the first sub-region, the second sub-region, and the third sub-region are sequentially arranged along a second direction, the second direction is perpendicular to the first direction and points away from the gate trench, and the average carrier concentration of the first sub-region and the average carrier concentration of the third sub-region are both higher than the average carrier concentration of the second sub-region.

[0055] Each step will be explained below. First, an initial body region and a drift region are prepared, stacked along a first direction (step S505). The carrier concentration in each portion of the initial body region is substantially the same. In actual manufacturing, a semiconductor substrate is first prepared, and then an epitaxial layer, i.e., the drift region, can be grown thereon. The drift region may have a relatively low concentration of N-type impurities. The N-type impurities may be a group V element, such as nitrogen. Next, P-type impurities may be implanted into the drift region using an ion implantation process to obtain a body region. The P-type impurities may be a group III element, such as aluminum. As shown in FIG. 6A, the initial body region 620 and the drift region 615 are stacked along a first direction.

[0056] Next, a gate trench 605 is formed in the initial body region and the drift region (step S510). As shown in FIG. 6B, in this step, the gate trench 605 extends along the first direction from a surface of the initial body region 620 away from the drift region 615 through the initial body region 620 and into the drift region 615. This step can be performed using an etching method. Note that the process of obtaining the gate trench by etching should not affect the impurity concentrations in the initial body region and the drift region. During etching, the gate trench should extend through the entire initial body region and into the drift region. The width of the gate trench may be at least 3 μm, for example, in the range of 3 μm to 5 μm, or even up to 10 μm.

[0057] In some embodiments, the cross-sectional shape of the gate trench may be rectangular, as shown in FIG. 6B. In other embodiments, the cross-sectional shape of the gate trench may be an inverted trapezoid or a V-shape. That is, the width of the bottom of the gate trench is smaller than the width of its top. In some embodiments, the gate trench has a rounded chamfer between the sidewalls and bottom, which can provide a breakdown prevention effect.

[0058] After forming the gate trench, dopants can be implanted into the initial body region by an ion implantation process (step S515) to obtain a trench-filled body region. As shown in FIG. 6C, the trench-filled body region 625 includes a first sub-region 621, a second sub-region 622, and a third sub-region 623. The first sub-region 621, the second sub-region 622, and the third sub-region 623 are sequentially arranged along a second direction, which is perpendicular to the first direction and points away from the gate trench 605. The average carrier concentration of the first sub-region 621 and the average carrier concentration of the third sub-region 623 are both higher than the average carrier concentration of the second sub-region 622. The term "trench-filled region" should be understood to mean the structure that the initial body region forms after dopants are implanted. The conductivity characteristics of the implanted dopants should be opposite to the conductivity characteristics of the existing dopants in the initial body region. As can be understood from the above characteristics, in this step, the ion implantation process must achieve the effect that the average carrier concentration in the trench filling region first decreases and then increases in the direction away from the gate trench. Therefore, in a transistor device manufactured by this method, the trench is spaced a certain distance from the interface between the gate insulator and the body region during forward conduction, thereby avoiding the interface scattering problem faced by trench carriers, reducing trench resistance, and improving the performance of the transistor device, and achieving the various excellent effects mentioned above. During the ion implantation process, some ions may penetrate into the drift region 615, but the specific extent of penetration is not limited.

[0059] In some embodiments, the temperature of the ion implantation process ranges from 500°C to 700°C because silicon carbide substrate material requires ion implantation in a high-temperature environment. The ion implantation dose may be such that the average carrier concentration of the second subregion 622 is about 60% to 80% of the average carrier concentration of the initial body region. The position of the second subregion 622 relative to the sidewall of the gate trench 605 and the width of the second subregion 622 along the second direction have already been described above and will not be repeated here.

[0060] In a more specific embodiment, step S515 may specifically include implanting an ion beam containing the dopant through the gate trench 605 into the initial body region in a direction that forms a non-zero angle with respect to the second direction. As shown in FIG. 6C , the direction of the ion beam forms a non-zero angle with respect to the second direction. The ion beam is obliquely implanted into the gate trench 605 and strikes the sidewalls and bottom of the gate trench, resulting in the doping element penetrating into the initial body region and drift region.

[0061] To improve the ion implantation effect and achieve a more uniform impurity concentration in the second subregion, a multiple-stage implantation method can be used. For example, "implanting the ion beam containing the dopant through the gate trench into the initial body region in a direction that forms a non-zero angle with respect to the second direction" may specifically include implanting the ion beam into the initial body region at different angles in at least two ion implantation processes. In multiple implantations, the ion beam implantation angle may be different for each implantation. When the angle between the ion beam and the second direction is small, the ion beam mainly strikes the upper portion of the gate trench sidewalls. When the angle between the ion beam and the second direction is large, the ion beam mainly strikes the lower portion of the gate trench sidewalls and the bottom of the gate trench. The number and angle of ion implantation are related to the aspect ratio of the gate trench. The smaller the aspect ratio of the gate trench, the deeper the gate trench will be, and the more ion implantation times may be required. In some embodiments, the angle between the ion beam and the second direction may be a minimum of 30° and a maximum of 60°. For example, in a first ion implantation, the angle between the ion beam and the second direction may be 30°, and in a second ion implantation, the angle between the ion beam and the second direction may be 60°. In some embodiments, three or more ion implantations may be required to achieve a better ion implantation effect.

[0062] After the ion implantation process, the semiconductor body can be annealed. Specifically, a method for manufacturing a transistor device according to an embodiment of the present application further includes annealing the trench-buried body region at a temperature ranging from 1500°C to 1700°C after implanting dopants into the initial body region through the ion implantation process to obtain a trench-buried body region. The annealing can repair lattice damage and migrate impurity atoms to lattice sites and activate them. If the substrate material is silicon carbide, a higher annealing temperature is required. In some embodiments, the annealing effect can be ensured by setting the annealing temperature in the range from 1500°C to 1700°C.

[0063] After forming the trench fill region and ensuring that the average carrier concentration of each subregion satisfies the above requirements, a gate oxide can be formed. Specifically, when the substrate material is silicon carbide, the method further includes performing a thermal oxidation process on the gate trench 605 to form a silicon dioxide gate oxide on the inner wall of the gate trench. As shown in FIG. 6D, performing the thermal oxidation process on the gate trench 605 supplies oxygen to the silicon carbide substrate, and the oxygen atoms and carbon atoms in the silicon carbide substrate form a silicon dioxide gate oxide 610, whose thickness is in the range of 1 nm to 100 nm.

[0064] Next, as shown in Figure 6E, a gate 606 is formed in the gate trench 605. The gate material may be polysilicon. Specifically, the gate can be formed by depositing and etching a polysilicon material.

[0065] Next, as shown in FIG. 6F, a heavily doped source region 635 can be formed in the trench-buried body region 625. Specifically, ions can be implanted into the trench-buried body region 625, and the implanted ions are the same as the ions implanted in the process of forming the second sub-region 622 described above. For example, if nitrogen ions are implanted into the initial body region in the ion implantation process of step S515, nitrogen ions must also be implanted in the process of forming the heavily doped source region. The ion concentration in the process of forming the heavily doped source region must be higher. For example, the impurity concentration of the heavily doped source region can be 10 19 cm -3 From 10 20 cm -3 The above steps result in a semiconductor body having a drift region, a body region, a gate insulator, a gate, and a heavily doped source region, and the carrier concentration in the body region first decreases and then increases along a direction away from the gate insulator.

[0066] A source and a drain can then be formed on the resulting semiconductor body to obtain a transistor device according to an embodiment of the present application as shown in Figure 1. Formation of the source and drain can be achieved by depositing a metal material and etching a pattern.

[0067] The transistor device fabricated by the above method has the various advantages previously described for the transistor device according to the embodiments of the present application, which will not be repeated here.

[0068] For clarity and ease of understanding, the examples in this application are primarily directed to N-trench transistor devices, but the application is equally applicable to P-trench transistor devices, provided that the dopant types and concentrations are adjusted accordingly.

[0069] As will be understood by those skilled in the art, although the steps of the methods in the examples of the present application are shown in the figures in a particular order, this does not require or imply that the steps must be performed in a particular order unless the context clearly dictates otherwise. Additionally or alternatively, multiple steps may be combined and performed as a single step, and / or a single step may be decomposed and performed as multiple steps. Furthermore, other method steps may be inserted between steps. The inserted steps may represent improvements to the methods as described herein or may be unrelated to the methods. Furthermore, a given step need not be fully completed before the next step begins.

[0070] In describing the embodiments of the present application, the orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the drawings and are intended merely to facilitate the description of the embodiments of the present application. They do not require the embodiments of the present application to be configured or operated in any particular orientation, and therefore should not be understood as limiting the present application.

[0071] In the description herein, references to terms such as "one embodiment," "another embodiment," and the like mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present application. In this specification, general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine different embodiments or examples described herein and features of different embodiments or examples without contradicting each other. Furthermore, please note that terms such as "first," "second," and the like are used for descriptive purposes only and should not be understood as indicating or implying relative importance or the number of technical features described.

[0072] The above description is merely a specific example of the present application, and the scope of protection of the present application is not limited thereto. Those skilled in the art can easily think of modifications or substitutions within the technical scope disclosed in the present application, all of which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be governed by the scope of protection of the claims.

Claims

1. a gate, a gate insulator, and a body region and a drift region stacked along a first direction; the gate includes opposing top and bottom surfaces and a side surface interposed between the top surface and the bottom surface, the bottom surface being in the first direction of the top surface; the gate insulator surrounds at least a portion of the bottom surface and the side surface of the gate; the gate insulator includes sidewalls and a bottom; the body region surrounds a portion of the sidewall of the gate insulator; and the gate insulator extends along the first direction from a surface of the drift region facing the body region into the drift region; the body region includes a first sub-region, a second sub-region, and a third sub-region arranged in sequence along a second direction, the second direction being perpendicular to the first direction and pointing away from the gate insulator, and an average carrier concentration of the first sub-region and an average carrier concentration of the third sub-region both being higher than an average carrier concentration of the second sub-region; a distance between a center line of the second sub-region along the first direction and a sidewall of the gate insulator is in the range of 5 nm to 10 nm; Transistor device.

2. the average carrier concentration of the second sub-region is 60% to 80% of the average carrier concentration of the third sub-region; The transistor device of claim 1 .

3. the average carrier concentration of the first sub-region is 90% to 100% of the average carrier concentration of the third sub-region; The transistor device of claim 2 .

4. the first sub-region and the third sub-region both include dopants of a first conductivity type, the drift region includes dopants of a second conductivity type, the second sub-region includes dopants of the first conductivity type and dopants of the second conductivity type; and In the second sub-region, the average dopant concentration of the dopant of the second conductivity type is 20% to 40% of the average dopant concentration of the dopant of the first conductivity type. The transistor device of claim 2 .

5. a width of the second subregion along the second direction that is 60% to 100% of a distance between a centerline of the second subregion along the first direction and a sidewall of the gate insulator; The transistor device of claim 1 .

6. a dopant concentration increasing region is present in the drift region at a position aligned with the second sub-region along the first direction, wherein an average dopant concentration of the second conductivity type dopant in the dopant concentration increasing region is higher than an average dopant concentration of the second conductivity type dopant in the drift region; The transistor device of claim 4 .

7. the substrate material of the body region and the drift region is silicon carbide; The transistor device of claim 1 .

8. a dimension of the gate insulator in the second direction that is 2 to 5 times the dimension of the gate insulator in the first direction; The transistor device of claim 1 .

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