Power diode and method for manufacturing a power diode

Abstract

A power diode (1) is provided, comprising a wafer having a cathode side (4) and an anode side (5) opposite the cathode side (4), a base layer (2) of a first conductivity type, an anode region (6) of a second conductivity type different from the first conductivity type provided on the anode side of the wafer, and a termination region (7) provided between the cathode side (4) and the anode side (5) of the wafer, the termination region (7) laterally surrounding the anode region (6), the termination region (7) comprising a first pocket (8) of a second conductivity type and at least two second pockets (9) of the second conductivity type, the first pocket (8) being laterally located between the anode region (6) and the at least two second pockets (9), the first pocket (8) having a first maximum doping concentration less than a second maximum doping concentration of each of the at least two second pockets (9). Further, a method for manufacturing the power diode (1) is provided.

Description

[Background technology]

[0001] US Patent Application Publication No. 2015 / 0303268 relates to a diode and a power conversion device. US Patent Application Publication No. 2020 / 0295178 relates to a semiconductor device and a method for manufacturing a semiconductor device. JP 2000114550 A relates to a diode and a power converter. Summary of the Invention [Problem to be solved by the invention]

[0002] SUMMARY OF THE INVENTION An embodiment of the present disclosure relates to a power diode having improved efficiency. Further embodiments of the present disclosure relate to a method for manufacturing a power diode. [Means for solving the problem]

[0003] This is achieved by the subject matter of the independent claims. Further embodiments are evident from the dependent claims in the following description.

[0004] A first aspect relates to a power diode. Here and hereinafter, the term "power" refers to a power diode for handling voltages, for example, above 100 volts, illustratively above 1000 volts.

[0005] According to an embodiment of the first aspect, a power diode includes a wafer having a cathode side and an anode side opposite the cathode side, the wafer having a base layer of a first conductivity type. For example, the wafer, illustratively the base layer, includes or is made of a semiconductor material. The semiconductor material is illustratively based on a wide bandgap material such as silicon or silicon carbide (SiC). The first conductivity type is, for example, an n-type. For example, the base layer includes a dopant, and the dopant is an n-type dopant.

[0006] The maximum doping concentration of the base layer is, for example, 5×1012 cm -3 5x10 or more 14 cm -3 Illustratively, the base layer has a uniform doping concentration.

[0007] The base layer may have, for example, a plane of primary stretching, with the transverse direction aligned parallel to the plane of primary stretching and the vertical direction aligned perpendicular to the plane of primary stretching.

[0008] Furthermore, the base layer has a first major surface facing the anode side and a second major surface facing the cathode side.

[0009] For example, the power diode includes a buffer layer of a first conductivity type disposed on the second major surface of the base layer. For example, the buffer layer includes or consists of a semiconductor material, which may be silicon-based. Illustratively, the semiconductor material of the base layer and the semiconductor material of the buffer layer are the same. For example, the buffer layer includes an additional dopant.

[0010] For example, the maximum doping concentration of the buffer layer is higher than the maximum doping concentration of the base layer, for example, at least one order of magnitude higher than the maximum doping concentration of the base layer.

[0011] For example, the buffer layer is configured to be in electrical contact with the cathode electrode. For example, the cathode electrode includes or is made of a metal. In this case, the cathode electrode is formed from a metal layer that directly contacts the buffer layer. For example, the cathode electrode completely covers the buffer layer on the second main surface. The cathode electrode is exemplarily configured to be in contact with the outside.

[0012] According to an embodiment of the first aspect, the power diode includes an anode region of a second conductivity type different from the first conductivity type provided on the anode-side wafer. For example, the anode region, i.e., the upper surface of the anode region, terminates flush with the second main surface of the base layer. That is, illustratively, the anode region does not protrude beyond the second main surface of the base layer in the vertical direction.

[0013] The second conductivity type is illustratively p-conductivity type, for example, the anode region includes a dopant, and the dopant is a p-type dopant.

[0014] For example, the anode region is configured to be in electrical contact with the anode electrode. For example, the anode electrode includes or consists of a metal. In this case, the anode electrode is formed of a metal layer that directly contacts the anode region. For example, the anode electrode does not protrude beyond the anode region in the lateral direction. The anode electrode is exemplarily configured to be able to contact the outside.

[0015] According to an embodiment of the first aspect, the power diode includes a termination region disposed between the cathode side and the anode side of the wafer. Exemplarily, the termination region extends from the cathode side to the anode side. For example, the termination region, i.e., the top surface of the termination region, terminates flush with the second main surface of the base layer.

[0016] According to an embodiment of the first aspect, the termination region laterally surrounds the anode region, i.e., the termination region and the anode region do not overlap each other in a lateral plan view, where "plan view" corresponds to a vertical direction, e.g., facing the anode side.

[0017] According to an embodiment of the first aspect, the termination region includes a first pocket of a second conductivity type and at least two second pockets of the second conductivity type. For example, the first pocket extends into the wafer from the anode side toward the cathode side. Similarly, the at least two second pockets extend into the wafer from the anode side toward the cathode side. For example, the first pocket and the second pocket are each spaced apart from the cathode side. The first pocket and the at least two second pockets, i.e., their upper surfaces, illustratively terminate flush with the second main surface of the base layer.

[0018] According to an embodiment of the first aspect, the first pocket is arranged laterally between the anode region and the at least two second pockets.

[0019] According to an embodiment of the first aspect, the first pocket has a first maximum doping concentration that is less than a second maximum doping concentration of each of the at least two second pockets.

[0020] For example, the first maximum doping concentration is 5×10 15 cm -3 5x10 or more 18 cm -3 The second maximum doping concentration is, for example, 5×10 15 cm -3 More than 1×10 19 cm -3 The following is the result.

[0021] For example, in the off state, the power diode blocks an applied voltage applied perpendicularly between the first and second major surfaces.

[0022] However, at the edge regions of the power diode, stray electric fields may appear and cause undesired breakdown. For example, the termination region causes the stray electric fields to attenuate laterally from the anode region to the edge region of the power diode.

[0023] The first pocket can further reduce this electric field, reduce power dissipation, and reduce the width of the termination region while keeping the applied voltage off.

[0024] According to at least one embodiment of the power diode, the at least two second pockets are laterally spaced apart from one another. Illustratively, the at least two second pockets do not directly contact one another and do not overlap one another in a lateral plan view.

[0025] According to at least one embodiment of the power diode, the first pocket and the at least two second pockets are laterally spaced apart from one another, i.e., illustratively, the first pocket and an immediately adjacent second pocket do not directly contact one another and do not overlap one another in a lateral plan view.

[0026] According to at least one embodiment of the power diode, the first pocket and the at least two second pockets each completely surround the anode region laterally.

[0027] The first pocket and the at least two second pockets surround the anode region in a frame-like manner, which means here and hereinafter that the first pocket and the at least two second pockets completely surround the anode region laterally and independently form their shape.

[0028] The anode region may have a polygonal shape, such as an oval, circle, or rectangle, in plan view. In the case of a polygonal shape, the edges of the polygon may be rounded. The shapes of the first pocket and the at least two second pockets may be the same. The diameter or edge length of the shape may illustratively increase from the first pocket to the second pocket outside the second pocket.

[0029] According to at least one embodiment of the power diode, the anode region and the at least two second pockets each include a first doped region and a second doped region. For example, the first doped region includes a first dopant, and the second doped region includes a second dopant. For example, the first dopant and the second dopant are the same. The first dopant and the second dopant are illustratively p-type dopants.

[0030] According to at least one embodiment of the power diode, the maximum doping concentration of the first doped region is greater than the maximum doping concentration of the second doped region, and illustratively the maximum doping concentration of the first doped region is equal to the first maximum doping concentration, and the maximum doping concentration of the second doped region is equal to the second maximum doping concentration.

[0031] According to at least one embodiment of the power diode, the first doped region extends vertically from the anode side to a first depth within the wafer, e.g., the first doped region extends vertically from the anode side of the base layer toward the cathode side, and the first doped region is spaced apart on the cathode side.

[0032] For example, the first depth is not less than 5 μm and not more than 15 μm. According to at least one embodiment of the power diode, the second doped region extends vertically from the anode side to a second depth within the wafer, e.g., the second doped region extends vertically in a direction from the anode side to the cathode side, and the second doped region is spaced apart on the cathode side.

[0033] For example, the second depth is 2 μm or less. In at least one embodiment of the power diode, the first depth is greater than the second depth. For example, the width of the first doped region is greater than the width of the second doped region in the lateral direction. That is, the second doped region is illustratively buried in the first doped region. Here and hereinafter, buried means that the outer surface of the second doped region facing the base layer is completely covered by the first doped region.

[0034] According to at least one embodiment of the power diode, the width of the anode region is greater in the lateral direction than the width of the first pocket and greater than the width of each of the at least two second pockets, each width being defined by the minimum extent of the corresponding element in the lateral direction.

[0035] For example, the width of the first pocket is 25% or less of the width of the anode region. According to at least one embodiment of the power diode, the width of the first pocket is greater in the lateral direction than the width of each of the at least two second pockets.

[0036] For example, the width of the at least two second pockets is 25% or less of the width of the first pocket.

[0037] According to at least one embodiment of the power diode, the power diode further comprises a cathode electrode and an anode electrode, the cathode electrode being provided on the wafer from the cathode side and the anode electrode being provided on the anode region.

[0038] According to at least one embodiment of the power diode, the anode electrode completely overlaps the second doped region of the anode region in a plan view and is in direct contact with the second doped region of the anode region.

[0039] According to at least one embodiment of the power diode, the first maximum doping concentration of the first pocket is at least one order of magnitude less than the second maximum doping concentration of each of the at least two second pockets.

[0040] A second aspect relates to a method for manufacturing a power diode. Illustratively, the method manufactures the power diode described hereinabove. Accordingly, all features disclosed in relation to the power diode are also disclosed in relation to the method, and vice versa.

[0041] According to an embodiment of the second aspect of the method, a base layer of a first conductivity type different from the second conductivity type is provided.

[0042] For example, a buffer layer of a first conductivity type is formed from the cathode side. According to an embodiment of the second aspect of the method, an anode region pocket and at least three zones are created by introducing a first dopant of a second conductivity type into the wafer from the anode side, such that each zone has a first maximum doping concentration in the wafer.

[0043] The first dopant may be incorporated onto or into the wafer, eg, the base layer, eg, by at least one of an ion implantation or a deposition process, followed by a diffusion process.

[0044] According to an embodiment of the second aspect of the method, a second dopant of a second conductivity type is introduced into the anode region pocket and the at least three zones such that an anode region and at least two second pockets having a second maximum doping concentration are created.

[0045] The second dopant may be incorporated onto or into the wafer, eg, the base layer, by at least one of an ion implantation or a deposition process, followed by a diffusion process.

[0046] According to an embodiment of the second aspect of the method, the zone into which the second dopant is not introduced is disposed between the anode region and the at least two second pockets, forming a first pocket.

[0047] According to an embodiment of the second aspect of the method, the first maximum doping concentration is less than the second maximum doping concentration.

[0048] According to at least one embodiment of the method, a first mask having at least four openings is applied to the anode side before introducing the first dopant, for example, one opening having a shape corresponding to the anode region to be produced, another opening having a shape corresponding to the first pocket to be produced, and another opening having a shape corresponding to the second pocket to be produced.

[0049] According to at least one embodiment of the method, a second mask having a smaller opening than the first mask is applied to the first mask before introducing the second dopant, the second mask covering the zone closest to the anode region pocket. That is, the anode region and at least two second pockets each comprise a first doped region and a second doped region, e.g., having a first maximum doping concentration of the first dopant and a second maximum doping concentration of the second dopant. The first pocket illustratively comprises only the first doped region having the first dopant.

[0050] According to at least one embodiment of the method, the first mask is an oxide mask. According to at least one embodiment of the method, the first mask is removed after creating the anode region and the at least two second pockets, e.g., the first mask and the second mask are removed after creating the anode region and the at least two second pockets.

[0051] According to at least one embodiment of the method, the cathode and anode electrodes are fabricated after creation of the anode region and the at least two second pockets.

[0052] Embodiments will now be described in more detail with reference to exemplary embodiments as illustrated in the accompanying drawings. [Brief explanation of the drawings]

[0053] [Figure 1] 1A and 1B schematically illustrate cross-sectional views of power diodes according to exemplary embodiments; [Figure 2] 1A and 1B schematically illustrate a plan view of a power diode according to an exemplary embodiment; [Figure 3] 3A and 3B illustrate schematic diagrams of doping concentrations of an exemplary power diode and a termination region of the power diode according to an exemplary embodiment. [Figure 4]3A and 3B illustrate schematic diagrams of an exemplary power diode and peak current density during switching of the power diode according to exemplary embodiments. [Figure 5] 1A and 1B illustrate schematic diagrams of an exemplary power diode and peak electric fields during switching of the power diode according to exemplary embodiments. [Figure 6] FIG. 2 is a diagram illustrating an example power diode and the power density of the power diode according to an example embodiment. [Figure 7] 1A and 1B illustrate schematic diagrams of an exemplary power diode and dynamic power dissipation of the power diode in accordance with exemplary embodiments. [Figure 8] 3A-3C illustrate schematically method steps of a method for manufacturing a power diode according to an exemplary embodiment; [Figure 9] 3A-3C illustrate schematically method steps of a method for manufacturing a power diode according to an exemplary embodiment; [Figure 10] 3A-3C illustrate schematically method steps of a method for manufacturing a power diode according to an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0054] The reference signs used in the drawings and their meanings are listed in summary form in the list of reference signs. As a rule, identical parts are provided with the same reference signs in the figures.

[0055] The power diode 1 comprises a wafer, for example a semiconductor body, having an anode side 5 and a cathode side 4 opposite the anode side 5. The wafer comprises a base layer 2 of a first conductivity type. Furthermore, the base layer 2 has a first main surface facing the anode side 5 and a second main surface facing the cathode side 4. For example, the semiconductor body further comprises a buffer layer 3 of the first conductivity type provided on the cathode side 4 of the semiconductor body and electrically connected to the second main surface of the base layer 2.

[0056] Both the buffer layer 3 and the base layer 2 contain n-type dopants, and therefore the first conductivity type is n-type. The maximum doping concentration of the buffer layer 3 is higher than the maximum doping concentration of the base layer 2.

[0057] Furthermore, the power diode 1 includes a cathode electrode 10 provided from the cathode side 4.

[0058] On the anode side 5, the wafer is provided with an anode region 6 of a second conductivity type different from the first conductivity type. The anode region 6 comprises a first doped region 15 extending vertically into the wafer from the anode side 5 to a first depth, and a second doped region 16 extending vertically into the wafer from the anode side 5 to a second depth, the first depth being greater than the second depth.

[0059] Furthermore, the width of the first doped region 15 of the anode region 6 is greater than the width of the second doped region 16 of the anode region 6. The upper surface of the first doped region 15 of the anode region 6, facing outward from the base layer 2, and the upper surface of the second doped region 16 of the anode region 6, are coplanar with each other. Furthermore, the upper surface and the second major surface of the base layer 2, facing outward from the buffer layer 3, are coplanar with each other. That is, the upper surface and the second major surface lie in a common plane extending laterally.

[0060] Both the first doped region 15 and the second doped region 16 contain p-type dopants, and therefore the second conductivity type is p-type. The first maximum doping concentration of the first doped region 15 is less than the second maximum doping concentration of the second doped region 16. For example, the maximum doping concentration of the first doped region 15 is at least one order of magnitude less than the second maximum doping concentration of the second doped region 16.

[0061] For example, the first maximum doping concentration is 5×10 15 cm -3 ~5×10 18 cm -3 and the second maximum doping concentration is 5×10 16 cm-3 ~5×10 19 cm -3 is included between.

[0062] An anode electrode 11 is provided on the first main surface 5 side of the anode region 6. The anode electrode 11 does not protrude beyond the anode region 6 in the lateral direction. The anode electrode 11 is in direct electrical contact with the second doped region 16 of the anode region 6, but is not in electrical contact with the second doped region 16 of the termination region 7.

[0063] Furthermore, the anode electrode 11 completely overlaps laterally with the second doped region 16 of the anode region 6. Here, the second doped region 16 protrudes beyond the anode electrode 11 in the lateral direction.

[0064] Alternatively, the anode electrode 11 can project laterally beyond the second doped region 16 of the anode region 6 so that the anode electrode 11 completely covers the top surface of the second doped region 16 .

[0065] The power diode 1 further comprises a termination region 7 disposed within the wafer from the anode side 5. The termination region 7 comprises a first pocket 8 of a second conductivity type and two second pockets 9 of the second conductivity type. The first pocket 8 comprises only a first doping region 15 having a first maximum doping concentration extending vertically to a first depth. The two second pockets 9 each comprise a first doping region 15 having a first maximum doping concentration also extending vertically to the first depth, and a second doping region 16 having a second maximum doping concentration extending vertically to a second depth. That is, the first maximum doping concentration of the first pocket 8 is less than the second maximum doping concentration of each of the two second pockets 9.

[0066] The width of each of the first doped regions 15 of the two second pockets 9 is greater than the width of the second doped regions 16 of the two second pockets 9. Furthermore, the upper surfaces of the first doped regions 15 of the first pocket 8 and the two second pockets 9 and the upper surfaces of the second doped regions 16 of the two second pockets 9 terminate in the same plane as each other. Furthermore, the upper surface and the second main surface of the base layer 2 terminate in the same plane as each other.

[0067] In the lateral direction, the first pocket 8 is provided between the anode region 6 and the two second pockets 9. Furthermore, the first pocket 8, the two second pockets 9, and the anode region 6 are spaced apart from one another in the lateral direction.

[0068] The first pocket 8 is also referred to as a resistive region because it serves to reduce the peak electric field and peak current density in the region of the first pocket 8 .

[0069] The termination region 7 completely surrounds the anode region 6 laterally, according to Figure 2. The first pocket 8 and the two second pockets 9 completely surround the anode region 6 in a frame-like manner.

[0070] The doping concentration [cm ] shown at the top of Fig. 3 -3 ] represents an exemplary power diode. The exemplary power diode comprises a termination region 7, which comprises only the second pocket 9 having a first doped region 15 and a second doped region 16.

[0071] In contrast, the termination area 7 [cm ] of the power diode 1 according to the exemplary embodiment shown in the bottom of FIG. -3 ] comprises a first pocket 8. The first pocket 8 comprises only a first doped region 15. The width of the first doped pocket is greater in the lateral direction than the width of each of the second pockets 9. The distance between the second pockets 9 can be increased toward the edges of the power diode 1.

[0072] In the diagram according to FIG. 4, the peak current density J [kA / cm 2 ] during switching from the on-state to the off-state of a power diode 1 having a doping concentration according to FIG. 3 at the level of the second main surface 2 ]. The x-axis corresponds to the lateral extension shown in FIG. 3. A first curve K1 corresponds to the doping concentration of the exemplary power diode 1 shown in particular in the upper part of FIG. 3. A second curve K2 corresponds to the doping concentration of the power diode according to the exemplary embodiment shown in particular in the lower part of FIG. 3.

[0073] In the diagram according to FIG. 5, the peak electric field E [V / cm] corresponding to the peak current density J in FIG. 4 is shown.

[0074] The diagram in FIG. 6 shows the power density P [kW / cm ] corresponding to the diagrams in FIGS. 4 and 5. 2 ] is shown.

[0075] The power dissipation [kW / cm ] shown at the top of Fig. 7 2 ] represents an exemplary power diode according to an exemplary power diode according to FIG.

[0076] In contrast, the power dissipation shown in the lower part of FIG. 7 represents a power diode 1 according to an exemplary embodiment, for example, as shown in the lower part of FIG.

[0077] The power dissipation according to FIG. 7 corresponds to the power dissipation in the diagram of FIG. The method for manufacturing the power diode 1 according to Figures 8, 9 and 10 includes applying a first mask 13 to the second main surface of the base layer 2. The first mask 13 has four openings 14.

[0078] 8, the anode region pocket 12 and three zones are created by introducing a first dopant of a second conductivity type having a first maximum doping concentration into the base layer 2 from a first major surface of the base layer 2 opposite the second major surface. That is, the first dopant is introduced to a first depth through an opening 14 in a first mask 13 in the base layer 2. This results in the anode region pocket 12 and three zones having the first maximum doping concentration.

[0079] Depending on the process of introducing the first dopant, the concentration of the first dopant may decrease continuously in the direction of the cathode side 4, i.e., the first maximum doping concentration is located near the top surface of the respective zone or pocket.

[0080] 9, a second mask 17 is provided on the first mask 13, the second mask 17 having one less opening 14 than the first mask 13. That is, the second mask 17 has three openings 14, and the openings 14 of the second mask 17 each have a smaller width than the openings 14 of the first mask 13. Furthermore, the second mask 17 covers the zone closest to the anode region pocket 12.

[0081] A second dopant is then introduced to a second depth through openings 14 in second mask 17 and two of the three zones in anode region pocket 12. This causes anode region 6 and two second pockets 9 to have a second maximum doping concentration.

[0082] After the creation of the anode region 6 and the two second pockets 9, a passivation region 18 including at least one passivation layer may be formed on the base layer 2 with one opening 14, the opening 14 of the passivation region 18 being located above the second doped region 16 of the anode region 6. The opening 14 of the passivation region 18 is smaller than the corresponding opening 14 of the second mask 17.

[0083] Through the openings 14 in the third mask 18, an anode electrode 11 is deposited on the second doped region 16 of the anode region 6. Furthermore, a cathode electrode 10 is deposited on the cathode side 4.

[0084] The passivation region 18, e.g., at least one passivation layer, is formed by standard photolithographic techniques after the formation of the anode electrode 11. Illustratively, the anode electrode 11 is formed by blanket deposition and subsequent etching by standard photolithographic techniques. [Explanation of symbols]

[0085] Reference sign 1. Power Diode 2. Base Layer 3. Buffer layer 4 Cathode side 5 Anode side 6 Anode region 7 Termination area 8. First Pocket 9 Second Pocket 10 cathode electrode 11 Anode electrode 12 Anode area pocket 13 The First Mask 14 Openings 15 First doped region 16 Second doped region 17 The Second Mask 18 The Third Mask K1 First curve K2 Second curve

Claims

1. A power diode (1) comprising a wafer having a cathode side (4) and an anode side (5) opposite the cathode side, the power diode (1) comprising: a base layer (2) of a first conductivity type included in the wafer; an anode region (6) of a second conductivity type different from the first conductivity type provided on the anode side of the wafer; a termination region (7) located between the cathode side (4) and the anode side (5) of the wafer; and the termination region (7) laterally surrounds the anode region (6), the termination region (7) comprises a first pocket (8) of the second conductivity type and at least two second pockets (9) of the second conductivity type, the first pocket (8) is located laterally between the anode region (6) and the at least two second pockets (9); the first pocket (8) has a first maximum doping concentration that is less than a second maximum doping concentration of each of the at least two second pockets (9); the first pocket (8), the at least two second pockets (9), and the anode region (6) are laterally spaced apart from one another; the first pocket (8), the at least two second pockets (9), and the anode region (6) are provided in the base layer (2); the base layer (2) is arranged laterally between the first pocket (8), the at least two second pockets (9), and the anode region (6); the anode region (6) and the at least two second pockets (9) each comprise a first doped region (15) and a second doped region (16); The maximum doping concentration of the first doped region (15) is lower than the maximum doping concentration of the second doped region (16). Power diode (1).

2. the first doped region (15) extends vertically from the anode side (5) to a first depth within the wafer; the second doped region (16) extends vertically from the anode side to a second depth within the wafer; the first depth is greater than the second depth; A power diode (1) according to claim 1.

3. A power diode (1) comprising a wafer having a cathode side (4) and an anode side (5) opposite the cathode side, wherein the power diode (1) a base layer (2) of a first conductivity type included in the wafer; an anode region (6) of a second conductivity type different from the first conductivity type provided on the anode side of the wafer; a termination region (7) located between the cathode side (4) and the anode side (5) of the wafer; and the termination region (7) laterally surrounds the anode region (6), the termination region (7) comprises a first pocket (8) of the second conductivity type and at least two second pockets (9) of the second conductivity type, the first pocket (8) is located laterally between the anode region (6) and the at least two second pockets (9); the first pocket (8) has a first maximum doping concentration that is less than a second maximum doping concentration of each of the at least two second pockets (9); the first pocket (8), the at least two second pockets (9), and the anode region (6) are laterally spaced apart from one another; the first pocket (8), the at least two second pockets (9), and the anode region (6) are provided in the base layer (2); the base layer (2) is arranged laterally between the first pocket (8), the at least two second pockets (9), and the anode region (6); The width of the first pocket (8) is greater in the lateral direction than the width of each of the at least two second pockets (9). Power diode (1).

4. A power diode (1) comprising a wafer having a cathode side (4) and an anode side (5) opposite the cathode side, wherein the power diode (1) a base layer (2) of a first conductivity type included in the wafer; an anode region (6) of a second conductivity type different from the first conductivity type provided on the anode side of the wafer; a termination region (7) located between the cathode side (4) and the anode side (5) of the wafer; and the termination region (7) laterally surrounds the anode region (6), the termination region (7) comprises a first pocket (8) of the second conductivity type and at least two second pockets (9) of the second conductivity type, the first pocket (8) is located laterally between the anode region (6) and the at least two second pockets (9); the first pocket (8) has a first maximum doping concentration that is less than a second maximum doping concentration of each of the at least two second pockets (9); the first pocket (8), the at least two second pockets (9), and the anode region (6) are laterally spaced apart from one another; the first pocket (8), the at least two second pockets (9), and the anode region (6) are provided in the base layer (2); the base layer (2) is arranged laterally between the first pocket (8), the at least two second pockets (9), and the anode region (6); the first maximum doping concentration of the first pocket (8) is at least one order of magnitude less than the second maximum doping concentration of each of the at least two second pockets (9); Power diode (1).

5. the first pocket (8) and the at least two second pockets (9) each completely surround the anode region (6) in the lateral direction; A power diode (1) according to any one of claims 1 to 4.

6. The width of the anode region (6) is greater in the lateral direction than the width of the first pocket (8) and greater than the width of each of the at least two second pockets (9). A power diode (1) according to any one of claims 1 to 4.

7. The power diode (1) A cathode electrode (10); Anode electrode (11) Furthermore, The cathode electrode (10) is provided on the wafer from the cathode side (4), The anode electrode (11) is provided on the anode region (6). A power diode (1) according to any one of claims 1 to 4.

8. The anode region (6) and the at least two second pockets (9) each comprise a first doped region (15) and a second doped region (16); The anode electrode (11) completely overlaps the second doped region (16) of the anode region (6) in a plan view. A power diode (1) according to claim 7.

9. 1. A method for manufacturing a power diode (1) comprising a wafer having a cathode side (4) and an anode side (5) opposite said cathode side (4), said method comprising the steps of: providing a base layer (2) included in said wafer of a first conductivity type different from a second conductivity type; creating an anode region pocket (12) and at least three zones by introducing a first dopant of the second conductivity type from the anode side (5) within the wafer, each zone having a first maximum doping concentration within the wafer; introducing a second dopant of said second conductivity type into said anode region pocket (12) and into at least two of said at least three zones so as to create an anode region (6) and at least two second pockets (9) having a second maximum doping concentration; Including, the zone into which the second dopant is not introduced is located between the anode region (6) and the at least two second pockets (9) and forms a first pocket (8); the first maximum doping concentration is less than the second maximum doping concentration; the first pocket (8), the at least two second pockets (9), and the anode region (6) are laterally spaced apart from one another; the first pocket (8), the at least two second pockets (9), and the anode region (6) are provided in the base layer (2); the base layer (2) is provided laterally between the first pocket (8), the at least two second pockets (9), and the anode region (6); method.

10. applying a first mask (13) having at least four openings (14) to the anode side (5) before introducing the first dopant, before introducing the second dopant, applying a second mask (17) having one less opening than the first mask (13) to the first mask (13), the second mask (17) covering the zone closest to the anode region pocket (12); 10. The method of claim 9.

11. the first mask (13) is an oxide mask; The method of claim 10.

12. removing the first mask (13) after the creation of the anode region (6) and the at least two second pockets (9); 12. The method according to claim 10 or 11.

13. after said creation of said anode region (6) and said at least two second pockets (9), producing a cathode electrode (10) and an anode electrode (11); The method according to any one of claims 9 to 11.

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