Feeder design with high current capacity

Abstract

To provide an improved feeder structure to a SiC power device.SOLUTION: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material (3) and comprising at least one epitaxially grown p-type region. An ohmic contact is applied on the at least one epitaxially grown p-type region. An epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3). The at least two p-type grids (4, 5) are applied in at least first and second regions at least close to at least first and second corners respectively. There is a region without any grids, in the n-type SiC material (3) between the first and second regions.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present invention relates to a SiC structure that integrates epitaxial PiN diodes with buried grid (BG) power device feeders and uses BG to protect the sharp corners of the PiN diodes from high electric fields during voltage blocking. [Background technology]

[0002] Current Schottky diodes, such as JBS or MPS diodes, and MOSFETs use integrated PiN diodes or pn body diodes to handle large surge currents. Problems with the prior art include: Relatively high forward voltage drop at high currents in PiN diodes due to limited injection efficiency and high ohmic contact resistance Switching from Schottky to PiN diode characteristics at high forward voltages, which causes a snapback effect due to the voltage drop across the PN junction in Schottky mode Bipolar degradation caused by ion implantation, which degrades device performance and lifetime Includes:

[0003] A built-in doping structure or buried grid (BG) can be used to shield the Schottky contact or MOSFET from the high electric field at the surface of the SiC power semiconductor. Therefore, it is desirable to mitigate the electric field at the surface of the semiconductor or at the interface to other electric field-sensitive materials such as gate oxides.

[0004] In JBS rectifiers, the P+ grid is primarily used to shield the Schottky contact in reverse mode, while in MPS rectifiers the built-in P+ grid has an additional function and acts as a shield for the corresponding P + The N junction is conductive in the on-state. +The N-junction generates hole injection into the drift, causing conductivity modulation similar to that of a PiN rectifier. This transitional behavior of the MPS diode from Schottky-like to PiN-like is desirable for power applications. It requires the formation of an ohmic contact to the P+ region. The P-well doping in a MOSFET has a similar function and is called the "body diode."

[0005] Forming a P+ grid by ion implantation is a common method in many devices, as ion implantation is a standard industrialized process. The advantage is the natural rounding of the grid due to straggling of implanted ions, which reduces electric field crowding. To achieve high implantation efficiency, the thickness and doping of the P+ region must be increased. Forming a thick, sufficiently highly doped P+ region can require high-energy and high-dose ion implantation. High-dose ion implantation can cause crystalline damage, resulting in so-called bipolar degradation, which significantly reduces the implantation efficiency of the P+ region. Furthermore, forming a low-resistance, uniform ohmic contact to the implanted P region has been challenging. Thus, the switch in on-state characteristics from Schottky or MOSFET operation to PiN operation occurs at very high voltages, causing a high snapback voltage, making it undesirable for power applications. Many commercially available SiC devices suffer from this slow implantation behavior.

[0006] The P+ region can be formed by either ion implantation or epitaxial growth process. The advantages and disadvantages of both processes are as follows: Ion implantation P region advantage: Selective doping of regions by masks, oxides, or photoresist masks depending on process temperature and / or implant dose Good doping control and uniformity across the wafer Well-known doping techniques Disadvantages: Low efficiency of the implanted emitter due to recombination at defect centers remaining from the implant damage → limiting the surge current capability of MPS rectifiers Doping level limitations due to increased implant damage with increasing implant dose Non-diffusion of acceptor and donor dopants in commonly used SiC → The implanted pn junction is located where the implant profile ends and where implant damage is large Thickness limitations due to implant energy limitations: a thickness of 1 μm requires an implant energy of 400–1000 keV depending on the implanted ions. High energy implantation is a costly process Epitaxial P region advantage: High injection efficiency due to the excellent quality of highly doped materials Control of grid thickness and doping profile Deep doped structure possible, no problem with grid thickness ●Doping without damage even at high concentrations High doping concentrations close to the semiconductor-semimetal transition are possible Disadvantages: Sharp corners in the epitaxial grid result in electric field concentrations that limit the blocking voltage of the device CMP or planarization process may be required

[0007] There are already known solutions in the art to improve implant efficiency by implementing either a highly doped epitaxial layer or a high dose ion implant, as detailed below.

[0008] Simultaneous formation of Schottky and ohmic contacts is disclosed in U.S. Patent No. 5,629,999 for a semiconductor device made from silicon carbide with Schottky and ohmic contacts made from nickel aluminum materials, but the implantation from the P+ implanted region is not efficient and the surface Schottky contact is sensitive to high electric fields.

[0009] The use of heterojunction barrier regions is described in detail in U.S. Patent No. 5,929,999, entitled "Semiconductor Device with Heterojunction Barrier Region and Method of Fabricating the Same." Injection from a P+ implant region is inefficient. Surface Schottky barriers are created that are sensitive to high electric fields, which can increase leakage current.

[0010] Implementing a non-implanted barrier region is disclosed in US Pat. No. 6,233,999, entitled "Semiconductor Device with Non-Implanted Barrier Region and Method for Fabricating the Same," which also makes the surface Schottky barrier sensitive to high electric fields that can increase leakage current.

[0011] Implementing a two-layer P+ / P grid with P / P+ is detailed in U.S. Patent No. 6,277,333, which discloses a silicon carbide junction barrier Schottky diode with suppressed minority carrier injection. Injection from the P+ implanted region is inefficient, and makes the surface Schottky sensitive to high electric fields, which can increase leakage current.

[0012] The use of P+ implants inside the trench together with epitaxial P+ regions is detailed in U.S. Patent No. 5,623,799, which discloses a supersurge diode. A Schottky contact is made on the trench surface, which can result in a field-sensitive Schottky contact and can also cause barrier non-uniformity, both of which increase leakage current.

[0013] The use of an additional P+ implanted region inside the P region to improve injection is disclosed in US Pat. No. 6,223,999. Injection from the P+ implanted region is not efficient. Surface Schottky contacts are sensitive to high electric fields.

[0014] Modification of the sharp corners of etched epitaxial P+ regions by growing an epitaxial layer in a rounded trench etch structure is disclosed in US Pat. No. 6,223,999. This is a complex process requiring advanced etching and planarization techniques.

[0015] The problem of sharp corners is also known from trench grid manufacturing by combining trench etching and ion implantation, where rounded corners have to be etched, see US Pat. No. 5,649,499.

[0016] Epitaxial termination is disclosed in US Pat. No. 5,629,399. There are high electric fields at the sharp corners of the etched epitaxial layer. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] U.S. Patent No. 6,936,850 [Patent Document 2] US Patent Application Publication No. 2011 / 021533 [Patent Document 3] U.S. Patent No. 9,466,674 [Patent Document 4] US Patent Application Publication No. 2006 / 0255423 [Patent Document 5] US Patent Application Publication No. 2014 / 0138705 [Patent Document 6] U.S. Patent No. 9,577,046 [Patent Document 7] U.S. Patent No. 6,897,133 [Patent Document 8] U.S. Patent No. 8,633,560 [Patent Document 9] U.S. Patent No. 6,673,662 Summary of the Invention [Problem to be solved by the invention]

[0018] It is an object of the present invention to obviate at least some of the drawbacks of the prior art and to provide an improved feeder structure for SiC power devices.

[0019] The present invention integrates epitaxial PiN diodes with the feeder of buried grid (BG) SiC power devices such as Schottky diodes or MOSFETs, and uses the BG to protect the sharp corners of the PiN from high electric fields during voltage blocking. This combines the low forward voltage drop of a Schottky diode or MOSFET at rated current with the efficient switchover of the PiN diode during surge currents or short-circuit conditions.

[0020] The proposed structure combines the advantages of an epitaxial P+ region with high injection efficiency and a P+ buried grid shield field-sensitive device region to reduce reverse leakage current and protect the sharp corners of the epitaxial P+ region. [Means for solving the problem]

[0021] In a first aspect, a structure of SiC semiconductor material is provided, comprising an n-type substrate (1), an n-type drift layer (2), and at least two p-type grids (4, 5) in an n-type SiC material (3), the structure comprising an n-type epitaxially grown layer (8) of SiC, the n-type epitaxially grown layer (8) being in contact with the at least two p-type grids (4, 5) and the n-type SiC material (3), the n-type epitaxially grown layer (8) being in contact with at least one epitaxially grown p-type region (7), an ohmic contact (9) being in contact with the at least one epitaxially grown p-type region (7), and at least one ohmic contact (10) being in contact with the at least one epitaxially grown p-type region (7) in a plane parallel to the n-type substrate (1). The projection of one epitaxially grown p-type region (7) has a boundary line (l) that limits the projection of at least one epitaxially grown p-type region (7), and the p-type grid (5) is provided so that at least the projection of the p-type grid (5) in a plane parallel to the n-type substrate (1) is around the boundary line (l) and the distance of any point around the periphery from the boundary line (l) is a maximum of 0.5 μm, and the p-type grid (5) is also provided so that the distance from the bottom of the at least one epitaxially grown p-type region (7) to the top of the p-type grid (5) is in the range of 0 to 5 μm, and the upward direction is provided by a direction vertically away from the n-type substrate (1).

[0022] Further aspects and embodiments are defined in the appended claims, which are specifically incorporated herein by reference.

[0023] Advantages include high surge current capability due to the low forward voltage drop of the epitaxial PiN diode due to improved injection efficiency resulting from the highly doped epitaxial P++ region (7).

[0024] A further advantage is the elimination of bipolar degradation caused by high dose ion implantation in the feeder region.

[0025] Yet another advantage is the control and elimination of snapback effects in the conducting or on-state by varying the ratio of PiN diode area to Schottky diode or MOSFET area.

[0026] Furthermore, the present invention provides design flexibility for different voltage classes by varying the dimensions and doping profile of the epitaxial PiN diode region.

[0027] The present invention will now be described with reference to the accompanying drawings, which are non-limiting examples shown to facilitate the use of the invention. [Brief explanation of the drawings]

[0028] [Figure 1a] Shown is a schematic cross section of a buried grid rectifier with a combination of an epitaxial PiN feeder and an implanted grid for shielding, where the P+ epilayer region (7) is centered above and aligned with the P+ implanted grid (5). [Figure 1b] A schematic cross section of a P+ epilayer region (7) shielded by additional overlapping P+ grids (4, 5) or alternatively by an overlapping extended P+ grid (5) is shown. [Figure 1c] Schematic cross-sectional views of different positioning of the P+ epilayer (7) spaced above the P+ grid (4, 5) are shown. [Figure 1d]1 shows portions of a device according to the present invention, with some portions omitted for clarity. Shown are a substrate (1), drift layer (2), n-type SiC material (3), and epitaxially grown p-type region (7), as well as a plane parallel to the substrate (1) and a projection of the epitaxially grown p-type region (7) on the plane, the plane including the boundary line (l) of the projection on the plane. The perimeter of the boundary line (l) on the plane is shown with a solid line such that the distance of any point on the perimeter from the boundary line (l) is a maximum of 0.5 μm. Any corners of the perimeter region are rounded such that the perimeter of the line is determined by a circle of radius 0.5 μm moving along the boundary line (l). [Figure 2a] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2b] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2c] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2d] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2e] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2f] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 2g] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3a] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3b] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3c] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3d]1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3e] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 3f] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4a] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4b] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4c] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4d] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4e] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4f] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 4g] 1b shows one step of one proposed fabrication process for the proposed structure of FIG. [Figure 5a] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 5b] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 5c] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 5d] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 5e] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 6a] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 6b] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 6c] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 6d] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 6e] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7a] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7b] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7c] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7d] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7e] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7f] 1c shows one step of one proposed fabrication process for the proposed structure. [Figure 7g] 1c shows one step of one proposed fabrication process for the proposed structure. DETAILED DESCRIPTION OF THE INVENTION

[0029] Before the present invention is disclosed and described in detail, it is to be understood that the invention is not limited to the particular compounds, compositions, method steps, substrates, and materials disclosed herein, as such compounds, compositions, method steps, substrates, and materials may vary slightly. It is also to be understood that the terminology used herein is used only for the purpose of describing particular embodiments, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims and their equivalents.

[0030] It must be noted that as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0031] "Embedded grid" as used throughout this specification and claims refers to a grid structure of material having one conductivity type in a material having the opposite conductivity type.

[0032] As used throughout this specification and claims, "conductivity type" refers to the type of conductivity in a semiconductor material. N-type indicates electron conduction, meaning that excess electrons move in the semiconductor to allow current to flow, while p-type indicates hole conduction, meaning that excess holes move in the semiconductor to allow current to flow. N-type semiconductor materials are achieved by donor doping, and p-type semiconductor materials are achieved by acceptor doping. In SiC, nitrogen is typically used as the donor dopant and aluminum is typically used as the acceptor dopant. When a material is a doped semiconductor such as SiC, the material has either conductivity type p or conductivity type n. Those skilled in the art will recognize that in a semiconductor device, if all p-doped materials are replaced with n-doped materials, all n-doped materials can also be replaced with p-doped materials, i.e., n and p can be swapped, and a similar device can still be obtained.

[0033] "Doped," as used throughout this specification and claims, indicates that impurities have been added to an intrinsic semiconductor, such as SiC, to modify its electrical properties and make it an extrinsic semiconductor.

[0034] "Epitaxial" as used throughout this specification and claims indicates that the material has been produced by epitaxial growth, in this case epitaxial growth of SiC.

[0035] "Substrate" as used throughout this specification and claims refers to a piece of material upon which a power device is constructed.

[0036] Unless otherwise defined, all terms and scientific terms used herein are intended to have the meaning commonly understood by one of ordinary skill in the art to which this invention pertains.

[0037] In a first aspect, a structure of SiC semiconductor material is provided, comprising an n-type substrate (1), an n-type drift layer (2), and at least two p-type grids (4, 5) in an n-type SiC material (3), the structure comprising an n-type epitaxially grown layer (8) of SiC, the n-type epitaxially grown layer (8) being in contact with the at least two p-type grids (4, 5) and the n-type SiC material (3), the n-type epitaxially grown layer (8) being in contact with at least one epitaxially grown p-type region (7), an ohmic contact (9) being in contact with the at least one epitaxially grown p-type region (7), and at least one ohmic contact (10) being in contact with the at least one epitaxially grown p-type region (7) in a plane parallel to the n-type substrate (1). The projection of one epitaxially grown p-type region (7) has a boundary line (l) that limits the projection of at least one epitaxially grown p-type region (7), and the p-type grid (5) is provided so that at least the projection of the p-type grid (5) in a plane parallel to the n-type substrate (1) is around the boundary line (l) and the distance of any point around the periphery from the boundary line (l) is a maximum of 0.5 μm, and the p-type grid (5) is also provided so that the distance from the bottom of the at least one epitaxially grown p-type region (7) to the top of the p-type grid (5) is in the range of 0 to 5 μm, and the upward direction is provided by a direction vertically away from the n-type substrate (1).

[0038] The perimeter of the boundary line (l) can be determined by moving a circle of radius 0.5 μm along the boundary line (l), locating the area swept by the circle within the perimeter, and determining that any point on the perimeter is at most 0.5 μm away from the boundary line (l). This is applicable to any shape of the boundary line (l). If the epitaxially grown p-type region (7) has a very long trench configuration, there may be two boundary lines. When viewed from above, i.e., from a position viewing the maximum area of the substrate (1), the p-type grid (5) is provided close to the boundary of the epitaxially grown p-type region (7), more specifically, within ±0.5 μm of the boundary line. This defines a perimeter of ±0.5 μm from the boundary line, and the p-type feeder layer (5) is provided at least around this perimeter, but it can also be provided outside this perimeter. The p-type grid (5) also needs to be provided fairly close to the epitaxially grown p-type region (7) when viewed from the side, i.e., when the device is cut across. The p-type feeder layer (5) is then in contact with the epitaxially grown p-type region (7) or is at most 5 μm below the epitaxially grown p-type region (7). Since the projection of the epitaxially grown p-type region (7) is used to determine the boundary line (l), the largest part of the epitaxially grown p-type region (7) determines the position of the p-type grid (5). Since the cross section of the p-type feeder layer (5) in the cross section seen in FIG. 1d is quite close to a right angle, this condition means that the p-type feeder layer (5) is provided at least close to the corners, so that they reduce the influence of the corners on the electric field.

[0039] In one embodiment, at least one epitaxially grown p-type region (7) is in contact with at least one of the at least two p-type grids (4, 5).

[0040] In one embodiment, at least one epitaxially grown p-type region (7) is not in contact with at least two p-type grids (4, 5).

[0041] In one embodiment, each of the at least two p-type grids (4, 5) comprises a plurality of ion-implanted grids.

[0042] In one embodiment, the width of the at least one epitaxially grown p-type region (7) is in the interval of 5 to 500 μm.

[0043] In one embodiment, the thickness of the at least one epitaxially grown p-type region (7) is in the interval 1 to 3 μm.

[0044] In one embodiment, the doping concentration of the at least one epitaxially grown p-type region (7) varies from the portion closest to the n-type SiC material (3) to the portion closest to the ohmic contact (9).

[0045] In one embodiment, the doping concentration of the at least one epitaxially grown p-type region (7) is highest in the portion closest to the ohmic contact (9).

[0046] In one embodiment, the doping concentration of the at least one epitaxially grown p-type region (7) is 1×10 19 cm -3 ~3×10 20 cm -3 5 × 10 excluding the layer closest to the ohmic contact (9) which is spaced 17 cm -3 ~1×10 19 cm -3 The interval is .

[0047] In one embodiment, the center of at least one epitaxially grown p-type region (7), calculated as the center of gravity, is aligned with the center of the grid-free region between the first and second regions in the n-type SiC material (3).

[0048] In one embodiment, there is a space between the at least one epitaxially grown p-type region (7) and the at least two p-type grids (4, 5) in the n-type SiC material (3), optionally with a connection between the at least one epitaxially grown p-type region (7) and the at least two p-type grids (4, 5).

[0049] In one embodiment, at least one epitaxially grown p-type region (7) is provided directly on at least two p-type grids (4, 5) in an n-type SiC material (3).

[0050] In one embodiment, there are at least four p-type grids (4, 5), and at least two p-type grids (5) closest to the first and second corners, respectively, are larger than the remaining p-type grids (4).

[0051] In one embodiment, the doping concentration of the at least two p-type grids (4, 5) is 3×10 17 cm -3 ~3×10 20 cm -3 The thicknesses of the at least two p-type grids (4, 5) are spaced apart by 0.5 to 2.5 μm, and the width of each of the at least two p-type grids (4, 5) is at least 0.5 μm.

[0052] In one embodiment, there are at least three p-type grids (4, 5), and the spacing between two adjacent p-type grids (4, 5) is 1-5 μm apart, without considering the area between the first and second regions in the n-type SiC material (3) without grids as spaces.

[0053] In one embodiment, the thickness of the n-type epitaxial growth layer (8) is at least 0.5 μm and the doping concentration is 1×10 14 cm -3 ~1×10 17 cm -3 The interval is .

[0054] In one embodiment, the thickness of the n-type epitaxially grown layer (8) is at least 0.5 μm thicker than the at least one epitaxially grown p-type region (7).

[0055] In one embodiment, the at least two p-type grids (4, 5) comprise a plurality of grids, at least some of which have a centrally positioned ledge beneath the grid, positioned away from the n-type epitaxial growth layer (8), and having a smaller lateral dimension than the grid. This feature improves the electric field shielding efficiency of the grids and reduces the electric field at the surface of the device. This increases blocking voltage and lowers leakage current without adding forward resistance. Alternatively, wider grid spacing can be used with this design, resulting in lower on-resistance. The structure is more tolerant to process variations such as misalignment, ion implant dose and energy variations, etch depth, etc.

[0056] In one embodiment, the at least two p-type grids (4, 5) comprise a plurality of grids, each having an upper and lower portion, the upper portion facing the n-type epitaxial growth layer (8), the upper portion fabricated using epitaxial growth, and the lower portion fabricated using ion implantation. In this embodiment, it is possible to fabricate grids with rounded corners and upper portions with high doping levels. It is possible to fabricate components with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.

[0057] In one embodiment, the at least two p-type grids (4, 5) are fabricated by ion implantation.

[0058] In a second aspect, there is provided a device comprising a structure as described above. In one embodiment, the device is selected from the group consisting of a MOSFET, a JFET, a JBS diode, and an insulated gate bipolar transistor (IGBT). In one embodiment, the device is an integration of at least two components, such as at least two of the mentioned components. One non-limiting example of an integration of at least two components is a MOSFET and a Schottky diode.

[0059] In a third aspect, there is provided a method for manufacturing a SiC structure as described above, the method comprising: a) providing a substrate having a drift layer and an n-type SiC material (3) thereon; b) adding a p-type layer by epitaxial growth of SiC; c) etching away unnecessary parts of the added p-type layer to obtain at least one epitaxially grown p-type region (7); d) producing at least two p-type grids (4, 5) by ion implantation in the n-type SiC material (3); e) adding an n-type layer (8) by epitaxial growth of SiC; Includes:

[0060] In one embodiment, step d) is performed before step b).

[0061] In one embodiment, the method is performed in the following order: steps a), b), c), d), e).

[0062] In one embodiment, the method is carried out in the order of steps a), d), e), b), c), with the additional step of etching trenches in the n-type layer (8) after step e) in areas intended for at least one epitaxially grown p-type region (7).

[0063] In one embodiment, the method includes adding an ohmic contact (9) at least partially on the at least one epitaxially grown p-type region (7).

[0064] In one embodiment, the method includes the step of adding a metal coating (12).

[0065] Those skilled in the art will recognize that even though the claims and this specification define p-type grids (4, 5), n-type epitaxially grown layers, etc., on n-type SiC material (3), all n-type and p-type materials can be interchanged, such as all n-doped (n-type) materials becoming p-doped (p-type) materials and all p-doped (p-type) materials becoming n-doped (n-type) materials. Today, the most common commercially available substrates are n-type, and as a result, in the claims and this specification, n-type substrates are selected, but the invention can be used with equally good results if all n-type and p-type materials are interchanged.

Claims

1. an n-type substrate; a drift layer disposed on the n-type substrate; an n-type SiC material disposed on the drift layer; at least two p-type grids arranged in the n-type SiC material at a first horizontal level parallel to the n-type substrate; Diode structure and A semiconductor device comprising: The diode structure comprises: at least one epitaxially grown p-type region disposed on the n-type SiC material disposed on the drift layer and disposed in a second horizontal level parallel to the n-type substrate; an n-type epitaxially grown layer of SiC disposed in contact with the at least two p-type grids and the n-type SiC material and disposed in contact with the at least one epitaxially grown p-type region; an ohmic contact disposed in contact with the at least one epitaxially grown p-type region; Equipped with the at least two p-type grids are positioned within a predetermined horizontal distance from a boundary line representing a perimeter of the at least one epitaxially grown p-type region at the second horizontal level, the at least two p-type grids having top surfaces that contact a bottom surface of the at least one epitaxially grown p-type region or are vertically separated from the bottom surface of the at least one epitaxially grown p-type region within the predetermined distance, the predetermined distance being 0.5 μm.

2. the at least one epitaxially grown p-type region is disposed in contact with at least one of the at least two p-type grids; or the at least one epitaxially grown p-type region is not disposed in contact with the at least two p-type grids; or 2. The semiconductor device of claim 1, wherein the at least one epitaxially grown p-type region is applied directly onto the at least two p-type grids in the n-type SiC material.

3. each of the at least two p-type grids includes a plurality of p-type grids, the plurality of p-type grids having ions implanted therein; or 10. The semiconductor device of claim 1, wherein the at least two p-type grids have ions implanted therein.

4. the width of the at least one epitaxially grown p-type region is in the range of 5 μm to 500 μm; or the thickness of the at least one epitaxially grown p-type region is in the range of 1 μm to 3 μm; or 2. The semiconductor device of claim 1, wherein the thickness of the n-type epitaxially grown layer is at least 0.5 μm thicker than the thickness of the at least one epitaxially grown p-type region.

5. 2. The semiconductor device of claim 1, wherein the at least two p-type grids include at least three p-type grids, and a space between adjacent p-type grids of the at least three p-type grids is in the range of 1 μm to 5 μm, excluding a region of the n-type SiC material without grids between the first region and the second region.

6. the doping concentration of the at least one epitaxially grown p-type region varies from closest to the n-type SiC material to closest to the ohmic contact; or 2. The semiconductor device of claim 1, wherein the doping concentration of the at least one epitaxially grown p-type region is highest in the portion closest to the ohmic contact.

7. 10. The semiconductor device of claim 1, further comprising a connection disposed in a space between said at least one epitaxially grown p-type region and said at least two p-type grids.

8. The semiconductor device of claim 1 , wherein the at least two p-type grids comprise a plurality of p-type grids.

9. 2. The semiconductor device of claim 1, wherein the at least two p-type grids include a plurality of p-type grids, each p-type grid having an upper portion and a lower portion, the upper portion facing the n-type epitaxial growth layer, the upper portion being an epitaxial growth layer, and the lower portion having ions implanted therein.

10. 10. The semiconductor device of claim 1, wherein the semiconductor device is selected from the group consisting of a MOSFET, a JFET, a JBS diode, and an insulated gate bipolar transistor (IGBT).

11. The semiconductor device of claim 10 , wherein the semiconductor device is an integration of at least two components.

12. 1. A method for manufacturing a structure in SiC, comprising: a) providing a substrate having a drift layer and an n-type SiC material thereon; b) adding a p-type layer by epitaxial growth of SiC; c) etching away unwanted portions of the p-type layer to obtain at least one epitaxially grown p-type region, the at least one epitaxially grown p-type region being in a second level; d) fabricating at least two p-type grids in the n-type SiC material on a first level; e) adding an n-type layer by epitaxial growth of SiC; Including, the at least two p-type grids are positioned within a predetermined horizontal distance from a boundary line representing a perimeter of the at least one epitaxially grown p-type region in the second level and are positioned to either contact the at least one epitaxially grown p-type region or be vertically separated from the at least one epitaxially grown p-type region within the predetermined distance, the predetermined distance being 0.5 μm.

13. The method of claim 12 , wherein step d) is performed before step b).

14. 13. The method of claim 12, wherein step d) is performed by ion implantation.

15. 15. The method of claim 14, wherein steps a), d), e), b), and c) are performed in that order, with the additional step of etching a trench in the n-type layer after step e) in areas intended for the at least one epitaxially grown p-type region.

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