Power semiconductor device and method of manufacturing the same

Abstract

Provided is a power semiconductor device in which heat dissipation from a semiconductor element is high. The power semiconductor device comprises a semiconductor device, a heat sink, grease, an adhesive, and a terminal block. The semiconductor device includes a semiconductor element, a sealing material for sealing the semiconductor element, and a power terminal electrically connected to the semiconductor element, wherein: a first region, which is a selective region of the lower surface of the semiconductor device, is adhered to the heat sink by the adhesive; and the semiconductor device contacts the heat sink through the grease at a second region, which is a region on the lower surface of the semiconductor device other than the selective region; the terminal block includes an electrode on the upper surface thereof; and the power terminal of the semiconductor device is fixed to the terminal block and electrically connected to the electrode of the terminal block.

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing a power semiconductor device. [Background technology]

[0002] A semiconductor device with a heat sink is disclosed in Patent Document 1. In the configuration of Patent Document 1, the heat sink is adhered to a package containing a semiconductor by a polymer adhesive that is used to cover the periphery of thermally conductive grease. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Utility Model Application Publication No. 02-000737 Summary of the Invention [Problem to be solved by the invention]

[0004] When a polymer adhesive is interposed between the heat sink and the thermally conductive grease, the adhesive has low thermal conductivity, which deteriorates the heat dissipation from the semiconductor element.

[0005] The present disclosure is intended to solve such problems, and has an object to provide a power semiconductor device that has high heat dissipation properties from semiconductor elements. [Means for solving the problem]

[0006] The power semiconductor device of the present disclosure comprises a semiconductor device, a heat sink, grease, an adhesive, and a terminal block, the semiconductor device comprising a semiconductor element, a sealing material for sealing the semiconductor element, and a power terminal electrically connected to the semiconductor element, a first region which is a selective region on the underside of the semiconductor device is bonded to the heat sink with the adhesive, the semiconductor device contacts the heat sink via grease in a second region which is a region of the underside of the semiconductor device other than the selective region, the terminal block has electrodes on its upper surface, the power terminal of the semiconductor device is fixed to the terminal block and electrically connected to the electrodes of the terminal block, the first region is a region that surrounds the entire periphery of the second region in a plan view, the sealing material is exposed in the second region, and a first groove is provided in the portion of the second region where the sealing material is exposed; the first groove is disposed within a region surrounded by the first region; Grease has entered the first groove. [Effects of the Invention]

[0007] The present disclosure provides a power semiconductor device with high heat dissipation from the semiconductor element.

[0008] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating a power semiconductor device according to a first embodiment. [Figure 2] 1 is a diagram illustrating a semiconductor device according to a first embodiment. [Figure 3] 1 is a diagram illustrating a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view of a power semiconductor device according to a first embodiment, viewed from above; [Figure 5] FIG. 10 is a diagram illustrating a power semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a plan view showing an example of a state in which the semiconductor device of the second embodiment is viewed from below. [Figure 7]It is a plan view showing an example of the state of the semiconductor device of Embodiment 2 seen from below. [Figure 8] It is a figure showing the power semiconductor device of Embodiment 3. [Figure 9] It is a figure showing the power semiconductor device of Embodiment 4. [Figure 10] It is a figure showing the power semiconductor device of Embodiment 5. [Figure 11] It is a plan view showing an example of the state of the semiconductor device of Embodiment 5 seen from below. [Figure 12] It is a figure showing the state during the manufacture of the power semiconductor device of Embodiment 6. [Figure 13] It is a figure showing the power semiconductor device of Embodiment 6. [Figure 14] It is a flowchart showing the manufacturing method of the power semiconductor device of Embodiment 7. [Figure 15] It is a figure showing the state during the manufacture of the power semiconductor device in the manufacturing method of the power semiconductor device of Embodiment 7. [Figure 16] It is a figure showing the power semiconductor device of the comparative example. [Figure 17] It is a figure showing the power semiconductor device of the comparative example. [Figure 18] It is a figure showing the power semiconductor device of the comparative example.

Embodiments for Carrying Out the Invention

[0010] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a diagram showing the power semiconductor device 1a of Embodiment 1.

[0011] [[ID=4�]]The power semiconductor device 1a includes a printed board 2 which is a circuit board, a heat sink 3, a terminal block 4, a semiconductor device 10a, bolts 32, an adhesive 34, and grease 35.

[0012] Fig. 2 is a diagram showing the semiconductor device 10a. Fig. 3 is a plan view of the semiconductor device 10a seen from above. Fig. 2 is a cross-sectional view taken along line AA in Fig. 3, for example.

[0013] As shown in FIGS. 2 and 3, the semiconductor device 10a includes a semiconductor element 11a, a semiconductor element 11b, a heat spreader 12, an insulating material 13, a metal foil 14, a sealing material 15, a wire 16, a plurality of main terminals 17, and a plurality of signal terminals 18.

[0014] The insulating material 13 is plate-shaped. The metal foil 14 is bonded onto the lower surface of the insulating material 13. The heat spreader 12 is bonded onto the upper surface of the insulating material 13. The metal foil 14 is exposed at the lower surface 20 of the semiconductor device 10a.

[0015] The semiconductor element 11a is, for example, a diode, and the semiconductor element 11b is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0016] The semiconductor elements 11a and 11b, and the wires 16 are sealed with a sealing material 15. The semiconductor device 10a is, for example, a transfer mold type semiconductor device. The sealing material 15 is, for example, a resin.

[0017] The main terminals 17 are partially sealed in the sealing material 15. The main terminals 17 protrude from the sealing material 15 at the side surfaces of the semiconductor device 10a. The signal terminals 18 are partially sealed in the sealing material 15. The signal terminals 18 protrude from the sealing material 15 at the side surfaces of the semiconductor device 10a.

[0018] The semiconductor element 11a and the semiconductor element 11b are each bonded to the upper surface of the heat spreader 12 by a bonding material 30. The bonding material 30 is, for example, a sintered metal material or solder.

[0019] The main terminals 17 are power terminals. The main terminals 17 shown in Fig. 2 are bonded to the semiconductor elements 11a and 11b by a bonding material 31 inside the sealing material 15. This electrically connects the main terminals 17 to the semiconductor elements 11a and 11b. Another main terminal 17 than the one shown in Fig. 2 is bonded to, for example, the heat spreader 12. The bonding material 31 is, for example, a sintered metal material or solder.

[0020] The signal terminals 18 are electrically connected to the semiconductor element 11b through wires 16 inside the encapsulant 15. Each signal terminal 18 is connected through the wire 16 to a signal pad (for example, a gate pad, a current sense pad, or a temperature sense pad) provided on the semiconductor element 11b.

[0021] 1, a region 20a (an example of a first region), which is a selective region of the lower surface 20 of the semiconductor device 10a, is bonded to the heat sink 3 with adhesive 34. Also, as shown in FIG. 1, the semiconductor device 10a is in contact with the heat sink 3 via grease 35 in a region 20b (an example of a second region), which is a region of the lower surface 20 of the semiconductor device 10a other than the region 20a.

[0022] The sealing material 15 is exposed on the surface of the semiconductor device 10a in the region 20a and part of the region 20b, and the metal foil 14 is exposed on the surface of the semiconductor device 10a in the region 20b.

[0023] The area 20a and the area 20b are, for example, flush with each other.

[0024] Region 20b, for example, overlaps with semiconductor elements 11a and 11b in a plan view, and also overlaps with heat spreader 12 in a plan view. Region 20a is, for example, a region in the outer periphery of the underside 20 of semiconductor device 10a, and region 20b is, for example, a region in the central part of the underside 20 of semiconductor device 10a. Region 20a may be, for example, the entire outer periphery of the underside 20 of semiconductor device 10a and surround region 20b, or it may be a part of the outer periphery of the underside 20 of semiconductor device 10a. Region 20b may include a part of the outer periphery of the underside 20 of semiconductor device 10a.

[0025] In the power semiconductor device 1a, heat generated by the semiconductor elements 11a and 11b is transferred to the heat sink 3 through, for example, the heat spreader 12, the insulating material 13, the metal foil 14, and the grease 35. The grease 35 has a higher thermal conductivity than the adhesive 34. Because there is a heat dissipation path from the semiconductor elements 11a and 11b to the heat sink 3 that passes through the grease 35 without passing through the adhesive 34, heat is easily transferred from the semiconductor elements 11a and 11b to the heat sink 3.

[0026] 1, the signal terminals 18 of the semiconductor device 10a are connected to the printed circuit board 2 by a bonding material 33. The bonding material 33 is, for example, solder. The signal terminals 18 are electrically connected to an electric circuit (not shown) formed on the printed circuit board 2.

[0027] 1, the terminal block 4 has an electrode 41 on its upper surface. The terminal block 4 is fixed to the heat sink 3. The main terminal 17 of the semiconductor device 10a is fixed to the terminal block 4 with a bolt 32. The main terminal 17 of the semiconductor device 10a is electrically connected to the electrode 41 of the terminal block 4. The terminal block 4 is configured to have, for example, an electrode (not shown) separate from the electrode 41 to which the main terminal 17 of the semiconductor device 10a is connected, and to allow current to be applied to the semiconductor device 10a from a circuit external to the semiconductor device 10a via the separate electrode.

[0028] FIG. 4 is a plan view of the power semiconductor device 1a as viewed from above. However, in FIG. 4, for clarity, the printed circuit board 2 is omitted. In FIG. 4, a configuration in which the power semiconductor device 1a includes three semiconductor devices 10a is shown, but the number of semiconductor devices 10a included in the power semiconductor device 1a may be one or two, or four or more.

[0029] As described above, the power semiconductor device 1a of the present embodiment includes a semiconductor device 10a, a heat sink 3, grease 35, and an adhesive 34. The semiconductor device 10a includes semiconductor elements 11a and 11b, and a sealing material 15 that seals the semiconductor elements 11a and 11b. A region 20a, which is a selective region on the lower surface 20 of the semiconductor device 10a, is adhered to the heat sink 3 by the adhesive 34. The semiconductor device 10a is in contact with the heat sink 3 via the grease 35 in a region 20b, which is a region other than the region 20a on the lower surface 20 of the semiconductor device 10a.

[0030] In the power semiconductor device 1a of the present embodiment, since the semiconductor device 10a is in contact with the heat sink 3 via the grease 35 in the region 20b, the heat dissipation from the semiconductor elements 11a and 11b is high.

[0031] In the power semiconductor device 1a of the present embodiment, the semiconductor device 10a is adhered to the heat sink 3 by the adhesive 34. By adhering the semiconductor device 10a to the heat sink 3 with the adhesive 34, components for fixing the semiconductor device 10a, such as the support column 51, spring 52, and pressing plate 53 in the power semiconductor device 1z (<Z. Comparative Example> for reference) described below, can be reduced. By reducing these, the semiconductor device 10a can be miniaturized and lightened, and the assembly man-hours can be reduced. Further, when the adhesive 34 surrounds the entire periphery of the grease 35 in plan view, pumping out is suppressed and the product life is improved.

[0032] <Z. Comparative Example> The power semiconductor device 1z of the comparative example is different from the power semiconductor device 1a of the first embodiment in that the semiconductor device 10a is fixed to the heat sink 3 by the pressing plate 53 and the spring 52, instead of being bonded and fixed by the adhesive 34 between the semiconductor device 10a and the heat sink 3. The power semiconductor device 1z is the same as the power semiconductor device 1a of the first embodiment in other respects.

[0033] FIG. 16 is a cross-sectional view of the power semiconductor device 1z of the comparative example. FIGS. 17 and 18 are plan views of the power semiconductor device 1z of the comparative example.

[0034] As shown in FIGS. 17 and 18, the pressing plate 53 is fastened by the support column 51 and the bolt 54. The pressing plate 53 is fixed to the heat sink 3 via the support column 51.

[0035] In FIG. 17, the printed circuit board 2 is omitted for clarity. In FIG. 18, the printed circuit board 2 and the pressing plate 53 are omitted for clarity.

[0036] <B. Second Embodiment> The power semiconductor device 1b of the present embodiment is different from the power semiconductor device 1a of the first embodiment in that the semiconductor device 10b is provided instead of the semiconductor device 10a. The power semiconductor device 1b is the same as the power semiconductor device 1a in other respects.

[0037] The semiconductor device 10b is different from the semiconductor device 10a in that, as shown in FIG. 5, the lower surface is protruded more downward (i.e., toward the heat sink 3 side) in the region 20b than in the region 20a. The semiconductor device 10b is the same as the semiconductor device 10a in other respects.

[0038] In the case of the semiconductor device 1b for power use as well, similar to the case of the semiconductor device 1a for power use, the region 20a of the lower surface 20 of the semiconductor device 10b is adhered to the heat sink 3 by the adhesive 34. Further, the semiconductor device 10b is in contact with the heat sink 3 via the grease 35 in the region 20b of the lower surface 20 of the semiconductor device 10b. The metal foil 14 is exposed on the surface of the semiconductor device 10b in the region 20b of the lower surface 20.

[0039] FIG. 6 is a plan view showing an example of the state of the semiconductor device 10b viewed from below. FIG. 7 is a plan view showing another example of the state of the semiconductor device 10b viewed from below. The region 20a may be the entire outer peripheral portion of the lower surface 20 as shown in FIG. 6 and surround the region 20b in plan view, or may be a part of the outer peripheral portion of the lower surface 20 as shown in FIG. 7. In FIG. 7, the region 20a is a region along two sides facing each other of the rectangular lower surface 20.

[0040] In the semiconductor device 10b, since the lower surface 20 protrudes more downward in the region 20b than in the region 20a, a step exists between the region 20a and the region 20b. The step is formed by the sealing material 15. That is, the side surface portion of the step between the region 20a and the region 20b is covered by the portion 23 of the sealing material 15 that protrudes more downward than the region 20a. The lower surface of the portion 23 of the sealing material 15 is included in the region 20b. That is, the sealing material 15 is exposed in the region 20b. The lower surface of the portion 23 of the sealing material 15 is flush with, for example, the lower surface of the metal foil 14, and the region 20b including the lower surface of the portion 23 of the sealing material 15 and the lower surface of the metal foil 14 is, for example, flat.

[0041] Due to the step between the region 20a and the region 20b, a certain distance between the heat sink 3 and the lower surface 20 can be ensured in the portion of the lower surface 20 that is the region 20a to ensure the strength of the adhesion by the adhesive 34, and the distance between the heat sink 3 and the lower surface 20 can be reduced in the portion of the lower surface 20 that is the region 20b to enhance the heat dissipation performance.

[0042] <C. Embodiment 3> The power semiconductor device 1c of this embodiment is different from the power semiconductor device 1b of Embodiment 2 in that it includes a semiconductor device 10c instead of the semiconductor device 10b. The power semiconductor device 1c is the same as the power semiconductor device 1b in other respects.

[0043] The semiconductor device 10c is different from the semiconductor device 10b in that a groove 230 is provided on the lower surface of the portion 23 of the sealing material 15, that is, the portion of the region 20b where the sealing material 15 is exposed. The semiconductor device 10c is the same as the semiconductor device 10b in other respects. FIG. 8 is a view showing the vicinity of the groove 230 in the power semiconductor device 1c.

[0044] In the power semiconductor device 1c, the grease 35 has entered the groove 230. When the grease 35 enters the groove 230 during the manufacture of the power semiconductor device 1c, the in-plane variation in the thickness of the grease 35 is suppressed, so the assembly accuracy is improved.

[0045] Although the power semiconductor device 1c has been described as having a structure in which the groove 230 is provided with respect to the power semiconductor device 1b of Embodiment 2, the power semiconductor device 1c may have a structure in which the groove 230 is provided with respect to the power semiconductor device 1a of Embodiment 1. Also in this case, the groove 230 is provided in the portion of the region 20b of the lower surface 20 of the semiconductor device 10c where the sealing material 15 is exposed. Also in this case, when the grease 35 enters the groove 230 during the manufacture of the power semiconductor device 1c, the in-plane variation in the thickness of the grease 35 is suppressed, so the assembly accuracy is improved.

[0046] <D. Embodiment 4> The power semiconductor device 1d of this embodiment is different from the power semiconductor device 1b of Embodiment 2 in that it includes a semiconductor device 10d instead of the semiconductor device 10b. The power semiconductor device 1d is the same as the power semiconductor device 1b in other respects.

[0047] The semiconductor device 10d is different from the semiconductor device 10b in that a groove 210 is provided in the region 20a. The semiconductor device 10d is the same as the semiconductor device 10b in other respects. FIG. 9 is a diagram showing the vicinity of the groove 210 in the power semiconductor device 1d.

[0048] The region 20a is, for example, entirely the surface of the encapsulant 15. When a part of the encapsulant 15 is exposed in the region 20a, the groove 210 is provided, for example, in the portion of the region 20a where the encapsulant 15 is exposed.

[0049] In the power semiconductor device 1d, since the adhesive 34 enters the groove 210, the strength of the adhesion between the semiconductor device 10d and the heat sink 3 via the adhesive 34 is improved by the anchor effect.

[0050] The power semiconductor device 1d has been described as having a structure in which a groove 210 is provided with respect to the power semiconductor device 1b of the second embodiment. However, the power semiconductor device 1d may have a structure in which a groove 210 is provided in the region 20a of the power semiconductor device 1a of the first embodiment or the region 20a of the power semiconductor device 1c of the third embodiment.

[0051] <E. Embodiment 5> The power semiconductor device 1e of the present embodiment is different from the power semiconductor device 1b of the second embodiment in that it includes a semiconductor device 10e instead of the semiconductor device 10b. The power semiconductor device 1e is the same as the power semiconductor device 1b in other respects.

[0052] The semiconductor device 10e is different from the semiconductor device 10b in that the encapsulant 15 has a plurality of protrusions 211. The semiconductor device 10e is the same as the semiconductor device 10b in other respects. FIG. 10 is a diagram showing the vicinity of the protrusion 211 in the power semiconductor device 1e.

[0053] As shown in FIG. 10, the protrusion 211 protrudes below the region 20b. The protrusion 211 is provided, for example, at the boundary between the region 20a and the region 20b.

[0054] FIG. 11 is a plan view showing an example of the semiconductor device 10e viewed from below. The protrusions 211 are provided at three locations as shown in FIG. 11, for example. When the protrusions 211 are provided dot-like on the lower surface 20 of the semiconductor device 10e, the protrusions 211 are preferably provided at three or more locations so that the orientation of the semiconductor device 10e is stable when the semiconductor device 10e is pressed against the heat sink 3.

[0055] In the power semiconductor device 1e, the semiconductor device 10e is adhered and fixed to the heat sink 3 by an adhesive 34 in a state where the protrusions 211 are in contact with the heat sink 3.

[0056] Since the protrusions 211 are in contact with the heat sink 3, the contact stress can be increased, and the semiconductor device can be stably fixed to the heat sink 3.

[0057] Although the power semiconductor device 1e has been described as having a structure in which the protrusions 211 are provided with respect to the power semiconductor device 1b of the second embodiment, the power semiconductor device 1e may have a structure in which the protrusions 211 are provided with respect to the power semiconductor devices 1a, 1c, or 1d of the first, third, or fourth embodiments.

[0058] <F. Embodiment 6> In the power semiconductor device 1f of the present embodiment, the height of the upper surface of the electrode 41 of the terminal block 4 is relatively lower with respect to the main terminal 17 than in the power semiconductor device 1b of the second embodiment. The power semiconductor device 1f is the same as the power semiconductor device 1b in other respects. The configuration of the semiconductor device 10f included in the power semiconductor device 1f is the same as the configuration of the semiconductor device 10b included in the power semiconductor device 1b.

[0059] In the power semiconductor device 1f, the height of the lower surface of the main terminal 17 at the boundary between the portion where the main terminal 17 of the semiconductor device 10f protrudes from the encapsulant 15 of the semiconductor device 10f, that is, the portion of the main terminal 17 that is encapsulated by the encapsulant 15 and the portion that is not encapsulated by the encapsulant 15, is higher than the upper surface of the electrode 41 of the terminal block 4.

[0060] FIG. 13 is a view showing the vicinity of the portion where the main terminal 17 of the semiconductor device 10f is fixed to the electrode 41 of the terminal block 4 in the power semiconductor device 1f. Further, FIG. 12 is a view showing the state during manufacturing, after the semiconductor device 10f is disposed on the heat sink 3 and before the main terminal 17 of the semiconductor device 10f is fixed to the electrode 41 of the terminal block 4 (refer to Embodiment 8 for the manufacturing method of the power semiconductor device 1f).

[0061] As shown in FIG. 12, before fastening and fixing the main terminal 17 and the terminal block 4 with the bolt 32 during the manufacture of the power semiconductor device 1f, for example, there is a gap W between the main terminal 17 and the electrode 41 of the terminal block 4 as shown in FIG. 12. By fastening the main terminal 17 to the terminal block 4 with the bolt 32 from such a state, the main terminal 17 is deformed downward and fixed to the terminal block 4. As a result, as shown in FIG. 13, the height of the lower surface of the main terminal 17 at the portion where the main terminal 17 of the semiconductor device 10f protrudes from the sealing material 15 of the semiconductor device 10f becomes higher than the upper surface of the electrode 41 of the terminal block 4.

[0062] When the main terminal 17 is deformed downward and fixed to the terminal block 4, the semiconductor device 10f is pressed against the heat sink 3, and the fixing between the semiconductor device 10f and the heat sink 3 becomes firm.

[0063] The power semiconductor device 1f has been described as having a configuration in which the height of the upper surface of the electrode 41 of the terminal block 4 is relatively lower than that of the main terminal 17, based on the configuration of the power semiconductor device 1b of Embodiment 2. However, the power semiconductor device 1f may have a configuration in which the height of the upper surface of the electrode 41 of the terminal block 4 is relatively lower than that of the main terminal 17, based on the configuration of the power semiconductor devices 1a, 1c, 1d, or 1e of Embodiments 1, 3, 4, or 5. <G. Embodiment 7>

[0064] <G. Embodiment 7> In the power semiconductor devices 1a to 1f according to Embodiments 1 to 6, the semiconductor elements 11a and 11b are semiconductor elements having, for example, a silicon semiconductor.

[0065] The semiconductor device for power applications of the present embodiment (hereinafter referred to as the power semiconductor device 1g) is any one of the power semiconductor devices 1a to 1f of the power semiconductor devices according to Embodiments 1 to 6, and is a power semiconductor device in which at least one of the semiconductor elements 11a and the semiconductor element 11b is a semiconductor element having a wide bandgap semiconductor. Both the semiconductor element 11a and the semiconductor element 11b may be semiconductor elements having a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, SiC, gallium nitride, gallium oxide, or diamond.

[0066] A semiconductor element having a wide bandgap semiconductor has a smaller element size than a semiconductor element having a Si semiconductor. Therefore, when using a semiconductor device including a semiconductor element having a wide bandgap semiconductor, it is often necessary to combine a large number of components such as the semiconductor devices 10a to 10f to form a power module. The power semiconductor devices 1a to 1f are, for example, the power module or a device including the power module.

[0067] When combining a large number of components such as the semiconductor devices 10a to 10f, in the configuration of the power semiconductor device 1z of the above <Z. Comparative Example>, the number of components such as the support column 51, the spring 52, and the pressing plate 53 increases and the cost also increases. However, in the power semiconductor device 1g of the present embodiment, components such as the support column 51, the spring 52, and the pressing plate 53 are unnecessary compared to the power semiconductor device 1z, the number of components can be suppressed, and the cost can be reduced. That is, the configurations of the power semiconductor devices 1a to 1f according to Embodiments 1 to 6 are more effective for suppressing the number of components when at least one of the semiconductor elements 11a and the semiconductor element 11b is a semiconductor element having a wide bandgap semiconductor.

[0068] <H. Embodiment 8> In the present embodiment, a manufacturing method of the power semiconductor devices 1a to 1g according to Embodiments 1 to 7 will be described.

[0069] 14 is a flowchart showing a method for manufacturing a power semiconductor device according to the present embodiment. In the following description, it is assumed that the power semiconductor device to be manufactured is power semiconductor device 1a, but power semiconductor device 1a may be replaced with any of power semiconductor devices 1b to 1g.

[0070] First, in step S1, there are prepared the semiconductor device 10a, the terminal block 4, and the heat sink 3. The terminal block 4 is fixed to the heat sink 3 in advance, for example.

[0071] Next, in step S2, grease 35 is applied to the region 20b of the lower surface 20 of the semiconductor device 10a by, for example, printing.

[0072] Next, in step S3, adhesive 34 is applied to region 20a of lower surface 20 of semiconductor device 10a.

[0073] Next, in step S4, the semiconductor device 10a is placed on the heat sink 3 and fixed by a clamp jig 50. After step S4 is completed, the semiconductor device 10a is placed on the heat sink 3 in a state where it is fixed to the heat sink 3 by the clamp jig 50, as shown in Fig. 15. The semiconductor device 10a is pressed against the heat sink 3 by the clamp jig 50.

[0074] Next, in step S5, with the semiconductor device 10a fixed by the clamp jig 50, the bolts 32 are tightened to fasten the main terminals 17 to the terminal block 4, thereby fixing the main terminals 17 to the terminal block 4. Instead of using the bolts 32, the main terminals 17 may be fixed to the terminal block 4 by welding.

[0075] Next, in step S6, the adhesive 34 is thermally cured while the semiconductor device 10a is fixed by the clamp jig 50. This bonds and fixes the semiconductor device 10a to the heat sink 3. After step S6, the semiconductor device 10a is released from the clamp jig 50.

[0076] Next, in step S7, the semiconductor device 10a fixed to the heat sink 3 is attached to the printed circuit board 2.

[0077] Through the above steps, the power semiconductor device 1a is obtained.

[0078] In steps S2 and S3, the grease 35 and adhesive 34 may be applied to the heat sink 3 instead of the lower surface 20 of the semiconductor device 10a.

[0079] The clamp jig used to fix the semiconductor device 10a in step S5 may be different from the clamp jig used to fix the semiconductor device 10a in step S6.

[0080] By performing steps S5 and S6 with the semiconductor device 10a fixed by the clamp jig 50, the main terminals 17 can be fastened and the adhesive can be thermally cured with the semiconductor device 10a pressed against the heat sink 3, regardless of variations in the amount of grease applied. This allows the semiconductor device 10a and the heat sink 3 to be firmly fixed together.

[0081] In the case of the power semiconductor device 1f of the sixth embodiment, after the semiconductor device 10f is placed on the heat sink 3 in step S4 and before the main terminal 17 is fixed to the terminal block 4 in step S5, in a state where no external force is applied to the main terminal 17, for example, a gap W exists between the lower surface of the main terminal 17 and the electrode 41 of the terminal block 4 (see FIG. 12). From this state, when the main terminal 17 is fixed to the terminal block 4, the main terminal 17 deforms downward and the semiconductor device 10f is pressed against the heat sink 3. This causes the semiconductor device 10f to be more firmly fixed to the heat sink 3.

[0082] After the semiconductor device 10f is placed on the heat sink 3 in step S4 and before the main terminal 17 is fixed to the terminal block 4 in step S5, the lower surface of the main terminal 17 and the upper surface of the electrode 41 of the terminal block 4 may be at the same height. In this case, too, when the main terminal 17 is fastened to the terminal block 4 with, for example, bolts 32, the main terminal 17 is fixed to the terminal block 4, and the main terminal 17 is deformed downward, pressing the semiconductor device 10f against the heat sink 3.

[0083] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate. [Explanation of symbols]

[0084] 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1z power semiconductor device, 2 printed circuit board, 3 heat sink, 4 terminal block, 10a, 10b, 10c, 10d, 10e, 10f semiconductor device, 11a, 11b semiconductor element, 12 heat spreader, 13 insulating material, 14 metal foil, 15 sealing material, 16 wire, 17 main terminal, 18 signal terminal, 20 underside, 20a, 20b area, 30, 31 bonding material, 32 bolt, 33 bonding material, 34 adhesive, 35 grease, 41 electrode, 50 clamp jig, 51 support, 52 spring, 53 holding plate, 54 bolt, 210, 230 groove, 211 protrusion, W gap.

Claims

1. a semiconductor device; A heat sink; Grease and Adhesive and A terminal block and Equipped with the semiconductor device includes a semiconductor element, a sealing material that seals the semiconductor element, and a power terminal that is electrically connected to the semiconductor element; a first region, which is a selective region on the underside of the semiconductor device, is bonded to the heat sink with the adhesive; the semiconductor device is in contact with the heat sink via the grease in a second region of the lower surface of the semiconductor device, the second region being a region other than the selective region; The terminal block has electrodes on an upper surface thereof, the power terminal of the semiconductor device is fixed to the terminal block and electrically connected to the electrode of the terminal block; the first region is a region that surrounds the entire periphery of the second region in a plan view, the sealing material is exposed in the second region, a first groove is provided in a portion of the second region where the sealing material is exposed, the first groove is disposed within a region surrounded by the first region, and the grease enters the first groove; Power semiconductor devices.

2. 2. The power semiconductor device according to claim 1, the first region is a region of the outer periphery of the lower surface of the semiconductor device; Power semiconductor devices.

3. 3. The power semiconductor device according to claim 1, Further comprising a circuit board; the semiconductor device further includes a signal terminal electrically connected to the semiconductor element; the signal terminal is connected to the circuit board; Power semiconductor devices.

4. 4. The power semiconductor device according to claim 1, the second region protrudes toward the heat sink more than the first region on the underside of the semiconductor device; a side portion of a step between the first region and the second region is covered with the sealing material; Power semiconductor devices.

5. 5. The power semiconductor device according to claim 1, The semiconductor device includes a wide bandgap semiconductor. Power semiconductor devices.

6. 6. The power semiconductor device according to claim 5, The wide bandgap semiconductor is a SiC semiconductor. Power semiconductor devices.

7. 7. The power semiconductor device according to claim 1, The terminal block is fixed to the heat sink. Power semiconductor devices.

8. 8. The power semiconductor device according to claim 1, a lower surface of the power terminal at a portion where the power terminal protrudes from the sealing material is higher than an upper surface of the electrode of the terminal block; Power semiconductor devices.

9. 9. The power semiconductor device according to claim 1, the power terminals of the semiconductor device are fixed to the electrodes of the terminal block, thereby pressing the semiconductor device against the heat sink; Power semiconductor devices.

10. A method for manufacturing a power semiconductor device according to any one of claims 1 to 9, comprising the steps of: providing the semiconductor device and the heat sink; With the semiconductor device fixed by a clamp jig, the adhesive is thermally cured to bond the semiconductor device and the heat sink together. A method for manufacturing a power semiconductor device.

11. A method for manufacturing a power semiconductor device according to any one of claims 1 to 9, comprising the steps of: preparing the semiconductor device, the terminal block, and the heat sink; placing the semiconductor device on the heat sink; and fixing the power terminals to the terminal block while the semiconductor device is placed on the heat sink and fixed by a clamping jig. A method for manufacturing a power semiconductor device.

12. 12. The method for manufacturing a power semiconductor device according to claim 11, After the semiconductor device is placed on the heat sink and fixed by a clamp jig that is the same as or different from the clamp jig, the adhesive is thermally cured to bond the semiconductor device and the heat sink together. A method for manufacturing a power semiconductor device.

13. 13. The method for manufacturing a power semiconductor device according to claim 11, further comprising the steps of: The semiconductor device is pressed against the heat sink by fixing the power terminal and the terminal block together. A method for manufacturing a power semiconductor device.

14. A method for manufacturing a power semiconductor device according to any one of claims 1 to 9, comprising the steps of: preparing the semiconductor device, the terminal block, and the heat sink; placing the semiconductor device on the heat sink; fixing the power terminal and the terminal block together in a state in which the semiconductor device is placed on the heat sink; The semiconductor device is pressed against the heat sink by fixing the power terminal and the terminal block together. A method for manufacturing a power semiconductor device.

15. 15. A method for manufacturing a power semiconductor device according to claim 13, further comprising the steps of: When the semiconductor device is placed on the heat sink and before the power terminal and the terminal block are fixed to each other, a gap exists between the lower surface of the power terminal and the electrode of the terminal block when no external force is applied to the power terminal. A method for manufacturing a power semiconductor device.

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