Photoconductive semiconductor switches fabricated laterally alongside GaN-on-Si field-effect transistors
The integration of GaN transistors and PCSS devices on a single chip using regrown gallium nitride material and transparent dielectric layers addresses switching speed and voltage limitations, enabling high-voltage, ultra-fast switching with compact integration.
Patent Information
- Application Number
- JP2023559708
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-04-01
- Filing Date
- 2022-03-30
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2042-03-30
AI Technical Summary
Conventional GaN-on-Si high-electron-mobility transistor switches are limited by switching speed and breakdown voltage, and existing GaN PCSS structures are standalone devices requiring separate integration with transistors and light sources.
An integrated circuit structure with a gallium nitride layer supporting both a transistor and a photoconductive semiconductor switch, integrated monolithically or via wafer-to-wafer bonding, using regrown gallium nitride material and transparent dielectric layers for optical control.
Enables high-voltage switching with ultra-fast speeds and compact integration of GaN transistors and PCSS devices, allowing independent control and functionality on a single chip.
Smart Images

Figure 0007720921000001 
Figure 0007720921000002 
Figure 0007720921000003
Abstract
Description
[Background technology]
[0001] The present disclosure is directed to improved gallium nitride (GaN) integrated circuit technology, particularly to structures including both GaN photoconductive semiconductor switches (PCSS) and / or photoconductive switching transistors and GaN transistors, and associated integrated circuit structures.
[0002] Currently, on-chip GaN-on-Si high-electron-mobility transistor (HEMT) switches and RF devices are controlled by electrical signals and are limited by the design and fabrication constraints of conventional semiconductor devices. For example, switching speed is limited by the device geometry and on / off current ratio. Another example involves the device's breakdown voltage. Breakdown voltage is the maximum voltage a device can handle before catastrophic failure. This voltage is determined by the breakdown of the HEMT semiconductor material and / or dielectric when the electric field peak at the drain side, a function of the applied drain bias and the gate-to-drain distance, exceeds the material's breakdown field. Current state-of-the-art GaN HEMT switches, operating in a safe operating region below the breakdown voltage, have a maximum operating voltage of approximately 650 V. Photoconductive semiconductor switches (PCSSs) and photoconductive switching transistors are different devices that offer high-voltage switching capabilities, ultrafast switching speeds, or fast energy pulses, switched by light rather than by a bias applied by a metal gate. This potentially increases operating voltage compared to conventional GaN HEMT switches and RF devices.
[0003] Furthermore, existing GaN PCSS structures are standalone devices fabricated through non-planar lift-off-based processes and connected to transistors, integrated circuits (ICs), and light sources (e.g., lasers and light-emitting diodes) as part of larger modules, either by wire bonding or circuit board designs.
[0004] What is needed for maximum performance and functional density are compactly integrated photoconductive semiconductor switches and photoconductive switching transistors. Summary of the Invention
[0005] In accordance with the present disclosure, there is provided an integrated circuit structure including a substrate having an upper surface, a gallium nitride layer disposed on the upper surface of the substrate, wherein the substrate and the gallium nitride layer comprise a wafer, and a photoconductive semiconductor switch disposed laterally alongside a transistor on the gallium nitride layer incorporated within the integrated circuit structure, wherein regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operably coupled to the wafer.
[0006] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include that the substrate comprises at least one of a silicon material and a silicon carbide material.
[0007] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include that the transistor comprises a field effect transistor.
[0008] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include that the photoconductive semiconductor switch includes a first electrical contact and a second electrical contact disposed on the GaN layer.
[0009] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include: the photoconductive semiconductor switch includes an aluminum gallium nitride layer disposed on a gallium nitride-on-silicon wafer; a first electrical contact and a second electrical contact disposed laterally on the gallium nitride layer of the wafer, away from the mesa; and a regrown gallium nitride material deposited over each of the first electrical contact and the second electrical contact, and disposed on the gallium nitride between the first electrical contact and the second electrical contact.
[0010] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include at least one of the regrown gallium nitride material and the gallium nitride layer forming a photoconductive circuit.
[0011] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include: the photoconductive semiconductor switch includes an aluminum gallium nitride layer disposed on a gallium nitride-on-silicon wafer; the first electrical contact and the second electrical contact are on a mesa disposed on the aluminum gallium nitride layer; an AlGaN-GaN two-dimensional electron-gas interface is present; windows are etched in the AlGaN layer; and a regrown GaN layer is deposited in the windows.
[0012] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include a regrown GaN layer disposed on the exposed gallium nitride layer at the window.
[0013] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include an integrated circuit structure further including a transparent silicon dioxide dielectric insulating layer configured to insulate the transistor from each of the first and second electrical contacts of the photoconductive semiconductor switch.
[0014] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include an integrated circuit structure further including a light source optically coupled to the photoconductive semiconductor switch.
[0015] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include the photoconductive semiconductor switch and the transistor each being configured to be utilized separately or interdependently.
[0016] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include a photoconductive semiconductor switch homogeneously integrated with a transistor on the gallium nitride-on-silicon wafer and configured to control the transistor.
[0017] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively further include the photoconductive semiconductor switch being homogeneously integrated with a transistor within the gallium nitride on silicon wafer and configured to be controlled by the transistor.
[0018] Further embodiments of any of the foregoing embodiments may additionally and / or alternatively include the dielectric and intermediate layers being transparent to the light source utilized to trigger the photoconductive semiconductor switch.
[0019] Further details of GaN-on-Si heterogeneous technology are provided in the following detailed description and accompanying drawings, in which like reference numerals represent like elements. [Brief explanation of the drawings]
[0020] [Figure 1] 1 is a schematic cross-sectional view of an exemplary lateral integrated circuit structure;
[0021] [Figure 2] FIG. 1 is a schematic cross-sectional view of an exemplary GaN PCSS.
[0022] [Figure 3] FIG. 1 is a schematic cross-sectional view of an exemplary GaN PCSS. DETAILED DESCRIPTION OF THE INVENTION
[0023] Referring to FIG. 1 , a lateral integrated circuit structure 10 is shown. The lateral integrated circuit structure 10 includes a transistor 12 electrically coupled to a PCSS 14, each laterally integrated and supported on a common substrate 16. The transistor 12 may be a FET, such as a GaN transistor, a Si transistor, and associated integrated circuit structures. The PCSS 14 may include a GaN PCSS. The substrate 16 may include silicon (Si) or a silicon carbide material (SiC). The substrate 16 includes a top surface 18.
[0024] A gallium nitride (GaN) layer is disposed on top surface 18 of substrate 16 to form GaN-on-Si wafer 22. GaN layer 20 supports transistor 12 and PCSS 14 in tandem such that transistor 12 and PCSS 14 are laterally integrated and incorporated into the same integrated circuit.
[0025] FET 12 includes an aluminum gallium nitride (AlGaN) layer 24 disposed on GaN layer 20. FET 12 includes a silicon nitride dielectric (SiN / dielectric) layer 26 disposed on AlGaN layer 24 adjacent each of the drain D, gate G, and source S of FET 12. A silicon dioxide dielectric (SiO2 / dielectric) layer 28 insulates the circuitry of transistor 12 as well as an intermediate layer 30, here SiNx, and a conductive interconnect 31 disposed within silicon dioxide dielectric layer 28. Dielectrics 28, 26, and intermediate layer 30 may be transparent to a light source 32 utilized to trigger the conductive path of PCSS 14. In an exemplary embodiment, if the dielectric or intermediate layer is not transparent, a window may be provided in the film to allow light transmission.
[0026] The PCSS 14 may include a first electrical contact 34 (PCSS-1) and a second electrical contact 36 (PCSS-2) disposed on the GaN layer. In an exemplary embodiment, a silicon dioxide dielectric layer 28 insulates each of the first and second electrical contacts 34 and 36 of the photoconductive semiconductor switch 14. In an exemplary embodiment, the dielectric layer 28 may be a silicon nitride or silicon dioxide material, or the like. In other exemplary embodiments, the first and second electrical contacts 34 and 36 do not have dielectric insulation. The photoconductive semiconductor switch 14 is typically a highly resistive region of a semiconductor material (such as GaN) that is doped, for example, unintentionally or with deep levels such as carbon or iron. This allows the material to block a significant amount of voltage with very low leakage current. However, when illuminated with a light source 32 having energy above or near the bandgap energy, a large amount of excited carriers are generated. These excited carriers form a low-resistance conductive path used for switching. The PCSS 14 provides high voltage switching capability, ultra-fast switching speeds, or fast energy pulses. The input voltage to the transistor 12 can be controlled by the on / off state of the PCSS 14, or vice versa.
[0027] 2 and 3, the GaN PCSS 14 can be fabricated on the wafer 22 in a variety of ways.
[0028] 2, in an exemplary embodiment, PCSS 14 may include a substrate 16 having a GaN layer 20 disposed thereon, which constitutes a wafer 22. First electrical contact 34 and second electrical contact 36 are formed on GaN layer 20 of wafer 22. Laterally arranged off- Mesa (off-mesa) Regrowth GaN material 40 is deposited over each of first electrical contact 34 and second electrical contact 36, and over gallium nitride layer 20 between first electrical contact 34 and second electrical contact 36, such that either regrown GaN material 40 and / or GaN layer 20 form photoconductive circuit 42.
[0029] 3, in an exemplary embodiment, PCSS 14 may include a substrate 16 having a GaN layer 20 disposed thereon, which constitutes wafer 22. First electrical contact 34 and second electrical contact 36 are disposed on AlGaN layer 24 such that an AlGaN-GaN two-dimensional interface (2DEG interface) exists. ,on- Mesa (on-mesa) The AlGaN layer 24 can be etched to form a GaN window 38 in the 2DEG layer 24. Regrown GaN 40 can be deposited in the window 38 in place of the gate metal (not shown). The regrown GaN 40 is formed on the exposed GaN layer 20 in the window 38 etched from the AlGaN layer 24.
[0030] The present disclosure provides photoconductive semiconductor switches and photoconductive switching transistors integrated monolithically or via wafer-to-wafer bonding or die stacking with transistors and light sources. To achieve this, subtractive planar processing techniques are required.
[0031] Technical advantages of the present disclosure include the direct integration of optical gate switches with GaN-on-Si process flows, enabling the high voltage capability and fast response time inherent in optical gate switches.
[0032] Another technical advantage of the present disclosure includes a structure comprising a single chip / wafer containing both GaN-on-Si transistor devices and GaN PCSS devices, where the final device has the functionality of the GaN transistor, Si transistor, and GaN PCSS utilized separately or interdependently.
[0033] Another technical advantage of the present disclosure includes a PCSS device controlling or being controlled by GaN+Si devices homogeneously integrated within the same wafer.
[0034] Another technical advantage of the present disclosure includes structures with multiple options of photoconductive materials, such as AlGaN / GaN-based substrates with free-standing or bonded regrown AlGaN / GaN, or AlGaN / GaN 2DEGs connected by narrow regions of photoconductive AlGaN / GaN material.
[0035] Another technical advantage of the present disclosure includes regrown AlGaN / GaN that can be configured and tuned independently of the epitaxial GaN in the substrate. Configuration and tuning parameters can include shape / thickness, doping, and concentration / stoichiometry.
[0036] Another technical advantage of the present disclosure includes that the method for fabricating GaN PCSS may be layer subtraction based using techniques traditional to Si foundries.
[0037] Another technical advantage of the present disclosure includes that both GaN PCSS transistors and GaN / Si transistors are fabricated simultaneously using the same processing steps.
[0038] Another technical advantage of the present disclosure includes the addition of PCSS to GaN-on-Si devices, which is an important addition, because it utilizes layers and structures not used in standalone GaN-on-Si devices or standalone PCSS devices.
[0039] Another technical advantage of the present disclosure includes that, unlike GaN-on-Si devices, the 2DEG layer must be completely buried.
[0040] Another technical advantage of the present disclosure includes that, unlike typical PCSS devices, an AlGaN / GaN high electron mobility transistor (HEMPT) epi substrate is used, as opposed to a bulk substrate optimized for photosensitivity.
[0041] A GaN-on-Si heterogeneous technology has been provided. While the GaN-on-Si heterogeneous technology has been described in the context of specific embodiments thereof, other unforeseen alternatives, modifications, and variations will be apparent to those skilled in the art upon reading the foregoing description. Accordingly, it is intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.
Claims
1. 1. An integrated circuit structure comprising: a substrate having a top surface; a gallium nitride layer disposed on the top surface of the substrate, the substrate and the gallium nitride layer comprising a wafer; a photoconductive semiconductor switch disposed laterally alongside a transistor on the gallium nitride layer integrated within the integrated circuit structure; a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operably coupled to the wafer; Integrated circuit structure.
2. 10. The integrated circuit structure of claim 1, wherein the substrate comprises at least one of a silicon material and a silicon carbide material.
3. The integrated circuit structure of claim 1 , wherein the transistor comprises a field effect transistor.
4. 10. The integrated circuit structure of claim 1, wherein said photoconductive semiconductor switch comprises a first electrical contact and a second electrical contact disposed on said gallium nitride layer.
5. 5. The integrated circuit structure of claim 4, wherein the transistor comprises an aluminum gallium nitride layer disposed on a gallium nitride-on-silicon wafer, the first electrical contact and the second electrical contact are off-mesa on the gallium nitride layer of the wafer disposed laterally spaced from the transistor, and the regrown gallium nitride material is deposited over each of the first and second electrical contacts and is disposed on the gallium nitride layer between the first and second electrical contacts.
6. The integrated circuit structure of claim 5 wherein at least one of the regrown gallium nitride material and the gallium nitride layer forms a photoconductive circuit.
7. 5. The integrated circuit structure of claim 4, wherein the photoconductive semiconductor switch comprises an aluminum gallium nitride layer disposed on a gallium nitride-on-silicon wafer, the first electrical contact and the second electrical contact are on-mesa disposed on the aluminum gallium nitride layer, an AlGaN-GaN two-dimensional electron gas interface exists, a window is etched in the AlGaN layer, and a regrown gallium nitride layer is deposited in the window.
8. 8. The integrated circuit structure of claim 7, wherein said regrown gallium nitride layer is disposed on an exposed gallium nitride layer in said window.
9. 5. The integrated circuit structure of claim 4, further comprising a transparent silicon dioxide dielectric insulating layer configured to insulate each of the first and second electrical contacts of the photoconductive semiconductor switch from the transistor.
10. 10. The integrated circuit structure of claim 1, further comprising a light source optically coupled to said photoconductive semiconductor switch.
11. 10. The integrated circuit structure of claim 1, wherein the photoconductive semiconductor switch and the transistor are utilized independently or interdependently.
12. 10. The integrated circuit structure of claim 1, wherein said photoconductive semiconductor switch is monolithically integrated with and controls said transistor on a gallium nitride-on-silicon wafer.
13. 6. The integrated circuit structure of claim 5, wherein the dielectric and intermediate layers disposed on the aluminum gallium nitride layer are transparent to a light source utilized to trigger the photoconductive semiconductor switch.
Citation Information
Patent Citations
Optical switch
JP2017049389A
Semiconductor device
JP2020004921A
Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems
US20100019279A1
Gallium Nitride Based Ultra-Violet Sensor With Intrinsic Amplification and Method of Operating Same
US20210043793A1
Optical device, semiconductor substrate, optical device producing method, and semiconductor substrate producing method
WO2010140370A1