Semiconductor device design method and semiconductor device design device

Abstract

This makes it possible to design a semiconductor device while adjusting the dopant concentration distribution in the lateral direction as well as the depth direction in the semiconductor device. [Solution] A semiconductor device design method includes a step of using a process simulator to process simulate dopant concentration distributions in LDD ion implantation regions and halo ion implantation regions provided on at least one side of a gate structure while changing the lateral moment of the dopant along the channel length direction of the gate structure.

Description

[Technical Field]

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and more particularly to a semiconductor device design method and apparatus. [Background technology]

[0002] 2. Description of the Related Art Technology CAD (TCAD) is used to simulate the manufacturing processes and electrical characteristics of various types of semiconductor devices, thereby designing the semiconductor devices.

[0003] For example, in the technology of designing MOSFETs, a method of calibrating a simulation by TCAD is disclosed (Patent Document 1). This document discloses a technology for adjusting the main parameters of a process simulation based on the measurement results of the electrical characteristics of an actual device using a transmission electron microscope (TEM), secondary ion mass spectrometry (SIMS), capacitance-voltage characteristic measurement, etc.

[0004] Also, for example, a method for calibrating the CV characteristic curve of a MOS capacitor in a TCAD simulation has been disclosed (Patent Document 2). An actual MOS capacitor is created, its CV characteristics are measured, and the fitting value of the gate oxide film thickness and the actual channel doping concentration are calculated. Then, according to the obtained gate oxide film thickness and channel doping concentration, the gate oxide film thickness and channel doping concentration are calibrated in the TCAD simulation to calculate the CV characteristic curve of the MOS capacitor. This process makes it possible to reproduce the measurement results of the CV characteristic curve of the MOS capacitor using the TCAD simulation.

[0005] Also, for example, a method for simulating an SRAM-type FPGA single-event upset effect is disclosed (Patent Document 3). In this document, the design and process parameters of a semiconductor device are set, a three-dimensional geometric shape of the semiconductor device is constructed using a modeling tool, the doped region and doping concentration are calibrated according to the IV characteristic curve, and the characteristics of incident heavy ions are acquired, and a single-event effect simulation is performed using a TCAD simulation method. Then, depending on the simulation results, particles with different energies are selected and the simulation is repeated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Chinese Patent Application Publication No. 102184879 [Patent Document 2] Chinese Patent Application Publication No. 107622959 [Patent Document 3] Chinese Patent Application Publication No. 103577643 Summary of the Invention [Problem to be solved by the invention]

[0007] Incidentally, the relationship between the channel length L and the threshold voltage Vt (Vt-L characteristics) of a MOSFET, as shown in Fig. 9, is affected by the lateral diffusion of the LDD ion-implanted regions (extensions) EX and halo ion-implanted regions (halos) HA in the LDD structure, as shown in Fig. 10. In conventional TCAD calibration, the impurity concentrations in the depth direction of the MOSFET extensions EX and halo HA are measured by secondary ion mass spectrometry (SIMS), and calibration is performed based on the impurity concentration profile obtained by this measurement.

[0008] However, while secondary ion mass spectrometry (SIMS) can analyze the impurity profile in the depth direction of MOSFETs, it is difficult to measure the lateral impurity profile along the channel length. Furthermore, energy dispersive X-ray spectroscopy (EDS) cannot obtain measurement intensity in low-concentration impurity regions, and scanning capacitance microscopy (SCM) and scanning microwave microscopy (SMM) lack high spatial resolution. Therefore, it is difficult to reproduce actual Vt-L characteristics through simulations using only calibration based on these measurement data. Furthermore, simply changing the impurity diffusion coefficient in simulations changes the impurity profile not only in the lateral direction but also in the depth direction, resulting in inaccurate results. [Means for solving the problem]

[0009] One aspect of the present invention is a method for designing a MOS-type semiconductor device using a process simulator, comprising the steps of: performing process simulation of dopant concentration distributions in an LDD ion implantation region and a halo ion implantation region provided on at least one side of a gate structure, while changing a lateral moment of the dopant along a channel length direction of the gate structure.

[0010] Here, it is preferable to further include a step of simulating the characteristics of a MOS type semiconductor device to which the dopant concentration distributions in the LDD ion implantation region and the Halo ion implantation region obtained in the process simulating step are applied, and to execute the process simulating step while changing the lateral moment so that the characteristics obtained in the device simulating step approach characteristics actually measured in a MOS type semiconductor device.

[0011] It is also preferable that the change of the lateral moment includes the steps of reading the lateral moment from a process simulator that executes the process simulation, changing the read lateral moment, and writing the changed lateral moment to the process simulator.

[0012] It is also preferable that the conductivity type of the impurity in the LDD ion implantation region is opposite to that of the impurity in the Halo ion implantation region.

[0013] Preferably, the MOS semiconductor device further comprises source and drain regions formed by conductive source / drain implantation on either side of the gate structure.

[0014] Another aspect of the present invention is a MOS-type semiconductor device design apparatus using a process simulator, characterized by comprising means for process-simulating dopant concentration distributions in an LDD ion implantation region and a halo ion implantation region provided on at least one side of a gate structure while changing a lateral moment of the dopant along a channel length direction of the gate structure.

[0015] Here, it is preferable to further include a device simulation means for simulating the characteristics of a MOS type semiconductor device to which the dopant concentration distributions in the LDD ion implantation region and the Halo ion implantation region obtained by the process simulation means are applied, and the process simulation is performed while changing the lateral moment so that the characteristics obtained by the device simulation means approach the characteristics actually measured in the MOS type semiconductor device.

[0016] Furthermore, it is preferable that the lateral moment is changed by performing a process of reading the lateral moment from a process simulator that executes the process simulation, a process of changing the read lateral moment, and a process of writing the changed lateral moment to the process simulator.

[0017] It is also preferable that the conductivity type of the impurity in the LDD ion implantation region is opposite to that of the impurity in the Halo ion implantation region.

[0018] Preferably, the MOS semiconductor device further comprises source and drain regions formed by conductive source / drain implantation on either side of the gate structure. [Effects of the Invention]

[0019] According to the present invention, it is possible to design a semiconductor device while adjusting the dopant concentration distribution in the lateral direction as well as the depth direction of the semiconductor device. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device design apparatus according to an embodiment of the present invention; [Figure 2] 1 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention; [Figure 3] FIG. 1 is a flowchart showing a semiconductor device design method according to an embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing an example of parameters set in an ion implantation process according to an embodiment of the present invention. [Figure 5] FIG. 10 is a flowchart showing a parameter change process according to an embodiment of the present invention. [Figure 6] 10A and 10B are diagrams showing examples of dopant concentration distributions in an LDD ion implantation region and a halo ion implantation region obtained by the semiconductor device design process according to the embodiment of the present invention. [Figure 7]10A and 10B are diagrams showing examples of dopant concentration distributions in an LDD ion implantation region and a halo ion implantation region obtained by the semiconductor device design process according to the embodiment of the present invention. [Figure 8] 10A and 10B are diagrams illustrating examples of characteristics obtained by a semiconductor device design process according to an embodiment of the present invention. [Figure 9] FIG. 1 is a diagram showing an example of characteristics obtained by a conventional semiconductor device design process. [Figure 10] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0021] [Configuration of semiconductor device design system] 1, a semiconductor device design apparatus 100 according to an embodiment of the present invention includes a processing unit 10, a storage unit 12, an input unit 14, an output unit 16, and a communication unit 18. The semiconductor device design apparatus 100 is capable of communicating with the outside via an information communication network 102 such as the Internet.

[0022] The processing unit 10 includes a means for performing arithmetic processing, such as a CPU. The processing unit 10 executes the process simulator program and the device simulator program stored in the storage unit 12 to realize the functions of the semiconductor device design apparatus 100 according to the present embodiment. The storage unit 12 includes storage means, such as a semiconductor memory or a memory card. The storage unit 12 is accessible to the processing unit 10 and stores the process simulator program, the device simulator program, and information required for processing them. The input unit 14 includes a means for inputting information. The input unit 14 includes, for example, a keyboard, a touch panel, buttons, etc., for receiving input from an administrator who executes the simulation. The output unit 16 includes a means for outputting information required for processing the semiconductor device design apparatus 100, such as a user interface screen (UI) for receiving input information from the administrator. The output unit 16 includes, for example, a display for displaying images to the administrator. The communication unit 18 includes an interface for communicating with external devices via the information and communication network 102. Communication by the communication unit 18 may be wired or wireless.

[0023] The information and communication network 102 is not limited to the Internet, but may be any network that can be communicatively connected to the semiconductor device design apparatus 100. The information and communication network 102 may be, for example, a dedicated line, a public line (telephone line, mobile communication line, etc.), a wired LAN (Local Area Network), a wireless LAN, etc., or may be a combination of these with the Internet.

[0024] In this embodiment, the design object is a MOS type semiconductor device, MOSFET 200. Fig. 2 shows the cross-sectional structure of the element of MOSFET 200, which is the design object.

[0025] The MOSFET 200 includes a substrate 20, an isolation region 22, a source region 24, a drain region 26, an LDD ion-implanted region 28, a halo ion-implanted region 30, a gate insulating layer 32, and a gate electrode .

[0026] The following description will be given taking an n-channel MOSFET 200 as an example, but is not limited to this and may be a p-channel MOSFET 200. In this case, the first conductivity type and the second conductivity type may be interchanged.

[0027] The substrate 20 is a substrate on whose surface the MOSFET 200 is formed. The substrate 20 may be, for example, a silicon substrate. However, the substrate 20 is not limited to a silicon substrate and may be a semiconductor substrate made of other materials. The substrate 20 has a first conductivity type. The substrate 20 may be, for example, a p-type. The element isolation region 22 is an insulating region for insulating adjacent elements. The element isolation region 22 is provided so as to surround the region where the MOSFET 200 is formed. The element isolation region 22 may be a shallow trench isolation (STI) region.

[0028] The source region 24 and the drain region 26 are disposed on either side of the gate electrode 34. The source region 24 and the drain region 26 are of a second conductivity type. The source region 24 and the drain region 26 may be, for example, an n-type. The dopant concentration of the source region 24 and the drain region 26 is, for example, 1×10 19 / cm 3 More than 1×10 21 / cm 3 It is preferable to set the following:

[0029] The LDD ion implantation regions 28 are regions that extend from the ends of the source region 24 and the drain region 26 on the gate electrode 34 side toward the gate electrode 34. The LDD ion implantation regions 28 are provided to reduce the effects of hot carriers caused by the acceleration of electron and hole carriers due to a high electric field in the channel region below the gate electrode 34. The LDD ion implantation regions 28 are of the same second conductivity type as the source region 24 and the drain region 26. The LDD ion implantation regions 28 may be of, for example, n-type. The LDD ion implantation regions 28 have a dopant concentration lower than the dopant concentration of the source region 24 and the drain region 26. The LDD ion implantation regions 28 are formed by implanting ions at a low concentration using the gate electrode 34 as a mask.

[0030] The halo ion implantation region 30 is formed to surround the LDD ion implantation region 28. The halo ion implantation region 30 is of the same first conductivity type as the channel region of the MOSFET 200. The halo ion implantation region 30 may be, for example, p-type. By providing the halo ion implantation region 30, the dopant concentration at both ends of the channel increases, and the contribution increases as the channel length shortens. As a result, the occurrence of the short channel effect, which reduces the threshold voltage (Vt) as the channel length shortens, can be suppressed, and leakage current can be reduced. The halo ion implantation region 30 can be formed in a self-aligned manner by performing oblique ion implantation after forming the gate electrode 34.

[0031] The gate insulating layer 32 is an insulating layer that constitutes the gate of the MOSFET 200. The gate insulating layer 32 is provided so as to straddle between the source region 24 and the drain region 26 in the surface region of the substrate 20. The gate insulating layer 32 may be formed of a silicon oxide layer (SiO2), a silicon nitride layer (SiN), a silicon oxynitride film (SiO x N y The thickness of the gate insulating layer 32 may be set appropriately depending on the characteristics of the MOSFET 200.

[0032] The gate electrode 34 is an electrode for applying a voltage to the gate of the MOSFET 200. The gate electrode 34 is formed on the gate insulating layer 32. The gate electrode 34 may be, for example, a polysilicon layer, a metal layer, a silicide, or a laminated structure of these. The film thickness of the gate electrode 34 may be set depending on the characteristics required for the MOSFET 200.

[0033] [Semiconductor device design method] A method for designing the MOSFET 200 according to this embodiment will now be described. Fig. 3 is a flowchart showing the method for designing the MOSFET 200 according to this embodiment.

[0034] First, a process simulation for manufacturing semiconductor devices was performed. For the process simulation, Synopsys' Sentauras and Taurus TCAD simulators were used.

[0035] This embodiment is characterized by the simulation of the ion implantation process of the LDD ion implantation region 28 and the halo ion implantation region 30 that constitute the gate structure of the MOSFET 200, and therefore the description will focus on this process. Note that the same process simulation as in the past can be applied to other components of the MOSFET 200.

[0036] In step S10, an initial setting process for the process simulation is performed. The process in this step causes the semiconductor device design device 100 to function as an initial setting means. A user uses the input unit 14 to input various parameters to be used in the process simulation to the semiconductor device design device 100. The various parameters may be acquired from an external device via the communication unit 18.

[0037] In step S12, a simulation is performed for a process preceding the ion implantation process for the LDD ion implantation region 28 and the halo ion implantation region 30. The processing in this step causes the semiconductor device design apparatus 100 to function as a preceding stage simulation means. The processing in this step can be performed in the same manner as conventional process simulation, and therefore a description thereof will be omitted.

[0038] In step S14, a simulation of the ion implantation process is performed. Through the processing in this step, the semiconductor device design apparatus 100 functions as an ion implantation simulation means. In this step, a simulation of the ion implantation process for the LDD ion implantation region 28 and the halo ion implantation region 30 is performed using the set parameters.

[0039] 4 shows an example of parameters used in the ion implantation simulation, in which the LDD ion implantation region 28 and the Halo ion implantation region 30 are set as a dual Pearson distribution.

[0040] The parameters include the type of dopant, the angle of ion implantation, and the dose of the dopant. In this example, the type of dopant is boron, the angle of ion implantation θ is 7°, and the dose of the dopant is 1×10 14 / cm 2 The angle θ of ion implantation indicates the angle with respect to a line perpendicular to the surface of the substrate 20, as shown in FIG.

[0041] The parameters include ion implantation energy, the material of the substrate 20, and parameters Rp, sigma (σ), gamma (γ), beta (β), and Lsigma, ratio related to the dual Pearson distribution. In this example, each parameter is set for an ion implantation energy of 10 to 100 keV. Here, the parameters related to the dual Pearson distribution include Rp (Projection Range), σ (Standard Deviation), γ, and β. Rp is also called the first moment parameter and indicates the average depth reached by ions in the ion implantation process. σ is also called the second moment parameter and indicates the standard deviation indicating how far the distribution spreads from Rp. γ is also called the third moment parameter and indicates the asymmetry of the distribution. β is also called the fourth moment parameter and indicates the sharpness of the shape near the peak of the distribution.

[0042] In this embodiment, the parameters further include Lsigma and Ratio. Lsigma is called the lateral moment. While σ is a parameter indicating the standard deviation indicating how much the dopant concentration distribution spreads in the depth direction of the substrate 20, Lsigma is a parameter indicating the standard deviation indicating how much the dopant concentration distribution spreads in the lateral direction (channel length direction) of the substrate 20.

[0043] In a typical simulation, L sigma is set to a fixed ratio with respect to σ when a process simulation is performed. In contrast, the present embodiment is characterized in that L sigma is set arbitrarily with respect to σ when a process simulation is performed.

[0044] Ratio is a parameter indicating the ratio of the first Pearson distribution F1 to the second Pearson distribution F2 in a dual Pearson distribution obtained by adding together the first Pearson distribution F1 and the second Pearson distribution F2. In this embodiment, ratio indicates the ratio of the first Pearson distribution F1 to the entire dual Pearson distribution. The second Pearson distribution F2 is similar to the first Pearson distribution F1, so a description thereof will be omitted.

[0045] The above parameters are set for the LDD ion implantation region 28 and the halo ion implantation region 30, respectively, and the ion implantation process for the LDD ion implantation region 28 and the halo ion implantation region 30 is simulated using these parameters.

[0046] In step S16, a simulation is performed for a process subsequent to the ion implantation process for the LDD ion implantation region 28 and the halo ion implantation region 30. The processing in this step causes the semiconductor device design apparatus 100 to function as a subsequent stage simulation means. The processing in this step can be performed in the same manner as conventional process simulation, and therefore a description thereof will be omitted.

[0047] In step S18, a device simulation is performed. For the device simulation, Sentauras and Taurus manufactured by Synopsys are used as TCAD simulators. Through the processing in this step, the semiconductor device design apparatus 100 functions as a device simulation means. The semiconductor device design apparatus 100 executes a device simulation for a semiconductor device having a configuration obtained in the process simulation performed in steps S10 to S16. This determines the characteristics of the semiconductor device. In this embodiment, a device simulation is performed for the MOSFET 200, including characteristics showing the dependency of the threshold voltage Vt on the channel length L. The results of the device simulation are stored in the storage unit 12 and presented to the user by the output unit 16.

[0048] In step S20, it is determined whether the simulation is to be terminated. By the processing in this step, the semiconductor device design apparatus 100 functions as an end determination means. If the simulation is not to be terminated, the processing proceeds to step S22; otherwise, the simulation is terminated.

[0049] The termination determination may be a determination as to whether the characteristics of the semiconductor device obtained in the device simulation in step S18 satisfy the design requirements. For example, if the dependency of the threshold voltage Vt on the channel length L of MOSFET 200 obtained in the device simulation in step S18 satisfies the design requirements required for the actual MOSFET 200, it is determined that the simulation is to be terminated; if not, the process proceeds to step S22 and the simulation is repeated.

[0050] However, the characteristics of the semiconductor device used for the end determination are not limited to the dependency of the threshold voltage Vt on the channel length L, and other characteristics of the semiconductor device may be used.

[0051] In step S22, a parameter change process is performed. By the process in this step, the semiconductor device design apparatus 100 functions as a parameter change unit. In this embodiment, a process for changing parameters related to the simulation of ion implantation in step S14 is performed. Specifically, a process for adjusting Lsigma, which indicates the lateral moment for each implantation parameter in the ion implantation process, is performed.

[0052] Lsigma may be adjusted automatically or may be set by the user using the input unit 14. When Lsigma is adjusted automatically, for example, the value of Lsigma may be increased or decreased at a constant rate from the initial value.

[0053] 5 shows a flowchart of the parameter change process. In step S30, parameters are read from the process simulator executed by the semiconductor device design apparatus 100 (parameter read means). For example, a process of reading the current value of Lsigma is performed. In step S32, a process of changing the value of the read parameter is performed. For example, a process of multiplying the current value of Lsigma by a constant α and updating it to a new value is performed. In step S34, a process of writing the changed parameter to the process simulator is performed. For example, the new value of Lsigma changed in step S32 is written to the process simulator.

[0054] When the processing in step S22 is completed, the processing returns to step S14, and the processing is repeated from the ion implantation process simulation using the newly set parameters.

[0055] [Example of semiconductor device design] 6 shows an example of the results of a process simulation of ion implantation into the LDD ion-implanted region 28 and the halo ion-implanted region 30 of the MOSFET 200, performed by applying the semiconductor device design method according to this embodiment. FIG. 7 shows the change in dopant concentration along a line extending in the channel length direction shown in FIG.

[0056] Fig. 6(a) shows the distribution of dopant concentrations in the LDD ion implantation region 28 and the halo ion implantation region 30 when Lsigma (Lσ) is set in the same manner as in the conventional semiconductor device design method. Fig. 6(b) shows the distribution of dopant concentrations in the LDD ion implantation region 28 and the halo ion implantation region 30 when the value of Lsigma (Lσ) for the LDD ion implantation region 28 is set to twice the conventional value. Fig. 6(c) shows the distribution of dopant concentrations in the LDD ion implantation region 28 and the halo ion implantation region 30 when the value of Lsigma (Lσ) for the halo ion implantation region 30 is set to 1.5 times the conventional value.

[0057] Figure 7(a) shows the variation of the dopant concentration along a line along the channel length direction for the dopant concentration distributions shown in Figures 6(a) and 6(b), and Figure 7(b) shows the variation of the dopant concentration along a line along the channel length direction for the dopant concentration distributions shown in Figures 6(a) and 6(c).

[0058] As shown in FIGS. 6 and 7, by adjusting the value of Lsigma (Lσ) for the LDD ion implantation region 28 and the halo ion implantation region 30, the dopant concentration distribution along the lateral direction (channel length direction) of the LDD ion implantation region 28 and the halo ion implantation region 30 is changed.

[0059] FIG. 8 shows the dependency of threshold voltage Vt on channel length L obtained by a device simulator for MOSFET 200 after the MOSFET 200 was designed by a process simulator.

[0060] 8, by adjusting the values of Lsigma (Lσ) for the LDD ion implantation region 28 and the halo ion implantation region 30, it is possible to obtain the dependency of the threshold voltage Vt on the channel length L that reflects the dopant concentration distribution of each of the LDD ion implantation region 28 and the halo ion implantation region 30. Figure 8 shows, as examples, a case where Lsigma (Lσ) is set as in the conventional semiconductor device design method as a reference value (ref), a case where the value of Lsigma (Lσ) for the LDD ion implantation region 28 is set to twice the conventional value (extension Lσ×2), and a case where the value of Lsigma (Lσ) for the halo ion implantation region 30 is set to 1.5 times the conventional value (halo Lσ×1.5).

[0061] As described above, according to this embodiment, it is possible to design a semiconductor device while adjusting the dopant concentration distribution in the lateral direction in addition to the depth direction in the semiconductor device.

[0062] The description of each embodiment disclosed herein will be given sequentially, focusing on differences from other embodiments. Identical or similar parts between the embodiments may be referred to. Since the device embodiments correspond to the method embodiments, the description will be relatively brief, and the details may be referred to the method embodiments.

[0063] The above description is of some preferred embodiments of the present invention and is not intended to limit its scope in any way. Variations and modifications made by those skilled in the art based on the above teachings are within the scope of the appended claims. [Explanation of symbols]

[0064] 10 processing unit, 12 memory unit, 14 input unit, 16 output unit, 18 communication unit, 20 substrate, 22 element isolation region, 24 source region, 26 drain region, 28 LDD ion implantation region, 30 Halo ion implantation region, 32 gate insulating layer, 34 gate electrode, 100 semiconductor device design device, 102 information communication network.

Claims

1. A method for designing a MOS semiconductor device using a process simulator, comprising: For an LDD ion implantation region and a halo ion implantation region provided on at least one side of a gate structure, a process simulation is performed on a dopant concentration distribution in the LDD ion implantation region and the halo ion implantation region while changing a lateral moment of a dopant along a channel length direction of the gate structure; performing a device simulation of characteristics of a MOS type semiconductor device to which the dopant concentration distributions in the LDD ion implantation region and the Halo ion implantation region obtained in the process simulation step are applied, performing the process simulation step while changing the lateral moment so that the characteristics obtained in the device simulation step satisfy design requirements for the characteristics of a MOS type semiconductor device; The method for designing a semiconductor device includes the steps of: reading the lateral moment from a process simulator that executes the process simulation; modifying the read lateral moment; and writing the modified lateral moment to the process simulator, wherein when a standard deviation of the dopant concentration distribution in the depth direction of the substrate is σ and the lateral moment, which is the standard deviation of the dopant concentration distribution in the channel length direction of the substrate, is Lsigma, Lsigma is not set to a constant ratio with respect to σ but is set arbitrarily with respect to σ.

2. 2. The semiconductor device design method according to claim 1, The change in the lateral moment is reading the lateral moment from a process simulator that performs the process simulation; modifying the retrieved lateral moment; writing the modified lateral moment to the process simulator; A semiconductor device design method comprising:

3. 2. The semiconductor device design method according to claim 1, The semiconductor device design method is characterized in that the conductivity type of the impurity in the LDD ion implantation region is opposite to the conductivity type of the impurity in the Halo ion implantation region.

4. 4. The semiconductor device design method according to claim 3, 10. A method for designing a semiconductor device, wherein the MOS type semiconductor device further comprises source and drain regions on either side of said gate structure formed by conductive source / drain implants.

5. A MOS type semiconductor device design device using a process simulator, a means for performing a process simulation of dopant concentration distributions in an LDD ion implantation region and a halo ion implantation region provided on at least one side of a gate structure while changing a lateral moment of a dopant along a channel length direction of the gate structure; means for performing device simulation of characteristics of a MOS type semiconductor device to which the dopant concentration distributions in the LDD ion implantation region and the Halo ion implantation region obtained by the process simulation means are applied, performing the process simulation while changing the lateral moment so that the characteristics obtained by the device simulation means satisfy design requirements for the characteristics of a MOS type semiconductor device; The change of the lateral moment comprises the steps of reading the lateral moment from a process simulator that executes the process simulation, changing the read lateral moment, and writing the changed lateral moment to the process simulator, wherein when a standard deviation of the dopant concentration distribution in the depth direction of the substrate is σ and the lateral moment, which is the standard deviation of the dopant concentration distribution in the channel length direction of the substrate, is Lsigma, Lsigma is not set to a constant ratio with respect to σ but is set arbitrarily with respect to σ.

6. 6. The semiconductor device design apparatus according to claim 5, 10. The semiconductor device design apparatus according to claim 9, wherein the conductivity type of the impurity in the LDD ion implantation region is opposite to the conductivity type of the impurity in the Halo ion implantation region.

7. 7. The semiconductor device design apparatus according to claim 5, The change in the lateral moment is reading the lateral moment from a process simulator that executes the process simulation; modifying the retrieved lateral moment; writing the modified lateral moment to the process simulator; A semiconductor device design device characterized by performing the above.

8. 6. The semiconductor device design apparatus according to claim 5, 10. A semiconductor device design apparatus, comprising: a MOS type semiconductor device further comprising a source region and a drain region formed by conductive source / drain implantation on either side of said gate structure.

Images