Transceiver for supplying high voltage for erase or program operations in a non-volatile memory system - Patents.com

Abstract

Numerous embodiments of a transceiver are disclosed that provides a high voltage for use during erase or program operations in a non-volatile memory system. In one embodiment, the transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, the transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 276,842, filed November 8, 2021, entitled "High Voltage Transceiver for Non-Volatile Memory System," and U.S. Patent Application No. 17 / 585,261, filed January 26, 2022, entitled "Transceiver for Providing High Voltages for Erase or Program Operations in a Non-Volatile Memory System."

[0002] FIELD OF THE INVENTION Numerous embodiments of a transceiver for providing high voltages for erase or program operations in a non-volatile memory system are disclosed. [Background technology]

[0003] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 (the "'130 patent") discloses an array of split-gate nonvolatile memory cells, a type of flash memory cell, which is incorporated herein by reference. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending above and toward the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased (where electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to tunnel through the intermediate insulator from the floating gate 20 to the word line terminal 22 by Fowler-Nordheim (FN) tunneling.

[0005] The memory cell 110 is programmed (electrons are placed on the floating gate) by hot electron source side injection (SSI) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased of electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased state, or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed state, or "0" state.

[0007] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 110 of FIG. 1 [Table 1]

[0008] Other types of flash memory cells are known, including other split-gate memory cell configurations.

[0009] For example, FIG. 2 shows a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0010] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 210 of FIG. 2 [Table 2]

[0011] Figure 3 shows another type of flash memory cell, a three-gate memory cell 310. Memory cell 310 is identical to memory cell 210 of Figure 2, except that memory cell 310 does not have a separate control gate. Erase operations (erasure occurs using the erase gate) and read operations are similar to those of memory cell 210 of Figure 2, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during the program operation to compensate for the lack of control gate bias.

[0012] Table 3 shows typical voltage and current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 310 of FIG. 3 [Table 3]

[0013] 4 shows another type of flash memory cell, a stacked gate memory cell 410. Memory cell 410 is similar to memory cell 110 of FIG. 1, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the floating gate (FG) to the substrate, and programming is accomplished by FN tunneling of electrons from the channel region 18 to the substrate. region The read operation is performed by channel hot electron (CHE) injection in the region between source region 14 and drain region 16, and is performed by electrons flowing from source region 14 toward drain region 16, similar to memory cell 110 of FIG. 1, at a high control gate voltage.

[0014] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 410 and substrate 12 to perform read, erase, and program operations on memory cell 410. Table 4: Operation of flash memory cell 410 of FIG. 4 [Table 4]

[0015] Other known non-volatile memory cells include FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron RAM).

[0016] As indicated above, non-volatile memory systems often require high voltages (e.g., voltages greater than the core voltage Vdd of the non-volatile memory array, such as 3.3 V or 5.0 V) for program and erase operations. Numerous techniques exist in the prior art for generating and supplying such high voltages to the appropriate memory cell terminals during program or erase operations. These techniques may utilize high voltage generation and transceiver circuitry. The high voltage generation and transceiver circuitry consumes a significant amount of power within a non-volatile memory system.

[0017] What is needed is an improved high voltage generation and transceiver circuit that consumes less power than prior art circuits. Summary of the Invention

[0018] Numerous embodiments of a transceiver for supplying high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, the transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, the transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.

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[0033] [Brief explanation of the drawings]

[0034] [Figure 1] 1 shows a prior art split-gate flash memory cell. [Figure 2] 1 illustrates another prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates a non-volatile memory system. [Figure 6] 1 shows an example of a high voltage generator. [Figure 7] 2 shows another example of a high voltage generator. [Figure 8A] 1 shows a high voltage transceiver. [Figure 8B] 1 shows a force-sense high voltage transceiver. [Figure 9] 2 shows another example of a high voltage transceiver. [Figure 10] 1 shows an example of a high voltage level shifter. [Figure 11] 2 shows another example of a high voltage level shifter. [Figure 12] 1 illustrates an example of a high voltage transceiver charge pump. [Figure 13] 1 illustrates an example of a high voltage transceiver regulator. [Figure 14] 1 shows an example of a charge pump stage. [Figure 15] 1 illustrates a non-volatile memory system with a high voltage transceiver. DETAILED DESCRIPTION OF THE INVENTION

[0035] 5 shows a non-volatile memory system 500. The non-volatile memory system 500 includes an array 501, a row decoder 502, a high voltage decoder 503, a column decoder 504, a bit line driver 505, control logic 506, a bias generator 507, a sense amplifier 508, and a high voltage generator 509.

[0036] Array 501 includes a plurality of nonvolatile memory cells arranged in rows and columns, each of which may be, for example, memory cell 110 of Figure 1, memory cell 210 of Figure 2, memory cell 310 of Figure 3, memory cell 410 of Figure 4, or any other type of nonvolatile memory cell.

[0037] Row decoder 502 selects one or more rows in array 501 for a program, erase, or read operation.

[0038] High voltage decoder 503 couples a high voltage to one or more rows in array 501 during a program or erase operation.

[0039] Column decoder 504 is coupled to all columns in array 501 and comprises a multiplexer for selecting one or more columns in array 501 during a read, program, or erase operation.

[0040] Bit line driver 505 supplies voltage to one or more selected columns during a program or erase operation.

[0041] The control logic 506 performs the read, program, or erase operations.

[0042] The bias generator 507 generates low voltages (e.g., voltages equal to or lower than the core voltage Vdd of the nonvolatile memory system 500) required for read, program, and erase operations. The high voltage generator 509 generates high voltages (e.g., voltages higher than the core voltage Vdd) required for program and erase operations through the high voltage decoder 503.

[0043] Sense amplifier 508 senses the value stored in a selected cell in a selected column during a read operation.

[0044] The following embodiments may be used in the high voltage generator 509 to reduce the power supply required by the high voltage generator 509 and / or to reduce the total power required by the high voltage generator 509 compared to prior art high voltage generators.

[0045] FIG. 6 shows a high voltage generator 600 comprising a high voltage pump and regulator 601 , a high voltage transceiver pump 602 , a high voltage transceiver 603 , and a pad 604 .

[0046] High voltage pump and regulator 601 receives a power supply voltage Vdd and an enable signal En, and generates a high voltage VHV, which is higher than Vdd, required for a program or erase operation (for example, but not limited to, voltage VHV in the range of 4V to 13V). High voltage pump and regulator 601 can include, for example, one or more charge pumps, regulators, and / or one or more high voltage level shifters.

[0047] A high voltage transceiver (HV TX) pump 602 receives a power supply voltage Vdd and an enable signal EN and generates a high voltage VHVTX that is higher than Vdd, for example, but not limited to, in the range of 6V to 15V as needed for operation of the HV transceiver 603. VHVTX is typically selected to be greater than VHV.

[0048] The high voltage transceiver pump 602 may comprise, for example, one or more charge pumps and / or one or more high voltage level shifters.

[0049] High voltage transceiver 603 receives high voltages VHV and VHVTX and a high voltage transceiver enable signal En_HVTX and controllably outputs a high voltage VHV2 (which high voltage VHV2 is selectably equal to high voltage VHV or VHVTX minus any threshold voltage drop created within high voltage transceiver 603) to VPP pad 604, or receives an external high voltage at VPP pad 604 and outputs that voltage on an internal VHV node for internal use. Receiving an external high voltage at VPP pad 604 and outputting that voltage to an internal VHV node is needed during various voltage stress tests (such as oxide stress tests) performed during manufacturing, for example, to screen for defects in array 501 or control logic 506. VPP pad 604 is an HV electrical terminal (e.g., an HV pad or pin).

[0050] The HV transceiver 603 can also monitor and / or measure an internal high voltage (i.e., a high voltage VHV or VHVTX). For example, the HV transceiver 603 can be used to trim the high voltage VHV to a target voltage (e.g., 11.5V for erasing or 10.5V for programming) by applying an HV trim algorithm to adjust the trim setting.

[0051] HV transceiver 603 also, in some embodiments, provides a high voltage during testing of array 501, such as high-volume testing, which is a process of testing multiple memory cells in parallel to reduce test time. For example, HV transceiver 603 can provide more power from an external high-voltage power supply via VPP pad 604 to replace or supplement power-limited internal HV charge pump circuitry. HV transceiver 603 thus allows the chip to utilize an external voltage source during the test process, resulting in lower area overhead and less power compared to situations where all of these voltages are generated on-chip.

[0052] 7 shows a high voltage generator 700 comprising a high voltage pump and regulator 701, a high voltage transceiver 702, and a VPP pad 703. The VPP pad 703 is an HV electrical terminal (eg, an HV pad or pin).

[0053] High voltage pump and regulator 701 receives a power supply voltage Vdd and an enable signal En and generates a high voltage VHV that is higher than voltage Vdd. High voltage pump and regulator 701 may include, for example, one or more charge pumps and / or one or more high voltage level shifters.

[0054] High voltage transceiver 702 receives a high voltage VHV from high voltage pump and regulator 701, as well as a high voltage transceiver enable signal En_HVTX. High voltage transceiver 702 can receive the high voltage VHV and output a high voltage VHV2 to a VPP pad 703, or can receive an externally generated high voltage supplied to VPP pad 703 and output that voltage to an internal VHV node (shown to the left of high voltage transceiver 702 in FIG. 7).

[0055] Figure 8A shows a high-voltage transceiver 800 that can be used in the high-voltage transceiver 603 of Figure 6 or the high-voltage transceiver 702 of Figure 7. The high-voltage transceiver 800 comprises a PMOS transistor 801 and a native NMOS transistor 802, arranged in a series configuration as shown, with a first terminal of the PMOS transistor 801 coupled to a first node 803 shown to receive a high voltage VHV, a second terminal of the PMOS transistor 801 coupled to a first terminal of the native NMOS transistor 802 at node 804, and a second terminal of the native NMOS transistor 802 coupled to a second node 805 shown as a VPP pad. The PMOS transistor 801 receives the high voltage VHV at its input, i.e., its first terminal, and the native NMOS transistor 802 outputs a high voltage VHV2 at a second node, the VPP pad (which may be the VPP pad 604 of Figure 6 or the VPP pad 703 of Figure 7). The PMOS transistor 801 and the NMOS transistor 802 are arranged in a cascode configuration, and there is high input-output isolation. The high voltage VHV is also called the first high voltage, and the high voltage VHV2 is also called the second high voltage.

[0056] The high voltage VHV is, for example, 12V. The PMOS transistor 801 receives the voltage VGP2 at its gate. When the PMOS transistor 801 conducts, this voltage approaches an intermediate voltage such as Vdd (for example, 1.8V representing "0") (the source / drain is the high voltage VHV which is 12V in this embodiment, and the VTP (threshold voltage) of the PMOS transistor 801 is typically <1V). The use of such a voltage (in this case, Vdd) at the gate of the PMOS transistor 801 reduces the voltage stress across the PMOS 801 (for example, by 1.8V, that is, stress voltage = 12V - 1.8V).

[0057] The native NMOS transistor 802 receives the voltage VGN2 at its gate. The native NMOS transistor 802 conducts when VGN2 exceeds the source voltage (near the high voltage VHV) by the threshold voltage VTN of the native NMOS transistor 802. For example, when VTN having a body effect is 0.7V, the native NMOS transistor 802 conducts when VGN2 is 12.7V. When it is desired that the native NMOS transistor 802 does not conduct or the high voltage transceiver 800 is not activated, the gate of the native NMOS transistor 802 can be connected to ground.

[0058] When the high voltage transceiver 800 is enabled by VGP2 and VGN2, the high voltage VHV2 on the VPP pad becomes approximately equal to the high voltage when VHV > VGP2 (= Vdd in this example) + VTP (due to the turn-on voltage of the PMOS). In this case, enabling the high voltage transceiver 800 is done by setting VGP2 = Vdd or 0V, VGN2 > 12.7V. In this case, when the high voltage transceiver 800 is disabled by setting VGP2 = VHV, or connecting the gate of the native NMOS 802 to ground, or setting VGN2 to an intermediate voltage such as Vdd, the voltage on the VPP pad is floating.

[0059] In another embodiment, the gate of PMOS transistor 801 can receive ground (0V) instead of VGP2.

[0060] 8B shows a high voltage transceiver 820 comprising a first circuit 811 and a second circuit 812. For example, the first circuit 811 can be used to sense a voltage VHV on a node 825 at a VPP1 pad 826, and the second circuit 812 can be used to force a voltage on a VPP2 pad 827 to the node 825.

[0061] 8A. In one mode, the input to the first circuit 811 is VHV on node 825, and the output is a high voltage VHV2 on VPP1 pad 826. In another mode, the input to the first circuit 811 is an externally generated high voltage supplied to VPP1 pad 826, and the output is a high voltage supplied to node 825.

[0062] The second circuit 812 comprises a PMOS 823 and a native NMOS 824, which are similar in function to the PMOS 821 and native NMOS 822. In one mode, the input to the second circuit 812 is a high voltage VHV on node 825, and the output is a high voltage VHV3 on a VPP2 pad 827. In another mode, the input to the first circuit 812 is an externally generated high voltage supplied to the VPP2 pad 827, and the output is a high voltage supplied to node 825.

[0063] In operation, one of the first circuit 811 and the second circuit 812 is used to supply a high voltage from the VPP1 pad 826 or the VPP2 pad 827, respectively, to node 825, and the other of the first circuit 811 and the second circuit 812 supplies a high voltage to the VPP1, VPP2 pads, respectively, from node 825. In other words, a voltage from one of the VPP1 pad 826 or the VPP2 pad 827 is forced to node 825, and the other of the VPP1 pad 826 or the VPP2 pad 827 can be used to sense the voltage at node 825.

[0064] 9 shows a high-voltage transceiver 900 that can be used for the high-voltage transceiver 603 of FIG. 6 or the high-voltage transceiver 702 of FIG. 7. The high-voltage transceiver 900 operates similarly to the high-voltage transceiver 800 of FIG. 8A. The high-voltage transceiver 900 includes a PMOS transistor 901, a native NMOS transistor 902, and an NMOS transistor 903, arranged in a cascode configuration as shown, providing high input-to-output isolation. The PMOS transistor 901 and the NMOS transistor 903 receive a high voltage VHV as an input, and the native NMOS transistor 902 outputs a high voltage VHV2 to its output node, a VPP pad 904 (which may be the VPP pad 604 of FIG. 6 or the VPP pad 703 of FIG. 7).

[0065] The high voltage VHV is, for example, 12V. The PMOS transistor 901 receives the voltage VGP2 at its gate, and the voltage VGP2 is set near Vdd when the PMOS transistor 901 is conducting. The NMOS transistor 903 connected in parallel with the PMOS transistor 901 receives the voltage VGN1A at its gate and requires a high voltage of VHV + VT (the threshold voltage of the NMOS transistor 903) to conduct. The native NMOS transistor 902 receives the voltage VGN2 at its gate. When it is desired that the native NMOS transistor 902 does not conduct or the high voltage transceiver 900 is not enabled, the gate of the native NMOS transistor 902 can be connected to ground. The native NMOS transistor 902 conducts when the voltage VGN2 exceeds the source voltage (approximately VHV) by the threshold voltage VTN of the native NMOS transistor 902. For example, when the threshold voltage VTN is 0.7V, the native NMOS transistor 902 conducts when VGN2 is 12.7V. The NMOS 903 is used to pass the voltage VHV when the high voltage VHV < VGP2 + VTP, in which case the PMOS 901 is not turned on.

[0066] In another embodiment, the transceiver 900 can have another circuit path of PMOS, NMOS, and native NMOS in parallel, as described above in relation to Figure 8B, to perform the forced application and sensing functions.

[0067] Figure 10 shows a high voltage level shifter (HV LS) 1000 that can be used in the high voltage pump and regulator 601 and 701 and the high voltage transceiver pump 602. The HV LS 1000 outputs either the high voltage VHV or ground to the output node HVLSO or HVLSO_B in response to the state of the signal EN.

[0068] High voltage level shifter 1000 includes inverters 1009 and 1010, NMOS transistors 1003, 1004, 1007, and 1008, and PMOS transistors 1001, 1002, 1005, and 1006 as shown.

[0069] The high-voltage level shifter 1000 receives a signal EN as an input (where "0" is ground and "1" is Vdd) and outputs voltages HVLSO and its complement, HVLSO_B, which can have a voltage level equal to VHVSUP (e.g., 12V), where HVLSO and its complement, HVLSO_B, have a larger voltage swing than the signal EN. For example, when EN is "1", its voltage is Vdd. HVLSO is also "1", its voltage is VHVSUP (e.g., 12V), and HVLSO_B is grounded. Similarly, when EN is "0", its voltage is grounded. HVLSO is also "grounded" and HVLSO_B becomes VHVSUP (e.g., 12V).

[0070] 11 shows a high voltage level shifter (HV LS) 1100 that can be used in high voltage pumps and regulators 601 and 701 and high voltage transceiver pump 602. High voltage level shifter 1100, in the configuration shown, comprises inverters 1102 and 1103, a level shifter 1101, and PMOS transistors 1104, 1105, 1106, and 1107. HV LS 1100 outputs either a high voltage VHV or Vdd at output node 1108.

[0071] Level shifter 1100 receives EN_HV as an input and outputs EN_HVLSO and its complement, EN_HVLSO_B, which can have a voltage level equal to VHVSUP (e.g., 12V) and have a larger voltage swing than EN. For example, when EN="1", EN_HVLSO is="1", =VHVSUP (e.g., 12V), and has a higher voltage than EN. Level shifter 1101 can optionally comprise high-voltage level shifter 1000 of FIG. 10. Inverters 1102 and 1103 generate signals EN_LV and EN_LV_B as shown.

[0072] When EN_HV is high, EN_LV is low, EN_LV_B is high, EN_HVLSO is high, and EN_HVLSO_B is low, which turns on PMOS transistors 1104 and 1105 and turns off PMOS transistors 1106 and 1107. As a result, output node 1108 is at the high voltage VHV.

[0073] When EN_HV is low, EN_LV is high, EN_LV_B is low, EN_HVLSO is low, and EN_HVLSO_B is high, which results in PMOS transistors 1104 and 1105 being turned off and PMOS transistors 1106 and 1107 being turned on, resulting in output node 1108=Vdd.

[0074] 12 shows a high-voltage transceiver charge pump (HVTXCP) 1200. The high-voltage transceiver charge pump 1200 receives an input of a high voltage VHV and generates a voltage OUT at node 1205. A native NMOS transistor 1204 is connected in a diode configuration. The input high voltage VHV is applied to the gate / drain of the native NMOS transistor 1204, and therefore VHV-VTN is the resulting voltage at its source as the internal voltage IN.

[0075] High-voltage clock signal CK_HVLSO and its complement CK_HVLSO_B are generated by high-voltage level shifter 1201. CK_HVLSO is applied to one lead of capacitor 1202, which supplies an internal voltage IN by CK_HVLSO during the high cycle. That voltage is received by native NMOS transistor 1203 connected in a diode configuration to generate a voltage OUT at node 1205 equal to (VHV-VTN)+V(CK_HSLSO)-VTN. V(CK_HVLSO) is the voltage of signal CK_HVLSO, which may be a divided voltage from high voltage VHV, denoted VHV_DIV.

[0076] For example, if the high voltage VHV=12V, VHV_DIV=4V, and VTN=0.7V, then the output voltage OUT=14.6V on node 1205. HVTXCP 1200 can be used to provide a high level >VHV+VTN for signal VGN2 for circuits 800 and 900.

[0077] The capacitor 1202 and the diode-connected NMOS 1203 constitute one charge pump stage. Since the HVTXCP 1203 has a high voltage VHV input and the pump clock has its power supply VHV_DIV, only one charge pump stage is needed, i.e., it has a high voltage VHV as its power supply and input to generate an output voltage > VHV + VTN. Optionally, there may be multiple charge pump stages.

[0078] 13 shows a high voltage transceiver regulator (HVTXREG) 1300 comprising a PMOS transistor 1301, an NMOS transistor 1302, and a current source 1303. PMOS 1301 and NMOS transistor 1302 are arranged in a cascode configuration to provide high input-output isolation to buffer the high voltage VHV_TX from the current source bias 1303. The NMOS transistor receives Vdd at its gate, and PMOS transistor 1301 receives the high voltage VHV at its gate. HVTXREG 1300 clamps the voltage on the source of PMOS 1301, i.e., voltage VHV_TX, to VHV+VTP because above this voltage, PMOS 1301 turns on, causing current to flow from VHV_TX to NMOS 1302 and from there to ground by current source 1303. This circuit can be used, for example, to regulate the output of HVTXCP 1200 to VHV+VTP. Multiple diodes (e.g., diode-connected PMOS transistors) can be placed from the VHV_TX supply node to the source of PMOS 1301 to provide a regulated high voltage on the VHV_TX node, e.g., =VHV+2 * VTP can be increased.

[0079] FIG. 14 shows a charge pump stage 1400 that can be used as the charge pump stage of the HVTXCP of FIG. 12. The charge pump stage 1400 includes capacitors 1401 and 1402 and native NMOS transistors 1403 and 1404, constituting a VT cancellation charge pump stage. The pumping capacitor 1401 is coupled to a clock signal CK1A at one terminal and to an input 1405 IN at the other terminal. The boost capacitor 1402 is coupled to a clock signal CK1B at one terminal and to the gate of a pass transistor native NMOS transistor 1404 at the other terminal. The drain and source of the native NMOS 1404 are coupled to the input 1405 IN at one terminal and to the output 1406 OUT at the other terminal. The source and drain of the native NMOS 1403 are coupled to the input 1405 IN at one terminal and to the gate of the NMOS 1404 at the other terminal. The gate of native NMOS 1403 is coupled to output 1406 OUT. CK1B is the inverse of CK1A.

[0080] In operation, clock signals CK1A and CK1B oscillate 90 degrees out of phase with each other. A voltage OUT at output 1406 is provided equal to the voltage at IN 1405 plus the peak voltage of CK1A.

[0081] 15 illustrates a non-volatile memory system 1500 similar to the non-volatile memory system 500 of FIG. 5, but including a high-voltage transceiver 1501 as part of the high-voltage generator 509. The high-voltage transceiver 1501 may be one of the high-voltage transceivers described above, such as high-voltage transceivers 603, 702, 800, 820, and 900. The high-voltage transceiver 1501 supplies a high voltage to the high-voltage decoder 503, which in turn applies the high voltage to one or more selected cells in the array 501 during an erase or program operation.

[0082] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A transceiver for a non-volatile memory system, the transceiver comprising: a PMOS transistor having a first terminal coupled to the first node, a second terminal, and a gate; a native NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor, a second terminal coupled to a second node, and a gate; the transceiver is capable of supplying a first high voltage to the first node in response to receiving a second high voltage at the second node, and capable of supplying a third high voltage to the second node in response to receiving a fourth high voltage at the first node, the first high voltage being equal to the second high voltage, and the third high voltage being equal to the fourth high voltage.

2. 2. The transceiver of claim 1, wherein the gate of the PMOS transistor receives a voltage that is less in magnitude than the first high voltage.

3. 10. The transceiver of claim 1, wherein an output signal of the transceiver is coupled to the non-volatile memory system for use in an erase or program operation of the non-volatile memory system.

4. 2. The transceiver of claim 1, wherein the gate of the native NMOS transistor is connected to ground when the transceiver is disabled.

5. 10. The transceiver of claim 1, further comprising a charge pump.

6. The transceiver of claim 1, further comprising a second PMOS transistor and a second native NMOS transistor forming a circuit path.

7. 1. A transceiver for a non-volatile memory, the transceiver comprising: a PMOS transistor having a first terminal, a second terminal, and a gate; an NMOS transistor having a first terminal coupled to the first terminal of the PMOS transistor coupled to a first node, a second terminal, and a gate; a native NMOS transistor having a first terminal coupled to the second terminal of the PMOS transistor and the second terminal of the NMOS transistor, a second terminal coupled to a second node, and a gate; the transceiver selectively supplies a first high voltage to the other of the first node and the second node in response to receiving a second high voltage at one of the first node and the second node.

8. 8. The transceiver of claim 7, wherein the first high voltage is used during an erase or program operation in a flash memory.

9. 8. The transceiver of claim 7, wherein the gate of the PMOS transistor receives a voltage that is less in magnitude than the first high voltage.

10. 8. The transceiver of claim 7, wherein the gate of the native NMOS transistor is connected to ground when the transceiver is not operating.

11. 8. The transceiver of claim 7, further comprising a charge pump.

12. 8. The transceiver of claim 7, further comprising a second PMOS transistor and a second native NMOS transistor forming a circuit path.

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