Semiconductor device, semiconductor device manufacturing method, and power conversion device

Abstract

To provide a technique capable of suppressing peeling between a sealing resin and a semiconductor element while suppressing lowering of productivity and increase in manufacture cost, in a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor element 1 diced in a quadrangular shape in top view from a semiconductor wafer 10, and a sealing resin 2 for sealing the semiconductor element 1. The semiconductor element 1 has a cell region 3 in which a main current flows, a terminal region 4 provided on the outer peripheral side of the cell region 3, and a protective film 5 covering the upper surface of the outer peripheral part of the terminal region 4. The protective film 5 has an extension part 5a extending up to the outermost end in four corners of the semiconductor element 1. The extension part 5a has a cut surface 5a continuous to a cut surface 4a of the terminal region 4 and does not extend up to the outermost end in four sides excluding the four corners of the semiconductor element 1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been commercially available in which reliability has been improved by covering semiconductor elements with an epoxy resin-based sealing resin.

[0003] In conventional semiconductor devices, the polyimide at the dicing line is generally opened to prevent clogging of the blade when dicing semiconductor elements from a semiconductor wafer, reducing productivity, and to prevent chipping on the periphery of the semiconductor element. As a result, there is a section of the semiconductor element that is missing polyimide for about 10 μm from the outermost edge.

[0004] When a semiconductor device formed by covering such a semiconductor element with an encapsulating resin is subjected to a temperature cycle test or the like, peeling occurs between the encapsulating resin and the semiconductor element from the area where there is no polyimide. This peeling can then develop into peeling of the polyimide from the semiconductor element, causing a problem of deterioration of the termination structure of the semiconductor device.

[0005] This problem has become particularly evident in semiconductor devices that include semiconductor elements made of SiC, which has a high Young's modulus, as the stress generated between the sealing resin and the semiconductor element during temperature cycling increases.

[0006] For example, Patent Document 1 discloses a technique in which, after dicing the semiconductor element from the semiconductor wafer, the outer periphery of the semiconductor element is further covered with a carbon-based adhesive in order to prevent the outer periphery of the semiconductor element from peeling off from the sealing resin. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2014 / 122892 Summary of the Invention [Problem to be solved by the invention]

[0008] However, in the technology described in Patent Document 1, after dicing the semiconductor element from the semiconductor wafer, the outer periphery of the semiconductor element is further covered with a carbon-based adhesive, which requires an additional process of forming a carbon-based adhesive layer using a stencil mask. As such, since an additional process is required for the semiconductor element after the wafer process is completed, there is a problem that the manufacturing cost of the semiconductor device increases significantly.

[0009] Therefore, an object of the present disclosure is to provide a technique capable of suppressing peeling between a sealing resin and a semiconductor element in a semiconductor device while suppressing a decrease in productivity and an increase in manufacturing costs. [Means for solving the problem]

[0010] The semiconductor device according to the present disclosure includes a semiconductor element diced into a square shape in top view from a semiconductor wafer, and a sealing resin that seals the semiconductor element. 、 The semiconductor element includes a cell region through which a main current flows, a termination region provided on the outer periphery side of the cell region, and a gate insulating film covering an upper surface of the outer periphery of the termination region. Contains polyimide a protective film, the protective film having extension portions extending to the outermost ends of the termination region at the four corners of the semiconductor element, the extension portions being integrally formed with the protective film, the extension portions having cut surfaces continuous with the cut surfaces of the termination region, and the protective film extending to the outermost ends of the termination region at the four sides of the semiconductor element excluding the four corners. A trench gate is provided in the cell region, and a step portion having the same depth as the trench gate is provided in the portion of the termination region covered by the extension portion, and the extension portion is embedded in the step portion. It is something. [Effects of the Invention]

[0011] According to the present disclosure, the semiconductor element has a protective film covering the upper surface of the outer periphery of the termination region, thereby reducing the stress received from the encapsulation resin. Furthermore, the extension portion has a cut surface that is continuous with the cut surface of the termination region, so there are no tolerances, such as alignment tolerances and processing tolerances, between the cut surface of the termination region and the cut surface of the extension portion. As a result, the upper surface of the outer periphery of the termination region is prevented from contacting the encapsulation resin at the four corners of the semiconductor element, further reducing the stress received by the semiconductor element from the encapsulation resin. As a result, peeling between the encapsulation resin and the semiconductor element is suppressed.

[0012] The extension portion has a cut surface that is continuous with the cut surface of the termination region, and the semiconductor element is diced from the semiconductor wafer after the protective film is formed. This eliminates the need for additional processes for the semiconductor element after the wafer process is completed, thereby suppressing increases in the manufacturing costs of the semiconductor device.

[0013] Furthermore, because the outermost edges of the four sides of the semiconductor element, excluding the four corners, are not covered with a protective film, the semiconductor elements can be diced from the semiconductor wafer while preventing clogging of the blade, thereby preventing a decrease in productivity of semiconductor devices. [Brief explanation of the drawings]

[0014] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a termination structure of a semiconductor device according to a first embodiment; [Figure 2] 10 is a diagram showing the results of a simulation of the stress reduction effect depending on the width of the extension portion of the semiconductor element included in the semiconductor device according to the first embodiment. FIG. [Figure 3] 1A and 1B are a top view and a cross-sectional view of a termination structure of a semiconductor device according to a modification of the first embodiment. [Figure 4] FIG. 10 is an explanatory diagram for explaining a method for manufacturing a semiconductor device according to a modification of the first embodiment. [Figure 5] FIG. 10 is a block diagram showing a configuration of a power conversion system according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] <First Embodiment> The first embodiment will be described below with reference to the drawings. FIG. 1(a) is a top view of a semiconductor device according to the first embodiment. FIG. 1(b) is a cross-sectional view taken along line AA in FIG. 1(a). FIG. 1(c) is a cross-sectional view taken along line BB in FIG. 1(a). Note that the sealing resin 2 is omitted from FIG. 1(a) to make the drawing easier to see. FIG. 2 is a diagram showing the results of a simulation of the stress reduction effect depending on the width of the extension portion 5a of the semiconductor element 1 included in the semiconductor device according to the first embodiment.

[0016] As shown in FIGS. 1(a), (b), and (c), the semiconductor device includes a semiconductor element 1 and a sealing resin 2. The semiconductor element 1 is formed into a quadrangular shape in top view by dicing a semiconductor wafer 10 (see FIG. 4) that includes a plurality of semiconductor elements 1. The semiconductor material of the semiconductor element 1 is, for example, silicon (Si) or silicon carbide (SiC). The sealing resin 2 is mainly composed of, for example, epoxy resin, and seals the semiconductor element 1.

[0017] The semiconductor element 1 comprises a cell region 3 where a plurality of cells are provided and through which a main current flows, a termination region 4 provided on the outer periphery side of the cell region 3, and a protective film 5 covering the upper surface of the outer periphery of the termination region 4. The cell region 3 is formed in a substantially rectangular shape and is the portion of the semiconductor element 1 excluding the outer periphery. The termination region 4 is the portion surrounding the cell region 3, i.e., the outer periphery of the semiconductor element 1.

[0018] The protective film 5 has extensions 5a that extend to the outermost edges at the four corners of the rectangular semiconductor element 1. The extensions 5a have cut surfaces that are continuous with the cut surfaces 4a of the termination region 4, and do not extend to the outermost edges at the four sides of the semiconductor element 1 excluding the four corners. Therefore, the top surface of the termination region 4 is exposed at the four sides of the semiconductor element 1 excluding the four corners.

[0019] The protective film 5 is mainly made of polyimide, for example, and is formed by a photolithography process during wafer processing. For example, a method is employed in which a photosensitive polyimide precursor solution is applied to the entire semiconductor wafer 10 (see FIG. 4), followed by pre-baking, forming a desired pattern by a photolithography process, and then baking.

[0020] In the case of non-photosensitive polyimide, a resist is used in a photolithography process, and the desired pattern is formed by etching through the resist. Forming a polyimide pattern in this way by applying the polyimide to the entire semiconductor wafer 10 and then etching it in a photolithography process allows the polyimide thickness to be uniform. After the polyimide formation process, any desired wafer processing is completed, and a dicing step is performed in which the semiconductor wafer 10 is diced to separate the individual semiconductor elements 1.

[0021] In the dicing process, a disk-shaped grinding blade is generally used, and in this case, polyimide is generally not provided on the dicing lines 11 (see FIG. 4) in order to prevent the grinding blade from clogging with polyimide.

[0022] In contrast to this, in this embodiment, the protective film 5 as a polyimide pattern extends to the dicing lines 11 at the four corners of the semiconductor element 1, and the extensions 5a are cut together with the termination region 4 by dicing with a blade.

[0023] If the protective film 5 extends to the dicing line 11, there is a risk of clogging the grinding stone of the blade, but by limiting the area covered by the protective film 5 to only the four corners of the semiconductor element 1, clogging of the grinding stone of the blade can be prevented.

[0024] Furthermore, the portion of protective film 5 that extends to dicing line 11 is cut off during dicing, so that extended portion 5a has a cut surface 5b that is continuous with cut surface 4a of termination region 4. Since there is almost no step on the continuous cut surface, it is possible to improve the conformity between cut surface 4a of termination region 4 and cut surface 5b of extended portion 5a.

[0025] Furthermore, because protective film 5 is mechanically cut by dicing, the polyimide thickness at cut surface 5b can be made equal to the polyimide thickness in other parts of protective film 5. In this way, the four corners of termination region 4 can be covered with protective film 5 of a uniform thickness, thereby reducing the stress generated between semiconductor element 1 and sealing resin 2.

[0026] Furthermore, it is desirable that the extension portions 5a extend at least 200 μm to the outermost edges at the four corners of the semiconductor element 1. As shown in Figure 2, increasing the width of the extension portions 5a reduces the stress generated at the interface between the protective film 5 and the termination region 4. When the width of the extension portions 5a is 200 μm, this stress can be reduced by half compared to when there are no extension portions 5a (0 μm).

[0027] Although not shown in Figure 2, increasing the width of extension 5a beyond 200 µm tends to further reduce the stress generated at the interface between protective film 5 and termination region 4. For example, an oxide film can be provided at the interface between extension 5a and termination region 4. By providing an oxide film, the adhesion between extension 5a and termination region 4 can be improved, thereby preventing extension 5a from peeling off from termination region 4 and further improving the reliability of the semiconductor device.

[0028] Moreover, an oxide film may or may not be provided on the dicing lines 11 other than the portion where the extension portion 5a is provided, and this can be selected arbitrarily based on other conditions.

[0029] <Modification of the First Embodiment> Next, a modified example of the first embodiment will be described. FIG. 3(a) is a top view of a semiconductor device according to a modified example of the first embodiment. FIG. 3(b) is a cross-sectional view taken along line CC in FIG. 3(a). FIG. 3(c) is a cross-sectional view taken along line DD in FIG. 3(a). Note that the sealing resin 2 is omitted from FIG. 3(a) to make the drawing easier to see. FIG. 4 is an explanatory diagram for explaining a method for manufacturing a semiconductor device according to a modified example of the first embodiment, and is a top view showing a portion of a semiconductor wafer 10 including a plurality of semiconductor elements 1.

[0030] For example, if the semiconductor element 1 is a MOSFET having a trench gate, a trenching process is performed to carve a trench for the trench gate into the upper surface of the semiconductor element 1. Normally, in the trenching process, the trench for the trench gate is formed only in the cell region 3. However, in a modification of the first embodiment, as shown in FIGS. 3(a), (b), and (c), a step portion 4b having a depth equivalent to that of the trench gate is formed directly below the extension portion 5a in the termination region 4, i.e., in the portion of the termination region 4 covered by the extension portion 5a. This improves the adhesion between the extension portion 5a and the termination region 4, and more effectively prevents the extension portion 5a from peeling off from the termination region 4.

[0031] Step portion 4b can be provided, for example, in a shape that chamfers the four corners of semiconductor element 1. In this case, step portion 4b may be provided in a linear chamfered shape, or in any chamfered shape such as a polygonal or curved shape that follows the R of the termination structure.

[0032] If the step portion 4b protrudes from the extension portion 5a, contact between the step portion 4b and the sealing resin 2 may cause a crack in the sealing resin 2, which may become the starting point for peeling off of the sealing resin 2. However, since the step portion 4b is covered by the extension portion 5a, such a problem does not occur.

[0033] 4, step portions 4b at the four corners of the semiconductor element 1 are not connected to adjacent semiconductor elements 1 on the semiconductor wafer 10. Therefore, the step pattern forming step portions 4b is discontinued within a region 12 that is completely removed by a blade on a dicing line 11.

[0034] In a typical photolithography process, a pattern is formed on the semiconductor wafer 10 using multiple shots, so pattern defects can be suppressed by preventing the trench patterns from overlapping between adjacent shots. Furthermore, the polyimide thickness of the extensions 5a can be further increased at the four corners of the semiconductor element 1, further reducing stress.

[0035] <Effects> As described above, the semiconductor device of this embodiment comprises a semiconductor element 1 diced into a square shape when viewed from above from a semiconductor wafer 10, and an encapsulating resin 2 that encapsulates the semiconductor element 1. The semiconductor element 1 has a cell region 3 through which a main current flows, a termination region 4 located on the outer periphery of the cell region 3, and a protective film 5 that covers the upper surface of the outer periphery of the termination region 4. The protective film 5 has extension portions 5a that extend to the outermost ends at the four corners of the semiconductor element 1, and the extension portions 5a have cut surfaces 5b that are continuous with the cut surfaces 4a of the termination region 4, and do not extend to the outermost ends on the four sides of the semiconductor element 1 except for the four corners.

[0036] Therefore, the semiconductor element 1 has a protective film 5 covering the upper surface of the outer periphery of the termination region 4, thereby reducing the stress it receives from the encapsulating resin 2. Furthermore, the extension portion 5a has a cut surface 5b that is continuous with the cut surface 4a of the termination region 4, so there are no tolerances, such as alignment tolerances or processing tolerances, between the cut surface 4a of the termination region 4 and the cut surface 5b of the extension portion 5a. As a result, the upper surface of the outer periphery of the termination region 4 is prevented from contacting the encapsulating resin 2 at the four corners of the semiconductor element 1, further reducing the stress the semiconductor element 1 receives from the encapsulating resin 2. As a result, peeling between the encapsulating resin 2 and the semiconductor element 1 is prevented. This improves the durability of the semiconductor device.

[0037] Further, the extension portion 5a has a cut surface 5b that is continuous with the cut surface 4a of the termination region 4, and the semiconductor element 1 is diced from the semiconductor wafer 10 after the formation of the protective film 5. This eliminates the need for additional processes on the semiconductor element 1 after the wafer process is completed, thereby suppressing an increase in the manufacturing cost of the semiconductor device.

[0038] Furthermore, since the outermost edges of the four sides of the semiconductor element 1, excluding the four corners, are not covered with the protective film 5, the semiconductor element 1 can be diced from the semiconductor wafer 10 while preventing clogging of the blade. This makes it possible to prevent a decrease in productivity of semiconductor devices.

[0039] Moreover, the protective film 5 contains polyimide. Since a material that can be formed by a conventional wafer process is used, the protective film 5 can be easily formed.

[0040] Furthermore, the extension portions 5a extend at least 200 μm to the outermost edges at the four corners of the semiconductor element 1, thereby sufficiently reducing the stress received from the sealing resin 2. This makes it possible to prevent the protective film 5 from peeling off, even when the protective film 5 is mainly made of photosensitive polyimide, which has half the peel resistance of non-photosensitive polyimide.

[0041] A trench gate is provided in the cell region 3, and a step portion 4b having the same depth as the trench gate is provided in the portion of the termination region 4 covered by the extension portion 5a.

[0042] Therefore, the adhesion between the extension portion 5a and the terminal region 4 can be improved, and the extension portion 5a can be more effectively prevented from peeling off from the terminal region 4.

[0043] Furthermore, the semiconductor material of the semiconductor element 1 is SiC. Conventionally, in semiconductor devices including semiconductor elements whose semiconductor material is SiC, which has a high Young's modulus, stress generated between the encapsulating resin and the semiconductor element during temperature cycling increases, resulting in a problem of deterioration of the termination structure of the semiconductor device. However, in the semiconductor device according to this embodiment, peeling between the encapsulating resin 2 and the semiconductor element 1 can be suppressed, thereby suppressing deterioration of the termination structure of the semiconductor device.

[0044] Furthermore, the step portion 4b is formed with a step pattern that extends to the portion that overlaps with the dicing line 11 of the semiconductor wafer 10, and the step pattern does not overlap with the step pattern of other adjacent semiconductor elements 1 on the semiconductor wafer 10, so that a step pattern can be formed for each shot. This makes it possible to avoid forming unnecessary patterns on the dicing line 11.

[0045] Furthermore, since the cut surface 5b of the extension portion 5a and the cut surface 4a of the terminal region 4 are formed by dicing with a blade, clogging of the blade is suppressed. This will be explained below.

[0046] As in the past, when the entire outer periphery of a semiconductor element is covered with a protective film and the semiconductor element covered with the protective film is diced with a blade, the blade becomes clogged with debris from the protective film. In contrast, in this embodiment, the portion covered with the protective film 5 is limited to the four corners of the semiconductor element 1, thereby reducing the time and number of dicing operations that can lead to clogging. In addition, debris from the protective film 5 is more likely to fall off while dicing the portion not covered with the protective film 5. As a result, the effect of suppressing clogging of the blade is obtained.

[0047] <Embodiment 2> In this embodiment, the semiconductor device according to the above-described embodiment 1 is applied to a power conversion device. Although application of the semiconductor device according to embodiment 1 is not limited to a specific power conversion device, a case in which the semiconductor device according to embodiment 1 is applied to a three-phase inverter will be described below as embodiment 2.

[0048] FIG. 5 is a block diagram showing a configuration of a power conversion system to which a power conversion device 200 according to the second embodiment is applied.

[0049] The power conversion system shown in Fig. 5 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0050] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 5 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal to the drive circuit 202 to control the drive circuit 202.

[0051] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0052] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown). By switching the switching elements, DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. However, the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. The semiconductor device according to the first embodiment described above is applied to at least one of the switching elements and freewheeling diodes of the main conversion circuit 201. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0053] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0054] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0055] In the power conversion device 200 according to this embodiment, the semiconductor device according to the first embodiment is applied as a switching element of the main conversion circuit 201, and therefore durability can be improved.

[0056] In the present embodiment, an example has been described in which the semiconductor device according to the first embodiment is applied to a two-level three-phase inverter, but the application of the semiconductor device according to the first embodiment is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to the first embodiment may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to the first embodiment can also be applied to a DC / DC converter or an AC / DC converter.

[0057] Furthermore, the power conversion device to which the semiconductor device according to the first embodiment is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0058] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0059] 1 semiconductor element, 2 sealing resin, 3 cell region, 4 termination region, 4a cut surface, 4b step portion, 5 protective film, 5a extension portion, 5b cut surface, 10 semiconductor wafer, 11 dicing line, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit.

Claims

1. a semiconductor element diced into a square shape in top view from a semiconductor wafer; a sealing resin that seals the semiconductor element, the semiconductor element has a cell region through which a main current flows, a termination region provided on the outer periphery side of the cell region, and a protective film including polyimide that covers an upper surface of an outer periphery of the termination region; the protective film has extension portions that extend to the outermost ends of the termination region at the four corners of the semiconductor element, The extension portion is integrally formed with the protective film, the extension portion has a cut surface that is continuous with the cut surface of the termination region, and the protective film does not extend to the outermost end of the termination region on four sides of the semiconductor element excluding the four corners, a trench gate is provided in the cell region; a step portion having a depth equal to that of the trench gate is provided in a portion of the termination region that is covered by the extension portion; The semiconductor device has the extension portion embedded in the step portion.

2. 2. The semiconductor device according to claim 1, wherein the extension portion extends at least 200 μm from an outer edge of the protective film on each of the four sides excluding the four corners of the semiconductor element to the outermost edge of the termination region.

3. 3. The semiconductor device according to claim 1, wherein the semiconductor material of the semiconductor element is SiC.

4. A semiconductor device as described in claim 1, wherein the step portion is provided in a polygonal or curved shape that conforms to the structure of the termination region.

5. 10. A method for manufacturing a semiconductor device according to claim 1, comprising: the step portion is formed in a step pattern extending to a portion overlapping a dicing line of the semiconductor wafer, The method for manufacturing a semiconductor device, wherein the step pattern does not overlap with step patterns of other semiconductor elements adjacent to the semiconductor wafer.

6. A method for manufacturing the semiconductor device according to any one of claims 1 to 4, comprising: A method for manufacturing a semiconductor device, wherein the cut surface of the extension portion and the cut surface of the termination region are formed by dicing with a blade.

7. a main conversion circuit including the semiconductor device according to any one of claims 1 to 4, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising:

Images