Layered substrate structure with aligned optical access to electrical devices - Patents.com

Abstract

The present disclosure relates to a layered substrate structure having aligned optical access to electrical devices formed thereon for laser processing and electrical device conditioning. According to an embodiment, a layered substrate structure is provided that includes an optical substrate having a first side and a second side, and a patterned bonding layer formed on the second side, the patterned bonding layer including a bonding region and an opening region, the opening region exposing a portion of the second side. The layered substrate structure further includes a device chip that includes at least one electrical component aligned with the optical substrate and the opening region, bonded to the patterned bonding layer via the bonding region. The at least one electrical component may include, for example, a thin-film wire, an air bridge, a qubit, an electrode, a capacitor, or a resonator.

Description

[Technical Field]

[0001] The present disclosure relates to layered substrate structures having aligned optical access to electrical devices formed thereon for laser processing and electrical device conditioning. [Background technology]

[0002] In large multi-qubit systems, the resonant frequencies of the qubits need to be precisely controlled to avoid signaling collisions. Due to variability in semiconductor processing, the original resonant frequencies of the qubits as fabricated typically deviate from the design target. Recent qubit packaging schemes envision bonding the qubit substrate to a handler wafer via an adhesive layer for additional processing and substrate thinning. Typically, a blanket metal ground plane covers the qubit substrate surface opposite the qubits, isolating the qubit electrodes from the wafer and adhesive layer. This continuous metal ground plane and adhesive layer block access to the qubit electrodes for laser processing and qubit tuning. Summary of the Invention

[0003] The following presents a summary in order to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements or to delineate the scope of different embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. The present disclosure relates to layered substrate structures having aligned optical access to electrical devices formed thereon for laser processing and electrical device conditioning.

[0004] According to embodiments, a layered substrate structure is provided that includes an optical substrate having a first side and a second side, and a patterned bonding layer formed on the second side, the patterned bonding layer including a bonding region and an opening region, the opening region exposing a portion of the second side. The layered substrate structure further includes a device chip that includes at least one electrical component aligned with the optical substrate and the opening region, bonded to the patterned bonding layer via the bonding region. In various embodiments, the at least one electrical component can include, but is not limited to, a thin-film metal structure (the thin-film metal structure formed from a superconducting metal), a thin-film wire, an air bridge, a qubit, an electrode, a capacitor, or a resonator.

[0005] In one or more embodiments, the device chip can be or can include a semiconductor chip having a thickness between about 50 micrometers (μm) and about 500 μm. The patterned bonding layer of the layered substrate structure can include a bonding material selected from the group consisting of polyimide polymer, indium, indium nitride, gold, gold nitride, platinum, platinum nitride, titanium, titanium nitride, tantalum, tantalum nitride, chromium, chromium nitride, tungsten, tungsten nitride, silver, silver nitride, copper, aluminum, aluminum oxide, and tin.

[0006] The layered substrate structure further includes one or more closed cavities formed between the optical substrate and the device chip within the open region, hi some implementations, the one or more cavities contain an inert gas and / or are formed in a vacuum, or a combination thereof, such that the one or more cavities are free of oxygen and water.

[0007] In some implementations, the device chip includes a bonding surface (through which the device chip is bonded to the patterned bonding layer) and a front surface opposite the bonding surface, with at least one electrical component formed on the front surface. Additionally or alternatively, at least one electrical component may be formed on the bonding surface. In any of these implementations, the layered substrate structure may further include a patterned metal layer formed on the bonding surface including one or more openings aligned with the opening region. In various implementations, the patterned metal layer comprises a superconducting metal material. The layered substrate structure may further include one or more alignment marks formed on the device chip at one or more defined locations that facilitate aligning the at least one electrical component with the opening region and the one or more openings.

[0008] The layered substrate structure further includes an aperture area providing at least 50% optical transmission to the at least one electrical component at a wavelength of about 1.5 micrometers (μm), and an optical path through the optical substrate. The optical substrate may be made of sapphire, quartz, or a quartz glass having a doping concentration of about 1E14 cm. -3 The optical substrate may comprise a material selected from the group consisting of: smaller, doped silicon. In some implementations, the optical substrate includes an anti-reflective coating formed on the first surface and the second surface.

[0009]

[0010] Additional embodiments relate to methods for forming a layered substrate structure having aligned optical access to electrical devices formed thereon for laser processing and electrical device adjustment. In one or more embodiments, the method includes forming one or more alignment marks in a device wafer from a first side of the device wafer, forming a ground plane layer on the first side, and forming one or more first openings in the ground plane layer at one or more defined locations relative to the one or more alignment marks. The method further includes forming one or more second openings in a bonding layer, bonding an optical substrate to the ground plane layer of the device wafer via the bonding layer having the one or more first openings aligned with the one or more second openings, and thinning a second side of the device wafer opposite the first side to expose the one or more alignment marks, resulting in the formation of a layered substrate structure.

[0010] In some embodiments, forming the one or more second openings includes patterning a bonding layer to form on the surface of the optical substrate. Additionally or alternatively, forming the one or more second openings includes depositing a bonding layer over one or more portions of the ground plane layer excluding the one or more first openings.

[0011] The method may further include forming one or more electrical components on the second side of the device wafer at one or more defined locations using the alignment marks, resulting in the one or more electrical components being aligned with the one or more first openings and the one or more second openings. In some implementations, the method may further include forming one or more closed cavities between the device wafer and the optical substrate at the one or more second openings as a result of bonding, wherein the bonding includes bonding the optical substrate to the device wafer in a vacuum or inert environment, resulting in removal of oxygen and water from the one or more closed cavities.

[0012] The disclosed subject matter also provides a method for preparing an electrical device formed on a layered substrate structure. In one embodiment, the method includes forming a device chip including a layered substrate structure including an optical substrate having a first side and a second side, a patterned bonding layer formed on the second side and including bonding regions and opening regions, the opening regions exposing a portion of the second side, and at least one electrical component bonded to the patterned bonding layer via the bonding regions and aligned with the optical substrate and the opening regions.

[0013] The method further includes contacting the laser beam with at least one electrical component through the optical substrate and the aperture region, and modifying a state or property of the at least one electrical component as a result of the contact. In various embodiments, the at least one electrical component may include, but is not limited to, a thin film metal structure (wherein the thin film metal structure is formed from a superconducting metal), a thin film wire, an air bridge, a qubit, an electrode, a capacitor, or a resonator. [Brief explanation of the drawings]

[0014] Numerous aspects, embodiments, objects and advantages of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout.

[0015] [Figure 1] 1 illustrates a cross-sectional view of a layered substrate structure having aligned optical access to electrical devices formed thereon according to embodiments described herein.

[0016] [Figure 2] 1 illustrates a cross-sectional view of a layered substrate structure having aligned optical access to electrical devices formed thereon according to embodiments described herein.

[0017] [Figure 3]1 shows a cross-sectional view of another layered substrate structure having aligned optical access to electrical devices formed thereon according to embodiments described herein.

[0018] [Figure 4] 1 shows a cross-sectional view of another layered substrate structure having aligned optical access to electrical devices formed thereon according to embodiments described herein.

[0019] [Figure 5A] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5B] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5C] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5D] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5E] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5F] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5G] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5H] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5I] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5J] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 5K] 1 illustrates an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein.

[0020] [Figure 6A] 1 illustrates another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 6B] 1 illustrates another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 6C] 1 illustrates another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein. [Figure 6D] 1 illustrates another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to embodiments described herein.

[0021] [Figure 7]FIG. 1 shows a high-level flow diagram of an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to one or more embodiments described herein.

[0022] [Figure 8] FIG. 1 shows a high-level flow diagram of another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to one or more embodiments described herein.

[0023] [Figure 9] 1 depicts a high-level flow diagram of an exemplary method for conditioning an electrical device formed on a layered substrate structure according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following detailed description is merely exemplary and is not intended to limit the embodiments and / or the application or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding Summary section or Detailed Description section.

[0025] One or more embodiments will now be described with reference to the drawings. Like reference numerals will be used to refer to like elements throughout. It should be understood that the various structures shown in the drawings (e.g., different layers, substrates, wafers, electrical components, etc.) are examples only and are not drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments can be practiced without these specific details. In addition, certain elements may be omitted from certain illustrations for clarity and / or simplicity, unless the description needs to focus on the omitted elements. Also, the same or similar reference numerals used throughout the drawings will be used to indicate the same or similar features, elements, or structures, and therefore, a detailed description of the same or similar features, elements, or structures will not be repeated for each drawing.

[0026] As used herein, unless otherwise specified, terms such as on, over, top, upper, located on, or atop refer to a first element being on a second element, although there may be intervening elements between the first and second elements. As used herein, unless otherwise specified, the term "direct," used in conjunction with the terms "on," "over," "top," "located on," "located on top," "in contact," "direct contact," or "direct contact," refers to a first element and a second element being connected without any intervening elements therebetween. As used herein, terms such as "above," "below," "up," "below," "directly above," "directly below," "aligned with," "adjacent to," "right," "left," "vertical," "horizontal," "top," "bottom," and variations thereof, refer to the disclosed structures as oriented in the drawing figures. As used herein, the term "aligned with" refers to elements being directly aligned along the same vertical or horizontal line relative to each other. For example, as used herein, the term aligned can refer to a first element being directly above or below a second element.

[0027] As used herein, the terms "substrate," "wafer," and "chip" are used interchangeably unless the context warrants a specific distinction between the terms. As used herein, the term "device chip" refers to a chip, substrate, or wafer that corresponds to or includes an electrical component or device. As used herein, the terms "electrical device," "electrical component," "electrical element," "electrical structure," and the like are used interchangeably unless the context warrants a specific distinction between the terms.

[0028] As used herein, the term "bonding" means that two structures (e.g., wafers, chips, substrates, etc.) are joined together in a fixed adhesive contact, allowing for the use of processing tools to manipulate the joined structures, to cut the joined structures, to thin / grind at least one of the structures, and the like. Thinning is known in the art to include, for example, grinding and chemical-mechanical polishing steps.

[0029] FIG. 1 shows a cross-sectional view of a layered substrate structure 100 having aligned optical access to electrical devices formed thereon, according to embodiments described herein.

[0030] The layered substrate structure 100 comprises a device chip 110 having a front surface 110-F and a back surface 110-B (also referred to as a bonding surface). The layered substrate structure 100 further comprises an optical substrate 122 (also referred to as a handler) bonded to the back surface 110-B of the device chip 110 via a patterned bonding layer 116. In the embodiment shown, the device chip 110 is further bonded or otherwise attached to a silicon interposer 102 via one or more solder joints 104.

[0031] Device chip 110 may include one or more electrical devices or components formed thereon and / or therein. In various embodiments, layered substrate structure 100 may be or correspond to a qubit package or structure, and device chip 110 may be or correspond to a qubit chip. In these embodiments, the one or more electrical components may include one or more qubits or qubit electrodes. However, layered substrate structure 100 and the other layered substrate structures described herein are not limited to qubit structures.

[0032] In the illustrated embodiment, device chip 110 includes electrical components formed on its backside 110-B, including electrical component 106 and electrical component 108. The type of electrical component 106 and / or the type of electrical component 108 may vary. For example, electrical component 106 and / or electrical component 108 may include, but are not limited to, thin-film metal structures (thin-film metal structures formed using superconducting metals), thin-film wires, air bridges, qubits, electrodes, capacitors, and / or resonators. In the illustrated embodiment, electrical component 108 corresponds to an air bridge, and electrical component 106 corresponds to a thin-film metal structure. The number of electrical components formed on the backside 110-B of device chip 110 may also vary.

[0033] The material and thickness of the device chip 110 can also vary. In some embodiments, the device chip 110 can be formed with silicon. Other suitable materials for the device chip 110 can include, but are not limited to, sapphire, quartz, silicon carbide, or other compound semiconductors. In various embodiments, the thickness of the device chip 110 can range from about 50 μm to about 800 μm. In some implementations, the thickness of the device chip 110 is preferably between about 50 μm and about 300 μm, and more preferably between about 50 μm and about 200 μm. In one exemplary embodiment, the thickness of the device chip 110 is about 100 μm.

[0034] The device chip 110 further includes a patterned metal layer 114 formed on the backside 110-B of the device chip 110. For example, in the illustrated embodiment, the patterned metal layer 114 includes an open region or opening that exposes a portion of the backside 110-B of the device chip 110. An extracted view of the central region of the layered substrate structure 100 within the dotted box 101 is shown in the lower left corner of FIG. 1 to provide a better view of the openings in the patterned metal layer 114. The open region or opening in the patterned metal layer 114 as shown in the extracted view of the dotted box 101 is referred to herein as a first opening 126. In the illustrated embodiment, the patterned metal layer 114 includes a single first opening 126. However, the number of first openings 126 in the patterned metal layer may vary. For example, in some embodiments, the patterned metal layer 114 may include multiple first openings 126 (or open regions), as described in more detail below with reference to FIGS. 2-4 .

[0035] In various embodiments, the patterned metal layer 114 may be or correspond to a patterned ground plane layer. In this regard, the patterned metal layer 114 may also be referred to herein as a patterned ground plane layer. The material of the patterned metal layer 114 may vary. In some embodiments, the patterned metal layer 114 comprises a superconducting metal. For example, the superconducting metal may include, but is not limited to, aluminum, niobium, and alloys of niobium with titanium or another metal. Other suitable materials for the patterned metal layer 114 may include nitrides, such as, but not limited to, niobium nitride, titanium nitride, and niobium with a barrier layer thereon, where the barrier may include the metal nitrides mentioned immediately above.

[0036] The device chip 110 may further include one or more through-silicon vias (TSVs) formed through the device chip 110 from the front surface 110-F to the back surface 110-B. For example, in the illustrated embodiment, the device chip 110 includes two TSVs 112. However, it should be understood that the number of TSVs 112 may vary. Each TSV electrically connects a patterned metal layer 114 on the back surface 110-B of the chip to an electrical component 106 formed on the front surface 110-F of the device chip. In this regard, each TSV 112 reaches through the front surface 110-F of the device chip 110 to make electrical contact with the patterned metal layer 114 and reaches through the back surface 110-B of the device chip to make electrical contact with the electrical component 106. The TSVs 112 may provide grounding for the device chip 110 and may also be used to facilitate aligning at least one electrical component on the device chip 110 with the first openings 126 in the patterned metal layer, as will be described in more detail below. The TSVs 112 may be formed in or through the device chip 110 using standard TSV processing techniques. For example, the TSVs 112 may be patterned via lithography using substrate processing (FEOL) and / or interconnect processing (BEOL).

[0037] The optical substrate 122 may comprise a transparent or translucent material that provides for the transmission therethrough of light (e.g., laser beam 124) emitted by a laser (not shown) of a desired wavelength. For example, in some embodiments, the optical substrate 122 may comprise a material having an optical transmission of between about 50% and about 90% at wavelengths between about 0.5 μm and about 3.0 μm. In another embodiment, the optical substrate 122 may comprise a material having an optical transmission characteristic of between about 50% and about 90% at wavelengths between about 1.0 μm and about 2.0 μm. In yet another embodiment, the optical substrate 122 may comprise a material having an optical transmission characteristic of between about 50% and about 90% at wavelengths between 1.0 and 2.0 μm, e.g., about 1.5 μm. Silicon is one material that meets these requirements and may be used to form the optical substrate 122.

[0038] It should be understood that the degree of light transmission and desired wavelength of the optical substrate 122 may vary depending on the type of material used for the optical substrate and the thickness of the optical substrate 122. In some embodiments, the optical substrate 122 may be formed using a quartz material, such as, but not limited to, sapphire and / or quartz. In another embodiment, the optical substrate 122 has a thickness of approximately 1E15 cm -3 Less than or equal to about 1E12cm, more preferably -3 The optical substrate 122 may be formed using lightly doped silicon, such as silicon having the following doping concentration (dopant atoms per cubic centimeter): 100 μm to 1500 μm. In some embodiments, the thickness of the optical substrate 122 may range from about 100 μm to about 1500 μm. In another exemplary embodiment, the thickness of the optical substrate 122 may range from about 200 μm to about 1000 μm. In another exemplary embodiment, the thickness of the optical substrate 122 may range from about 400 μm to about 900 μm. In yet another embodiment, the thickness of the optical substrate 122 may be about 725 μm.

[0039] The optical substrate 122 may further include an anti-reflective coating formed on the front surface 122-F and / or the back surface 122-B of the optical substrate. For example, in the illustrated embodiment, the optical substrate 122 includes a first anti-reflective coating 120a formed on the back surface 122-B of the optical substrate 122 and a second anti-reflective coating 122b formed on the front surface 122-F of the optical substrate. The materials used for the anti-reflective coatings formed on both sides of the optical substrate 122 may be the same. In some embodiments, the anti-reflective coatings (e.g., including the first anti-reflective coating 120a and the second anti-reflective coating 120b) may include silicon nitride (SiN), such as SiN. The anti-reflective coatings have a different refractive index (RI) than the optical substrate 122. Other suitable materials for the anti-reflective coatings (e.g., including the first anti-reflective coating 120a and the second anti-reflective coating 120b) include silicon nitride (SiN), such as SiN. x N y(x and y may include any number) may include, but are not limited to, SiN, silicon oxide (SiO), aluminum oxide (AlO), aluminum nitride (AlN), titanium nitride (TiN), and various other forms of magnesium fluoride (MgF).

[0040] The thickness of the first antireflective coating 120a and the second antireflective coating 120b can vary. In some embodiments, the thickness of each of the first antireflective coating 120a and the second antireflective coating 120b can be between about 50 nanometers (nm) and about 500 nm. In another exemplary embodiment, the thickness of each of the first antireflective coating 120a and the second antireflective coating 120b can be between about 100 nm and about 250 nm. In another exemplary embodiment, the thickness of each of the first antireflective coating 120a and the second antireflective coating 120b can be between about 150 nm and about 200 nm. In one example implementation, the thickness of each of the first antireflective coating 120a and the second antireflective coating 120b can be about 187 nm.

[0041] The layered substrate structure 100 further includes a patterned bonding layer 116 formed between the back surface 110-B of the device chip 110 and the back surface 122-B of the optical substrate 122, bonding the device chip 110 to the optical substrate 122. The patterned bonding layer 116 may include one or more open areas or openings (or more specifically, a first anti-reflective coating formed on the back surface 122-B) exposing the back surface 122-B of the optical substrate 122, and one or more bonding areas. Referring to the extracted view in the dotted box 101, the open areas or openings in the patterned bonding layer 116 are referred to herein as second openings 128. In the illustrated embodiment, the patterned bonding layer 116 includes a single second opening 128. However, the number of second openings 128 in the patterned bonding layer may vary. For example, in some embodiments, as will be described in more detail below with reference to Figures 2-4, the patterned bonding layer 116 can include a plurality of second openings 128 (or opening areas) and a plurality of bonding areas.

[0042] The patterned bonding layer 116 may be formed on the back surface 110-B of the device chip 110 and / or the back surface 122-B of the optical substrate 122, or a combination thereof, such that the second opening 128 is aligned with the first opening 126. More specifically, the bonding portion of the patterned bonding layer 116 may be formed on and / or bonded to the metal portion of the patterned metal layer 114 on the back surface 110-B of the device chip 110 excluding the first opening 126.

[0043] The material used for the patterned bonding layer 116 can vary. In some embodiments, the patterned bonding layer 116 can be formed using an adhesive material. For example, the adhesive material can include a polyimide polymer or another adhesive material (e.g., a thermoplastic polyimide adhesive) that can be patterned. Other adhesives are available, as known to those skilled in the art. In other embodiments, the patterned bonding layer 116 can include a metal bonding layer, and the device chip 110 can be bonded to the optical substrate 122 via metal-to-metal bonding. For example, in some implementations, the patterned metal layer 114 can be formed on the backside of the optical substrate 122-B (or, more specifically, the first antireflective coating 120a), with the metal bonding portions located at defined positions relative to the metal portions of the patterned metal layer 114. The metal bonding portions of the patterned bonding layer 116 can then be solder-bonded or thermocompression-bonded to the metal portions of the patterned metal layer 114 via metal-to-metal bonding. In these embodiments, the patterned bonding layer 116 may include one or more metals or metal layers including, but not limited to, indium, indium nitride, gold, gold nitride, platinum, platinum nitride, titanium, titanium nitride, tantalum, tantalum nitride, chromium, chromium nitride, tungsten, tungsten nitride, silver, silver nitride, copper, aluminum, aluminum oxide, and / or tin.

[0044] The layered substrate structure 100 further includes a closed cavity 118 formed between the optical substrate 122 and the device chip 110 as a result of the first opening 126 in the patterned metal layer 114 and the second opening 128 in the patterned bonding layer 116. In this regard, the closed cavity 118 includes the first opening 126 in the patterned metal layer 114 and the second opening 128 in the patterned bonding layer 116. In some embodiments, the device chip 110 can be bonded to the optical substrate 122 in an inert environment (e.g., in an inert gas environment such as nitrogen, argon, and / or other inert gases) and / or under vacuum, such that the closed cavity 118 is free of or has only very low concentrations of oxygen and / or water. As a result, any metal components and structures exposed within the cavity are protected from oxidation and / or corrosion. In embodiments in which the device chip 110 is bonded to the optical substrate 122 in an inert environment, the closed cavity 118 may contain an inert gas, such as nitrogen, argon, or another inert gas.

[0045] The dimensions of the first opening 126 in the patterned metal layer 114, the second opening 128 in the patterned bonding layer 116, and the closed cavity 118 can vary. For example, in some embodiments, the first opening 126 or the second opening 128, or a combination thereof, can have a diameter (or edge-to-edge length, for non-circular openings) between about 10 μm and about 2000 μm. In other embodiments, the first opening 126 and / or the second opening 128 can have a diameter (or edge-to-edge length, for non-circular openings) between about 10 μm and about 1000 μm. In other embodiments, the first opening 126 and / or the second opening 128 can have a diameter (or edge-to-edge length, for non-circular openings) between about 10 μm and about 800 μm. In another embodiment, first opening 126 and / or second opening 128 can have a diameter between about 10 μm and about 500 μm. In another embodiment, first opening 126 and / or second opening 128 can have a diameter between about 10 μm and about 100 μm. In various embodiments, first opening 126 can be smaller than second opening 128. The shape or geometry of first opening 126 and second opening 128 can vary. For example, each opening can be circular, square, rectangular, and / or various other shapes.

[0046] 1 provides a direct optical path from the front surface 122-F of the optical substrate 122, through the optical substrate 122, the closed cavity 118, and the device chip 110, to the electrical component 108 formed on the front surface 110-F of the device chip 110. In the illustrated embodiment, a laser beam 124 is shown transmitted through this optical path to reach the electrical component 108. In this regard, the design of the layered substrate structure 100 aligns the electrical component 108 with the first opening 126 in the patterned metal layer 114 and the second opening 128 in the patterned bonding layer 116, such that the electrical component 108 is within the line of sight of the laser beam 124 transmitted through the optical substrate 122 and the device chip 110. As a result, the design of layered substrate structure 100 provides for laser beam 124 to optically access or contact electrical component 108 through optical substrate 122, second opening 128 and first opening 126, and device chip 110 to modify a state or property of electrical component 108. For example, in the embodiment shown, electrical component 108 corresponds to an air bridge. In this exemplary embodiment, laser beam 124 may be used to open and / or close the air bridge via a direct optical path through optical substrate 122, second opening 128, first opening 126, and device chip 110 to electrical component 108. In another example where electrical component 108 includes a qubit, laser beam 124 may be used to alter the resonant frequency of the qubit.

[0047] The device chip 110 may further include one or more alignment marks 113 that facilitate aligning the electrical components 108 with the first openings 126 in the patterned metal layer 114 and the second openings 128 in the patterned bonding layer 116 during fabrication of the layered substrate structure 100. Additionally or alternatively, the TSVs 112 may be used as alignment marks during fabrication of the layered substrate structure 100. In some embodiments, the alignment marks 113 may also include metal TSVs formed through the device chip 110 from the front surface 110-F of the device chip to the back surface 110-B of the device chip. In some embodiments, the alignment marks 113 and / or the TSVs 112 formed through the device chip 110 may have a circular or rectangular shape, or may have various shapes used for lithographic alignment, including squares, crosses, rectangles, boxes, and parallel lines.

[0048] In this regard, the alignment marks 113 (and / or TSVs 112) may be formed at defined or known locations through the device chip 110 and exposed on both the front surface 110-F and the back surface 110-B of the device chip 110 during fabrication of the layered substrate structure 100. The first openings 126 in the patterned metal layer 114 and the second openings 128 in the patterned bonding layer 116 may also be formed at defined or known locations relative to the alignment marks 113 (and / or TSVs 112) on the back surface 110-B of the device chip during fabrication. As a result, the locations of the first openings 126 in the patterned metal layer 114 and the second openings 128 in the patterned bonding layer 116 relative to the alignment marks 113 (and / or TSVs 112, or a combination thereof) exposed on the front surface 110-F of the device chip are known. For example, according to the layered substrate structure 100, the locations of the first opening 126 and the second opening 128 are known to be directly between the alignment marks 113 (and / or TSVs 112), or at a defined distance from the respective alignment marks 113 (and / or TSVs 112), or a combination thereof. Accordingly, using the exposed alignment marks 113 (and / or TSVs 112) on the front surface 110-F of the device chip 110 as guides, the electrical component 108 can be disposed / formed on the front surface 110-F of the device chip 110 directly between the alignment marks, ensuring that the electrical component 108 is in a position aligned with the first opening 126 and the second opening 128. Additional details regarding the fabrication of the layered substrate structure 100 are provided below with reference to FIGS. 5A-5J and 6A-6C.

[0049] 2 shows a cross-sectional view of a layered substrate structure 200 having aligned optical access to electrical devices formed thereon, according to embodiments described herein. Layered substrate structure 200 includes the same or similar features and functionality as layered substrate structure 100, with some structural variations. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0050] The layered substrate structure 200 includes electrical devices on both the front and back sides of the device chip, which can be accessed and adjusted, respectively, via a laser beam 124 from the front side 122-F of the optical substrate 122 through the optical substrate 122. For example, unlike the layered substrate structure 100, in the layered substrate structure 200, the electrical components 108 are formed directly on the back side 110-B of the device chip on the exposed portion of the device chip 110 within the first opening 126. The layered substrate structure 200 also includes additional electrical components 202 formed on the front side 110-F of the device chip. The type and number of electrical components 202 can vary. For example, the electrical components 202 can include, but are not limited to, thin-film metal structures (thin-film metal structures formed using superconducting metals), thin-film wires, air bridges, qubits, electrodes, capacitors, and / or resonators.

[0051] An extracted view of a central region of the layered substrate structure 200 within the dotted box 201 is shown in the lower left corner of FIG. 2 . As shown in the extracted view of the dotted box 201, the electrical component 108 is located directly on the backside 110-B of the device chip 110 between the metal portions of the patterned metal layer 114 within the first opening 126. In this position, an optical path to the electrical component 108 is provided directly through the second opening 128 in the optical substrate 122 and the patterned bonding layer 116. In this regard, the electrical component 108 is aligned with the second opening 128. In this embodiment, the electrical component 108 corresponds to an air bridge, although it should be understood that the type of electrical component 108 may vary. For example, the electrical component 108 may include, but is not limited to, a thin-film metal structure (wherein the thin-film metal structure is formed using a superconducting metal), a thin-film wire, an air bridge, a qubit, an electrode, a capacitor, and / or a resonator. The number of electrical components formed on the backside of the device chip 110 within the first opening 126 may also vary.

[0052] Opening areas 204 are further established between the electrical component 108 and the metal portion of the patterned metal layer 114 on the side opposite the electrical component 108. These opening areas 204 provide an optical path for laser access to additional electrical components 202 formed on the front surface 110-F of the device chip. In particular, the components 202 are each aligned with and positioned directly below the opening areas 204. As a result, the electrical components 202 can each be optically accessed by the laser beam 124 through the optical substrate 122 (e.g., from the front surface 122-F), the second opening 128, the opening areas 204, and the device substrate. The alignment marks 113 (and / or the TSVs 112) can also provide for aligning the electrical components 202 with the opening areas 204 using the same or similar techniques described with reference to FIG. 1 .

[0053] The size of the aperture area 204 can vary. In this regard, the size of the first opening 126 and the second opening 128 can be adapted to accommodate the size of the electrical component 108 while providing sufficient opening space on either side of the electrical component 108 to form an aperture area 204 large enough to pass a laser beam 124 of a desired diameter.

[0054] 3 shows a cross-sectional view of another layered substrate structure 300 having aligned optical access to electrical devices formed thereon, according to embodiments described herein. Layered substrate structure 300 has some structural variations but includes the same or similar features and functionality as layered substrate structure 100 and layered substrate structure 200. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0055] Layered substrate structure 300 differs from layered substrate structure 200 and layered substrate structure 100 with respect to the number of openings in patterned metal layer 114 and patterned bonding layer 116. For example, in the illustrated embodiment, both patterned metal layer 114 and patterned bonding layer 116 include three aligned openings.

[0056] An extracted view of a central region of layered substrate structure 300 within dotted box 301 is shown in the lower left corner of Figure 3. As shown in the extracted view of dotted box 301, patterned metal layer 114 includes three first openings 126, and patterned bonding layer 116 includes three second openings 128. Each first opening 126 is further aligned with a corresponding second opening 128. Layered substrate structure 300 also includes three closed cavities 118. It should be understood that the three openings and cavities are shown for illustrative purposes only, and that the number of first openings 126, second openings 128, and closed cavities 118 may be unlimited.

[0057] Similar to layered substrate structure 100 and layered substrate structure 200, device chip 110 includes electrical components formed thereon aligned with respective first openings 126 and respective second openings 128, thereby providing an optical path for laser beam 124 access to the electrical components through optical substrate 122 (e.g., from front surface 122-F), second opening 128, first opening 126, and device chip 110. In the illustrated embodiment, these electrical components include electrical component 108 and electrical component 202 formed on front surface 110-F of device chip 110. The type and number of electrical components formed on front surface 110-F of device chip 110 can vary. Alignment marks 113 (and / or TSVs 112) can also provide alignment of electrical component 108 and electrical component 202 with corresponding openings in patterned metal layer 114 and patterned bonding layer 116, as described with reference to FIG. 1 .

[0058] 1 , in some embodiments, the device chip 110 can be bonded to the optical substrate 122 in an inert environment (e.g., in an inert gas environment such as nitrogen, argon, and / or other inert gas) and / or under vacuum, resulting in the closed cavity 118 being free of, or containing only very low concentrations of, oxygen and / or water. As a result, any metal components and structures exposed within the closed cavity 118 are protected from oxidation and / or corrosion. In embodiments in which the device chip 110 is bonded to the optical substrate 122 in an inert environment, the closed cavity 118 can contain an inert gas, such as nitrogen, argon, or another inert gas.

[0059] 4 shows a cross-sectional view of another layered substrate structure 400 having aligned optical access to electrical devices formed thereon, according to embodiments described herein. Layered substrate structure 400 includes the same or similar features and functionality as layered substrate structure 100, layered substrate structure 200, and layered substrate structure 300, although with some structural variations. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0060] Similar to the layered substrate structure 300, the layered substrate structure 400 includes a plurality of (e.g., three) first openings 126 in the patterned metal layer 114 and a plurality of aligned second openings 128 in the patterned bonding layer 116. The layered substrate structure 400 also includes a plurality of closed cavities 118. The layered substrate structure 400 differs from the layered substrate structure 300 with respect to the location of the electrical components 108. In this regard, the location of the electrical components 108 in the layered substrate structure 400 is similar to that in the layered substrate structure 200, with the electrical components 108 formed on the backside 110-B of the device chip. Similar to the layered substrate structure 200, the layered substrate structure 400 includes electrical devices on both the front and backside of the device chip 110, aligned with at least one second opening 128 and at least one first opening, respectively. As a result, each of the electrical devices (eg, electrical component 202 and electrical component 108 ) can be accessed and adjusted via laser beam 124 through optical substrate 122 and from front surface 122 -F of optical substrate 122 .

[0061] 5A-5J illustrate an exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to one or more embodiments. The fabrication method illustrated in FIGS. 5A-5J is illustrated in connection with fabricating layered substrate structure 100. However, it should be understood that the disclosed techniques may similarly be applied to forming layered substrate structure 200, layered substrate structure 300, layered substrate structure 400, and similar layered substrate structures. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0062] 5A, in one or more embodiments, a manufacturing process may involve preparing an optical substrate 122 by polishing its front surface 122-F and back surface 122-B and depositing an anti-reflective coating on both surfaces, resulting in structure 501. As shown in FIG. 5B, a bonding layer 116′ may then be formed on the back surface 122-B of the optical substrate 122 (e.g., on the first anti-reflective coating 120a), resulting in structure 502. For example, in some embodiments where a polyimide polymer is used for the bonding layer 116′, the back surface 122-B may be coated with the polyimide polymer and subsequently cured. Optionally, additional layers may be present between the first anti-reflective coating 120a and the bonding layer 116′. Thereafter, as shown in FIG. 5C, the bonding layer 116′ can be patterned (e.g., using lithography or another suitable method) to form a patterned bonding layer 116 having a second opening 128 on the back surface 122-F of the optical substrate 122, resulting in structure 503.

[0063] 5D , preparing the device chip 110 may involve forming alignment marks 113 and TSVs 112 through a portion of the device chip 110, resulting in structure 504. For example, in the embodiment shown, the alignment marks 113 and TSVs are only formed partially through the device chip 110, and they do not extend to the front surface 110-F of the device chip. In other embodiments, the alignment marks 113 and TSVs may be formed throughout the entire device chip 110, extending to both the back surface 110-B and the front surface 110-F of the device chip 110. In some embodiments, both the alignment marks 113 and the TSVs 112 may be formed in the same manner and comprise the same material. For example, in some embodiments, both the alignment marks 113 and the TSVs 112 may be formed by etching thin lines or openings (or cutouts) in the device chip 110 (e.g., via lithography) and then filling them with a metal, such as a superconducting metal or metal nitride.

[0064] In some embodiments, after the alignment marks 113 and the TSVs 112 are formed, a metal layer 114' may be deposited on the backside 110-B of the device chip 110, resulting in structure 505. Thereafter, as shown in FIG. 5F , the alignment marks 113 (and / or the TSVs) may be used to pattern (e.g., using lithography or another suitable method) the metal layer 114' to form a patterned metal layer 114 having first openings 126 on the backside 110-B of the device, resulting in structure 506. In this regard, the location of the alignment marks 113 (and / or the TSVs 112) may be visible through the metal layer 114' due to the transparency of the metal layer and / or the topography of the metal layer in combination with the formed alignment marks 113 (and / or the TSVs 112). For example, in some implementations, the topography of the metal layer 114′ may have protrusions or depressions at the locations of the alignment marks 113 (and / or TSVs 112) due to the structure of the alignment marks 113 (and / or TSVs 112) and the thin material of the deposited metal layer 114. Thus, the locations of the alignment marks 113 (and / or TSVs 112) visible from the backside 110-B of the device chip 110 may be used when patterning the metal layer 114′ to position the first openings 126 at defined locations relative to the alignment marks 113 (and / or TSVs 112). For example, the metal layer 114′ may be etched a defined distance (D1) away from each alignment mark 113 visible through the metal layer 114′ on the backside 110-F of the device chip.

[0065] FIG. 5G illustrates bonding structure 504 (e.g., optical substrate 122) to structure 506 (e.g., device chip) via patterned bonding layer 116 and aligning first opening 126 in patterned metal layer 114 with second opening 128 in patterned bonding layer 116, resulting in structure 507 shown in FIG. 5H. In this regard, structure 504 can be bonded to structure 506 such that the bonding portion of patterned bonding layer 116 is aligned with and bonded to the metal portion of patterned metal layer 114. In some embodiments, a camera (e.g., an infrared (IR) camera) can be used during this bonding step to facilitate alignment. Additionally, in various embodiments, this bonding step can be performed in a vacuum and / or inert environment so that oxygen and water particles are removed from the resulting closed cavity 118. In implementations in which an inert environment is used, the resulting closed cavity 118 contains an inert gas (e.g., nitrogen, argon, or another inert gas).

[0066] After the device chip 110 is bonded to the optical substrate 122 (or handler), the front surface 110-F can be ground down to a desired thickness, thereby exposing the alignment marks 113 and TSVs 112 on the front surface 110-F, resulting in structure 508, as shown in FIG. 5I.

[0067] 5J illustrates forming electrical components (e.g., electrical component 108 and electrical component 106) on the front surface of structure 508, resulting in structure 509. At this point, the locations of first opening 126 and second opening 128 within the structure are not visible because these openings are entirely enclosed within the structure (e.g., within closed cavity 118). However, electrical component 108 can be aligned with these openings and precisely positioned on front surface 110-F of device chip 110 using alignment marks 113. In this regard, because the location of first opening 126 is known to be a defined distance D1 between each alignment mark 113, electrical component 108 can be formed between the alignment marks using this distance reference as a guide, ensuring that electrical component 108 is positioned in alignment with first opening 126.

[0068] FIG. 5K illustrates bonding the structure 508 to the silicon interposer 102 via one or more solder joints 104, resulting in the layered substrate structure 100.

[0069] 6A-6D illustrate another exemplary method for forming a layered substrate structure having aligned optical access to electrical devices formed thereon. The fabrication method illustrated in FIGS. 6A-6D is illustrated in connection with fabricating layered substrate structure 100. However, it should be understood that the disclosed techniques may similarly be applied to forming layered substrate structure 200, layered substrate structure 300, layered substrate structure 400, and similar layered substrate structures. Repeated descriptions of similar elements employed in each embodiment are omitted for purposes of brevity.

[0070] According to the manufacturing method described with reference to FIGS. 5A-5K, a patterned bonding layer 116 was formed on the optical substrate 122. In another embodiment, the patterned bonding layer 116 may be formed on the patterned metal layer 114. In this regard, FIG. 6A shows a structure 506 that may be formed using the techniques described with reference to FIGS. 5D-5F. In this embodiment, as shown in FIG. 5B, the patterned bonding layer 116 may be formed directly on the metal portion of the patterned metal layer 114, resulting in structure 601. Then, as shown in FIG. 6C, structure 601 may be bonded to structure 506 via the patterned bonding layer 116, resulting in structure 507, which is again shown in FIG. 6D. Structure 507 may be further processed according to the techniques described with reference to FIGS. 5I and 5K.

[0071] 7 shows a high-level flow diagram of an exemplary method 700 for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to one or more embodiments described herein. In various embodiments, method 700 provides an exemplary method for forming layered substrate structure 100, layered substrate structure 200, layered substrate structure 300, and / or layered substrate structure 400. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0072] The method 700 may include forming, at 702, one or more alignment marks (e.g., alignment marks 113 and / or TSVs 112) through the device wafer (e.g., device chip 110) from a first side (e.g., backside 110-B) of the device wafer. The method 700 further includes forming, at 704, a ground plane layer (e.g., metal layer 114′) on the first side, and forming, at 706, one or more first openings (e.g., one or more first openings 126) in the ground plane layer at one or more defined locations relative to the one or more alignment marks (e.g., resulting in the formation of a patterned metal layer 114). The method 700 further includes forming, at 708, one or more second openings (e.g., one or more second openings 128) in a bonding layer (e.g., resulting in the formation of a patterned bonding layer 116). In some embodiments, forming the one or more second openings includes patterning a bonding layer to form on the surface of the optical substrate. Additionally or alternatively, forming the one or more second openings includes depositing a bonding layer over one or more portions of the ground plane layer excluding the one or more first openings.

[0073] Method 700 further includes bonding the optical substrate to a ground plane layer of the device wafer via a bonding layer having one or more first openings aligned with the one or more second openings at 710. Method 700 further includes thinning a second side of the device wafer opposite the first side (e.g., front side 110-F) to expose the one or more alignment marks, resulting in the formation of a layered substrate structure (e.g., layered substrate structure 100, layered substrate structure 200, layered substrate structure 300, and / or layered substrate structure 400) at 712.

[0074] 8 shows a high-level flow diagram of another exemplary method 800 for forming a layered substrate structure having aligned optical access to electrical devices formed thereon, according to one or more embodiments described herein. In various embodiments, method 800 provides an exemplary method for forming layered substrate structure 100, layered substrate structure 200, layered substrate structure 300, and / or layered substrate structure 400. Repeated descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0075] Method 800 may include, at 802, forming one or more alignment marks (e.g., alignment marks 113 and / or TSVs 112) through the device wafer (e.g., device chips 110) from a first side (e.g., backside 110-B) of the device wafer. Method 800 further includes, at 804, forming a ground plane layer (e.g., metal layer 114′) on the first side, and, at 806, forming one or more first openings (e.g., one or more first openings 126) in the ground plane layer at one or more defined locations relative to the one or more alignment marks (e.g., resulting in the formation of patterned metal layer 114). Method 800 further includes, at 808, forming one or more second openings (e.g., one or more second openings 128) in a bonding layer (e.g., resulting in the formation of patterned bonding layer 116). Method 800 further includes bonding the optical substrate to a ground plane layer of the device wafer via a bonding layer having one or more first openings aligned with the one or more second openings at 810. Method 800 further includes thinning a second side of the device wafer opposite the first side (e.g., front side 110-F) to expose the one or more alignment marks, resulting in the formation of a layered substrate structure (e.g., layered substrate structure 100, layered substrate structure 200, layered substrate structure 300, and / or layered substrate structure 400) at 812.

[0076] Method 800 further includes, at 812, forming one or more electrical components (e.g., electrical component 106, electrical component 108, electrical component 202, and the like) on the second side (e.g., front side 110-F) of the device wafer at one or more defined locations using the alignment marks, such that the one or more electrical components are aligned with the one or more first openings and the one or more second openings. In some implementations, the method may further include forming one or more closed cavities (e.g., one or more closed cavities 118) between the device wafer and the optical substrate at the one or more second openings as a result of bonding, wherein the bonding includes bonding the optical substrate to the device wafer in a vacuum or inert environment, thereby removing oxygen and water from the one or more closed cavities.

[0077] 9 shows a high-level flow diagram of an exemplary method 900 for conditioning an electrical device formed on a layered substrate structure according to one or more embodiments described herein. Repetitive descriptions of similar elements employed in each embodiment are omitted for the sake of brevity.

[0078] According to method 900, at 902, a layered substrate structure is formed (e.g., layered substrate structure 100, layered substrate structure 200, layered substrate structure 300, and / or layered substrate structure 400), the layered substrate structure including: an optical substrate having a first side and a second side; a patterned bonding layer formed on the second side and including a bonding region and an opening region (the opening region exposing a portion of the second side); and a device chip (e.g., electrical component 106, electrical component 108, electrical component 202, or the like) bonded to the patterned bonding layer via the bonding region and including at least one electrical component aligned with the optical substrate and the opening region. Method 900 further includes, at 904, contacting a laser beam (e.g., laser beam 124) with the at least one electrical component through the optical substrate and the opening region; and, at 906, modifying a state or property of the at least one electrical component as a result of the contact. For example, in embodiments in which at least one electrical component includes an air bridge, a laser beam can be used to open and close the air bridge. In another example in which at least one electrical component includes a qubit, a laser beam can be used to change the resonant frequency of the qubit. In other embodiments, the state or properties of an electrical device, such as a transistor, resistor, diode, or the like, can be altered using a laser beam. In this method, the laser beam (e.g., laser beam 124) can operate at any wavelength that provides optical transmission through optical substrate 122. For example, the laser wavelength can be selected from a wavelength range of 1000 to 0.2 microns, with the range of 0.5 to 3 microns being a preferred range. For example, a wavelength of 1.5 microns can be used in various embodiments.

[0079] What has been described above includes example embodiments of the present invention. Of course, it is not possible to describe every conceivable combination of components or methodologies for purposes of describing the claimed subject matter, but it is understood that many further combinations and permutations of the subject innovation are possible. Accordingly, the claimed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. Additionally, the above description of illustrated embodiments of the present disclosure, including those described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples have been described in this disclosure for purposes of illustration, those skilled in the art will recognize that various modifications are possible that are deemed within the scope of such embodiments and examples.

[0080] In this regard, with respect to any figure or numerical range for a given characteristic, a figure or parameter from one range may be combined with another figure or parameter from a different range for the same characteristic to produce a numerical range. Other than in the working examples, or where otherwise indicated, all numbers, values, and / or formulas referring to amounts of materials, reaction conditions, and the like, used in the specification and claims are understood to be modified in all instances by the term "about."

[0081] While what are considered example features of the present invention have been shown and described, those skilled in the art will recognize that various other modifications may be made and equivalents may be substituted without departing from the claimed subject matter. Additionally, many modifications may be made to adapt a particular situation to the teachings of the claimed subject matter without departing from the central concept described herein. Therefore, it is intended that the claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may include all aspects that come within the scope of the appended claims and equivalents thereof.

[0082] Additionally, while a particular feature of the subject innovation may be disclosed with respect to only one of multiple implementations, such feature may be combined with one or more other features of other implementations, as may be desirable or advantageous for any given or particular application. Further, to the extent that the terms "comprises," "including," "having," "comprising," variations thereof, and other similar words are used in either the detailed description or the claims, these terms are intended to be inclusive in the same manner as the term "comprising," as open-ended transitional phrases that do not exclude any additional or other elements.

[0083] Additionally, the words "example" or "exemplary" are used in this disclosure to mean serving as an example, instance, or illustration. Any aspect or design described in this disclosure as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or "exemplary" is intended to present concepts in a specific manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A, X uses B, or X uses both A and B, then "X uses A or B" is satisfied under any of the aforementioned plural cases. Additionally, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more" unless otherwise specified or clear from the context that the singular is intended.

Claims

1. an optical substrate having a first surface and a second surface; a patterned bonding layer formed on the second surface, the patterned bonding layer including a bonding region and an opening region exposing a portion of the second surface; and a device chip including at least one electrical component bonded to the patterned bonding layer through the bonding region and aligned with the optical substrate and the opening region; Equipped with The layered substrate structure, wherein the device chip includes a bonding surface that bonds the device chip to the patterned bonding layer and a front surface opposite the bonding surface, and the at least one electrical component is formed on the front surface.

2. an optical substrate having a first surface and a second surface; a patterned bonding layer formed on the second surface, the patterned bonding layer including a bonding region and an opening region exposing a portion of the second surface; and a device chip including at least one electrical component bonded to the patterned bonding layer through the bonding region and aligned with the optical substrate and the opening region; Equipped with the device chip includes a bonding surface that bonds the device chip to the patterning bonding layer and a front surface opposite the bonding surface; the bonding surface of the device chip is provided with a patterned metal layer including one or more openings aligned with the opening regions of the patterned bonding layer; the bonding region of the patterned bonding layer is bonded to an upper surface of the patterned metal layer; The layered substrate structure wherein the at least one electrical component is also aligned with the opening in the patterned metal layer.

3. 3. The layered substrate structure of claim 2, wherein the device chip includes a bonding surface that bonds the device chip to the patterned bonding layer and a front surface opposite the bonding surface, and the at least one electrical component is formed on the front surface.

4. 3. The layered substrate structure of claim 2, wherein the device chip includes a bonding surface that bonds the device chip to the patterned bonding layer and a front surface opposite the bonding surface, and the at least one electrical component is formed on the bonding surface.

5. The layered substrate structure of claim 1 , further comprising one or more closed cavities formed between the optical substrate and the device chip within the open region.

6. 6. The layered substrate structure of claim 1, further comprising an optical path through the aperture area and the optical substrate, the aperture area providing at least 50% optical transmission to the at least one electrical component at wavelengths between 0.5 and 3.0 micrometers.

7. 2. The layered substrate structure of claim 1, wherein the device chip includes a bonding surface that bonds the device chip to the patterned bonding layer and a front surface opposite the bonding surface, the bonding surface including a patterned metal layer formed thereon that includes one or more openings aligned with the opening regions.

8. An optical substrate having a first surface and a second surface; a patterned bonding layer formed on the second surface, the patterned bonding layer including a bonding region and an opening region exposing a portion of the second surface; and a device chip including at least one electrical component bonded to the patterned bonding layer through the bonding region and aligned with the optical substrate and the opening region; Equipped with the device chip includes a bonding surface for bonding the device chip to the patterned bonding layer and a front surface opposite the bonding surface, the bonding surface including a patterned metal layer formed thereon, the patterned metal layer including one or more openings aligned with the opening region; The layered substrate structure, wherein the patterned metal layer comprises a superconducting metallic material.

9. 9. The layered substrate structure of claim 1, further comprising one or more alignment marks formed on the device chip at one or more defined locations that facilitate aligning the at least one electrical component with the opening area.

10. 10. The layered substrate structure of claim 1, wherein the at least one electrical component is selected from the group consisting of a thin film metal structure, a thin film wire, an air bridge, a qubit, an electrode, a capacitor, and a resonator.

11. 11. The layered substrate structure of claim 1, wherein the optical substrate includes an anti-reflective coating formed on the first surface and the second surface.

12. The optical substrates include sapphire, quartz, and cubic centimeters (cm －３ 12. The layered substrate structure of claim 1, comprising a material selected from the group consisting of doped silicon having a doping concentration of less than about 1E14 dopant atoms per 1000 .mu.m.

13. 13. The layered substrate structure of claim 1, wherein the patterned bonding layer comprises a bonding material selected from the group consisting of polyimide polymer, indium, indium nitride, gold, gold nitride, platinum, platinum nitride, titanium, titanium nitride, tantalum, tantalum nitride, chromium, chromium nitride, tungsten, tungsten nitride, silver, silver nitride, copper, aluminum, aluminum oxide, and tin.

14. a device wafer including a ground plane layer formed on a first surface thereof, the ground plane layer including one or more first openings aligned with at least one electrical component of the device wafer; and an optical substrate bonded to the first surface via a patterned bonding layer including at least one second opening aligned with at least one of the one or more first openings; A layered substrate structure comprising:

15. 15. The layered substrate structure of claim 14, wherein the at least one electrical component is formed on a second side of the device wafer opposite the first side, the device wafer including one or more alignment marks for aligning the at least one electrical component with the one or more first openings.

16. forming one or more alignment marks in the device wafer from a first side of the device wafer; forming a ground plane layer on the first surface; forming one or more first openings in the ground plane layer at one or more defined locations relative to the one or more alignment marks; forming one or more second openings in the bonding layer; bonding an optical substrate to the ground plane layer of the device wafer via the bonding layer having the one or more first openings aligned with the one or more second openings; and thinning a second side of the device wafer opposite the first side to expose the one or more alignment marks, resulting in a layered substrate structure. A method for providing the above.

17. 17. The method of claim 16, wherein forming the one or more second openings comprises patterning the bonding layer to form on a surface of the optical substrate.

18. 18. The method of claim 16 or 17, wherein forming the one or more second openings comprises depositing the bonding layer over one or more portions of the ground plane layer excluding the one or more first openings.

19. 19. The method of claim 16, further comprising forming one or more closed cavities between the device wafer and the optical substrate at the one or more second openings as a result of the bonding step, wherein the bonding step comprises bonding the optical substrate to the device wafer in a vacuum or inert environment, thereby removing oxygen and water from the one or more closed cavities.

20. 20. The method of claim 16, further comprising: forming at least one electrical component on the second side of the device wafer at the one or more defined locations using the alignment marks, such that the at least one electrical component is aligned with the one or more first openings and the one or more second openings.

21. contacting the at least one electrical component with a laser beam through the optical substrate, at least one first opening of the one or more first openings, and at least one second opening of the one or more second openings; and modifying a state or characteristic of the at least one electrical component as a result of the contacting step.

21. The method of claim 20, further comprising:

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