Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suitably sticking substrates and a manufacturing method thereof.SOLUTION: According to an embodiment, a method for manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so as to warp the first substrate. The method also includes forming a second metal pad in each of a plurality of second regions on a second substrate via a prescribed pattern. In addition, the method includes sticking the first substrate and the second substrate after the first metal pad and the second metal pad are formed. Furthermore, the method includes making a correction, when forming the prescribed pattern in each of the plurality of second regions on the second substrate, to change a position of the prescribed pattern in each of the plurality of second regions in a direction approaching the center of the second substrate for a first direction, and in a direction separating from the center of the second substrate for a second direction.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When manufacturing a semiconductor device by bonding substrates together, there is a possibility that the substrates cannot be bonded together properly due to warping of at least one of the substrates. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. US2017 / 0069503 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device that allows substrates to be suitably bonded to each other and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so as to cause warping of the first substrate. The method further includes forming a predetermined pattern in each of a plurality of second regions on a second substrate, and forming a second metal pad in each of the plurality of second regions on the second substrate where the predetermined pattern is formed. The method further includes, after the first metal pads and the second metal pads are formed, bonding the first substrate and the second substrate together so that a first surface on which the first metal pads are formed faces a second surface on which the second metal pads are formed. In addition, the method further includes, when forming the predetermined pattern in each of the plurality of second regions on the second substrate, correcting the position of the predetermined pattern in each of the plurality of second regions by changing the position of the predetermined pattern in a first direction toward the center of the second substrate and by changing the position of the predetermined pattern in a second direction away from the center of the second substrate. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the structure of a columnar portion of the first embodiment. [Figure 3] 4 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 1A and 1B are a plan view and a perspective view showing a first example of a bonding method according to a first embodiment. [Figure 6] 4A and 4B are a plan view and a perspective view showing a second example of the bonding method according to the first embodiment. [Figure 7] 10A and 10B are a plan view and a perspective view showing a third example of the bonding method according to the first embodiment. [Figure 8] FIG. 10 is a plan view showing a modified example of the third example of the bonding method according to the first embodiment. [Figure 9] FIG. 2 is a perspective view schematically showing warpage occurring in the array wafer of the first embodiment. [Figure 10] FIG. 2 is a plan view showing details of the bonding method of the first embodiment. [Figure 11] 4 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 12, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. The semiconductor device in Fig. 1 is, for example, a three-dimensional memory. As will be described later, the semiconductor device in Fig. 1 is manufactured by bonding an array wafer including an array region 1 and a circuit wafer including a circuit region 2.

[0009] The array region 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film (SiO2 film) or a silicon nitride film (SiN film). The interlayer insulating film 13 is, for example, a silicon oxide film or a stacked film including a silicon oxide film and another insulating film. The memory cell array 11, the insulating film 12, the interlayer insulating film 13, and structures within the interlayer insulating film 13 are examples of a first film.

[0010] The circuit region 2 is provided below the array region 1. The symbol S indicates the boundary surface (bonding surface) between the array region 1 and the circuit region 2. The circuit region 2 includes an interlayer insulating film 14 and a substrate 15 below the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon (Si) substrate. The interlayer insulating film 14 and the structures within the interlayer insulating film 14 are examples of a second film. The substrate 15 is an example of a second substrate.

[0011] 1 shows the X direction and Y direction, which are parallel to the surface of the substrate 15 and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the substrate 15. These X direction, Y direction, and Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. The X direction is an example of a first direction, and the Y direction is an example of a second direction.

[0012] The array region 1 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in a memory cell array 11. FIG. 1 shows a staircase structure 21 of the memory cell array 11. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 24 and is also electrically connected to a source line SL. The source line SL includes a lower layer SL1 that is a semiconductor layer and an upper layer SL2 that is a metal layer.

[0013] The circuit region 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit region 2 also includes a plurality of contact plugs 33 provided on the gate electrodes 32, source diffusion layers, or drain diffusion layers of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and including a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wires.

[0014] The circuit region 2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a metal layer including a Cu (copper) layer. The circuit region 2 functions as a control circuit (logic circuit) that controls the operation of the array region 1. This control circuit is composed of a transistor 31 and the like, and is electrically connected to the metal pads 38. The metal pads 38 are an example of second metal pads.

[0015] The array region 1 includes a plurality of metal pads 41 provided on the metal pads 38 and a plurality of via plugs 42 provided on the metal pads 41. The array region 1 also includes a wiring layer 43 provided on the via plugs 42 and including a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wirings. The metal pads 41 are, for example, a metal layer including a Cu layer. The bit lines BL are included in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc. The metal pad 41 is an example of a first metal pad.

[0016] The array region 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on the via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of FIG. 1. The passivation film 47 is, for example, a stacked insulating film including a silicon oxide film and a silicon nitride film, and has an opening P that exposes the top surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through the opening P.

[0017] 2 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment, showing one of the plurality of columnar portions CL shown in FIG.

[0018] 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on an interlayer insulating film 13 (see FIG. 1). The word lines WL are, for example, metal layers including a W (tungsten) layer. The insulating layers 51 are, for example, silicon oxide films.

[0019] The columnar portion CL includes, in this order, a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, an insulating film such as a silicon nitride film, and is formed on the side surfaces of the word line WL and the insulating layer 51 via the block insulating film 52. The charge storage layer 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and is formed on the side surfaces of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0020] 3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0021] 3 shows an array wafer W1 including a plurality of array regions 1 and a circuit wafer W2 including a plurality of circuit regions 2. The orientation of the array wafer W1 in FIG. 3 is opposite to the orientation of the array region 1 in FIG. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. FIG. 3 shows the array wafer W1 before its orientation is reversed for bonding, and FIG. 1 shows the array region 1 after its orientation is reversed for bonding, bonding, and dicing.

[0022] 3, reference symbol S1 denotes the top surface of the array wafer W1, and reference symbol S2 denotes the top surface of the circuit wafer W2. The array wafer W1 includes a substrate 16 provided under an insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 16 is an example of a first substrate.

[0023] In this embodiment, as shown in FIG. 3, first, the memory cell array 11, insulating film 12, interlayer insulating film 13, staircase structure 21, metal pad 41, etc. are formed on the substrate 16 of the array wafer W1, and the interlayer insulating film 14, transistor 31, metal pad 38, etc. are formed on the substrate 15 of the circuit wafer W2. For example, via plugs 45, wiring layer 44, wiring layer 43, via plugs 42, and metal pad 41 are formed in this order on the substrate 16. Also, contact plugs 33, wiring layer 34, wiring layer 35, wiring layer 36, via plugs 37, and metal pad 38 are formed in this order on the substrate 15. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that S1 and S2 face each other. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pads 41 and 38. In this way, the substrate 16 and the substrate 15 are bonded together with the interlayer insulating films 13 and 14 interposed therebetween.

[0024] Thereafter, the substrate 15 is thinned by CMP (Chemical Mechanical Polishing), the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device shown in FIG. 1 is manufactured. Note that the metal pads 46 and the passivation film 47 are formed on the insulating film 12, for example, after the substrate 15 is thinned and the substrate 16 is removed.

[0025] In this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together, but instead, array wafers W1 may be bonded together. The contents described above with reference to Figures 1 to 4 and the contents described below with reference to Figures 5 to 12 are also applicable to bonding array wafers W1 together.

[0026] 1 shows the boundary surface between interlayer insulating film 13 and interlayer insulating film 14 and the boundary surface between metal pad 41 and metal pad 38, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of metal pad 41 or the side surface of metal pad 38, or the positional deviation between the side surface of metal pad 41 and metal pad 38.

[0027] Furthermore, the semiconductor device of this embodiment may be traded in the state shown in FIG. 1 after being cut into a plurality of chips, or in the state shown in FIG. 4 before being cut into a plurality of chips. FIG. 1 shows the semiconductor device in the state of chips, and FIG. 4 shows the semiconductor device in the state of a wafer. In this embodiment, a plurality of chip-shaped semiconductor devices (FIG. 1) are manufactured from one wafer-shaped semiconductor device (FIG. 4).

[0028] Next, with reference to FIGS. 5 to 8, three examples of a method (bonding method) for bonding the array wafer W1 and the circuit wafer W2 of this embodiment will be described.

[0029] FIG. 5 is a plan view and a perspective view showing a first example of the bonding method according to the first embodiment.

[0030] FIG. 5(a) shows the array wafer W1 immediately before bonding. The array wafer W1 includes multiple chip regions A1 and scribe regions B1 provided between these chip regions A1. Each chip region A1 corresponds to one array region 1. The scribe region B1 has a shape that combines multiple straight lines extending in the X direction and multiple straight lines extending in the Y direction. FIG. 5(a) also shows the center C1 of the array wafer W1 and a notch D1 in the array wafer W1. In FIG. 5(a), the notch D1 is located in the -Y direction from the center C1.

[0031] FIG. 5(b) shows the circuit wafer W2 immediately before bonding. The circuit wafer W2 also includes multiple chip regions A2 and scribe regions B2 provided between these chip regions A2. Each chip region A2 corresponds to one circuit region 2. The scribe region B2 has a shape that combines multiple straight lines extending in the X direction and multiple straight lines extending in the Y direction. FIG. 5(b) also shows the center C2 of the circuit wafer W2 and the notch D2 of the circuit wafer W2. In FIG. 5(b), the notch D2 is located in the -Y direction from the center C2.

[0032] The arrow Pa in FIG. 5(a) indicates a deviation between the design positions and the actual positions of various structures in the array wafer W1. FIG. 5(a) shows that the actual positions of these structures are shifted to the upper right relative to their design positions. Examples of these structures include memory cells in the memory cell array 11, metal pads 41, and via plugs 45 (see FIG. 3, etc.). Such deviations in position may occur, for example, when there is a problem with the semiconductor manufacturing equipment.

[0033] 5(c), like FIG. 4, shows how the array wafer W1 and the circuit wafer W2 are bonded together. Straight lines X1, Y1, and Z1 pass through the center C1 of the array wafer W1 and extend in the X, Y, and Z directions, respectively. Straight lines X2, Y2, and Z2 pass through the center C2 of the circuit wafer W2 and extend in the X, Y, and Z directions, respectively. A notch D1 (not shown) in the array wafer W1 is located in the -Y direction from the center C1, and a notch D2 (not shown) in the circuit wafer W2 is located in the -Y direction from the center C2.

[0034] FIG. 5(c) further shows regions 100-104 on the surface (bottom surface) of array wafer W1 and regions 200-204 on the surface (top surface) of circuit wafer W2. Region 100 is located at center C1, and regions 101, 102, 103, and 104 are located in the +X direction, -X direction, +Y direction, and -Y direction of region 100, respectively. Similarly, region 200 is located at center C2, and regions 201, 202, 203, and 204 are located in the +X direction, -X direction, +Y direction, and -Y direction of region 200, respectively. Note that the distance between region 100 and each of regions 101-104 is the same as the distance between region 200 and each of regions 201-204. Each of regions 100-104 includes one or more metal pads 41, and each of regions 200-204 includes one or more metal pads 38. Areas 100 to 104 are examples of first areas, and areas 200 to 204 are examples of second areas.

[0035] Typically, the array wafer W1 and the circuit wafer W2 are bonded together so that the regions 100-104 overlap the regions 200-204, respectively. However, in the array wafer W1 of this example, a misalignment occurs as shown in FIG. 5(a). Therefore, when bonding the array wafer W1 and the circuit wafer W2 of this example, the position of the circuit wafer W2 is translated in the direction indicated by arrow Qa. This makes it possible to bond the array wafer W1 and the circuit wafer W2 together so that the metal pads 41 and 38 (see FIG. 4, etc.) come into contact with each other. Such translational movement correction can be achieved by translating the circuit wafer W2 within the semiconductor manufacturing equipment.

[0036] FIG. 6 is a plan view and a perspective view showing a second example of the bonding method according to the first embodiment.

[0037] 6(a) and 6(b) show the array wafer W1 and the circuit wafer W2, respectively, immediately before bonding. The arrow Pb in FIG. 6(a) indicates the deviation between the design positions and the actual positions of various structures in the array wafer W1. FIG. 6(a) shows that the actual positions of these structures have moved counterclockwise relative to their design positions. Such deviations can occur, for example, when there is a problem with the semiconductor manufacturing equipment.

[0038] FIG. 6(c), like FIG. 4, shows how the array wafer W1 and the circuit wafer W2 are bonded together. In this example, the array wafer W1 has a misalignment as shown in FIG. 6(a). Therefore, when bonding the array wafer W1 and the circuit wafer W2 together, the position of the circuit wafer W2 is rotated in the direction indicated by arrow Qb. This allows the array wafer W1 and the circuit wafer W2 to be bonded together so that the metal pads 41 and 38 are in contact with each other. Such rotation correction can be achieved by rotating the circuit wafer W2 within the semiconductor manufacturing equipment.

[0039] FIG. 7 is a plan view and a perspective view showing a third example of the bonding method according to the first embodiment.

[0040] 7(a) and 7(b) show the array wafer W1 and the circuit wafer W2, respectively, immediately before bonding. The arrow Pc in FIG. 7(a) indicates the deviation between the design positions and the actual positions of various structures within the array wafer W1. FIG. 7(a) shows that the actual positions of these structures have moved away from the center C1 relative to their design positions. This corresponds to the actual structures being enlarged compared to the design structures. Such deviations can occur, for example, when there is a problem in the lithography exposure process.

[0041] FIG. 7(c), like FIG. 4, shows how the array wafer W1 and the circuit wafer W2 are bonded together. The array wafer W1 in this example has a misalignment as shown in FIG. 7(a). Therefore, when manufacturing the circuit wafer W2 in this example, various structures within the circuit wafer W2 are enlarged as shown by arrow Qc. Examples of these structures include the gate electrode 32 of the transistor 31, the contact plug 33, and the metal pad 38 (see FIG. 3, etc.). The circuit wafer W2 manufactured in this manner is then bonded to the array wafer W1. This allows the array wafer W1 and the circuit wafer W2 to be bonded together so that the metal pads 41 and 38 are in contact with each other. This enlargement correction can be achieved by changing the exposure magnification in the exposure process when manufacturing the circuit wafer W2.

[0042] The translational correction in the first example and the rotational correction in the second example are performed when the array wafer W1 and the circuit wafer W2 are bonded together after the circuit wafer W2 is manufactured, whereas the magnification correction in the third example is performed when the circuit wafer W2 is manufactured.

[0043] FIG. 8 is a plan view showing a modified example of the third example of the bonding method according to the first embodiment.

[0044] Figure 8(a) shows the array wafer W1 immediately before bonding. The array wafer W1 shown in Figure 8(a) is the same as the array wafer W1 shown in Figure 7(a). Therefore, arrows Pc in Figure 8(a) indicate the deviations between the designed positions and the actual positions of various structures in the array wafer W1.

[0045] FIG. 8(b) also shows the array wafer W1 immediately before bonding. The arrow Pd in FIG. 8(b) indicates the deviation between the design and actual positions of various structures within the array wafer W1. FIG. 8(b) shows that the actual positions of these structures have moved toward the center C1 relative to their design positions. This corresponds to the actual structures being scaled down compared to the design structures. This deviation can occur, for example, when there is a problem with the lithography exposure process. In this case, instead of scaling down the structures within the circuit wafer W2, scaling down the structures within the circuit wafer W2 is performed. This allows the array wafer W1 and the circuit wafer W2 to be bonded together so that the metal pads 41 and 38 are in contact with each other.

[0046] FIG. 8(c) also shows the array wafer W1 immediately before bonding. The arrows Pe in FIG. 8(c) indicate the deviations between the design and actual positions of various structures within the array wafer W1. FIG. 8(c) shows that the actual positions of these structures have shifted toward or away from the center C1 relative to their design positions. For example, for positions along the X direction, the actual positions have shifted toward or away from the center C1 relative to their design positions. On the other hand, for positions along the Y direction, the actual positions have shifted away from the center C1 relative to their design positions. Such deviations can occur, for example, when the array wafer W1 is warped. Correcting the positions of structures within the circuit wafer W2 in this case will be described later.

[0047] FIG. 9 is a perspective view schematically showing warpage occurring in the array wafer W1 of the first embodiment.

[0048] In this embodiment, when the memory cell array 11, insulating film 12, interlayer insulating film 13, etc. are formed on the substrate 16 as shown in Fig. 3, warping occurs in the substrate 16 due to the influence of the memory cell array 11, insulating film 12, interlayer insulating film 13, etc. As a result, the array wafer W1 warps as shown in Fig. 9. However, in Fig. 9, the warping generated in the array wafer W1 is illustrated larger than the actual warping in order to make the drawing easier to see.

[0049] 9, the warpage of the array wafer W1 (substrate 16) occurs such that the direction of warpage in a cross section taken along the X direction is opposite to the direction of warpage in a cross section taken along the Y direction. For example, in an XZ cross section passing through the center C1 (see FIG. 8(c) and the like) of the array wafer W1, the array wafer W1 in FIG. 9 is warped in a downwardly convex shape. On the other hand, in a YZ cross section passing through the center C1 of the array wafer W1, the array wafer W1 in FIG. 9 is warped in an upwardly convex shape. Therefore, the warpage of the array wafer W1 in FIG. 9 occurs such that the direction of warpage in the XZ cross section is opposite to the direction of warpage in the YZ cross section.

[0050] Such warpage of the array wafer W1 is caused by, for example, the influence of the word lines WL. Similar to FIG. 3, FIG. 9 schematically shows the word lines WL extending in the X direction. The word lines WL are, for example, metal layers including a W (tungsten) layer. The shape of the word lines WL has large anisotropy between the X direction and the Y direction, which causes warpage of the array wafer W1.

[0051] 10A and 10B are plan views showing details of the bonding method of the first embodiment, each showing the structure of the array wafer W1 and the circuit wafer W2 before bonding in plan view.

[0052] FIG. 10(a) shows an array wafer W1 that has warped due to the formation of the memory cell array 11, insulating film 12, interlayer insulating film 13, etc. on a substrate 16. The shape of the array wafer W1 shown in FIG. 10(a) is the same as the shape of the array wafer W1 shown in FIG. 9. FIG. 10(a) shows deviations between the designed and actual positions of various regions on the surface of the array wafer W1. In FIG. 10(a), the positions of regions 100 to 104 have shifted to regions 100' to 104', respectively, due to warpage in the array wafer W1. The positions of regions 100 to 104 correspond to the designed positions, and the positions of regions 100' to 104' correspond to the actual positions. For example, a metal pad 41 that is provided in region 101 in the design is actually provided in region 101'. The shapes of regions 100' to 104' may be deformed from the shapes of regions 100 to 104, respectively, due to warpage.

[0053] Arrows P1 to P4 shown in FIG. 10(a) indicate the misalignment between the positions of the regions 101 to 104 and the positions of the regions 101' to 104', respectively. The region 101' is shifted in the -X direction relative to the region 101. The region 102' is shifted in the +X direction relative to the region 102. The region 103' is shifted in the +Y direction relative to the region 103. The region 104' is shifted in the -Y direction relative to the region 104. Therefore, the positions of the regions 101' to 104' are shifted toward the center C1 along the X direction relative to the positions of the regions 101 to 104, and are shifted away from the center C1 along the Y direction. On the other hand, the position of the region 100' coincides with the position of the region 100. In this embodiment, such misalignment occurs due to warpage of the array wafer W1.

[0054] FIG. 10(b) shows the circuit wafer W2 when alignment marks M0 to M4 are formed on the substrate 15. In this embodiment, a plurality of recesses are formed in the substrate 15, and alignment marks M0 to M4 are embedded in these recesses. Thereafter, transistors 31 and interlayer insulating films 14 are formed on the substrate 15 via the alignment marks M0 to M4 (FIG. 3). At this time, the positions of various structures in the circuit wafer W2 are set based on the positions of the alignment marks M0 to M4. Examples of these structures include the gate electrode 32 of the transistor 31, the contact plug 33, and the metal pad 38. The alignment marks M0 to M4 are, for example, metal patterns formed from metal. The alignment marks M0 to M4 are examples of predetermined patterns.

[0055] In this embodiment, to address warpage of the array wafer W1, the positions of the alignment marks M0 to M4 are shifted when they are formed. FIG. 10(b) shows how the positions of the alignment marks M0 to M4 are shifted from the positions of the regions 200 to 204 to the positions of the regions 200′ to 204′, respectively. Therefore, the positions of the regions 200 to 204 correspond to the design positions of the alignment marks M0 to M4 before the positions are shifted. On the other hand, the positions of the regions 200′ to 204′ correspond to the actual positions of the alignment marks M0 to M4 after the positions are shifted. The shapes of the regions 200′ to 204′ may be modified from the shapes of the regions 200 to 204. Such positional correction of the alignment marks M0 to M4 can be achieved, for example, by correcting (changing) the exposure position in the exposure process when forming openings for the alignment marks M0 to M4 in the substrate 15.

[0056] Arrows Q1 to Q4 in FIG. 10(b) indicate the deviations between the positions of regions 201 to 204 and regions 201' to 204', respectively. Region 201' is shifted in the -X direction relative to region 201. Region 202' is shifted in the +X direction relative to region 202. Region 203' is shifted in the +Y direction relative to region 203. Region 204' is shifted in the -Y direction relative to region 204. Therefore, the positions of regions 201' to 204' are shifted toward center C2 along the X direction relative to regions 201 to 204, and are shifted away from center C2 along the Y direction relative to regions 201 to 204. Meanwhile, the position of region 200' coincides with the position of region 200. In this way, the position corrections of regions 200 to 204 in this embodiment are performed in the same direction as the positional deviations of regions 100 to 104 corresponding to regions 200 to 204. This makes it possible to correct the positions of the alignment marks M0 to M4 on the circuit wafer W2 in a direction that reduces the influence of warpage on the array wafer W1.

[0057] As described above, the positions of various structures within the circuit wafer W2 are set based on the positions of the alignment marks M0 to M4. Therefore, when the positions of the alignment marks M0 to M4 are corrected, the positions of these structures are also corrected. This makes it possible to bond the array wafer W1 and the circuit wafer W2 together so that the metal pads 41 and 38 are in contact with each other, even if the array wafer W1 is warped (FIG. 4).

[0058] 10(b) shows five alignment marks M0 to M4, the number of alignment marks in the circuit wafer W2 may be other than 5. The alignment marks are arranged, for example, in the scribe region B2 of the circuit wafer W2 (see FIG. 5(b), etc.).

[0059] Furthermore, the warpage described above may occur in the circuit wafer W2 instead of the array wafer W1, or may occur in both the array wafer W1 and the circuit wafer W2. However, in the semiconductor device of this embodiment, the array wafer W1 contains more metal layers than the circuit wafer W2, and therefore the array wafer W1 is more likely to warp than the circuit wafer W2. Furthermore, the alignment mark position correction may be applied to the alignment marks of the array wafer W1 instead of the alignment marks of the circuit wafer W2, or may be applied to the alignment marks of both the circuit wafer W2 and the array wafer W1. Furthermore, the alignment mark position correction of this embodiment may be applied when three or more wafers are bonded together.

[0060] Here, the position correction of the alignment marks M0 to M4 will be described in further detail.

[0061] In this embodiment, a plurality of array wafers W1 and a plurality of circuit wafers W2 are manufactured (FIG. 3), and one of these array wafers W1 is bonded to one of these circuit wafers W2 (FIG. 4). This produces a single bonded wafer including one array wafer W1 and one circuit wafer W2. In this embodiment, this bonding process is repeated multiple times to produce multiple bonded wafers.

[0062] In this embodiment, when manufacturing N bonded wafers (N is an integer of 2 or more), first, one array wafer W1 is manufactured and the warpage of this array wafer W1 is measured. Next, N-1 array wafers W1 and N circuit wafers W2 are manufactured. At this time, the positions of the alignment marks M0 to M4 of the circuit wafer W2 are corrected based on the results of the warpage measurement. This makes it possible to bond the array wafer W1 and the circuit wafer W2 of each bonded wafer so that the metal pads 41 and 38 are in contact with each other.

[0063] In this way, when manufacturing N bonded wafers in this embodiment, the warpage of only one array wafer W1 is measured without measuring all of the N array wafers W1. The reason is that these array wafers W1 have the same structure, and therefore the warpage patterns of these array wafers W1 are expected to be the same. This makes it possible to reduce the burden of measuring the warpage. Note that the array wafer W1 to be measured for warpage may be a wafer that is actually used in manufacturing bonded wafers, or may be a wafer that is not actually used in manufacturing bonded wafers.

[0064] In this way, when one array wafer W1 and one circuit wafer W2 are manufactured and bonded together, the warpage may be measured from this array wafer W1, or may be measured from another wafer (array wafer W1) having the same structure as this array wafer W1. In this case, the positions of the alignment marks M0 to M4 on this circuit wafer W2 may be corrected based on the warpage measurement results of the former, or may be corrected based on the warpage measurement results of the latter.

[0065] Whether the positions of the alignment marks M0 to M4 have been corrected can be determined, for example, by preparing data on the designed positions of the alignment marks M0 to M4, measuring the actual positions of the alignment marks M0 to M4, and comparing the measured results with the prepared data. Also, if the designed positions of the four alignment marks M1 to M4 are equidistant from the center C2, it is possible to determine whether corrections have been made by measuring whether the actual positions of the four alignment marks M1 to M4 are equidistant from the center C2.

[0066] 11 and 12 are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. This method corresponds to an example of a method for manufacturing the circuit wafer W2 shown in FIG.

[0067] First, a resist film 61 is formed on the substrate 15, and an opening 61a is formed in the resist film 61 by lithography and etching (FIG. 11(a)). As a result, the upper surface of the substrate 15 is exposed in the opening 61a.

[0068] Next, using the resist film 61 as a mask, alignment marks 62 are formed in the substrate 15 through the openings 61a (FIG. 11(a)). The alignment marks 62 are formed, for example, by forming openings in the substrate 15 by RIE (Reactive Ion Etching) and embedding the alignment marks 62 in the openings. In this case, the resist film 61 may be removed before embedding the alignment marks 62. The alignment marks 62 correspond to any of the alignment marks M0 to M4 described above. The alignment marks 62 are, for example, a metal layer such as an aluminum (Al) layer, a W (tungsten) layer, or a Cu (layer).

[0069] The alignment marks 62 of this embodiment are formed by the method described with reference to Fig. 10(b). For example, the formation positions (exposure positions) of the openings 61a during lithography are corrected based on the measurement results of the warpage of the array wafer W1. This corrects the positions of the openings in the substrate 15, and as a result, the positions of the alignment marks 62 are corrected.

[0070] Next, after removing the resist film 61, an underlayer 63, a layer to be processed 64, and a resist film 65 are formed in this order on the substrate 15 and the alignment mark 62 (FIG. 11(b)). The layer to be processed 64 is, for example, a metal layer for the contact plug 33, any one of the wiring layers 34 to 36, a metal layer for the via plug 37, or a metal layer for the metal pad 38.

[0071] Next, the resist film 65 is patterned by lithography and etching (FIG. 12(a)). As a result, a pattern (resist pattern) 65a is formed from the resist film 65. FIG. 12(a) shows how the position of the pattern 65a has changed from the position indicated by the symbol R1 as a result of position correction of the alignment mark 62.

[0072] Next, the layer to be processed 64 is processed by RIE using the resist film 65 as a mask (FIG. 11(b)). As a result, a pattern 64a is formed from the layer to be processed 64. The pattern 64a is, for example, a contact plug 33, wiring in the wiring layers 34 to 36, a via plug 37, or a metal pad 38. FIG. 12(b) shows how the position of the pattern 64a has changed from the position indicated by the symbol R2 as a result of the position correction of the pattern 64a. Thereafter, the resist film 65 is removed.

[0073] In this way, the circuit wafer W2 of this embodiment is manufactured. Thereafter, the array wafer W1 and the circuit wafer W2 are bonded together (FIG. 4), thereby manufacturing the semiconductor device of this embodiment.

[0074] As described above, when forming the alignment marks M0 to M4 (62) of the circuit wafer W2 of this embodiment, correction is performed to change the positions of the alignment marks M0 to M4 in the X direction toward the center C2 and in the Y direction away from the center C2. Therefore, according to this embodiment, even if the array wafer W1 has a warp as shown in FIG. 9, the array wafer W1 and the circuit wafer W2 can be suitably bonded together.

[0075] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0076] 1: array area, 2: circuit area, 11: memory cell array, 12: insulating film, 13: interlayer insulating film, 14: interlayer insulating film, 15: substrate, 16: substrate, 21: staircase structure portion, 22: contact plug, 23: word wiring layer, 24: via plug, 31: transistor, 32: gate electrode, 33: contact plug, 34: wiring layer, 35: wiring layer, 36: wiring layer, 37: via plug, 38: metal pad, 41: metal pad, 42: via plug, 43: wiring layer, 44: wiring layer, 45: via plug, 46: metal pad, 47: passivation film, 51: insulating layer, 52: block insulating film, 53: charge storage layer, 54: tunnel insulating film, 55: channel semiconductor layer, 56: core insulating film, 61: resist film, 61a: opening, 62: alignment mark, 63: underlayer, 64: Processing layer, 64a: Pattern, 65: Resist film, 65a: Pattern, 100~104, 100'~104': area, 200~204, 200'~204': Area

Claims

1. forming a first metal pad in each of a plurality of first regions on the first substrate so that the first substrate is warped; forming a predetermined pattern in each of a plurality of second regions on the second substrate; forming second metal pads in each of the plurality of second regions on the second substrate on which the predetermined pattern is formed; After the first metal pads and the second metal pads are formed, the first substrate and the second substrate are bonded together so that a first surface on which the first metal pads are formed faces a second surface on which the second metal pads are formed. This includes: When forming the predetermined pattern in each of the plurality of second regions on the second substrate, a correction is performed to change the position of the predetermined pattern in each of the plurality of second regions in a direction toward the center of the second substrate in a first direction and in a direction away from the center of the second substrate in a second direction. The method for manufacturing a semiconductor device further comprises:

2. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising, before bonding the first substrate and the second substrate together, forming a first film including the first metal pad on the first substrate, and forming a second film including the second metal pad on the second substrate.

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the first film includes a memory cell array, and the second film includes a circuit for controlling the memory cell array.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the warpage of the first substrate occurs such that the direction of the warpage in a cross section taken along the first direction is opposite to the direction of the warpage in a cross section taken along the second direction.

5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the first direction and the second direction are parallel to the surface of the second substrate and perpendicular to each other.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the predetermined pattern is formed in the second substrate.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the predetermined pattern is made of metal.

8. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the predetermined pattern is an alignment mark.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the position of said second metal pad is set based on the position of said alignment mark.

10. The method for manufacturing a semiconductor device according to claim 1 , wherein the position of the predetermined pattern is corrected based on a measurement result of the warpage of the first substrate.

11. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the position of the predetermined pattern is corrected based on a measurement result of warpage of a substrate different from the first substrate and on which a film identical to the first film is formed.

12. A second substrate; second metal pads provided in each of a plurality of second regions on the second substrate and provided above the second substrate via a predetermined pattern; a first metal pad provided on the second metal pad; a first substrate provided above the first metal pads and having a warp, the first metal pads being provided in each of a plurality of first regions below the first substrate; Equipped with A semiconductor device, wherein the position of the specified pattern in each of the plurality of second regions is shifted in a first direction toward the center of the second substrate and in a second direction away from the center of the second substrate.

13. a second film provided on the second substrate and including the second metal pad; a first film provided on the second film and including the first metal pad; The semiconductor device according to claim 12 , wherein the first substrate is provided on the first film.

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