Radio Frequency Switch Control Circuit

Abstract

To provide a device and a method for radio frequency (RF) switch control.SOLUTION: In an RF switch system 290, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level shifting n-type transistor between a first output providing a first switch control signal and a negative charge pump voltage, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level shifting n-type transistor and controlled by a first switch enable signal.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to electronic systems, and more particularly to radio frequency (RF) communication systems. [Background technology]

[0002] Radio frequency (RF) communication systems can be used to transmit and / or receive signals over a wide range of frequencies, for example, RF signals in a frequency range of about 30 kHz to 300 GHz, such as the range of about 400 MHz to about 7.125 GHz for Frequency Range 1 (FR1) of the fifth generation (5G) communication standard, or the range of about 24.250 GHz to about 71.000 GHz for Frequency Range 2 (FR2) of the 5G communication standard.

[0003] Examples of RF communication systems include, but are not limited to, mobile phones, tablets, base stations, network access points, customer premises equipment (CPE), laptops, and wearable electronic devices. Summary of the Invention

[0004] In certain embodiments, the present disclosure relates to a portable device. The portable device includes a power management system including a positive charge pump configured to generate a positive charge pump voltage, a negative charge pump configured to generate a negative charge pump voltage, and a voltage regulator configured to generate a regulated voltage. The portable device also includes a front-end system including a radio frequency switch controlled by a first switch control signal and a level shifter operable to level-shift a first switch enable signal to generate the first switch control signal at a first output. The level shifter includes a first level-shift n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output, a first level-shift p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulated voltage and a gate of the first level-shift n-type transistor, controlled by the first switch enable signal.

[0005] In some embodiments, the level shifter is further operable to level-shift the second switch enable signal to generate a second switch control signal at the second output. The second switch enable signal is complementary in polarity to the first switch enable signal. According to certain embodiments, the level shifter further includes a second level-shift n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage, a third cascode p-type transistor, and a third level-shift n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage. According to various embodiments, the level shifter further includes a fourth level-shift n-type transistor and a second cascode n-type transistor in series between the second output and the negative charge pump voltage, and a second level-shift p-type transistor and a fourth cascode p-type transistor in series between the positive charge pump voltage and the second output.

[0006] In some embodiments, the front-end system further includes a power amplifier configured to provide a radio frequency signal to the radio frequency switch.

[0007] In some embodiments, the power management system further includes a charge pump clock generator, the charge pump clock generator including a multi-phase oscillator configured to generate a plurality of oscillator clock signals, and a clock phase logic and combining circuit configured to process the plurality of oscillator clock signals to generate a first clock signal at a frequency higher than an oscillator frequency of the multi-phase oscillator, the first clock signal operable to control at least one of the positive charge pump or the negative charge pump. According to certain embodiments, the clock phase logic and combining circuit is further configured to generate a second clock signal out of phase with the first clock signal, the first clock signal operable to control the positive charge pump and the second clock signal operable to control the negative charge pump.

[0008] In certain embodiments, the present disclosure relates to a radio frequency switch system including a radio frequency switch configured to receive a radio frequency signal and controlled by a first switch control signal, a positive charge pump configured to generate a positive charge pump voltage, a negative charge pump configured to generate a negative charge pump voltage, a voltage regulator configured to generate a regulated voltage, and a level shifter operable to level shift a first switch enable signal to generate the first switch control signal at a first output, the level shifter including a first level shift n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output, a first level shift p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output, and a second cascode p-type transistor between the regulated voltage and a gate of the first level shift n-type transistor, the second cascode p-type transistor being controlled by the first switch enable signal.

[0009] In some embodiments, the level shifter is further operable to level-shift the second switch enable signal to generate a second switch control signal at the second output, the second switch enable signal being complementary in polarity to the first switch enable signal. According to certain embodiments, the level shifter further includes a second level-shift n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage, a third cascode p-type transistor, and a third level-shift n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage. According to some embodiments, the level shifter further includes a fourth level-shift n-type transistor and a second cascode n-type transistor in series between the negative charge pump voltage and the second output, and a second level-shift p-type transistor and a fourth cascode p-type transistor in series between the positive charge pump voltage and the second output. According to various embodiments, the radio frequency switch system further includes a first enable level shift circuit configured to level shift the first switch enable signal to generate a first level-shifted switch enable signal that controls the gate of the second level-shift p-type transistor, and a second enable level shift circuit configured to level shift the second switch enable signal to generate a second level-shifted switch enable signal that controls the gate of the first level-shift p-type transistor. According to certain embodiments, the gates of the first cascode p-type transistor and the fourth cascode p-type transistor are connected to a ground voltage. According to some embodiments, the gates of the second level-shift n-type transistor and the fourth level-shift n-type transistor are connected to a drain of a third level-shift n-type transistor, and the gates of the first level-shift n-type transistor and the third level-shift n-type transistor are connected to a drain of the second level-shift n-type transistor.According to various embodiments, a radio frequency switch includes a series transistor switch electrically connected between an input terminal and an output terminal and controlled by a first switch control signal, and a shunt transistor switch electrically connected between the input terminal and a ground voltage and controlled by a second switch control signal.

[0010] In some embodiments, the radio frequency switch system further includes a charge pump clock generator, the charge pump clock generator including a multi-phase oscillator configured to generate a plurality of oscillator clock signals, and a clock phase logic and combining circuit configured to process the plurality of oscillator clock signals to generate a first clock signal at a frequency higher than an oscillator frequency of the multi-phase oscillator, the first clock signal being operable to control at least one of the positive charge pump or the negative charge pump. According to certain embodiments, the clock phase logic and combining circuit is further configured to generate a second clock signal out of phase with the first clock signal, the first clock signal being operable to control the positive charge pump and the second clock signal being operable to control the negative charge pump.

[0011] In various embodiments, the voltage regulator is a low dropout regulator.

[0012] In certain embodiments, the present disclosure relates to a level shifter for a radio frequency switch, the level shifter including a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a first output providing a first switch control signal and a negative charge pump voltage, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between the positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor, the second cascode p-type transistor being controlled by a first switch enable signal.

[0013] In some embodiments, the level shifter further includes a second level-shifting n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage, a third cascode p-type transistor, and a third level-shifting n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage. According to certain embodiments, the level shifter further includes a fourth level-shifting n-type transistor and a second cascode n-type transistor in series between the second output and the negative charge pump voltage, and a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge pump voltage and the second output. According to various embodiments, the level shifter further includes a first enable level-shifting circuit configured to level-shift the first switch enable signal to generate a first level-shifted switch enable signal that controls the gate of the second level-shifting p-type transistor, and a second enable level-shifting circuit configured to level-shift the second switch enable signal to generate a second level-shifted switch enable signal that controls the gate of the first level-shifting p-type transistor. According to some embodiments, the gate of the first cascode p-type transistor and the gate of the fourth cascode p-type transistor are connected to ground voltage. According to a number of embodiments, the gate of the second level shift n-type transistor and the gate of the fourth level shift n-type transistor are connected to the drain of the third level shift n-type transistor, and the gate of the first level shift n-type transistor and the gate of the third level shift n-type transistor are connected to the drain of the second level shift n-type transistor. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic diagram of an example of a communication network. [Figure 2A] FIG. 1 is a schematic diagram of an example of a communication link using carrier aggregation. [Figure 2B] 2B illustrates various examples of uplink carrier aggregation for the communication link of FIG. 2A. [Figure 2C] 2B illustrates various examples of downlink carrier aggregation for the communication link of FIG. 2A. [Figure 3A] 1 is a schematic diagram of an example of a downlink channel using multiple-input multiple-output (MIMO) communication. [Figure 3B] 1 is a schematic diagram of an example of an uplink channel using MIMO communication. [Figure 3C] FIG. 10 is a schematic diagram of another example of an uplink channel using MIMO communication. [Figure 4] FIG. 1 is a schematic block diagram of a power amplifier system according to an embodiment. [Figure 5A] FIG. 1 is a schematic diagram of a level shifter according to an embodiment. [Figure 5B] 5B is a graph of an example of a waveform of the level shifter of FIG. 5A. [Figure 6] FIG. 1 is a schematic diagram of a charge pump according to one embodiment. [Figure 7A] FIG. 2 is a schematic diagram of a charge pump clock generator according to one embodiment. [Figure 7B] FIG. 1 is a schematic diagram of frequency multiplication logic for a charge pump clock generator of one embodiment. [Figure 7C] 1 is a graph of an example of waveforms for a positive charge pump and a negative charge pump operating at different clock frequencies. [Figure 8A] FIG. 10 is a schematic diagram of a charge pump clock generator according to another embodiment. [Figure 8B] FIG. 1 is a schematic diagram of frequency multiplication logic for a charge pump clock generator of one embodiment. [Figure 8C] 10 is a graph of an example of waveforms for a charge pump clock generator. [Figure 9] FIG. 1 is a schematic block diagram of a radio frequency (RF) switch system according to an embodiment. [Figure 10A] FIG. 2 is a schematic diagram of a package module according to an embodiment. [Figure 10B]FIG. 10B is a schematic cross-sectional view of the package module taken along line 10B-10B in FIG. 10A. [Figure 11] FIG. 10 is a schematic diagram of an RF switch network according to another embodiment. [Figure 12] FIG. 1 is a schematic diagram of a mobile device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in numerous different forms, as defined and covered, for example, by the claims. Reference is made herein to the drawings in which like reference numbers indicate identical or functionally similar elements. It is understood that the elements depicted in the drawings are not necessarily drawn to scale. It is further understood that certain embodiments may include more elements than shown in the drawings and / or a subset of the elements depicted in the drawings. Furthermore, some embodiments may include any suitable combination of features from two or more drawings.

[0016] The International Telecommunication Union (ITU) is a specialized agency of the United Nations (UN) responsible for global issues relating to information and communications technology, including the global sharing of radio spectrum.

[0017] The 3rd Generation Partnership Project (3GPP®) is a collaborative project between a group of telecommunications standards organizations around the world, such as the Association of Radio Industries and Businesses (ARIB), Telecommunications Technology Committee (TTC), China Communications Standards Association (CCSA), Alliance for Telecommunications Industry Solutions (ATIS), Telecommunications Technology Association (TTA), European Telecommunications Standards Institute (ETSI), and Telecommunications Standards Development Society of India (TSDSI).

[0018] 3GPP, within the ITU, develops and maintains technical specifications for various mobile communications technologies, including, for example, second-generation (2G) technologies (e.g., Global System for Mobile Communications (GSM) and Enhanced Data Rates for GSM Evolution (EDGE)), third-generation (3G) technologies (e.g., Universal Mobile Telecommunications System (UMTS) and High-Speed Packet Access (HSPA)), and fourth-generation (4G) technologies (e.g., Long Term Evolution (LTE) and LTE-Advanced).

[0019] Technical specifications maintained by 3GPP can be expanded and revised through specification releases, which may span multiple years and specify a wide range of new features and advancements.

[0020] In one example, 3GPP introduced carrier aggregation (CA) for LTE in Release 10. 3GPP initially introduced two downlink carriers but expanded this to include up to five downlink carriers and up to three uplink carriers in Release 14. Other examples of new features and advancements provided by 3GPP releases include, but are not limited to, Licensed Assisted Access (LAA), enhanced LAA (eLAA), Narrowband Internet of Things (NB-IOT), Vehicle-to-Everything (V2X), and High Power User Equipment (HPUE).

[0021] 3GPP introduced Phase 1 of fifth-generation (5G) technology in Release 15 and Phase 2 of 5G technology in Release 16. Subsequent 3GPP releases will further evolve and enhance 5G technology, which is also referred to herein as 5G New Radio (NR).

[0022] 5G NR supports or will support various features such as communication over millimeter wave spectrum, beamforming capabilities, high spectral efficiency waveforms, low latency communication, multiple radio numerology, and / or non-orthogonal multiple access (NOMA). Although such RF capabilities provide network flexibility and increase user data rates, supporting such features presents certain technical challenges.

[0023] The teachings herein are applicable to a wide variety of communication systems, including, but not limited to, communication systems that use advanced cellular technologies such as LTE-Advanced, LTE-Advanced Pro, and / or 5GNR.

[0024] 1 is a schematic diagram of an example of a communications network 10. The communications network 10 includes a macrocell base station 1, a small cell base station 3, and various examples of user equipment (UE), including a first mobile device 2a, a wirelessly connected car 2b, a laptop 2c, a stationary wireless device 2d, a wirelessly connected train 2e, a second mobile device 2f, and a third mobile device 2g.

[0025] Although particular examples of base stations and user equipment are shown in FIG. 1, a communications network may include many different types and / or numbers of base stations and user equipment.

[0026] For example, in the illustrated example, communication network 10 includes a macrocell base station 1 and a small cell base station 3. Small cell base station 3 may operate at relatively lower power, shorter distances, and / or fewer concurrent users than macrocell base station 1. Small cell base station 3 may also be referred to as a femtocell, picocell, or microcell. Although communication network 10 is shown as including two base stations, communication network 10 may be implemented to include more or fewer base stations and / or other types of base stations.

[0027] Although various examples of user equipment are shown, the teachings herein are applicable to a wide variety of user equipment, including, but not limited to, mobile phones, tablets, laptops, Internet of Things (IoT) devices, wearable electronics, customer premises equipment (CPE), wirelessly connected vehicles, wireless relays, and / or a wide variety of other communication devices. Furthermore, user equipment includes not only currently available communication devices that operate in cellular networks, but also subsequently developed communication devices that can readily implement the inventive systems, processes, methods, and devices described and claimed herein.

[0028] 1 supports communications using various cellular technologies, including, for example, 4G LTE and 5G NR. In certain implementations, communication network 10 is further adapted to provide a wireless local area network (WLAN), such as WiFi. Although various examples of communication technologies have been provided, communication network 10 may be adapted to support a wide variety of communication technologies.

[0029] Various communication links of communication network 10 are depicted in FIG. 1. The communication links may be duplexed in a variety of ways, including, for example, using frequency division duplexing (FDD) and / or time division duplexing (TDD). FDD is a type of radio frequency communication that uses different frequencies for transmitting and receiving signals. FDD can offer several advantages, such as high data rates and low latency. In contrast, TDD is a type of radio frequency communication that uses approximately the same frequency for transmitting and receiving signals, with transmit and receive communications alternating in time. TDD can offer several advantages, such as efficient use of spectrum and variable allocation of throughput between transmit and receive directions.

[0030] In certain implementations, user equipment may communicate with base stations using one or more of 4G LTE, 5G NR, and WiFi technologies. In certain implementations, enhanced license-assisted access (eLAA) is used to aggregate one or more licensed frequency carriers (e.g., licensed 4G LTE and / or 5G NR frequencies) with one or more unlicensed carriers (e.g., unlicensed WiFi frequencies).

[0031] 1, the communication links include not only communication links between UEs and base stations, but also UE-to-UE communication and base station-to-base station communication. For example, communication network 10 may be implemented to support self-fronthaul and / or self-backhaul.

[0032] The communication link can operate over a wide variety of frequencies. In certain implementations, communication is supported using 5G NR technology over one or more frequency bands below 6 gigahertz (GHz) and / or over one or more frequency bands above 6 GHz. For example, the communication link can provide Frequency Range 1 (FR1), Frequency Range 2 (FR2), or a combination thereof.

[0033] For example, 5G NR may operate with different specifications across the 5G frequency bands, including specifications with flexible numerology compared to 4G's fixed numerology. The FR1 (400 MHz to 7125 MHz) band operates with numerology subcarrier spacings of 15 kHz, 30 kHz, and 60 kHz. In addition, FR2, which includes FR2-1 (24 GHz to 52 GHz) and FR2-2 (52 GHz to 71 GHz), operates with numerology subcarrier spacings of 60 kHz, 120 kHz, and 240 kHz, allowing it to handle high phase noise and Doppler effects (e.g., for train applications up to 500 km / h).

[0034] In certain implementations, base stations and / or user equipment communicate using beamforming. For example, beamforming can be used to converge signal strength to overcome path losses, such as high losses associated with communication over high signal frequencies. In certain embodiments, one or more user equipment, such as mobile phones, communicate using beamforming in the millimeter wave frequency band ranging from 30 GHz to 300 GHz and / or in the upper centimeter wave frequencies ranging from 6 GHz to 30 GHz, particularly 24 GHz to 30 GHz. In one embodiment, one or more of the mobile devices supports the HPUE power class specification.

[0035] Different users of communication network 10 may share available network resources, such as the available frequency spectrum, in a wide variety of ways.

[0036] In one example, frequency division multiple access (FDMA) is used to divide a frequency band into multiple frequency carriers, with one or more carriers allocated to a particular user. Examples of FDMA include, but are not limited to, single-carrier FDMA (SC-FDMA) and orthogonal FDMA (OFDMA). OFDMA is a multi-carrier technique that divides the available bandwidth into multiple mutually orthogonal narrowband subcarriers that can be allocated separately to different users.

[0037] Other examples of shared access include, but are not limited to, time division multiple access (TDMA), in which users are assigned specific time slots to use the frequency resources, code division multiple access (CDMA), in which frequency resources are shared among different users by assigning each user a unique code, spatial division multiple access (SDMA), in which beamforming is used to provide shared access through spatial division, and non-orthogonal multiple access (NOMA), in which power domains are used for multiple access purposes. For example, NOMA may be used to serve multiple users with the same frequency, time, and / or code but at different power levels.

[0038] Enhanced Mobile Broadband (eMBB) refers to technology that increases the system capacity of LTE networks. For example, eMBB may refer to communication with a peak data rate of at least 10 Gbps and a minimum of 100 Mbps for each user. Ultra-reliable low-latency communication (uRLLC) refers to technology for very low-latency communication, e.g., less than 2 milliseconds. uRLLC can be used for mission-critical communications, such as for autonomous driving and / or remote surgery applications. Massive Machine-Type Communication (mMTC) refers to low-cost, low-data-rate communications associated with wireless connections to everyday objects, e.g., communications associated with Internet of Things (IoT) applications.

[0039] The communications network 10 of FIG. 1 may be used to support a wide variety of advanced communications features, including, but not limited to, eMBB, uRLLC, and / or mMTC.

[0040] 2A is a schematic diagram of an example communication link using carrier aggregation, which can be used to increase the bandwidth of a communication link by supporting communication across multiple frequency carriers, thereby increasing user data rates, and improving network capacity by utilizing fragmented spectrum allocations.

[0041] In the illustrated example, a communication link is provided between a base station 21 and a mobile device 22. As shown in Figure 2A, the communication link includes a downlink channel (DL) used for RF communication from the base station 21 to the mobile device 22 and an uplink channel (UL) used for RF communication from the mobile device 22 to the base station 21.

[0042] Although FIG. 2A illustrates carrier aggregation in the context of FDD communications, carrier aggregation can also be used for TDD communications.

[0043] In certain implementations, the communication link may provide asymmetric data rates for the downlink and uplink channels. For example, the communication link may support a relatively high downlink data rate to enable high-speed streaming of multimedia content to a mobile device, while providing a relatively low data rate for uploading data from the mobile device to the cloud.

[0044] In the illustrated example, the base station 21 and the mobile device 22 communicate via carrier aggregation, which can be used to selectively increase the bandwidth of the communication link. Carrier aggregation includes contiguous aggregation, in which contiguous carriers are aggregated within the same operating frequency band. Carrier aggregation may also be non-contiguous, and may include frequency-separated carriers within a common band or different bands.

[0045] In the example shown in FIG. 2A, the uplink channel is divided into three aggregated component carriers f UL1 , f UL2 and f UL3 In addition, the downlink channel includes five aggregated component carriers f DL1 , f DL2 , f DL3 , f DL4 and f DL5 Although an example component carrier aggregation is shown, more or fewer carriers may be aggregated for the uplink and / or downlink. Furthermore, the number of aggregated carriers may be varied over time to achieve desired uplink and downlink data rates.

[0046] For example, the number of carriers aggregated for uplink and / or downlink communications for a particular mobile device may change over time, e.g., as the device moves through the communications network and / or as network usage conditions change over time.

[0047] Figure 2B shows various examples of uplink carrier aggregation for the communication link of Figure 2A, including a first carrier aggregation scenario 31, a second carrier aggregation scenario 32, and a third carrier aggregation scenario 33, which schematically depict three types of carrier aggregation.

[0048] Carrier aggregation scenarios 31 to 33 are based on the first component carrier f UL1 , second component carrier f UL2 , and the third component carrier f UL3 2B illustrates different spectrum allocations for the uplink and downlink. Although FIG. 2B is shown in the context of aggregating three component carriers, carrier aggregation can also be used to aggregate more or fewer carriers. Furthermore, although shown in the context of the uplink, the aggregation scenario is also applicable to the downlink.

[0049] The first carrier aggregation scenario 31 illustrates intra-band contiguous carrier aggregation, in which component carriers that are adjacent in frequency and within a common frequency band are aggregated. For example, the first carrier aggregation scenario 31 illustrates intra-band contiguous carrier aggregation, in which component carriers f UL1 , f UL2 and f UL3 Draw the aggregation of.

[0050] Continuing with reference to FIG. 2B, a second carrier aggregation scenario 32 illustrates intra-band non-contiguous carrier aggregation in which two or more component carriers at non-adjacent frequencies but within a common frequency band are aggregated. For example, the second carrier aggregation scenario 32 illustrates an ... UL1 , f UL2 and f UL3 Draw the aggregation of.

[0051] The third carrier aggregation scenario 33 illustrates intra-band discontinuous carrier aggregation in which component carriers at non-adjacent frequencies and in multiple frequency bands are aggregated. For example, the third carrier aggregation scenario 33 illustrates intra-band discontinuous carrier aggregation in which component carriers f UL1 and f UL2 and component carrier f of the second frequency band BAND2 UL3 It depicts the convergence of

[0052] 2C illustrates various examples of downlink carrier aggregation for the communication link of FIG. 2A. These examples are for the first component carrier f DL1 , second component carrier f DL2 , third component carrier f DL3 , 4th component carrier f DL4 and 5th component carrier f DL5 2C depicts various carrier aggregation scenarios 34-38 for different spectrum allocations. Although FIG. 2C is shown in the context of aggregating five component carriers, carrier aggregation can also be used to aggregate more or fewer carriers. Furthermore, although shown in the context of the downlink, the aggregation scenarios are also applicable to the uplink.

[0053] A first carrier aggregation scenario 34 illustrates the aggregation of component carriers that are contiguous and located within the same frequency band. Additionally, a second carrier aggregation scenario 35 and a third carrier aggregation scenario 36 illustrate two examples of aggregations that are discontinuous but located within the same frequency band. Furthermore, a fourth carrier aggregation scenario 37 and a fifth carrier aggregation scenario 38 illustrate two examples of aggregations in which component carriers that are non-adjacent frequencies and located within multiple frequency bands are aggregated. As the number of component carriers to be aggregated increases, the complexity of the possible carrier aggregation scenarios also increases.

[0054] 2A-2C, individual component carriers used in carrier aggregation may have different frequencies, including, for example, frequency carriers in the same band or in multiple bands. In addition, carrier aggregation is applicable to implementations where individual component carriers have approximately the same bandwidth, and also applicable to implementations where individual component carriers have different bandwidths.

[0055] A given communication network allocates a primary component carrier (PCC) or anchor carrier for the uplink and a PCC for the downlink to a particular user device. Additionally, when a mobile device communicates using a single frequency carrier for either the uplink or downlink, the user device communicates using the PCC. To improve bandwidth for uplink communications, an uplink PCC can be aggregated with one or more uplink secondary component carriers (SCCs). Additionally, to improve bandwidth for downlink communications, a downlink PCC can be aggregated with one or more downlink SCCs.

[0056] In certain implementations, a communication network provides a network cell for each component carrier. Additionally, the primary cell operates using a PCC, while the secondary cell operates using an SCC. The primary and secondary cells may have different coverage areas due to differences in carrier frequencies and / or network environments.

[0057] Licensed Assisted Access (LAA) refers to downlink carrier aggregation in which licensed frequency carriers associated with a mobile operator i are aggregated with frequency carriers in unlicensed spectrum, such as WiFi. LAA uses downlink PCCs in the licensed spectrum to carry control and signaling information associated with the communication link, while unlicensed spectrum is aggregated, when available, for wider downlink bandwidth. LAA may operate by dynamically adjusting secondary carriers to avoid and / or coexist with WiFi users. Enhanced Licensed Assisted Access (eLAA) is an evolution of LAA that aggregates licensed and unlicensed spectrum for both the downlink and uplink. Furthermore, NR-U may operate over LAA / eLAA via the 5 GHz band (5150-5925 MHz) and / or the 6 GHz band (5925-7125 MHz).

[0058] 3A and 3B are schematic diagrams of an example downlink channel using multiple-input, multiple-output (MIMO) communication, respectively, and an example uplink channel using MIMO communication.

[0059] MIMO communications uses multiple antennas over a common frequency spectrum to simultaneously communicate multiple data streams. In certain implementations, the data streams operate with different reference signals to enhance data reception at the receiver. MIMO communications benefit from a higher SNR, improved coding, and / or reduced signal interference due to spatial multiplexing in the wireless environment.

[0060] MIMO order refers to the number of separate data streams transmitted or received. For example, the MIMO order of downlink communication can be described by the number of transmit antennas at a base station and the number of receive antennas at a UE, such as a mobile device. For example, two-by-two (2x2) DLMIMO refers to MIMO downlink communication using two base station antennas and two UE antennas. Additionally, four-by-four (4x4) DLMIMO refers to MIMO downlink communication using four base station antennas and four UE antennas.

[0061] In the example shown in Figure 3A, downlink MIMO communication is provided by transmitting using M antennas 43a, 43b, 43c, ... 43m at base station 41 and receiving using N antennas 44a, 44b, 44c, ... 44n at mobile device 42. Figure 3A therefore shows an example of mxn DL MIMO.

[0062] Similarly, the MIMO order of uplink communications can be described by the number of transmit antennas at a UE, such as a mobile device, and the number of receive antennas at a base station. For example, 2x2UL MIMO refers to MIMO uplink communications using two UE antennas and two base station antennas. Additionally, 4x4UL MIMO refers to MIMO uplink communications using four UE antennas and four base station antennas.

[0063] In the example shown in Figure 3B, uplink MIMO communication is provided by transmission using N antennas 44a, 44b, 44c, ... 44n at mobile device 42 and reception using M antennas 43a, 43b, 43c, ... 44m at base station 41. Figure 3B therefore shows an example of nxm U L MIMO.

[0064] By increasing the level or order of MIMO, the data bandwidth of the uplink and / or downlink channels can be increased.

[0065] MIMO communication is applicable to various types of communication links, such as FDD and TDD communication links.

[0066] 3C is a schematic diagram of another example of an uplink channel using MIMO communication. In the example shown in FIG. 3C, the uplink MIMO communication is provided by transmission using N antennas 44a, 44b, 44c, ... 44n of the mobile device 42. Additionally, a first portion of the uplink transmission is received using M antennas 43a1, 43b1, 43c1, ... 43m1 of the first base station 41a, while a second portion of the uplink transmission is received using M antennas 43a2, 43b2, 43c2, ... 43m2 of the second base station 41b. Additionally, the first base station 41a and the second base station 41b communicate with each other via wired, optical, and / or wireless links.

[0067] The MIMO scenario of FIG. 3C illustrates an example in which multiple base stations cooperate to facilitate MIMO communications.

[0068] 4 is a schematic block diagram of one embodiment of a power amplifier system 140. The illustrated power amplifier system 140 includes an RF switching circuit 127 including a series switch transistor 125 and a shunt switch transistor 126. The illustrated power amplifier system 140 further includes a charge pump 122, a level shifter 123, a directional coupler 124, a power amplifier bias circuit 130, a power amplifier 132, and a transmitter 133. The illustrated transmitter 133 includes a baseband processor 134, an I / Q modulator 137, a mixer 138, and an analog-to-digital converter (ADC) 139. Although not shown in FIG. 4 for clarity, the transmitter 133 may include circuitry associated with receiving signals via one or more receive paths such that a transceiver function is achieved.

[0069] The baseband processor 134 may be used to generate in-phase (I) and quadrature (Q) signals that may be used to represent a sine wave or sinusoidal signal of a desired amplitude, frequency, and phase. For example, the I signal may be used to represent the in-phase component of a sine wave, and the Q signal may be used to represent the quadrature component of the sine wave, thereby providing an equivalent representation of the sine wave. In certain implementations, the I and Q signals are provided to the I / Q modulator 137 in digital form. The baseband processor 134 may be any suitable processor configured to process baseband signals. For example, the baseband processor 134 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Furthermore, in some implementations, more than one baseband processor 134 may be included in the power amplifier system 140.

[0070] The I / Q modulator 137 is configured to receive the I and Q signals from the baseband processor 134 and process the I and Q signals to generate an RF signal. For example, the I / Q modulator 137 may include a number of digital-to-analog converters (DACs) that convert the I and Q signals to analog form, a mixer that upconverts the I and Q signals to radio frequencies, and a signal combiner that combines the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 132. In certain implementations, the I / Q modulator 137 may include one or more filters configured to filter frequency components of the signal being processed.

[0071] The power amplifier bias circuit 130 can receive one or more control signals from the baseband processor 134, which can be used to generate one or more bias signals for the power amplifier 132. The control signals can include, for example, bias settings, or level and / or enable functions. The power amplifier 132 can receive an RF signal from an I / Q modulator 137 of the transmitter 133.

[0072] The level shifter 123 can turn the series switch transistor 125 and the shunt switch transistor 126 on and off in a complementary manner. For example, the level shifter 123 can be used to cause the power amplifier 132 to provide an amplified RF signal to the antenna 114 via the series switch transistor 125 by turning on the series switch transistor 125 and turning off the shunt switch transistor 126. In addition, the level shifter 123 can be used to provide a high impedance path between the output of the power amplifier 132 and the antenna 114 while providing a termination to the output of the power amplifier by turning off the series switch transistor 125 and turning on the shunt switch transistor 126. To control the state of the RF switching circuit 127, the level shifter 123 can receive a switch enable signal (not shown in FIG. 4 ) from any suitable circuit, such as a transmitter 133.

[0073] The directional coupler 124 may be disposed between the output of the power amplifier 132 and the source of the series switch transistor 125, thereby enabling measurement of the output power of the power amplifier 132 without including the insertion loss of the series switch transistor 125. The sensed output signal from the directional coupler 124 is provided to a mixer 138. The mixer 138 may downshift the frequency components of the sensed output signal by multiplying the sensed output signal by a reference signal at a controlled frequency to generate a downshifted signal. The downshifted signal may be provided to an ADC 139, which may convert the downshifted signal into a digital format suitable for processing by the baseband processor 134.

[0074] The baseband processor 134 may be configured to dynamically adjust the I and Q signals to optimize the operation of the power amplifier system 140 by including a feedback path between the output of the power amplifier 132 and the baseband processor 134. For example, configuring the power amplifier system 140 in this manner may assist in controlling the power added efficiency (PAE) and / or linearity of the power amplifier 132.

[0075] In the illustrated configuration, charge pump 122 provides a positive charge pump voltage and a negative charge pump voltage to level shifter 123. In certain configurations (e.g., when the switches are implemented with n-type transistors), the positive charge pump voltage is used to bias the gate voltage of series switch transistor 125 and / or shunt switch transistor 126 when on, while the negative charge pump voltage is used to bias the gate voltage of series switch transistor 125 and / or shunt switch transistor 126 when off.

[0076] Although each of the series switch transistor 125 and the shunt switch transistor 126 is depicted as a single transistor, stacks of multiple transistors are typically used to implement each of the series switch transistor 125 and the shunt switch transistor 126. For example, stacking the transistors helps meet a desired power handling capability. Additionally, details of the predetermined biasing of the series switch transistor 125 and the shunt switch transistor 126, such as gate resistors and other biasing, are not depicted in FIG. 4 for the sake of brevity.

[0077] 5A is a circuit diagram of one embodiment of a level shifter 210. The level shifter 210 includes a first n-type metal-oxide semiconductor (NMOS) level-shifting transistor 171, a second NMOS level-shifting transistor 172, a third NMOS level-shifting transistor 173, a fourth NMOS level-shifting transistor 174, a first NMOS cascode transistor 181, a second NMOS cascode transistor 182, a first p-type metal-oxide semiconductor (PMOS) level-shifting transistor 191, a second PMOS level-shifting transistor 192, a first PMOS cascode transistor 193, a second PMOS cascode transistor 194, a third PMOS cascode transistor 195, a fourth PMOS cascode transistor 196, a first effective level shifter 207, and a second effective level shifter 208.

[0078] In the illustrated embodiment, the level shifter 210 generates a switch enable signal SW EN , inverted switch enable signal SW ENB , the regulated voltage V (from a voltage regulator such as a low-dropout regulator) REG , the negative charge pump voltage V (from the negative charge pump) NEG , and the positive charge pump voltage V (from the positive charge pump) POS The level shifter 210 receives a non-inverting switch control output SW CTL and inverting switch control output SW CTLB Although both of these outputs are used in certain applications, in other applications only one of the level shifter outputs is used.

[0079] The first enable level shifter 207 outputs the switch enable signal SW EN to generate a level-shifted switch enable signal in the voltage domain of the positive charge pump (first enable level shifter 207 and second enable level shifter 208 are V POS and ground). In addition, the second enable level shifter 208 outputs an inverted switch enable signal SW ENB to generate a level-shifted inverted switch enable signal in the voltage domain of the positive charge pump. Although shown as receiving a pair of switch enable signals of complementary polarity, in other embodiments, level shifter 210 receives a single switch enable signal that can be inverted (e.g., using an inverter) to generate the pair of switch enable signals.

[0080] As shown in FIG. 5A, the first NMOS level shift transistor 171 and the first NMOS cascode transistor 181 are connected to the negative charge pump voltage V NEG and inverting switch control output SWCTLB , while the first PMOS level shift transistor 191 and the first PMOS cascode transistor 193 are connected in series (from source to drain) between the positive charge pump voltage V POS and inverting switch control output SW CTLB Furthermore, the fourth NMOS level shift transistor 174 and the second NMOS cascode transistor 182 are connected in series (from source to drain) between the negative charge pump voltage V NEG and non-inverting switch control output SW CTL , while the second PMOS level shift transistor 192 and the fourth PMOS cascode transistor 196 are connected in series (source to drain) between the positive charge pump voltage V POS and non-inverting switch control output SW CTL and are connected in series (from source to drain) between

[0081] In the illustrated embodiment, the gate of the first NMOS level shift transistor 171 and the gate of the third NMOS level shift transistor 173 are connected to the drain of the second NMOS level shift transistor 172. In addition, the gate of the second NMOS level shift transistor 172 and the gate of the fourth NMOS level shift transistor 174 are connected to the drain of the third NMOS level shift transistor 173. The gates and drains of the second NMOS level shift transistor 172 and the third NMOS level shift transistor 173 are cross-coupled.

[0082] The gates of the first NMOS cascode transistor 181 and the second NMOS cascode transistor 182 are connected to the regulated voltage VREG. In addition, the gate of the second PMOS cascode transistor 194 is controlled by a switch enable signal SWEN, while the gate of the third PMOS cascode transistor 195 is controlled by an inverted switch enable signal SWENB.

[0083] The gates of the first PMOS cascode transistor 193 and the fourth PMOS cascode transistor 196 are grounded. In addition, the gate of the first PMOS level shift transistor 191 receives a level shift inverting switch enable signal, while the gate of the second PMOS level shift transistor 192 receives a level shift switch enable signal.

[0084] The level shifter 210 provides several advantages, including low current draw from the charge pump voltages VPOS and VNEG, low voltage headroom, and robust latching (of the cross-coupled transistors 172 and 173) during low-voltage operation. Additionally, the regulated voltage VREG is low impedance to maintain robust operation and is also quickly active after startup. That is, the level shifter 210 is associated with a fast startup time and can perform level shifting even when the charge pump voltages VPOS and / or VNEG are not at steady-state values, such as immediately after power-up sequencing and / or startup.

[0085] 5B is a graph of example waveforms for level shifter 210 of FIG. 5A. The graph includes waveforms for the positive charge pump voltage VPOS, the negative charge pump voltage VNEG, the switch control output SWCTL, and the inverting switch control output SWCTLB for an example in which the positive and negative charge pumps, driving many level shifters, experience large current draws at predetermined time instances (approximately 12 microseconds (μs) and 27 μs in this simulation) associated with switch state changes (e.g., at the end of a transmit or receive time window in a time division duplexing (TDD) application).

[0086] As shown in FIG. 5B, even when a large current is drawn by the charge pump power supply, the level shifter 210 continues to operate properly.

[0087] 6 is a schematic diagram of one embodiment of a charge pump 220. The charge pump 220 includes a first group of clock inverters 211a / 212a / 213a, a second group of clock inverters 211b / 212b / 213b, a first flying capacitor Cfly1, a second flying capacitor Cfly2, a first NMOS transistor 215, a second NMOS transistor 216, a first PMOS transistor 217, and a second PMOS transistor 218.

[0088] 6, charge pump 220 includes a first clock input CLK that receives a non-inverted clock signal to drive a first group of clock inverters 211a / 212a / 213a and a second clock input CLK_B that receives an inverted clock signal to drive a second group of clock inverters 211b / 212b / 213b. The first group of clock inverters 211a / 212a / 213a are sized to buffer the non-inverted clock signal to provide sufficient drive strength to drive the first terminal of the first flying capacitor Cfly1. Similarly, the second group of clock inverters 211b / 212b / 213b are sized to buffer the inverted clock signal to provide sufficient drive strength to drive the first terminal of the second flying capacitor Cfly2.

[0089] The clock inverters may include any suitable number of inverters and may be scaled in any suitable manner (1x, 4x, and 12x in this example). That is, although an example of three inverters with 4x scaling is shown, more or fewer inverters and / or different scaling may be used. In certain implementations, the buffered clock signals used to drive the flying capacitors correspond to a pair of non-overlapping clock signals.

[0090] 6, charge pump 220 includes a first terminal VP and a second terminal VN. Based on the connectivity of the first terminal VP and the second terminal VN, charge pump 220 can act as a positive charge pump (e.g., VPOS is generated at the first terminal VP having a boosted voltage compared to the second terminal VN being connected to a normal supply voltage applied to the pins of the die) or a negative charge pump (e.g., VNEG is generated at the second terminal VN having a reduced or buck voltage compared to the first terminal VP being connected to ground).

[0091] 7A is a schematic diagram of one embodiment of a charge pump clock generator 230. The charge pump clock generator 230 includes a multi-phase oscillator (corresponding to a seven-phase ring oscillator 221 in this example). The charge pump clock generator 230 further includes a clock phase logic circuit 222 (implemented as AND gates 222a, 222b, 222c, 222d, 222e, 222f, and 222g in this example) and a clock phase combining circuit 223.

[0092] In the illustrated embodiment, the ring oscillator 221 generates a clock signal clk <1> , clk <2> , clk <3> , clk <4> , clk <5> , clk <6> and clk <7> These clock signals have a common frequency but different phases (e.g., equally separated). In addition, AND gates 222a, 222b, 222c, 222d, 222e, 222f, and 222g perform logical operations on adjacent clock signal phases to generate clock phase signals ph1, ph2, ph3, ph4, ph5, ph6, and ph7. These clock phase signals are processed by a phase combining circuit 223 to generate a clock signal CLK having a frequency multiplied by the oscillation frequency of the ring oscillator 221.

[0093] In this example, the AND gates are each operated by a corresponding enable signal EN1, EN2, EN3, EN4, EN5, EN6, and EN7, each of which selectively enables one or more of the clock phase signals ph1, ph2, ph3, ph4, ph5, ph6, and ph7.

[0094] Charge pump clock generator 230 advantageously synthesizes a clock signal at a higher frequency than oscillator 221. This in turn reduces frequency spurs and / or undesirable clock noise in the charge pump output voltage (e.g., VPOS or VNEG) generated by a charge pump that uses the clock signal to control pumping.

[0095] 7B is a schematic diagram of one embodiment of frequency multiplication logic 240 for a charge pump clock generator. Frequency multiplication logic 240 includes clock phase logic circuit 232 (implemented in this example as AND gates 232a, 232b, 232c, 232d, 232e, 232f, 232g, 232h, and 232i) and clock phase combining circuit 233 (implemented in this example as OR gates 233a, 233b, 234, and 235).

[0096] In the illustrated embodiment, the clock phase logic circuit generates nine clock signals (CLK <1> , CLK <2> , CLK <3> , CLK <4> , CLK <5> , CLK <6> , CLK <7> , CLK <8> and CLK <9> ) to process the clock signal phase CLK_a <1> , CLK_a <2> , CLK_a <3> , CLK_a <4> , CLK_a <5> , CLK_a <6> , CLK_a <7> , CLK_a <8> and CLK_a <9> The phase combiner circuit 233 logically ORs the clock signal phases to generate a boosted clock signal FCLK_BOOST that has a higher frequency than the frequency of the received clock signal from the multi-phase oscillator.

[0097] 7C is a graph of example waveforms for a positive charge pump and a negative charge pump operating at different clock frequencies. As shown by the waveforms, a faster clock speed is advantageous for providing a charge pump with high output drive capability and / or initial ramp-up time.

[0098] Although fast clock speeds are desirable, using a fast resonator introduces frequency spurs and / or undesirable clock noise. In accordance with the teachings herein, fast pumping, small frequency spurs, and / or low clock noise are achieved by using a slow running oscillator to synthesize a fast clock signal for the charge pump.

[0099] 8A is a schematic diagram of another embodiment of a charge pump clock generator 250. The charge pump clock generator 250 includes a multi-phase oscillator (corresponding to a seven-phase ring oscillator 241 in this example). The charge pump clock generator 230 further includes a clock phase logic and combining circuit 242 (implemented as exclusive OR gates 242a, 242b, and 242c in this example).

[0100] The clock phase logic and combining circuit 242 processes the oscillator clock signal from the multi-phase oscillator to generate a first multiplied clock signal (CLK_DBL <1> or pvg) (for example, CLK_DBL <1> can be inverted to generate the pair of input clock signals CLK and CLKB to the charge pump 220 of FIG. 6), and a second multiplied clock signal (CLK_DBL <3> or nvg).

[0101] Advantageously, the first and second multiplied clock signals are of a common frequency but are out of phase to spread out the time instances of current draw in the positive and negative charge pumps, i.e., improved performance is achieved compared to configurations in which the clock signals to the positive and negative charge pumps are in phase (phase aligned).

[0102] 8B is a schematic diagram of the frequency multiplication logic 260 for the charge pump clock generator 260 of one embodiment. In this example, the clock signal phase (CLK <1> , CLK <3> , CLK <5> and CLK <8> ) are used to synthesize clock signals CLK_DBL1 and CLK_DBL2, each with double the frequency (doubled). In addition, an OR gate 253 is used to synthesize clock signals CLK_DBL1 and CLK_DBL2, each with double the frequency (doubled). <1> , CLK <3> , CLK <5> and CLK <8> ) is generated a clock signal CLK_4x having four times the frequency (frequency quadrupling).

[0103] 8C is a graph of an example of waveforms for a charge pump clock generator. The waveforms correspond to a charge pump clock generator including frequency multiplication logic 260 of FIG. 8B. As shown in FIG. 8C, frequency quadrupling is achieved.

[0104] 9 is a schematic block diagram of an RF switch system 290 according to one embodiment. The RF switch system 290 includes RF switches 291a, 291b, ... 291n, a switch controller 292, a positive charge pump 293 that generates a positive charge pump voltage VPOS, a negative charge pump 294 that generates a negative charge pump voltage VNEG, and a charge pump clock generator 295.

[0105] As shown in FIG. 9, the switch controller 292 includes a voltage regulator (corresponding to a low dropout regulator 297 in this example) that generates a regulated voltage VREG, and level shifters 298a, 298b, . . . 298n.

[0106] 9, the level shifters 298a, 298b, ... 298n operate to level-shift the switch enable signals SWENa, SWENb, ... SWENn and generate switch control signals SWCTLa, SWCTLb, ... SWCTLn for the RF switches 291a, 291b, ... 291n, respectively. As shown in FIG. 9, the level shifters 298a, 298b, ... 298n receive the regulated voltage VREG, the positive charge pump voltage VPOS, and the negative charge pump voltage VNEG, respectively. In addition, the charge pump clock generator 295 generates clock signals for the positive charge pump 293 and the negative charge pump 294.

[0107] The level shifters 298a, 298b, . . . 298n and / or the charge pump clock generator 295 may be implemented according to any of the embodiments herein.

[0108] Although the illustrated RF switch system 290 includes three level shifters and three switches, it may include any number of level shifters and switches.

[0109] Fig. 10A is a schematic diagram of a package module 300 according to one embodiment. Fig. 10B is a schematic cross-sectional view of the package module 300 taken along line 10B-10B in Fig. 10A.

[0110] Package module 300 includes an IC or die 301, a surface mount component 303, wire bonds 308, a package substrate 320, and an encapsulation structure 340. Package substrate 320 includes pads 306 formed from conductors disposed therein. Additionally, die 301 includes pads 304, and wire bonds 308 are used to electrically connect pads 304 of die 301 to pads 306 of package substrate 301.

[0111] As shown in Figures 10A and 10B, die 301 includes charge pump 122, level shifter 123 and switch 127, which may be as previously described.

[0112] Package substrate 320 may be configured to receive multiple components, such as die 301, which may include surface mount capacitors and / or inductors, and surface mount components 303.

[0113] As shown in FIG. 10B , package module 300 includes a plurality of contact pads 332. The plurality of contact pads 332 are positioned on the side of package module 300 opposite the side used to attach semiconductor die 301. Configuring package module 300 in this manner can assist in connecting package module 300 to a circuit board, such as a phone board for a wireless device. Example contact pads 332 can be configured to provide RF signals, bias signals, power low voltages, and / or power high voltages to die 301 and / or surface-mounted components 303. As shown in FIG. 10B , electrical connection between contact pads 332 and die 301 can be facilitated by connections 333 through package substrate 320. Connections 333 can represent electrical paths formed through package substrate 320, such as connections associated with vias and conductors in a multi-layer stack package substrate.

[0114] In some embodiments, package module 300 may also include one or more package structures, for example, to provide protection and / or facilitate handling of package module 300. Such package structures may include an overmold or encapsulation structure 340 formed over package substrate 320 and the components and die disposed thereon.

[0115] It will be understood that although package module 300 is depicted in the context of wire bond based electrical connections, one or more features of the present disclosure may be implemented in other package configurations, such as, for example, a flip chip configuration.

[0116] 11 is a schematic diagram of an RF switch network 420 according to another embodiment. The RF switch network 420 includes a first series transistor switch 361, a second series transistor switch 365, a first input shunt transistor switch 381, a second input shunt transistor switch 385, a first output shunt transistor switch 401, and a second output shunt transistor switch 405.

[0117] RF switch network 420 of Figure 11 illustrates another embodiment of an RF switch network suitable for use in an RF switch system such as RF switch system 120 of Figure 4. However, other implementations are possible, including, but not limited to, RF switch networks including more or fewer series transistor switches and / or more or fewer shunt transistor switches.

[0118] In the illustrated embodiment, the first series transistor switch 361 is electrically connected between the first RF input terminal RF_IN1 and the RF output terminal RF_OUT, and the second series transistor switch 365 is electrically connected between the second RF input terminal RF_IN2 and the RF output terminal RF_OUT. Additionally, the first input shunt transistor switch 381 is electrically connected between the first RF input terminal RF_IN1 and ground, and the second input shunt transistor switch 385 is electrically connected between the second RF input terminal RF_IN2 and ground. Furthermore, the first output shunt transistor switch 401 is electrically connected between the RF output terminal RF_OUT and ground, and the second output shunt transistor switch 405 is electrically connected between the RF output terminal RF_OUT and ground.

[0119] 11 , a first switch control voltage VCTL1 controls the first series transistor switch 361, and a first inverted switch control voltage VCTL1B controls the first input shunt transistor switch 381 and the first output shunt transistor switch 401. Furthermore, a second switch control voltage VCTL2 controls the second series transistor switch 365, and a second inverted switch control voltage VCTL2B controls the second input shunt transistor switch 385 and the second output shunt transistor switch 405. In certain implementations, a first level shifter generates the first switch control voltage VCTL1 and the first inverted switch control voltage VCTL1B, while a second level shifter generates the second switch control voltage VCTL2 and the second inverted switch control voltage VCTL2B.

[0120] Each depicted transistor switch includes a number of transistors in series to achieve a desired power handling capability, which are biased using corresponding gate and channel resistors.

[0121] For example, first series transistor switch 361 includes NFETs 371a, 371b, ... 371n, gate resistors 372a, 372b, ... 372n, and channel resistors 373a, 373b, ... 373n. Additionally, second series transistor switch 365 includes NFETs 375a, 375b, ... 375n, gate resistors 376a, 376b, ... 376n, and channel resistors 377a, 377b, ... 377n. Furthermore, first input shunt transistor switch 381 includes NFETs 391a, 391b, gate resistors 392a, 392b, and channel resistors 393a, 393b. Additionally, the second input shunt transistor switch 385 includes NFETs 395a and 395b, gate resistors 396a and 396b, and channel resistors 397a and 397b. Furthermore, the first output shunt transistor switch 401 includes NFETs 411a and 411b, gate resistors 412a and 412b, and channel resistors 413a and 413b. Additionally, the second output shunt transistor switch 405 includes NFETs 415a and 415b, gate resistors 416a and 416b, and channel resistors 417a and 417b.

[0122] 12 is a schematic diagram of one embodiment of a mobile device 800. The mobile device 800 includes a baseband system 801, a transceiver 802, a front-end system 803, an antenna 804, a power management system 805, a memory 806, a user interface 807, and a battery 808.

[0123] The mobile device 800 can be used to communicate using a wide variety of communication technologies, including, but not limited to, 2G, 3G, 4G (LTE, LTE Advanced, and LTE Advanced Pro), 5GNR, WLAN (e.g., WiFi), WPAN (e.g., Bluetooth® and ZigBee®), WPAN (e.g., WiMax), and / or GPS technologies.

[0124] The transceiver 802 generates RF signals for transmission and processes incoming RF signals received from the antenna 804. It will be appreciated that various functions associated with transmitting and receiving RF signals may be accomplished by one or more components collectively represented in Figure 12 as the transceiver 802. In one example, separate components (e.g., separate circuits or dies) may be provided to handle certain types of RF signals.

[0125] The front-end system 803 aids in conditioning signals transmitted to and / or received from the antenna 804. In the illustrated embodiment, the front-end system 803 includes a number of level shifters 810, a number of power amplifiers (PAs) 801, a number of low noise amplifiers (LNAs) 812, a number of filters 813, a number of switches 814, and a signal splitting / combining circuit 815. However, other implementations are possible.

[0126] For example, the front-end system 803 may provide a number of functions, including, but not limited to, amplifying transmit signals, amplifying receive signals, filtering signals, switching between different bands, switching between different power modes, switching between transmit and receive modes, duplexing signals, multiplexing signals (e.g., diplexing or triplexing), or any combination thereof.

[0127] In certain implementations, the mobile device 800 supports carrier aggregation, providing flexibility for increasing peak data rates. Carrier aggregation can be used for both frequency division duplexing (FDD) and time division duplexing (TDD), and may be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers are aggregated within the same operating frequency band. Carrier aggregation may also be non-contiguous, including frequency-separated carriers within a common band or different bands.

[0128] The multiple antennas 804 may include antennas used for a variety of different types of communication. For example, the antennas 804 may include antennas for transmitting and / or receiving signals associated with a variety of different frequencies and communication standards.

[0129] In certain implementations, the antennas 804 support MIMO and / or switched diversity communications. For example, MIMO communications use multiple antennas to communicate multiple data streams over a single radio frequency channel. MIMO communications benefit from high signal-to-noise ratios, improved coding, and / or reduced signal interference due to spatial multiplexing in the wireless environment. Switched diversity refers to communications in which a particular antenna is selected to operate at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on various factors, such as an observed bit error rate and / or signal strength indicator.

[0130] The mobile device 800 may operate with beamforming in certain implementations. For example, the front-end system 803 may include amplifiers with controllable gain and phase shifters with controllable phase to provide beamforming and directionality for transmitting and / or receiving signals using the antenna 804. For example, in the context of signal transmission, the amplitude and phase of transmit signals provided to the antenna 804 may be controlled so that signals radiating from the antenna 804 combine using constructive and destructive interference to generate an aggregate transmit signal exhibiting a beam-like quality with strong signal strength propagating in a given direction. In the context of signal reception, the amplitude and phase may be controlled so that more signal energy is received when the signal arrives at the antenna 804 from a particular direction. In certain implementations, the antenna 804 may include one or more arrays of antenna elements to enhance beamforming.

[0131] The baseband system 801 is coupled to a user interface 807 that facilitates the processing of various user inputs and outputs (I / O), such as voice and data. The baseband system 801 provides a digital representation of a transmit signal to the transceiver 802, which processes it to generate an RF signal for transmission. The baseband system 801 also processes a digital representation of a receive signal that is provided by the transceiver 802. As shown in FIG. 12 , the baseband system 801 is coupled to a memory 806 to facilitate operation of the mobile device 800.

[0132] The memory 806 may be used for a wide variety of purposes, such as storing data and / or instructions to facilitate operation of the mobile device 800 and / or to provide storage of user information.

[0133] The power management system 805 provides a number of power management functions for the portable device 800. In certain implementations, the power management system 805 includes a PA supply control circuit that controls the supply voltages of the plurality of power amplifiers 811. For example, the power management system 805 may be configured to vary the supply voltages provided to one or more of the plurality of power amplifiers 811 to improve efficiency, such as power added efficiency (PAE).

[0134] 12, the power management system 805 receives battery voltage from a battery 808. The battery 808 may be any suitable battery for use in the portable device 800, including, for example, a lithium-ion battery.

[0135] The portable device 800 may include any combination of features of the present disclosure. For example, in certain embodiments, the power management system 805 includes a positive charge pump that generates a positive charge pump voltage, a negative charge pump that generates a negative charge pump voltage, and a voltage regulator that generates a regulated voltage. Additionally, the front-end system 803 includes an RF switch (of the plurality of switches 814) controlled by a level shifter (of the plurality of level shifters 810), which receives the positive charge pump voltage, the negative charge pump voltage, and the regulated voltage.

[0136] Conclusion

[0137] Although some of the above-described embodiments have been given as examples related to mobile devices, the principles and advantages of these embodiments can be used for any other system or device requiring RF switching.

[0138] Unless the context clearly requires otherwise, throughout the specification and claims, terms like "comprises," "comprises," and the like should be interpreted in an inclusive sense, i.e., "including, but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements being connected either directly or via one or more intermediate elements. Similarly, the term "connected," as generally used herein, also refers to two or more elements being connected either directly or via one or more intermediate elements. Additionally, when used in this application, the terms "herein," "above," "below," and words of similar import shall refer to this application as a whole, and not to any particular portions of this application. Where the context permits, terms in the above Detailed Description using singular or plural numbers may also include the plural or singular number, respectively. The terms "or" and "or" referring to a list of two or more items cover all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0139] Furthermore, unless specifically stated or understood otherwise within the context of use, conditional language used herein, such as "may," "could," "could," "might," "for example," "such as," and the like, among others, generally intends that certain embodiments include certain features, elements, and / or conditions, while other embodiments do not. That is, such conditional language is generally not intended to imply that features, elements, and / or conditions are present in any manner required in one or more embodiments, or that one or more embodiments necessarily include logic that determines, with or without authorial input or prompting, whether or not these features, elements, and / or conditions are included or should be performed in any particular embodiment.

[0140] The above description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments and examples of the invention have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the invention. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines or use systems having blocks with steps in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks may be shown to be performed in serial, these processes or blocks may instead be performed in parallel or may be performed at different times.

[0141] The teachings of the invention provided herein may be applied to other systems, not necessarily those described above. Elements and acts of the various embodiments described above may be combined to provide further embodiments.

[0142] While certain embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications of the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. 1. A mobile device, comprising: a power management system including a positive charge pump configured to generate a positive charge pump voltage, a negative charge pump configured to generate a negative charge pump voltage, and a voltage regulator configured to generate a regulated voltage; a front-end system including a radio frequency switch controlled by a first switch control signal and a level shifter operable to level shift the first switch enable signal to generate the first switch control signal at a first output; Including, The level shifter a first level shift n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output; a first level shifting p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output; a second cascode p-type transistor between the regulated voltage and the gate of the first level shift n-type transistor, the second cascode p-type transistor being controlled by the first switch enable signal; , including mobile devices.

2. the level shifter is further operable to level shift the second switch enable signal to generate a second switch control signal at a second output; 2. The handheld device of claim 1, wherein the second switch enable signal is complementary in polarity to the first switch enable signal.

3. The level shifter further comprises: a second level shifting n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage; a third cascode p-type transistor; and a third level shifting n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage; The mobile device of claim 2 , comprising:

4. The level shifter further comprises: a fourth level shift n-type transistor and a second cascode n-type transistor in series between the second output and the negative charge pump voltage; a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge pump voltage and the second output; The mobile device of claim 3 , comprising:

5. The mobile device of claim 1 , wherein the front-end system further comprises a power amplifier configured to provide a radio frequency signal to the radio frequency switch.

6. the power management system further includes a charge pump clock generator; The charge pump clock generator a multi-phase oscillator configured to generate a plurality of oscillator clock signals; a clock phase logic and combining circuit configured to process the plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillator frequency of the multi-phase oscillator; Including, 2. The portable device of claim 1, wherein the first clock signal is operable to control at least one of the positive charge pump or the negative charge pump.

7. the clock phase logic and combining circuitry is further configured to generate a second clock signal that is out of phase with the first clock signal; the first clock signal is operable to control the positive charge pump; 7. The portable device of claim 6, wherein the second clock signal is operable to control the negative charge pump.

8. 1. A radio frequency switching system comprising: a radio frequency switch configured to receive a radio frequency signal and controlled by a first switch control signal; a positive charge pump configured to generate a positive charge pump voltage; a negative charge pump configured to generate a negative charge pump voltage; a voltage regulator configured to generate a regulated voltage; a level shifter operable to level shift the first switch enable signal to generate the first switch control signal at a first output; Including, The level shifter a first level shift n-type transistor and a first cascode n-type transistor in series between the negative charge pump voltage and the first output; a first level shifting p-type transistor and a first cascode p-type transistor in series between the positive charge pump voltage and the first output; a second cascode p-type transistor between the regulated voltage and the gate of the first level shift n-type transistor, the second cascode p-type transistor being controlled by the first switch enable signal; 1. A radio frequency switching system comprising:

9. the level shifter is further operable to level shift the second switch enable signal to generate a second switch control signal at a second output; 9. The radio frequency switch system of claim 8, wherein said second switch enable signal is complementary in polarity to said first switch enable signal.

10. The level shifter further comprises: a second level shifting n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage; a third cascode p-type transistor; and a third level shifting n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage; 10. The radio frequency switch system of claim 9, comprising:

11. The level shifter further comprises: a fourth level shift n-type transistor and a second cascode n-type transistor in series between the negative charge pump voltage and the second output; a second level-shifting p-type transistor and a fourth cascode p-type transistor in series between the positive charge pump voltage and the second output; 11. The radio frequency switch system of claim 10, comprising:

12. a first enable level shift circuit configured to level shift the first switch enable signal to generate a first level-shifted switch enable signal that controls a gate of the second level-shifting p-type transistor; a second enable level shift circuit configured to level shift the second switch enable signal to generate a second level-shifted switch enable signal that controls a gate of the first level-shifting p-type transistor; The radio frequency switch system of claim 11 further comprising:

13. 12. The radio frequency switch system of claim 11, wherein a gate of the first cascode p-type transistor and a gate of the fourth cascode p-type transistor are connected to a ground voltage.

14. a gate of the second level-shift n-type transistor and a gate of the fourth level-shift n-type transistor are connected to a drain of the third level-shift n-type transistor; 12. The radio frequency switch system of claim 11, wherein a gate of the first level shifting n-type transistor and a gate of the third level shifting n-type transistor are connected to a drain of the second level shifting n-type transistor.

15. The radio frequency switch a series transistor switch electrically connected between an input terminal and an output terminal and controlled by the first switch control signal; a shunt transistor switch electrically connected between the input terminal and a ground voltage and controlled by a second switch control signal; 10. The radio frequency switch system of claim 9, comprising:

16. further comprising a charge pump clock generator; The charge pump clock generator a multi-phase oscillator configured to generate a plurality of oscillator clock signals; a clock phase logic and combining circuit configured to process the plurality of oscillator clock signals to generate a first clock signal having a frequency higher than an oscillator frequency of the multi-phase oscillator; Including, 10. The radio frequency switch system of claim 9, wherein the first clock signal is operable to control at least one of the positive charge pump or the negative charge pump.

17. the clock phase logic and combining circuitry is further configured to generate a second clock signal that is out of phase with the first clock signal; the first clock signal is operable to control the positive charge pump; 17. The radio frequency switch system of claim 16, wherein the second clock signal is operable to control the negative charge pump.

18. 9. The radio frequency switch system of claim 8, wherein the voltage regulator is a low dropout regulator.

19. 1. A level shifter for a radio frequency switch, comprising: a first level shift n-type transistor; a first cascode n-type transistor in series with the first level shift n-type transistor between a first output providing a first switch control signal and the negative charge pump voltage; a first level shift p-type transistor; a first cascode p-type transistor in series with the first level shifting p-type transistor between a positive charge pump voltage and the first output; a second cascode p-type transistor between the regulated voltage and the gate of the first level shift n-type transistor, the second cascode p-type transistor being controlled by the first switch enable signal; 2. A level shifter comprising:

20. The level shifter further comprises: a second level shifting n-type transistor in series with the second cascode p-type transistor between the regulated voltage and the negative charge pump voltage; a third cascode p-type transistor; and a third level shifting n-type transistor in series with the third cascode p-type transistor between the regulated voltage and the negative charge pump voltage; 20. The level shifter of claim 19, comprising:

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