Imaging devices and electronic devices

Abstract

An imaging device according to one embodiment of the present disclosure includes: a first substrate provided with a first surface and a second surface, and, on a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate provided with a third surface and a fourth surface, and, on a second semiconductor substrate, a first transistor constituting a pixel circuit that outputs a pixel signal based on a charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; and a third substrate provided with a fifth surface and a sixth surface, and, on a third semiconductor substrate, a second transistor constituting a pixel circuit, the third substrate being stacked on the second substrate with the fourth surface and the fifth surface facing each other.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device having a three-dimensional structure and an electronic device equipped with the same. [Background technology]

[0002] The miniaturization of the area per pixel in two-dimensional imaging devices has been achieved by introducing microprocessing and improving packaging density. In recent years, three-dimensional imaging devices have been developed to further reduce the size of imaging devices and increase pixel density. In three-dimensional imaging devices, for example, a first substrate on which a photoelectric conversion unit PD is formed is bonded to a second substrate on which a charge storage capacitor unit and multiple MOS transistors are formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-219339 Summary of the Invention

[0004] Meanwhile, there is a demand for further reduction in pixel size in imaging devices.

[0005] It is desirable to provide an imaging device that allows pixel size to be reduced, and an electronic device that includes the imaging device.

[0006] In one embodiment of the present disclosure 1stThe imaging device includes a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on the first semiconductor substrate; a second substrate having a third surface and a fourth surface, and having a first transistor that constitutes a pixel circuit that outputs a pixel signal based on electric charges output from the sensor pixel on the second semiconductor substrate, and stacked on the first substrate with the first surface and the third surface facing each other; and a third substrate having a fifth surface and a sixth surface, and having a second transistor that constitutes a pixel circuit on the third semiconductor substrate, and stacked on the second substrate with the fourth surface and the fifth surface facing each other. The sensor pixel has a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds the charge output from the light receiving element via the transfer transistor. The pixel circuit has a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor. The amplification transistor is formed on the second substrate, and the reset transistor and the selection transistor are formed on the third substrate. . A second imaging device according to an embodiment of the present disclosure includes: a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on the first semiconductor substrate; a second substrate having a third surface and a fourth surface, and having a first transistor that configures a pixel circuit on the second semiconductor substrate to output a pixel signal based on charges output from the sensor pixels, and stacked on the first substrate with the first surface facing the third surface; and a third substrate having a fifth surface and a sixth surface, and having a second transistor that configures the pixel circuit on the third semiconductor substrate, and stacked on the second substrate with the fourth surface facing the fifth surface. The sensor pixels each include a light receiving element, a transfer transistor electrically connected to the light receiving element, and a transfer transistor that transfers the charge output from the light receiving element via the transfer transistor. The pixel circuit has a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor.The pixel circuit has a seventh surface and an eighth surface, and a fourth semiconductor substrate has a third transistor that constitutes the pixel circuit, and further has a fourth substrate that is stacked on the third substrate with the sixth surface and the seventh surface facing each other.The second substrate has an amplification transistor formed thereon, and the third substrate has a reset transistor formed thereon and a selection transistor formed thereon.A third imaging device according to an embodiment of the present disclosure includes: a first substrate having a first surface and a second surface, the first semiconductor substrate having sensor pixels that perform photoelectric conversion; a second substrate having a third surface and a fourth surface, the second semiconductor substrate having a first transistor that constitutes a pixel circuit that outputs a pixel signal based on charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface facing the third surface; and a third substrate having a fifth surface and a sixth surface, the third semiconductor substrate having a second transistor that constitutes the pixel circuit, the third substrate being stacked on the second substrate with the fourth surface facing the fifth surface. The sensor pixels and the first transistor are electrically connected by bonding pad electrodes formed on the first surface and the third surface, respectively. The first transistor and the second transistor are electrically connected by bonding pad electrodes formed on the fourth surface and the fifth surface, respectively. One of the gate electrode, source region, and drain region of the first transistor is directly connected to the pad electrode formed on the fourth surface.

[0007] In one embodiment of the present disclosure 1st The electronic device is the one of the embodiments of the present disclosure. 1st It is equipped with an imaging device. A second electronic device according to an embodiment of the present disclosure includes the second imaging device according to the embodiment of the present disclosure. A third electronic device according to an embodiment of the present disclosure includes the third imaging device according to the embodiment of the present disclosure.

[0008] In one embodiment of the present disclosure 1st to 3rd Imaging device and one embodiment 1st to 3rd In electronic devices, the first and second transistors that make up the pixel circuit are formed on different substrates (second and third substrates), and the second and third substrates are stacked in this order on the first substrate that has the sensor pixels that perform photoelectric conversion, thereby reducing the area required to form the pixel circuit in a plan view. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view illustrating a configuration of an imaging device according to a first embodiment of the present disclosure. [Figure 2] 2 is a diagram illustrating an example of an equivalent circuit of the imaging device illustrated in FIG. [Figure 3] 2 is a schematic plan view showing an example of the layout of the first substrate shown in FIG. 1. FIG. [Figure 4] 2 is a schematic plan view showing an example of the layout of a lower wiring layer of the second substrate shown in FIG. 1. FIG. [Figure 5] 2 is a schematic plan view showing an example of the layout of an upper wiring layer of the second substrate shown in FIG. 1. FIG. [Figure 6] 2 is a schematic plan view showing an example of the layout of a lower wiring layer of the third substrate shown in FIG. 1. FIG. [Figure 7] 2 is a schematic plan view showing an example of the layout of an upper wiring layer of the third substrate shown in FIG. 1. FIG. [Figure 8] FIG. 1 is a perspective view illustrating a transistor having a three-dimensional structure. [Figure 9A] 2A to 2C are cross-sectional views illustrating an example of a manufacturing process for the imaging device shown in FIG. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a step subsequent to FIG. 9C. [Figure 9E] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9D. [Figure 9F] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9E. [Figure 9G] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9F. [Figure 10A] 1. FIG. 4 is a cross-sectional view illustrating another example of the manufacturing process of the imaging device shown in FIG. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing a step subsequent to FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D is a schematic cross-sectional view showing a step subsequent to FIG. 10C. [Figure 10E] FIG. 10B is a schematic cross-sectional view showing the step subsequent to FIG. 10D. [Figure 10F] FIG. 10B is a schematic cross-sectional view showing a step subsequent to FIG. 10E. [Figure 11] FIG. 10 is a cross-sectional view illustrating a configuration of an imaging device according to a second embodiment of the present disclosure. [Figure 12] 12 is a diagram illustrating an example of an equivalent circuit of the imaging device illustrated in FIG. [Figure 13] FIG. 10 is a cross-sectional view illustrating a configuration of an imaging device according to a third embodiment of the present disclosure. [Figure 14]FIG. 14 is a diagram illustrating an example of an equivalent circuit of the imaging device illustrated in FIG. [Figure 15] FIG. 10 is a cross-sectional view illustrating a configuration of an imaging device according to a fourth embodiment of the present disclosure. [Figure 16] FIG. 10 is a cross-sectional view illustrating a configuration of an imaging device according to a fifth embodiment of the present disclosure. [Figure 17] FIG. 13 is a diagram illustrating an example of an equivalent circuit of an imaging device according to a sixth embodiment of the present disclosure. [Figure 18] 18 is a cross-sectional view schematically illustrating an example of a cross-sectional configuration of the imaging device illustrated in FIG. 17. [Figure 19] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 1. [Figure 20] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 2. [Figure 21] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 3. [Figure 22] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 3. [Figure 23] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 4. [Figure 24] FIG. 17 is a cross-sectional view schematically illustrating another example of the cross-sectional configuration of the imaging device shown in FIG. 16, as Modification 5. [Figure 25] FIG. 13 is an exploded perspective view illustrating a schematic configuration of an imaging device according to a seventh embodiment of the present disclosure. [Figure 26] 26 is a cross-sectional view illustrating an example of the configuration of the imaging device illustrated in FIG. 25. FIG. [Figure 27] FIG. 26 is a diagram illustrating another example of the circuit configuration of the imaging device shown in FIG. [Figure 28] 28 is an exploded perspective view showing a schematic configuration of an imaging device having the circuit configuration shown in FIG. 27. FIG. [Figure 29] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including the imaging devices according to the first to seventh embodiments and the first to fifth modifications. [Figure 30]30 is a diagram illustrating an example of an imaging procedure in the imaging system of FIG. 29. [Figure 31] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 32] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 33] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 34] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. [Figure 35] FIG. 10 is a cross-sectional schematic diagram illustrating an example of a cross-sectional configuration of an imaging device according to a modified example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows. 1. First embodiment (example of an imaging device in which a plurality of pixel transistors constituting a pixel circuit are formed separately on a second substrate and a third substrate) 1-1. General configuration of the imaging device 1-2. Specific configuration of the imaging device 1-3. Manufacturing method of imaging device 1-4. Actions and Effects 2. Second embodiment (example of an imaging device in which an amplification transistor is provided on a second substrate and a reset transistor and a selection transistor are provided on a third substrate) 3. Third embodiment (example of an imaging device in which an amplification transistor, a reset transistor, and a selection transistor are provided separately on a second substrate, a third substrate, and a fourth substrate, respectively) 4. Fourth embodiment (example of imaging device in which gate electrodes of pixel transistors are formed from metal) 5. Fifth embodiment (example in which the gate electrode of the amplification transistor and the source / drain region of the reset transistor are directly connected to the pad electrodes) 6. Sixth embodiment (an example of an imaging device further including a capacitance element and a switching transistor for switching between connected and disconnected states of the capacitance element) 7. Variations 7-1. Modification 1 (Example in which a capacitive element having an MIM structure is provided) 7-2. Modification 2 (Example in which a capacitive element having an MIM structure is provided) 7-3. Modification 3 (Example in which a capacitive element is provided on a third substrate) 7-4. Modification 4 (Example in which a capacitance element and a switching transistor are provided on the third substrate) 7-5. Modification 5 (Example in which a capacitive element is provided on the bonding surface of the third substrate to the second substrate) 8. Seventh embodiment (example of an imaging device in which a fifth substrate on which a logic circuit is provided is further stacked) 9. Application Examples 10. Application Examples

[0011] <1. First embodiment> (1-1. General configuration of imaging device) FIG. 1 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1) according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of an equivalent circuit of the imaging device 1 illustrated in FIG. 1. FIG. 3 is a diagram illustrating an example of a layout of the first substrate 100 of the imaging device 1 illustrated in FIG. 1. FIGS. 4 and 5 are diagrams illustrating an example of a wiring layout on the second substrate 200 side of the imaging device 1 illustrated in FIG. 1. FIGS. 6 and 7 are diagrams illustrating an example of a wiring layout on the second substrate 200 side of the imaging device 1 illustrated in FIG. 1. Note that FIG. 1 illustrates a cross section of the imaging device 1 corresponding to line II illustrated in FIGS. 4 to 7. The imaging device 1 includes, for example, three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The imaging device 1 is an imaging device having a three-dimensional structure in which the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order.

[0012] The first substrate 100 has a semiconductor substrate 10 and a wiring layer 40. The semiconductor substrate 10 has a first surface (front surface) 10A and a second surface (back surface) 10B that face each other, and the wiring layer 40 is provided on the first surface 10A of the semiconductor substrate 10. The second substrate 200 has a semiconductor substrate 20 and a wiring layer 50. The semiconductor substrate 20 has a first surface (front surface) 20A and a second surface (back surface) 20B that face each other, and the wiring layer 50 is provided with a lower wiring layer 50A on the first surface 20A side of the semiconductor substrate 20 and an upper wiring layer 50B on the second surface 20B side. The third substrate 300 has a semiconductor substrate 30 and a wiring layer 60. The semiconductor substrate 30 has opposing first and second surfaces (front and back surfaces) 30A and 30B, and as the wiring layer 60, a lower wiring layer 60A is provided on the first surface 30A side of the semiconductor substrate 10, and an upper wiring layer 60B is provided on the second surface 30B side.

[0013] In the imaging device 1, the first substrate 100 and the second substrate 200 are stacked with the wiring layer 40 provided on the first surface 10A of the semiconductor substrate 10 and the lower wiring layer 50A provided on the first surface 20A of the semiconductor substrate 20 interposed therebetween. That is, the first substrate 100 and the second substrate 200 are stacked face-to-face. The second substrate 200 and the third substrate 300 are stacked with the upper wiring layer 50B provided on the second surface 20B of the semiconductor substrate 20 and the lower wiring layer 60A provided on the first surface 30A of the semiconductor substrate 30 interposed therebetween. That is, the second substrate 200 and the third substrate 300 are stacked face-to-back.

[0014] The first substrate 100 has a plurality of sensor pixels 11 that perform photoelectric conversion on a semiconductor substrate 10. Specifically, the first substrate 100 is provided with a photodiode PD (light receiving element 12), a floating diffusion FD, a well tap 13, and a transfer transistor TR. The second substrate 200 and the third substrate are each provided with a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel 11. The pixel circuit has, for example, three transistors, specifically, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL.

[0015] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0016] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the power supply line VDD.

[0017] The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit.

[0018] The amplification transistor AMP generates a pixel signal whose voltage corresponds to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source-follower amplifier and outputs a pixel signal whose voltage corresponds to the level of the charge generated in the photodiode PD (light-receiving element 12). When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to that potential via the vertical signal line VSL to, for example, a logic circuit (described later).

[0019] In the imaging device 1 of this embodiment, of the amplification transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit, for example, the amplification transistor AMP and the reset transistor RST are provided on the semiconductor substrate 20 of the second substrate 200, and the selection transistor SEL is provided on the semiconductor substrate 30 of the third substrate 300.

[0020] The semiconductor substrate 10 corresponds to a specific example of a "first semiconductor substrate" in the present disclosure, the first surface 10A corresponds to a specific example of a "first surface" in the present disclosure, and the second surface 10B corresponds to a specific example of a "second surface" in the present disclosure. The semiconductor substrate 20 corresponds to a specific example of a "second semiconductor substrate" in the present disclosure, the first surface 20A corresponds to a specific example of a "third surface" in the present disclosure, and the second surface 20B corresponds to a specific example of a "fourth surface" in the present disclosure. The semiconductor substrate 30 corresponds to a specific example of a "third semiconductor substrate" in the present disclosure, the first surface 30A corresponds to a specific example of a "fifth surface" in the present disclosure, and the second surface 30B corresponds to a specific example of a "sixth surface" in the present disclosure. The amplifier transistor AMP and the reset transistor correspond to a specific example of a "first transistor" in the present disclosure, and the select transistor SEL corresponds to a specific example of a "second transistor" in the present disclosure.

[0021] (1-2. Specific Configuration of the Imaging Device) In the imaging device 1, for example, a plurality of sensor pixels 11 are repeatedly arranged in an array on the semiconductor substrate 10 constituting the first substrate 100. For example, a pixel sharing unit including a plurality of sensor pixels 11 serves as a repeating unit, and these are repeatedly arranged in an array in the row and column directions. In the present embodiment, the pixel sharing unit is composed of four sensor pixels 11, and the four sensor pixels 11 share one floating diffusion FD. One pixel circuit is formed for each of the four sensor pixels 11. The sensor pixels 11 have common components. In FIG. 3, in order to distinguish the components of each sensor pixel 11 from one another, an identification number (1, 2, 3, 4) is added to the end of the photodiode PD constituting the light receiving element 12 provided in each sensor pixel 11. In the following, when it is necessary to distinguish the components of each sensor pixel 11 from one another, an identification number (1, 2, 3, 4) corresponding to the identification number at the end of the code of the component of each sensor pixel 11 will be added, but when it is not necessary to distinguish the components of each sensor pixel 11 from one another, the identification number at the end of the code of the component of each sensor pixel 11 will be omitted.

[0022] In each sensor pixel 11, for example, the cathode of the photodiode PD (light receiving element 12) is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD (light receiving element 12) is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD.

[0023] The floating diffusion FD shared by the four sensor pixels 11 is electrically connected to the input terminal of a common pixel circuit. Specifically, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the reset transistor RST. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to, for example, a drive signal line (not shown). The drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line VSL, and the gate of the selection transistor SEL is connected to, for example, a drive signal line (not shown).

[0024] The semiconductor substrate 10 is made of, for example, a silicon substrate. The semiconductor substrate 10 has, for example, a photodiode PD (light receiving element 12), a floating diffusion FD, a well tap 13, and a transfer transistor TR on the first surface 10A side.

[0025] The semiconductor substrate 20 is made of, for example, a silicon substrate. Although not shown, the semiconductor substrate 20 is divided into multiple parts by element isolation regions having, for example, an STI (Shallow Trench Isolation) structure, a DTI (Deep Trench Isolation) structure, or an FTI (Full Trench Isolation) structure. As described above, an amplifier transistor AMP and a reset transistor RST are provided in each of the semiconductor substrates 20 divided by STI or the like. Each of the amplifier transistor AMP and the reset transistor RST has, for example, a planar structure and includes a gate electrode 52G, a source region 21S, and a drain region 21D.

[0026] The gate electrode 52G is provided on the first surface 20A side of the semiconductor substrate 20 via a gate insulating film 51 made of, for example, silicon oxide (SiO2). The gate electrode 52G is formed using, for example, polysilicon (Poly-Si). The source region 21S and the drain region 21D are provided on either side of a channel region facing the gate electrode 52G. The source region 21S and the drain region 21D each have a stacked structure of a diffusion layer 211 provided in the semiconductor substrate 20 and in which, for example, an impurity is diffused, and a low-resistance layer 212 made of silicide formed using a salicide (self-aligned silicide) process, such as cobalt silicide (CoSi2) or nickel silicide (NiSi).

[0027] The semiconductor substrate 30 is made of, for example, a silicon substrate and is divided into multiple parts by element isolation regions having, for example, an STI structure, a DTI structure, or an FTI structure, similar to the semiconductor substrate 20. As described above, the select transistor SEL is provided on the semiconductor substrate 30. Like the amplifier transistor AMP and the reset transistor RST, the select transistor SEL has, for example, a planar structure and includes a gate electrode 62G, a source region 31S, and a drain region 31D.

[0028] The gate electrode 62G is provided on the first surface 30A side of the semiconductor substrate 30 via a gate insulating film 61 made of, for example, silicon oxide (SiO2). The gate electrode 62G is formed of, for example, polysilicon (Poly-Si). The source region 31S and the drain region 31D are provided on either side of a channel region facing the gate electrode 62G. The source region 31S and the drain region 31D each have a stacked structure of a diffusion layer 311 provided in the semiconductor substrate 20 and in which, for example, an impurity is diffused, and a low-resistance layer 312 made of silicide formed using a salicide process using, for example, cobalt silicide (CoSi2) or nickel silicide (NiSi).

[0029] The amplifier transistor AMP, reset transistor RST, and select transistor SEL are not limited to a planar structure and may have a three-dimensional structure. Fig. 8 shows a Fin-FET as an example of a transistor having a three-dimensional transistor structure. The Fin-FET has, for example, a fin 1110X having a source region 1110S and a drain region 1110D made of silicon (Si), and a gate electrode 1120.

[0030] The fins 1110X are flat and are provided in multiple upright positions on, for example, a silicon substrate 1110. The multiple fins 1110X extend, for example, in the X direction and are aligned in the Y direction. An insulating film 1130 made of, for example, SiO2 is provided on the silicon substrate 1110, and the fins 110X extend upright so as to penetrate this insulating film 1130. In other words, a portion of the fin 110X is buried in the insulating film 1130. The side and top surfaces of the fin 1110X exposed from the insulating film 1130 are covered with a gate insulating film 1140 made of, for example, HfSiO, HfSiON, TaO, or TaON. The gate electrode 1120 extends across the fin 1110X in the Z direction, which intersects with the extension direction (X direction) of the fin 1110X. A channel region 1110C is formed in the fin 1110X at the intersection with the gate electrode 1120, and a source region 1110A and a drain region 1110D are formed on either side of the channel region 1110C.

[0031] The Fin-FET can increase the channel width (W) and channel length (L) of the transistor depending on the height of the fin 1110X. Therefore, by using transistors having a three-dimensional structure such as the Fin-FET for the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL, it is possible to increase the channel width (W) and channel length (L) with the same layout area compared to the case of a planar structure.

[0032] Alternatively, the amplifier transistor AMP, the reset transistor RST, and the selection transistor SEL may have a full-depletion transistor structure, which allows the formation of pixel transistors with good voltage linearity.

[0033] In the wiring layer 40, for example, wiring 41 connected to the floating diffusion FD and wiring 42 including gates of the transfer transistors TR (for example, TRG1, TRG2, TRG3, TRG4) are formed in an interlayer insulating layer 43. The wiring 41 and the wiring 42 are provided in this order from the first surface 10A side of the semiconductor substrate 10 in the interlayer insulating layer 43. One or more pad electrodes 44 used for bonding with a second electrode, for example, are exposed on the surface of the interlayer insulating layer 43. The wiring 41 and the wiring 42, and the wiring 42 and one pad electrode 44 (pad electrode 441) are electrically connected to each other, for example, via vias.

[0034] The lower wiring layer 50A is provided on the first surface 20A side of the semiconductor substrate 20, and has wiring 52 including, for example, gate electrodes 52G of the amplifier transistor AMP and the reset transistor RST in an interlayer insulating layer 53. One or more pad electrodes 54 used for bonding to the first substrate 100 are exposed on the surface of the interlayer insulating layer 53 facing the first substrate 100. In the lower wiring layer 50A, the gate electrode 52G of the amplifier transistor AMP and the source region 21S of the reset transistor RST are each connected to one pad electrode 54 (pad electrode 541) through a via. That is, the gate electrode 52G of the amplifier transistor AMP and the source region 21S of the reset transistor RST are electrically connected through the pad electrode 541 and the via.

[0035] The upper wiring layer 50B is provided on the second surface 20B side of the semiconductor substrate 20. The upper wiring layer 50B has, for example, an interlayer insulating layer 53 continuing from the lower wiring layer 50A, and one or more pad electrodes 55 exposed on its surface facing the third substrate 300 and used for bonding to the third substrate 300. In the upper wiring layer 50B, the source region 21S of the amplifier transistor AMP and one pad electrode 55 (pad electrode 551) are electrically connected through vias. Furthermore, one pad electrode 55 is used as, for example, a power supply line VDD, and the drain region 21D of the amplifier transistor AMP and the drain region 21D of the reset transistor RST are electrically connected to each other through vias.

[0036] The lower wiring layer 60A is provided on the first surface 30A side of the semiconductor substrate 30, and has, for example, wiring 62 including a gate electrode 62G of the select transistor SEL in an interlayer insulating layer 63. One or more pad electrodes 64 used for bonding to the second substrate 200 are exposed on the surface of the interlayer insulating layer 63 facing the second substrate 200. In the lower wiring layer 60A, the source region 31S of the select transistor SEL is connected to one pad electrode 64 (pad electrode 641) through a via.

[0037] The upper wiring layer 60B is provided on the second surface 30B side of the semiconductor substrate 30. The upper wiring layer 60B has, for example, an interlayer insulating layer 63 continuing from the lower wiring layer 60A, and one or more pad electrodes 65 exposed on the surface opposite to the surface facing the third substrate 300. One pad electrode 65 is used, for example, as a vertical signal line VSL, and is electrically connected to the drain region 31D of the select transistor SEL through a via.

[0038] The wiring 41 and pad electrodes 44, 54, 55, 64, and 65 provided in each wiring layer 40, 50A, 50B, 60A, and 60B can each be formed using a metal material primarily composed of copper (Cu). The pad electrodes 44, 54, 55, 64, and 65 are formed, for example, as copper electrodes, with a barrier metal such as titanium nitride (TiN) formed around them. The pad electrodes 44, 54, 55, 64, and 65 may contain other metals as long as the performance of the copper electrodes is not impaired. Vias connecting the wirings can be formed, for example, using tungsten (W) or copper (Cu).

[0039] In this embodiment, the first substrate 100 and the second substrate 200, and the second substrate 200 and the third substrate 300 are connected by bonding pad electrodes to each other. Specifically, the first substrate 100 and the second substrate 200 are bonded together such that the first surface 10A of the semiconductor substrate 10 faces the first surface 20A of the semiconductor substrate 20, and one or more pad electrodes 44 and one or more pad electrodes 54 exposed on the surfaces of the wiring layer 40 and the lower wiring layer 50A provided on the first surfaces 10A and 20A, respectively, are bonded to each other. The second substrate 200 and the third substrate 300 are bonded together by bonding one or more pad electrodes 45 and one or more pad electrodes 64 exposed on the respective surfaces of the upper wiring layer 50B and the lower wiring layer 60A provided on the second surface 20B and the first surface 30A, respectively, so that the second surface 20B of the semiconductor substrate 20 faces the first surface 30A of the semiconductor substrate 30.

[0040] (1-3. Manufacturing method of imaging device) The imaging device 1 of this embodiment can be manufactured, for example, as follows.

[0041] First, as shown in FIG. 9A, the wiring layer 40 of the first substrate 100, the lower wiring layer 50A and the lower wiring layer 61A are formed on separate substrates (semiconductor substrates 10, 20, 30), and a high-temperature activation process is performed.

[0042] 9B, the pad electrode 44 exposed on the surface of the wiring layer 40 is bonded to the pad electrode 54 exposed on the surface of the lower wiring layer 50A using a face-down method. Next, as shown in FIG. 9C, the semiconductor substrate 20 is thinned from the second surface 20B side by, for example, chemical mechanical polishing (CMP).

[0043] 9D, an upper wiring layer 50B is formed on the second surface 20B of the semiconductor substrate 20. This forms the second substrate 200. Next, as shown in FIG. 9E, the pad electrode 55 exposed on the surface of the upper wiring layer 50B is bonded to the pad electrode 64 exposed on the surface of the lower wiring layer 60A using a face-down method.

[0044] Next, as shown in Fig. 9F, the semiconductor substrate 30 is thinned from the second surface 30B side by, for example, CMP. Thereafter, as shown in Fig. 9G, an upper wiring layer 60B is formed on the second surface 30B of the semiconductor substrate 30. This forms the third substrate 300. With the above steps, the imaging device 1 shown in Fig. 1 is completed.

[0045] In the above method, the semiconductor substrates 20 and 30 are thinned by, for example, CMP, but the silicon substrates can be reused by using, for example, the following method.

[0046] 10A, for example, hydrogen ions are implanted into the semiconductor substrates 20 and 30 to form peeling layers 20X and 30X in the substrates, respectively. Then, as shown in Fig. 10B, a wiring layer 40 is formed on the first surface 10A of the semiconductor substrate 10, a lower wiring layer 50A is formed on the first surface 20A of the semiconductor substrate 20, and a lower wiring layer 61A is formed on the first surface 30A of the semiconductor substrate 30, and a high-temperature activation process is performed.

[0047] Next, as shown in Fig. 10C, the pad electrode 44 exposed on the surface of the wiring layer 40 of the first substrate 100 is bonded face-down to the pad electrode 54 exposed on the surface of the lower wiring layer 50A. Subsequently, as shown in Fig. 10D, the semiconductor substrate 20 on the release layer 20X is peeled off. Next, as shown in Fig. 10E, the remaining semiconductor substrate 20 is thinned to a predetermined thickness by, for example, CMP.

[0048] 10F, an upper wiring layer 50B is formed using a method similar to the manufacturing method described above, and then the pad electrode 55 exposed on the surface of the upper wiring layer 50B of the second substrate 200 is bonded to the pad electrode 64 exposed on the surface of the lower wiring layer 60A. Next, similar to the semiconductor substrate 20, the semiconductor substrate 30 on the release layer 30X is peeled off, and the remaining semiconductor substrate 30 is thinned to a predetermined thickness by, for example, CMP. Next, an upper wiring layer 60B is formed on the second surface 30B of the semiconductor substrate 30. This completes the imaging device 1 shown in FIG. 1.

[0049] (1-4. Actions and Effects) In the imaging device 1 of the present embodiment, of the amplifier transistor AMP, reset transistor RST, and select transistor SEL that constitute the pixel circuit, the amplifier transistor AMP and reset transistor RST are formed on the second substrate 200, and the select transistor SEL is formed on the third substrate 300. This reduces the formation area of the pixel circuit in a plan view. This will be described below.

[0050] As mentioned above, miniaturization of the area per pixel in two-dimensional image sensors has been achieved by introducing microprocessing and improving packaging density. In recent years, three-dimensional image sensors have been developed to further reduce the size of image sensors and increase pixel density. In three-dimensional image sensors, as pixel size decreases due to an increase in the number of pixels, studies are underway to mount pixel transistors on a substrate separate from the sensor substrate.

[0051] However, as pixel miniaturization continues, it will be difficult to reduce the power supply voltage used by pixels, making it difficult to reduce the area of pixel transistors as per general scaling rules. Also, from the viewpoint of noise, a larger area is advantageous in terms of the ratio (W / L) of the channel width (W) to the channel length (L) of the pixel transistor, so a significant reduction in area is not desirable.

[0052] In contrast to this, in the present embodiment, the multiple transistors that make up the pixel circuit are formed separately on different substrates. Specifically, the amplifier transistor AMP and the reset transistor RST are formed on the second substrate 200, and the select transistor SEL is formed on the third substrate 300. This makes it possible to reduce the formation area of the pixel circuit in a plan view.

[0053] As described above, in the imaging device 1 of this embodiment, it is possible to reduce the pixel size without reducing the formation area of the amplification transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit.

[0054] Furthermore, when pixel transistors are formed on multiple substrates and stacked on each other as in the present embodiment, the transistors are generally activated for each layer. This transistor activation is performed in a high-temperature process, which may deteriorate the characteristics of the sensor pixels and transistors formed on the underlying substrates.

[0055] In contrast to this, in the present embodiment, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL are formed in advance on the respective semiconductor substrates 20, 30, and after an activation process is performed, the pad electrodes are bonded together to connect the first substrate 100, the second substrate 200, and the third substrate 300. This makes it possible to prevent deterioration of the characteristics of the sensor pixels 11 formed on the first substrate 100 and the transistors (for example, in the present embodiment, the transfer transistor TR, the amplification transistor AMP, etc.) formed on the substrates below.

[0056] Furthermore, in this embodiment, the first substrate 100 and the second substrate 200 are connected by bonding the pad electrodes 44 and 54, and the second substrate 200 and the third substrate 300 are connected by bonding the pad electrodes 55 and 64. This makes it easier to electrically connect the substrates than when connecting the substrates using connecting wiring such as through-hole wiring. Also, since a region for forming the connecting wiring is not required, the degree of freedom in layout is improved.

[0057] The following describes the second to seventh embodiments and modifications 1 to 5. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0058] <2. Second Embodiment> Fig. 11 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1A) according to a second embodiment of the present disclosure. Fig. 12 is a diagram illustrating an example of an equivalent circuit of the imaging device 1A illustrated in Fig. 11. The imaging device 1A of this embodiment differs from the first embodiment in that, of the amplifier transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit, for example, the amplifier transistor AMP is provided on the semiconductor substrate 20 of the second substrate 200, and the reset transistor RST and selection transistor SEL are provided on the semiconductor substrate 30 of the third substrate 300.

[0059] In general, from the viewpoint of parasitic capacitance, it is preferable that the amplifying transistor AMP be closer to the floating diffusion FD. Also, from the viewpoint of noise, it is preferable that the amplifying transistor AMP have a larger ratio (W / L) of channel width (W) to channel length (L) than the reset transistor RST and the select transistor SEL.

[0060] In contrast to this, in the present embodiment, only the amplification transistor AMP is provided on the semiconductor substrate 20 of the second substrate 200, and the reset transistor RST and the selection transistor SEL are provided on the semiconductor substrate 30 of the third substrate 300. Therefore, in addition to the effect of the first embodiment, there is an effect that it is possible to secure a sufficient formation area for the amplification transistor AMP.

[0061] <3. Third Embodiment> Fig. 13 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1B) according to a third embodiment of the present disclosure. Fig. 14 is a diagram illustrating an example of an equivalent circuit of imaging device 1B shown in Fig. 13. Imaging device 1B of this embodiment differs from the first and second embodiments in that the amplification transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit are provided separately on second substrate 200, third substrate 300, and fourth substrate 400, respectively.

[0062] As described above, in this embodiment, the amplifier transistor AMP is provided on the semiconductor substrate 20 of the second substrate 200, the reset transistor RST is provided on the semiconductor substrate 30 of the third substrate 300, and the select transistor SEL is provided on the semiconductor substrate 70 of the fourth substrate 400. Therefore, in addition to the effects of the first embodiment, there is an effect that it is possible to secure sufficient formation areas for the amplifier transistor AMP, the reset transistor RST, and the select transistor. Also, it is possible to further reduce the pixel size.

[0063] <4. Fourth embodiment> 15 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1C) according to a fourth embodiment of the present disclosure. The imaging device 1C of this embodiment differs from the first to third embodiments in that the gate wirings TRG1, TRG2, TRG3, and TRG4 of the transfer transistor TR and the gate electrodes 52G and 62G of the amplification transistor AMP, reset transistor RST, and selection transistor SEL are made of a metal material instead of polysilicon (Poly-Si).

[0064] Examples of metal materials constituting the gate wirings TRG1, TRG2, TRG3, and TRG4 of the transfer transistor TR and the gate electrodes 52G and 62G of the amplifier transistor AMP, reset transistor RST, and select transistor SEL include metals with a high work function (WF), such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).Other materials that can be used include tungsten (W) and aluminum (Al).

[0065] When the gate electrodes 52G, 62G are formed using a metal material as described above, it is preferable that the gate insulating films 51, 61 are each made of a high-dielectric material (high-K material) such as hafnium oxide (HfO2).

[0066] As described above, in this embodiment, the gate wirings TRG1, TRG2, TRG3, and TRG4 of the transfer transistor TR and the gate electrodes 52G and 62G of the amplification transistor AMP, reset transistor RST, and selection transistor SEL are formed using a metal material, which has the effect of reducing the influence of IR drop on each of the transistors TR, AMP, RST, and SEL in addition to the effect of the first embodiment.

[0067] Furthermore, in this embodiment, the gate wirings TRG1, TRG2, TRG3, and TRG4 of the transfer transistors TR are formed using a metal material, so that the gate wirings TRG1, TRG2, TRG3, and TRG4 can be routed as they are, as shown in FIG. 15. This makes it possible to reduce the total number of wirings in the wiring layer 40 of the first substrate 100. This makes it possible to reduce the parasitic capacitance of the amplification transistor AMP. Furthermore, it makes it possible to reduce the number of steps in the manufacturing process.

[0068] <5. Fifth Embodiment> 16 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1D) according to a fifth embodiment of the present disclosure. The imaging device 1D of this embodiment differs from the first to fourth embodiments in that the source region 21S of the amplifier transistor AMP and the pad electrode 55 (pad electrode 551) in the upper wiring layer 50B of the second substrate 200 are electrically connected directly to each other, and the drain regions 21D of the amplifier transistor AMP and the reset transistor RST are electrically connected directly to the power supply line VDD without using vias.

[0069] In this manner, in the present embodiment, the source region 21S of the amplifier transistor AMP is directly connected to the pad electrode 551, and the drain regions 21D of the amplifier transistor AMP and the reset transistor RST are directly connected to the power supply line VDD. Therefore, in addition to the effect of the first embodiment, there is an effect that it is possible to reduce the number of steps in the manufacturing process.

[0070] 6. Sixth Embodiment Fig. 17 illustrates an example of an equivalent circuit of an imaging device (imaging device 1E) according to a sixth embodiment of the present disclosure. Fig. 18 schematically illustrates an example of a cross-sectional configuration of the imaging device 1E illustrated in Fig. 17. The imaging device 1E of this embodiment differs from the first to fifth embodiments in that a capacitive element C and a switching transistor TRX are provided between the floating diffusion FD and the amplification transistor AMP.

[0071] In this embodiment, the capacitive element C and the switching transistor TRX are provided on the second substrate 200 together with the amplification transistor AMP and the reset transistor RST, respectively.

[0072] The capacitance element C has a configuration in which, for example, a diffusion layer 211 formed by diffusing impurities into the semiconductor substrate 20, an insulating film 511 having a configuration similar to that of the gate insulating film 51 of the amplifier transistor AMP, etc., and a conductive film 521 made of, for example, polysilicon (Poly-Si), similar to the gate electrode 52G of the amplifier transistor AMP, etc., are stacked in this order.

[0073] The switching transistor TRX switches the connection between the pixel circuit and the capacitance element C. The switching transistor TRX has a configuration similar to that of, for example, the amplification transistor AMP. Specifically, the switching transistor TRX has, for example, a planar structure and includes a gate electrode 52G, a source region 21S, and a drain region 21D. The gate electrode 52G is provided on the first surface 20A side of the semiconductor substrate 20 via a gate insulating film 51 made of, for example, silicon oxide (SiO2) or the like, and is formed using, for example, polysilicon (Poly-Si). The source region 21S and the drain region 21D are provided on either side of a channel region facing the gate electrode 52G and have a stacked structure including, for example, a diffusion layer 211 in which impurities are diffused and a low-resistance layer 212 made of silicide formed using a salicide process using, for example, cobalt silicide (CoSi2) or nickel silicide (NiSi).

[0074] The capacitive element C and the switching transistor TRX are electrically connected to each other, for example, through one pad electrode 55 (pad electrode 552) exposed on the surface facing the third substrate 300 in the upper wiring layer 50B and vias provided between the pad electrode 552 and the capacitive element C and between the pad electrode 552 and the source region 21S of the switching transistor TRX. The source region 21S of the switching transistor TRX is further electrically connected, through a via, to one pad electrode 541 exposed on the surface facing the first substrate 100 in the lower wiring layer 50A and bonded to a pad electrode 441 on the first substrate 100 side. The drain region 21D of the switching transistor TRX is electrically connected, through a via, to one pad electrode 54 (pad electrode 542) that is not used for bonding to the first substrate 100. The gate electrode 52G of the amplification transistor AMP and the source region 21S of the reset transistor RST are electrically connected to this pad electrode 542, respectively, through vias. That is, the drain region 21D of the switching transistor TRX is electrically connected to the gate electrode 51G of the amplification transistor AMP and the source region 21S of the reset transistor RST.

[0075] As described above, in this embodiment, the capacitance element C and the switching transistor TRX are provided between the floating diffusion FD and the amplification transistor AMP, making it possible to vary the capacitance of the floating diffusion FD. Therefore, in addition to the effects of the first embodiment, it is possible to realize a so-called global shutter function.

[0076] In this way, in the imaging device 1 etc. of the present disclosure, the amplification transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit are formed separately on multiple substrates, making it possible to add a capacitance element C and a switching transistor TRX.

[0077] In this embodiment, an example has been shown in which the capacitive element C is used to realize the global shutter function, but the capacitive element C can also be used to add capacitance to prevent signal fluctuations in the circuit.

[0078] <7. Variations> In the sixth embodiment, an example is shown in which the capacitance element C is formed by stacking, in this order, a diffusion layer 211 in which impurities are diffused in the semiconductor substrate 20, an insulating film 511 made of, for example, silicon oxide (SiO2), and a conductive film 521 made of, for example, polysilicon (Poly-Si), but the capacitance element C may have other configurations.

[0079] (7-1. Variation 1) 19 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device 1E according to Modification 1 of the present disclosure. The imaging device 1E of this modification differs from the sixth embodiment in that a capacitance element C1 having a metal-insulator-metal laminated structure is provided as the capacitance element C.

[0080] The capacitive element C1 has a so-called MIM structure in which, for example, a metal film 522, an insulating film 523, and a metal film 524 are stacked in this order on a conductive film 521 that is stacked in this order on the first surface 20A side of the semiconductor substrate 20. The metal films 522 and 524 can each be formed using, for example, titanium nitride (TiN). The insulating film 523 can be formed using, for example, a high-dielectric material (high-K material). The metal film 524 extends, for example, in the planar direction and is electrically connected to a via that electrically connects the source region 21S of the switching transistor TRX to the pad electrode 44.

[0081] In this way, the capacitive element C (capacitive element C1) may have an MIM structure and may be electrically connected to the source region 21S of the switching transistor TRX, for example, in the lower wiring layer 50A. This makes it possible to form the capacitive element C1 in advance before the bonding process with the first substrate 100.

[0082] (7-2. Variation 2) 20 is a schematic diagram illustrating an example of a cross-sectional configuration of an image pickup device 1E according to Modification 2 of the present disclosure. The image pickup device 1E of this modification differs from Modification 1 in that the capacitive element C2 having a metal-insulator-metal laminated structure is exposed on the surface of the upper wiring layer 50B facing the third substrate 300.

[0083] The capacitive element C2 has a so-called MIM structure, similar to the capacitive element C1. In this modification, the capacitive element C2 has a configuration in which one pad electrode 55 (pad electrode 553) exposed on the surface facing the third substrate 300, an insulating film 523, and a metal film 524 are stacked. The metal film 524 is electrically connected to the source region 21S of the switching transistor TRX, for example, through a via.

[0084] In this way, the capacitance element C (capacitance element C2) may have an MIM structure, and for example, one of the pad electrodes 54 (pad electrode 553) exposed on the surface of the interlayer insulating layer 53 of the upper wiring layer 50B may be used as the metal film of the capacitance element C2. This makes it easier to manufacture than the capacitance element C of the first modification.

[0085] (7-3. Variation 3) Fig. 21 illustrates an example of an equivalent circuit of an image pickup device 1E according to Modification 3 of the present disclosure. Fig. 22 schematically illustrates an example of a cross-sectional configuration of the image pickup device 1E illustrated in Fig. 21. The image pickup device 1E of this modification differs from the sixth embodiment and Modifications 1 and 2 in that a capacitive element C3 is provided on the third substrate 300.

[0086] The capacitive element C3 has a configuration in which, similar to the capacitive element C in the sixth embodiment, a diffusion layer 311 formed by diffusing impurities into the semiconductor substrate 30, an insulating film 611 having a configuration similar to the gate insulating film 61 of the select transistor SEL etc., and a conductive film 621 made of, for example, polysilicon (Poly-Si) similar to the gate electrode 62G of the select transistor SEL are stacked in this order. In this modification, the diffusion layer 311 is electrically connected, via a via, to one pad electrode 65 (pad electrode 651) exposed on the surface of the interlayer insulating layer 63 opposite to the second substrate 200 side. In addition, the conductive film 621 is electrically connected to the source region 20S of the switching transistor TRX via one pad electrode 64 (pad electrode 642) exposed on the surface of the interlayer insulating layer 63 facing the second substrate 200 and a via provided therebetween, and one pad electrode 552 exposed on the surface of the upper wiring layer 50B of the second substrate 200 facing the third substrate 300 and a via provided between the pad electrode 552 and the source region 20S of the switching transistor TRX.

[0087] In this way, the capacitive element C (capacitive element C3) may be provided on the third substrate 300. This makes it possible to increase the capacitance of the capacitive element C3 without putting pressure on the formation region of each transistor that constitutes the pixel circuit.

[0088] (7-4. Variation 4) 23 is a schematic diagram illustrating an example of a cross-sectional configuration of an image pickup device 1E according to Modification 4 of the present disclosure. The image pickup device 1E of this modification differs from Modification 3 in that the switching transistor TRX (switching transistor TRX1) is provided on the third substrate 300 together with the capacitive element C3.

[0089] The switching transistor TRX1 of this modification has the same configuration as the switching transistor TRX of the sixth embodiment. Specifically, the switching transistor TRX1 has, for example, a planar structure, and has a gate electrode 62G, a source region 31S, and a drain region 31D, similar to the select transistor SEL.

[0090] The capacitive element C3 and the switching transistor TRX1 are electrically connected to each other, for example, in the upper wiring layer 60B, via one pad electrode 652 and vias provided between the pad electrode 652 and the capacitive element C3 and between the pad electrode 652 and the source region 31S of the switching transistor TRX1. The source region 31S of the switching transistor TRX1 is further electrically connected to a pad electrode 643 exposed on a surface of the lower wiring layer 60A facing the second substrate 200, via a via. The drain region 31D of the switching transistor TRX1 is electrically connected to a pad electrode 644 exposed on a surface of the lower wiring layer 50A of the second substrate 200 facing the first substrate, via a via and a stacked film of a diffusion layer 211 and a low-resistance layer 212. As a result, the source region 31S of the switching transistor TRX1 is electrically connected to the floating diffusion FD, and the drain region 31D of the switching transistor TRX1 is electrically connected to the gate electrode 51G of the amplification transistor AMP and the source region 21S of the reset transistor RST.

[0091] In this way, the switching transistor TRX (switching transistor TRX1) may be provided on the third substrate 300.

[0092] (7-5. Variation 5) 24 is a schematic diagram illustrating an example of a cross-sectional configuration of an image pickup device 1E according to Modification 5 of the present disclosure. The image pickup device 1E of this modification differs from Modification 2 in that, for example, a capacitive element C5 having an MIM structure is exposed on a surface of a lower wiring layer 60A of the third substrate 300 that faces the second substrate 200.

[0093] The capacitive element C5 has a configuration similar to that of the capacitive element C2. Specifically, the capacitive element C5 has a configuration in which one pad electrode 645 exposed on the surface facing the second substrate 200, an insulating film 661, and a metal film 662 are stacked. The pad electrode 645 is electrically connected to the source region 21S of the switching transistor TRX through the pad electrode 551 of the second substrate 200 and a via. The metal film 662 extends, for example, in the planar direction and is electrically connected, for example, to one pad electrode 646 exposed on the surface facing the second substrate 200, similar to the pad electrode 645.

[0094] In this way, the capacitive element C (capacitive element C5) may use, for example, one of the multiple pad electrodes 64 (pad electrode 645) exposed on the surface of the interlayer insulating layer 63 of the lower wiring layer 60A as the metal film of the capacitive element C2.

[0095] It should be noted that the sixth embodiment and modifications 1 to 5 can be appropriately combined. For example, modifications 3 and 4 have been described using capacitance elements C3 and C4 each made up of a diffusion layer 311, an insulating film 611, and a conductive film 621. However, capacitance elements C3 and C4 may have an MIM structure similar to capacitance elements C1 and C2 shown in modifications 1 and 2.

[0096] Furthermore, in the sixth embodiment and modifications 1 to 5, examples have been shown in which the capacitive element C and the switching transistor TRX are further provided, but a resistive element or the like may also be provided.

[0097] 8. Seventh Embodiment Fig. 25 is an exploded perspective view illustrating a schematic configuration of an imaging device (imaging device 2) according to a seventh embodiment of the present disclosure. Fig. 26 is a schematic diagram illustrating an example of a cross-sectional configuration of the imaging device 2 illustrated in Fig. 25. The imaging device 2 of this embodiment differs from the first to sixth embodiments and modifications 1 to 5 in that a fifth substrate 500 provided with a logic circuit 510 is further stacked on the third substrate 300, which is formed by stacking, in this order, a first substrate 100 having a pixel unit 110 in which a plurality of sensor pixels 11 are arranged in an array, a second substrate 200 provided with an amplifier transistor AMP and a reset transistor RST (pixel transistor 210) that constitute a pixel circuit, and a third substrate 300 provided with a select transistor SEL (pixel transistor 310) that constitutes a pixel circuit.

[0098] On the fifth substrate 500, for example, as described above, a logic circuit 510 is formed on the semiconductor substrate 90 having a first surface 90A and a second surface 90B facing each other. The logic circuit 510 controls the amplifier transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel unit 110 and the pixel transistors 210 and 310, and processes pixel signals obtained from each pixel circuit. The logic circuit 510 has, for example, a logic unit 512 (SC, IO, CPU, IF), an analog unit 513 (ADC, CM, DAC), and a memory unit 514 (static RAM (SRAM), dynamic RAM (DRAM), magnetoresistive memory (MRAM), resistive change memory (ReRAM), ferroelectric memory (FeRAM), phase change memory (PCRAM), or flash memory).

[0099] As described above, in the imaging device 2 of this embodiment, the logic circuit 510 is further provided on the fifth substrate 500, and these are stacked on the third substrate 300. This provides the effect of making it possible to reduce the size of the imaging device 1 in addition to the effect of the first embodiment described above.

[0100] Furthermore, in the present embodiment, an example has been shown in which the amplification transistor AMP, reset transistor RST, and selection transistor SEL that constitute the pixel circuit are formed separately on two substrates, the second substrate 200 and the third substrate 300, and the fifth substrate 500 is laminated on the third substrate 300, but this is not limiting. For example, as in the image pickup device 1B in the third embodiment, the amplification transistor AMP, reset transistor RST, and selection transistor SEL may be formed separately on three substrates, the second substrate 200, the third substrate 300, and the fourth substrate 400, and the fifth substrate 500 may be laminated on the fourth substrate.

[0101] Furthermore, in this embodiment, an example has been shown in which the logic circuit 510 is mounted on one substrate (the fifth substrate 500), but the logic circuit 510 may be divided into multiple substrates, similar to the pixel circuits of the present disclosure, and these may be stacked on, for example, the third substrate 300.

[0102] 27, for example, an ADC circuit including a memory (MEM) may be provided in a pixel circuit provided for each sensor pixel 11 or each pixel shared unit, and this may be formed on the fifth substrate 500. The ADC circuit portion including the MEM can be reduced in area by applying a state-of-the-art core, and therefore can be mounted for each sensor pixel 11. Furthermore, by forming the MEM portion of the ADC circuit using the above-mentioned MRAM, ReRAM, FeRAM, PCRAM, flash memory, or the like, it becomes possible to form, as shown in FIG. 28, for example, one sensor pixel 11A provided on the first substrate 100, pixel transistors 210A and 310A corresponding to one sensor pixel 11A provided on each of the second substrate 200 and the third substrate 300, and an ADC circuit 520A provided on the fifth substrate 500 in approximately the same area.

[0103] <9. Application Examples> FIG. 29 shows an example of a schematic configuration of an imaging system 3 including the imaging devices (for example, the imaging device 1) according to the first to seventh embodiments and the first to fifth modifications.

[0104] The imaging system 3 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 3 includes, for example, the imaging device 1 according to the above-described embodiment and its modifications, an optical system 241, a shutter device 242, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 3, the imaging device 1 according to the above-described embodiment and its modifications, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0105] The imaging device 1 according to the above-described embodiment and its modified examples outputs image data corresponding to incident light. The optical system 241 includes one or more lenses, guides light (incident light) from a subject to the imaging device 1, and forms an image on the light-receiving surface of the imaging device 1. The shutter device 242 is disposed between the optical system 241 and the imaging device 1, and controls the light irradiation period and light blocking period of the imaging device 1 under the control of a drive circuit. The DSP circuit 243 is a signal processing circuit that processes signals (image data) output from the imaging device 1 according to the above-described embodiment and its modified examples. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is a panel-type display device, such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging device 1 according to the above-described embodiment and its modified examples. The storage unit 246 records image data of moving or still images captured by the imaging device 1 according to the above-described embodiment and its modified examples on a recording medium, such as a semiconductor memory or a hard disk. The operation unit 247, in accordance with operations by the user, issues operation commands for various functions of the imaging system 3. The power supply unit 248 appropriately supplies various types of power to these power sources as operating power sources for the imaging device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to the above-described embodiment and its modified examples.

[0106] Next, the imaging procedure in the imaging system 3 will be described.

[0107] 30 shows an example of a flowchart of the imaging operation in the imaging system 3. The user operates the operation unit 247 to instruct the start of imaging (step S101). Then, the operation unit 247 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit) executes imaging in a predetermined imaging method (step S103).

[0108] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data that has undergone the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 3.

[0109] In this application example, the imaging device 1 according to the above-described embodiment and its modification example is applied to an imaging system 3. This allows the imaging device 1 to be made smaller or have higher resolution, and therefore a small or high-resolution imaging system 3 can be provided.

[0110] <10. Application Examples> (Example of application to a moving object) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0111] FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0112] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0113] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0114] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0115] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0116] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0117] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0118] The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0119] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0120] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0121] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 57, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0122] FIG. 32 is a diagram showing an example of the installation position of the imaging unit 12031.

[0123] In FIG. 32, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0124] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0125] 32 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0126] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0127] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0128] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0129] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0130] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0131] (Application example to endoscopic surgery system) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0132] FIG. 33 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0133] 33 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11153 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0134] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0135] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0136] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0137] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0138] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0139] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0140] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0141] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0142] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0143] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0144] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0145] FIG. 34 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0146] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0147] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0148] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0149] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0150] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0151] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0152] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0153] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0154] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0155] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0156] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0157] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0158] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0159] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0160] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0161] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0162] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0163] The present disclosure has been described above with reference to the first to seventh embodiments, their first to fifth modifications, and application examples. However, the present disclosure is not limited to the above-described embodiments and can be modified in various ways. For example, in the above-described embodiments, the substrates (e.g., the first substrate 100, the second substrate 200, and the third substrate 300) are electrically connected by bonding pad electrodes to each other. However, the present disclosure is not limited to this. For example, as shown in FIG. 35, the first substrate 100 and the second substrate 200 (specifically, the floating diffusion FD provided on the first substrate 100 and the amplification transistor AMP provided on the second substrate 200) may be electrically connected via a through-hole wiring 86. Also, although not shown, for example, the first substrate 100 and the third substrate, the first substrate 100 and the fourth substrate, the second substrate 200 and the third substrate 300, the second substrate 200 and the fourth substrate 400, or the third substrate 300 and the fourth substrate 400 may be electrically connected to each other via through wiring.

[0164] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0165] The present disclosure can also be configured as follows. According to the present technology configured as follows, the first transistor and the second transistor that constitute the pixel circuit are formed on different substrates (second substrate and third substrate), and the second substrate and the third substrate are stacked in this order on the first substrate having the sensor pixel that performs photoelectric conversion. This reduces the formation area of the pixel circuit in a plan view, making it possible to reduce the pixel size. (1) a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on a first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, a second transistor constituting the pixel circuit on a third semiconductor substrate, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; An imaging device comprising: (2) the first transistor is disposed with a gate surface facing the first surface of the first substrate, The imaging device according to (1), wherein the second transistor is disposed with a gate surface facing the fourth surface of the second substrate. (3) the sensor pixel and the first transistor are electrically connected by bonding pad electrodes formed on the first surface and the third surface, respectively; The imaging device described in (1) or (2), wherein the first transistor and the second transistor are electrically connected by bonding pad electrodes formed on the fourth surface and the fifth surface, respectively. (4) The imaging device according to (3), wherein the pad electrode is formed primarily of copper. (5) The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor, The imaging device described in any one of (1) to (4), wherein the pixel circuit has a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates a voltage signal corresponding to the level of charge held in the floating diffusion as the pixel signal, and a selection transistor that controls the output timing of the pixel signal from the amplification transistor. (6) the amplification transistor and the reset transistor are formed on the second substrate; The imaging device according to (5), wherein the selection transistor is formed on the third substrate. (7) the amplifying transistor is formed on the second substrate, The imaging device according to (5), wherein the reset transistor and the selection transistor are formed on the third substrate. (8) a fourth semiconductor substrate having a seventh surface and an eighth surface, a third transistor constituting the pixel circuit, and a fourth substrate stacked on the third substrate with the sixth surface and the seventh surface facing each other; the amplifying transistor is formed on the second substrate, the reset transistor is formed on the third substrate, The imaging device according to (5), wherein the selection transistor is formed. (9) The imaging device described in any one of (5) to (8), wherein the gate electrodes of the transfer transistor, the reset transistor, the amplification transistor and the selection transistor are formed using polysilicon or a metal material. (10) The imaging device described in any one of (5) to (9), wherein the gate of the transfer transistor is formed using a metal material, and the gate of the transfer transistor and the floating diffusion are directly connected. (11) The imaging device described in any one of (3) to (10), wherein the gate electrode, source region, or drain region of the first transistor is directly connected to the pad electrode formed on the fourth surface. (12) The imaging device according to any one of (1) to (11), wherein the first transistor and the second transistor have a planar structure or a three-dimensional structure. (13) The imaging device according to any one of (1) to (12), wherein a capacitive element is further provided on the second substrate or the third substrate. (14) The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor, the pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor; The imaging device according to (13), wherein the capacitive element is disposed between the floating diffusion and the amplifying transistor. (15) The imaging device according to (14), further comprising a switching transistor that switches between connection and non-connection of the capacitance element and the pixel circuit. (16) The imaging device according to (14) or (15), wherein the capacitive element has a metal-insulator-metal laminated structure or a metal-oxide-metal laminated structure. (17) The imaging device according to any one of (1) to (16), wherein a resistive element is further provided on the second substrate or the third substrate. (18) The imaging device according to any one of (1) to (17), further comprising a fifth substrate stacked above the third substrate so that the ninth surface and the sixth surface face each other, the fifth substrate having a ninth surface and a tenth surface, and a logic circuit for processing the pixel signals on a fifth semiconductor substrate. (19) The imaging device according to (18), wherein the pixel circuit further includes an ADC circuit that converts an analog signal into a digital signal and holds the digital signal, and the ADC circuit is provided on the fifth substrate. (20) The imaging device described in (19), wherein the sensor pixel provided on the first substrate, the first transistor provided on the second substrate, the second transistor provided on the third substrate, and the ADC circuit provided on the fifth substrate have approximately the same formation area. (twenty one) The imaging device according to (19) or (20), wherein the ADC circuit includes any one of a magnetoresistive memory, a resistance change memory, a ferroelectric memory, a phase change memory, and a flash memory. (twenty two) An imaging device described in any one of (1) to (21), wherein any of the first substrate and the second substrate, the first substrate and the third substrate, and the second substrate and the third substrate are electrically connected to each other via through-wiring that penetrates either or both of the second semiconductor substrate and the third semiconductor substrate. (twenty three) a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on a first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, a second transistor constituting the pixel circuit on a third semiconductor substrate, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; An electronic device having an imaging device comprising:

[0166] This application claims priority based on Japanese Patent Application No. 2020-064019, filed on March 31, 2020, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0167] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion in a first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor; the pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor; the amplifying transistor is formed on the second substrate, The reset transistor and the selection transistor are formed on the third substrate. Imaging device.

2. the first transistor is disposed with a gate surface facing the first surface of the first substrate, The imaging device according to claim 1 , wherein the second transistor is disposed with a gate surface facing the fourth surface of the second substrate.

3. the sensor pixel and the first transistor are electrically connected by bonding pad electrodes formed on the first surface and the third surface, respectively; The imaging device according to claim 1 , wherein the first transistor and the second transistor are electrically connected by bonding pad electrodes formed on the fourth surface and the fifth surface, respectively.

4. The imaging device according to claim 3 , wherein the pad electrode is formed primarily from copper.

5. The imaging device according to claim 1 , wherein the gate electrodes of the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor are formed using polysilicon or a metal material.

6. The imaging device according to claim 1 , wherein the gate of the transfer transistor is formed using a metal material, and the gate of the transfer transistor and the floating diffusion are directly connected to each other.

7. 4. The imaging device according to claim 3, wherein one of a gate electrode, a source region, and a drain region of the first transistor is directly connected to the pad electrode formed on the fourth surface.

8. The imaging device according to claim 1 , wherein the first transistor and the second transistor have a planar structure or a three-dimensional structure.

9. The imaging device according to claim 1 , wherein the second substrate or the third substrate is further provided with a capacitive element.

10. An imaging device as described in Claim 9, wherein the capacitive element is arranged between the floating diffusion and the amplifying transistor.

11. The imaging device according to claim 10 , further comprising a switching transistor that switches between connection and disconnection of the capacitance element and the pixel circuit.

12. 11. The imaging device according to claim 10, wherein the capacitive element has a metal-insulator-metal laminated structure or a metal-oxide-metal laminated structure.

13. The imaging device according to claim 1 , wherein the second substrate or the third substrate is further provided with a resistive element.

14. 2. The imaging device according to claim 1, further comprising a fifth substrate having a ninth surface and a tenth surface, a fifth semiconductor substrate having a logic circuit for processing the pixel signals, and stacked above the third substrate so that the ninth surface and the sixth surface face each other.

15. The imaging device according to claim 14 , wherein the pixel circuit further includes an ADC circuit that converts an analog signal into a digital signal and holds the digital signal, and the ADC circuit is provided on the fifth substrate.

16. 16. The imaging device according to claim 15, wherein the sensor pixel provided on the first substrate, the first transistor provided on the second substrate, the second transistor provided on the third substrate, and the ADC circuit provided on the fifth substrate have substantially the same formation area.

17. 16. The imaging device according to claim 15, wherein the ADC circuit includes any one of a magnetoresistive memory, a resistance change memory, a ferroelectric memory, a phase change memory, and a flash memory.

18. 2. The imaging device according to claim 1, wherein any one of the first substrate and the second substrate, the first substrate and the third substrate, and the second substrate and the third substrate is electrically connected to each other via through-wiring that penetrates either or both of the second semiconductor substrate and the third semiconductor substrate.

19. A first substrate having a first surface and a second surface, and a first semiconductor substrate having sensor pixels that perform photoelectric conversion; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor; the pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor; a fourth semiconductor substrate having a seventh surface and an eighth surface, a third transistor constituting the pixel circuit, and a fourth substrate stacked on the third substrate with the sixth surface and the seventh surface facing each other; the amplifying transistor is formed on the second substrate, the reset transistor is formed on the third substrate; The select transistor is formed Imaging device.

20. A first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on the first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; the sensor pixel and the first transistor are electrically connected by bonding pad electrodes formed on the first surface and the third surface, respectively; the first transistor and the second transistor are electrically connected by bonding pad electrodes formed on the fourth surface and the fifth surface, respectively; The gate electrode, the source region, or the drain region of the first transistor is directly connected to the pad electrode formed on the fourth surface. Imaging device.

21. a first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion in a first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor; the pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor; the amplifying transistor is formed on the second substrate, The reset transistor and the selection transistor are formed on the third substrate. An electronic device having an imaging device.

22. A first substrate having a first surface and a second surface, and having sensor pixels that perform photoelectric conversion on the first semiconductor substrate; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; The sensor pixel includes a light receiving element, a transfer transistor electrically connected to the light receiving element, and a floating diffusion that temporarily holds charge output from the light receiving element via the transfer transistor; the pixel circuit includes a reset transistor that resets the potential of the floating diffusion to a predetermined position, an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of charge held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor; a fourth semiconductor substrate having a seventh surface and an eighth surface, a third transistor constituting the pixel circuit, and a fourth substrate stacked on the third substrate with the sixth surface and the seventh surface facing each other; the amplifying transistor is formed on the second substrate, the reset transistor is formed on the third substrate; The select transistor is formed An electronic device having an imaging device.

23. A first substrate having a first surface and a second surface, and a first semiconductor substrate having sensor pixels that perform photoelectric conversion; a second substrate having a third surface and a fourth surface, and including a first transistor on a second semiconductor substrate that constitutes a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, the second substrate being stacked on the first substrate with the first surface and the third surface facing each other; a third substrate having a fifth surface and a sixth surface, the third substrate having a second transistor that configures the pixel circuit, and stacked on the second substrate with the fourth surface and the fifth surface facing each other; the sensor pixel and the first transistor are electrically connected by bonding pad electrodes formed on the first surface and the third surface, respectively; the first transistor and the second transistor are electrically connected by bonding pad electrodes formed on the fourth surface and the fifth surface, respectively; The gate electrode, the source region, or the drain region of the first transistor is directly connected to the pad electrode formed on the fourth surface. An electronic device having an imaging device.

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