Low-power flip-flop with reduced parasitic capacitance

Abstract

Parasitic-aware single-edge triggered flip-flops reduce clock power through layout optimizations enabled through process-circuit co-optimization. Static pass-gate master-slave flip-flops utilize novel layout optimizations that enable significant power reduction. The layout eliminates the clock poly above the notch in the diffusion region. A poly line implements the clock node. The poly line is aligned between the n-type and p-type active regions.

Description

[Technical Field]

[0001] This application is a continuation of and claims the benefit of priority to U.S. Patent Application No. 16 / 727,742, entitled "LOW POWER FLIP-FLOP WITH REDUCED PARASITIC CAPACITANCE," filed December 26, 2019, which is incorporated by reference in its entirety. [Background technology]

[0002] Clocks are one of the most significant power contributors and limitations for power-constrained server and / or mobile microprocessors and SoCs (systems-on-chip), discrete and / or integrated graphics, AI (artificial intelligence) and / or special-purpose accelerators. Reducing power in budget-constrained systems improves performance by allowing more cores, memory, or processing elements to be integrated, improving battery life in mobile and edge devices. Dynamic clock power is the largest contributor, consuming up to 60% of the total chip power consumption, for example, when the majority of the load is on the final flip-flop.

[0003] Flip-flops (FFs) are fundamental circuits used in all digital synchronous systems and contribute the most to clock power, making them extremely low-power. Today's FFs already use the smallest sized devices and cannot be further miniaturized to reduce power. With process technology scaling, circuits are limited by variations to enable low-voltage operation for high energy efficiency. This limits the smallest possible device size and prevents further dynamic power savings through transistor sizing. As process technology scales (e.g., below 7nm process technology nodes), performance, power, and area (PPA) gains slow, requiring new circuit innovations to improve PPA, particularly to reduce clock power. Furthermore, the demand for higher-frequency central processing units (CPUs), graphics, and AI accelerators drives deeper pipelines, further increasing clock power. [Brief explanation of the drawings]

[0004] The disclosed embodiments will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which should not be construed to limit the disclosure to particular embodiments but are merely for purposes of illustration and understanding. [Figure 1] A multi-bit transmission gate flip-flop (FF) with a data input multiplexer (Mux-D) is shown. [Figure 2A] 2A and 2B each show a layout of a portion of the multi-bit transmission gate FF of FIG. [Figure 2B] 2A and 2B each show a layout of a portion of the multi-bit transmission gate FF of FIG. [Figure 3] 1 illustrates a parasitic-aware multi-bit FF with a tri-state master, according to some embodiments. [Figure 4] 1 illustrates a layout of a parasitic-aware multi-bit FF according to some embodiments. [Figure 5] 1 illustrates a smart device or computer system or SoC (System on Chip) having parasitic-aware multi-bit FFs according to some embodiments of the disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] Within FFs, parasitic capacitance contributes a significant portion of power consumption. Experimental data shows that clock power is split approximately 50% equally between device and interconnect parasitic capacitance. Therefore, according to various embodiments, careful optimization of parasitic capacitance layout effects is used to achieve low clock power. Scaled FinFET and gate-all-around (GAA) devices at process technology nodes below 7 nm have increased parasitic capacitance, and therefore, according to various embodiments, scaling boosters such as contact-over-active gate (COAG) can enable new low-power layout optimizations.

[0006] Some embodiments describe a parasitic-aware single-edge triggered flip-flop that reduces clock power through layout optimization enabled through process-circuit co-optimization. Some embodiments disclose a static pass-gate master-slave flip-flop that utilizes novel layout optimizations that enable significant power reduction. While the increased use of minimum device sizes due to technology scaling has increased the contribution of increased parasitic capacitance to clock power, new scaling boosters such as COAG enable new layout structures to minimize these issues.

[0007] The flip-flops of various embodiments are low-power FFs that use digital synchronous CPUs, GPUs (graphics processor units), and AI accelerators. The process-circuit co-optimized flip-flops of various embodiments reduce power by eliminating metal routes and diffusion notches, thereby reducing device and interconnect parasitic capacitance. Note that this parasitic capacitance contribution only gets worse as technology scales.

[0008] There are numerous technical advantages of the various embodiments. For example, the circuits of the various embodiments demonstrate ISO performance / ISO area with power savings of 15% to 25% over mid-height library and multi-bit FF configurations, which directly improves chip-level power. Other technical advantages will be apparent from the various figures and embodiments.

[0009] In the following description, numerous details are set forth to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. Also, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments of the present disclosure.

[0010] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more component signal paths and / or may have arrows at one or both ends to indicate the primary direction of information flow. Such indications are not intended to be limiting. Rather, the lines are used to aid in easy understanding of a circuit or logic unit in connection with one or more exemplary embodiments. The signals represented are dictated by design needs or preferences and may, in practice, have one or more signals that can travel in either direction and may be implemented with any suitable type of signaling scheme.

[0011] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things that are connected, without any intermediate devices.

[0012] The term "analog signal" as used herein generally refers to a continuous signal in which the time-varying characteristics (variables) of the signal are representative of some other time-varying quantity, i.e., similar to another time-varying signal.

[0013] The term "digital signal" refers to a physical signal that represents a series of discrete values (a quantified, discrete-time signal), such as any bit stream or an analog signal that has been digitized (sampled and analog-to-digital converted).

[0014] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0015] The term "adjacent" as used herein generally refers to the position of one thing next to (e.g., immediately adjacent to, or in close proximity with one or more things between them) or abutting (e.g., adjoining) another thing.

[0016] The terms "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired functionality.

[0017] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0018] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, which may subsequently result in a reduction in layout area. The term "scaling" also generally refers to miniaturizing layouts and devices within the same technology node. The term "scaling" can also refer to adjusting (e.g., slowing down or speeding up, i.e., scaling down or scaling up, respectively) signal frequency relative to another parameter, such as power supply level. The terms "substantially," "close," "approximately," "near," and "about" generally refer to within ±10% of a target value.

[0019] Unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc. to describe common objects is intended merely to indicate that different instances of similar objects are being referred to and is not intended to imply that the objects so described must be in a given sequence, temporally, spatially, in ranking, or in any other way.

[0020] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0021] In the specification and claims, where present, the terms "left," "right," "front," "rear," "top," "bottom," "upper," "lower," and the like are used for descriptive purposes and are not necessarily used to describe permanent relative positions.

[0022] It is noted that elements of a figure having the same reference number (or name) as elements of another figure may operate or function in a similar manner as described, but are not limited to such.

[0023] For purposes of the embodiments, the transistors in the various circuit and logic blocks described herein are metal-oxide-semiconductor (MOS) transistors or their derivatives, where MOS transistors include drain, source, gate, and bulk terminals. Transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, gate-all-around cylindrical transistors, tunneling FETs (TFETs), square wire, rectangular ribbon transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functionality, such as carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are, in other words, equal terminals and are used interchangeably herein. On the other hand, TFET devices have asymmetrical source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., may also be used without departing from the scope of the disclosure.

[0024] Figure 1 shows a multi-bit transmission gate flip-flop (FF) 100 with a data input multiplexer (Mux-D). Multi-bit flip-flops have become an industry standard for reducing clock power in flip-flops and are integrated into many synthesis and APR tool flows. Multi-bit FF 100 can be expressed as multiple FFs 1011-101, where 'N' is greater than 1. NEach of the multiple FFs receives a scan select signal ssb (and its inverse ss). Inverter 102 generates the inverse ss of the scan select bar. Each of the multiple FFs shares clock buffers or inverters 103 and 104, which provide clocks to nodes nc1 and nc2. Here, node names are used interchangeably with signal names. For example, clk can refer to the node clk or the clock signal depending on the context. Each FF receives a scan input and a data input. For N FFs, there are N scan inputs (e.g., sd[N-1:0]) and N data inputs (e.g., d[N-1:0]). The output 'o' of each FF can be merged into an N-bit bus (e.g., o[N-1:0]).

[0025] One such FF (e.g., 101 N ) is shown in Figure 1. FF101 N includes a scan input multiplexer that selects either scan input sd or data input d according to scan select signals ss and ssb. The multiplexer has two tri-state inverters 121a and 121b. An inverter 122 receives an output n12 from one of the two tri-state inverters 121a and 121b. A master latch receives the output of inverter 122. The master latch includes a transmission pass gate 123 and a memory element. The memory element includes a cross-coupled inverter, inverter 124, and tri-state inverter 125. Clock nodes nc1 and nc2 control transmission gate 123. The clock on nodes nc1 and nc2 controls tri-state inverter 125. Here, nodes nk3 and nk4 are the state nodes of the master latch. A transmission gate 126 couples the master latch to the slave latch. The memory element of the slave latch includes an inverter 127 and a tri-state inverter 128. The state nodes of the slave latch are nk5 and nk6. The state stored in node nk5 is output via inverter 129 to output node o.

[0026] The multi-bit FF concept involves grouping physically close flip-flops and combining them into a single standard cell with a shared, miniaturized local clock inverter. This reduces the power contribution and clock pin capacitance of the local clock inverter, but the internal clock devices per flip-flop remain at eight, and all clock nodes nc1 and nc2 must be metal-connected together. Also, to achieve low-voltage operation, the master feedforward device 124 must be enlarged (e.g., 2x) to prevent write-back disturbances. This size constraint can increase clock power due to diffusion notches and / or increase layout area.

[0027] One drawback of the multi-bit flip-flop technology of Figure 1 is that due to the sharing of the local clock inverter, parasitic capacitance becomes a significant portion of the cell power, resulting in lower power consumption. Because clock nodes nc1 and nc2 must be connected together with other flip-flops in the multi-bit structure, this increases the capacitance contribution of the interconnect. With scaled process technologies, the capacitance of the local interconnect increases to finish standard cells.

[0028] 2A-2B show layouts 200 and 220, respectively, of a portion of the multi-bit transmission gate FF of FIG. 1. Layout 200 shows p-type devices within well or diffusion 201 and n-type devices underneath them. Region 202 represents the source / drain region of the p-type transistor, and region 203 represents the source / drain region of the n-type transistor. The diffusion notch parasitic capacitance increases the clock nc1 or nc2 parasitic capacitance. The nc1 poly and nc2 poly are disconnected and misaligned. To align these clock polys in a conventional manner, the clock power savings from metal reduction would be offset by the increased diffusion notch capacitance contribution and would not be routable, resulting in very little power savings. The vertical lines are poly lines 204. Layout 200 is of device region 130, which includes inverter 122, pass gate 123, and tri-state inverter 125. 2A-2B show nodes nk3, nk5, n12, nc1, and nc2, where the polylines for clock nodes nc1 and nc2 are split (e.g., not connected to each other in the poly layer) and connected together with metal wiring in higher metal layers (e.g., metal layer 0 (M0) and metal layer 1 (M1)).

[0029] Layout 220 shows devices 124 and 126 and their associated nodes nc1, nk4, nk5, power (vcc), and ground (vss). As described herein, to achieve low-voltage operation, master feedforward device 124 must be oversized (e.g., 2x) to prevent writeback failures. This size constraint can increase clock power and / or increase layout area due to a diffusion notch (e.g., 222). Clock polylines nc1 and nc2 above respective diffusions 222 and 223 introduce capacitance that is larger than one minimum-sized gate capacitance. This extra capacitance results in higher power consumption. One reason for the notch is the design rule constraint for device 124 of 2x.

[0030] 3 illustrates a parasitic-aware multi-bit FF 300 with a tri-state master, according to some embodiments. Various embodiments reduce the clock power of the flip-flop, which is the most dominant part of the flip-flop power, since data activity has a much lower toggle rate.

[0031] The multi-bit FF300 is a process-circuit co-optimized FF3011-301, where 'N' is a number greater than 1. N One such FF301 N ) is shown. FF301 N The FF 101 includes a scan input multiplexer that selects either the scan input sd or the data input d according to scan select signals ss and ssb. The multiplexer has two tri-state inverters 121a and 121b. The output n12 from one of the tri-state inverters 121a / b is directly received by a tri-state inverter 330. The tri-state inverter 330 replaces the inverter 122 and pass gate 123 of the FF 101. The tri-state inverter 330 is part of a master latch, which also includes a memory element coupled to the output of the tri-state inverter 330. The output nk3 of the inverter 330 is received by the memory element. The memory element has a cross-coupled inverter consisting of an inverter 324 and a tri-state inverter 125. Clocks nc1 and nc2 control the tri-state inverter 330 and the tri-state inverter 125. Here, nodes nk3 and nk4 are the state nodes of the master latch. A transmission gate 126 couples the master latch to the slave latch. The memory element of the slave latch has an inverter 127 and a tristate inverter 128. The state nodes of the slave latch are nk5 and nk6. The state stored in node nk5 is output to output node o via inverter 129.

[0032] FIG. 4 illustrates a layout 400 of a parasitic-aware multi-bit FF 301 according to some embodiments. Layout 400 eliminates the diffusion notch seen when a 2× master inverter 124 is interfaced with a 1× pass gate 123. Removing pass gate 123 and replacing it with a tri-state inverter 330 results in reduced clock power, especially after aligning clock polys nc1 and nc2. Aligning clock polys nc1 and nc2 results in the elimination of numerous inter-cell routings to finish the cell, reducing clock power. Because layout 400 uses more horizontal resources (e.g., metal layer 0 (M0)) within the cell layout, in some embodiments, circuit modifications to FF 100 are made. For example, in some embodiments, a tri-state inverter 330 replaces the master inverter-pass gate (devices 122 and 123) of FIG. 1. The tri-state inverter 330 reduces the need to use metal to route connections. This modification to the circuit allows for aligned clock polys nc1 and nc2. The layout 400 of the new parasitic-aware multi-bit quad flip-flop 301 with aligned clock poly does not exhibit any spreading notches. The 2x inverter 124 (now device 324) is legged and interleaved with other devices.

[0033] In some embodiments, the multi-bit FF (or vectored FF) transmits the clock (nc2) and the inverse of the clock (nc1) to multiple flip-flops (301 1-N ) and a pair of inverters (103 and 104) for providing each FF (e.g., 301 N). For example, the pair of inverters (103 and 104) is shared by the multiple flip-flops. The FF is circuit-process co-optimized and includes a tri-state inverter 330 controllable by a clock (nc2) and an inverse of the clock (nc1). In various embodiments, within the layout of the FF, the clock and the inverse of the clock are routed on aligned poly lines between the p-type and n-type active regions, as shown in FIG. 4. For example, the poly routes for nc1 and nc2 extend smoothly from region 202 to region 203, connecting the gates of the n-type and p-type transistors without using higher metal layers (e.g., metal 0 (M0), metal 1 (M1), and / or their associated vias). Therefore, the capacitance on the clock nodes nc1 and nc2 is reduced, which directly reduces the power consumption of the FF.

[0034] The FF further includes a first memory (e.g., inverter 324 and tri-state inverter 125) coupled to the output nk3 of tri-state inverter 330. This first memory is part of the master latch. Replacing inverter 122 and pass gate 123 with a single tri-state inverter 330 further simplifies the layout of the FF. In various embodiments, the layout of inverter 324 uses legged devices. The legged devices are, according to various embodiments, made to a minimum device size. For example, inverter 324 spans at least two devices, such that each leg is a minimum device size leg. Because all other devices are made to a minimum device size, the notch in the diffusion region of FIG. 2B is also mitigated. The legging in the layout of inverter 324 aligns the polylines of clock nodes nc1 and nc2 between the diffusion regions. As described with reference to FIG. 2B, the diffusion notch increases the clock power on clock nodes nc1 and nc2 and requires an additional metal layer to connect the polylines of nc1 and nc2. Layout 400 eliminates the drawbacks of the diffusing notch.

[0035] In various embodiments, the FF includes a slave latch including a pass gate 126 coupled to a first memory. The pass gate 126 is controllable by a clock and an inverse of the clock. Clock nodes nc1 and nc2 are aligned between p and n diffusion regions, thereby reducing clock switching capacitance. The slave latch further includes a second memory (e.g., inverter 127 and tristate inverter 128) coupled to the pass gate 126. An output inverter 129 (part of the FF) drives the state on the storage node (e.g., nk5) of the slave latch to the output o.

[0036] Table 1 shows the performance, power, and area (PPA) simulation comparison using the 7nm mid-height standard cell library. [Table 1]

[0037] FF circuit 301 demonstrates ISO performance / ISO area with a power savings of 15%-19% at a typical value of 0.65V and 100°C. For high frequency chips with a large number of flip-flops, the total chip-level power can be, for example, up to 60%, with 30% coming from the flip-flops. Based on these estimates, FF 300 and its layout 400 can save approximately 1-3% of the total chip-level power, depending on the flip-flop usage.

[0038] While the embodiments of FIGS. 3 and 4 are shown with scan-controllable multiplexers, the FFs can be implemented without scan-controllable multiplexers. In one such embodiment (not shown), the input of tri-state inverter 330 directly receives the data input 'd'. The other devices of the master latch and slave latch remain the same, with the same electrical connections and size. In this embodiment, the multi-bit FF is similar to, but smaller than, the multi-bit FF of FIG. 3. For example, the signal routing for sd[N-1:0], ssb, and inverter 102 is eliminated. In some embodiments, any of the inverters (e.g., 102, 103, 104, 324, 127, 129) can be replaced with NAND or NOR gates to provide additional knobs for gating signals. For example, a control signal to a NAND or NOR gate can enable the NAND or NOR gate to behave as an inverter or output a fixed, predetermined value in response to the logic level of the control signal.

[0039] FIG. 5 illustrates a smart device or computer system or SoC (system-on-chip) having a parasitic-aware multi-bit FF according to some embodiments of the disclosure. In some embodiments, device 2500 represents a suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IoT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It is understood that certain components are shown schematically, and not all components of such a device are shown in device 2500. Any component therein can have a parasitic-aware multi-bit FF. For example, any critical timing path can use a high-performance, low-power parasitic-aware multi-bit FF.

[0040] In one example, device 2500 includes a system on a chip (SoC) 2501. An example boundary of SoC 2501 is shown in FIG. 5 using a dotted line, and some example components are shown as being included within SoC 2501, although SoC 2501 may include any suitable components of device 2500.

[0041] In some embodiments, device 2500 includes a processor 2504. Processor 2504 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, processing core, or other processing means. The processing operations performed by processor 2504 include the execution of an operating platform or operating system on which applications and / or device functions execute. These processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting computing device 2500 to other devices, and / or the like. These processing operations may also include operations related to audio I / O and / or display I / O.

[0042] In some embodiments, the processor 2504 includes multiple processing cores (also referred to as cores) 2508a, 2508b, 2508c. While only three cores 2508a, 2508b, 2508c are shown, the processor 2504 may include any other suitable number of processing cores, such as tens or hundreds of processing cores. The processor cores 2508a, 2508b, 2508c may be implemented on a single integrated circuit (IC) chip. Furthermore, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, or other components.

[0043] In some embodiments, the processor 2504 includes a cache 2506. In one example, sections of the cache 2506 may be dedicated to individual cores 2508 (e.g., a first section of the cache 2506 is dedicated to core 2508a, a second section of the cache 2506 is dedicated to core 2508b, etc.). In one example, one or more sections of the cache 2506 may be shared between two or more of the cores 2508. The cache 2506 may be divided into different hierarchies, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0044] In some embodiments, processor core 2504 may include a fetch unit that fetches instructions (including instructions with conditional branches) for execution by core 2504. The instructions may be fetched from any storage device, such as memory 2530. Processor core 2504 may also include a decode unit that decodes the fetched instructions. For example, the decode unit may decode the fetched instructions into multiple micro-operations. Processor core 2504 may include a schedule unit that performs various operations associated with storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready to be dispatched (e.g., until all source values of the decoded instruction are available). In one embodiment, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to the execution units for execution.

[0045] The execution units may execute dispatched instructions after being decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In one embodiment, the execution units may include two or more execution units (e.g., an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution units may also perform various arithmetic operations, such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In one embodiment, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution units.

[0046] The execution units may also execute instructions out of order. Thus, in one embodiment, processor core 2504 may be an out-of-order processor core. Processor core 2504 may also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In one embodiment, retiring an executed instruction may result in the processor state being committed from the execution of the instruction, physical registers used by the instruction being deallocated, and so on. Processor core 2504 may also include a bus unit that enables communication between components of processor core 2504 and other components via one or more buses. Processor core 2504 may also include one or more registers that store data accessed by various components of core 2504 (e.g., values related to assigned application priorities and / or subsystem state (mode) associations, etc.).

[0047] In some embodiments, device 2500 includes connection circuitry 2531. For example, connection circuitry 2531 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks), e.g., that enable device 2500 to communicate with external devices. Device 2500 can be isolated from external devices, such as, for example, other computing devices, wireless access points, or base stations.

[0048] In one example, the connection circuit 2531 may include multiple different types of connections. Generalizingly, the connection circuit 2531 may include cellular connection circuitry, wireless connection circuitry, etc. The cellular connection circuitry of the connection circuit 2531 generally refers to cellular network connections provided by a wireless carrier, such as those provided via a global system for mobile communications (GSM) or a variation or derivative thereof, a code division multiple access (CDMA) or a variation or derivative thereof, a time division multiplexing (TDM) or a variation or derivative thereof, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or a variation or derivative thereof, a 3GPP Long Term Evolution (LTE) system or a variation or derivative thereof, a 3GPP LTE-Advanced (LTE-A) system or a variation or derivative thereof, a fifth generation (5G) wireless system or a variation or derivative thereof, a 5G mobile network system or a variation or derivative thereof, a 5G New Radio (NR) system or a variation or derivative thereof, or other cellular service standard. The wireless connection circuitry (or wireless interface) of the connection circuitry 2531 refers to a wireless connection that is not cellular and can include a personal area network (e.g., Bluetooth, near field, etc.), a local area network (e.g., Wi-Fi, etc.), and / or a wide area network (e.g., WiMax, etc.), and / or other wireless communications. In one example, the connection circuitry 2531 can include a network interface, such as a wired or wireless interface, such that a system embodiment can be incorporated into a wireless device, such as a mobile phone or personal digital assistant.

[0049] In some embodiments, device 2500 includes a control hub 2532, which represents hardware devices and / or software components involved in interacting with one or more I / O devices. For example, processor 2504 may communicate with one or more of a display 2522, one or more peripheral devices 2524, a storage device 2528, one or more other external devices 2529, etc. via control hub 2532. Control hub 2532 may be a chipset, a platform control hub (PCH), and / or the like.

[0050] For example, control hub 2532 illustrates one or more connection points for additional devices to connect to device 2500, e.g., through which a user may interact with the system. For example, devices that may be attached to device 2500 (e.g., device 2529) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I / O devices used in specific applications, such as, for example, card readers or other devices.

[0051] As described above, the control hub 2532 can interact with audio devices, the display 2522, and the like. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the device 2500. Furthermore, audio output can be provided instead of, or in addition to, a display output. In another example, if the display 2522 includes a touchscreen, the display 2522 also functions as an input device that can be managed, at least in part, by the control hub 2532. Additional buttons or switches can also be present on the computing device 2500 to provide I / O functions managed by the control hub 2532. In one embodiment, the control hub 2532 manages devices such as an accelerometer, a camera, a light sensor, or other environmental sensors, or other hardware that can be included in the device 2500. The input can be part of direct user interaction and can also provide environmental input to the system to affect its operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other mechanisms).

[0052] In some embodiments, the control hub 2532 may couple to various devices using any suitable communication protocol, such as, for example, PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High-Definition Multimedia Interface (HDMI), Firewire, etc.

[0053] In some embodiments, display 2522 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide visual and / or tactile displays for a user to interact with device 2500. Display 2522 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, display 2522 includes a touchscreen (or touchpad) device that provides both output and input to a user. In one example, display 2522 may communicate directly with processor 2504. Display 2522 may be one or more of an internal display, such as in a mobile electronics device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, display 2522 may be a head-mounted display (HMD), such as a stereoscopic display used in virtual reality (VR) or augmented reality (AR) applications.

[0054] In some embodiments, although not shown, in addition to (or instead of) the processor 2504, the device 2500 may include a graphics processing unit (GPU) including one or more graphics processing cores that may control one or more aspects of displaying content on the display 2522.

[0055] The control hub 2532 (or platform controller hub) may include hardware interfaces and connectors and software components (eg, drivers, protocol stacks) for making peripheral connections to, for example, peripheral devices 2524 .

[0056] It will be understood that device 2500 may be a peripheral to other computing devices or may have peripheral devices connected to it. Device 2500 may have a "docking" connector for connecting to other computing devices, such as for purposes of managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2500. Additionally, the docking connector may allow device 2500 to connect to certain peripherals that allow computing device 2500 to control content output to, for example, an audiovisual system or other system.

[0057] In addition to dedicated docking connectors or other proprietary connection hardware, device 2500 can provide peripheral connectivity through common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), Mini Display Port (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0058] In some embodiments, the connection circuitry 2531 may be coupled to the control hub 2532, for example, in addition to or instead of being directly coupled to the processor 2504. In some embodiments, the display 2522 may be coupled to the control hub 2532, for example, in addition to or instead of being directly coupled to the processor 2504.

[0059] In some embodiments, device 2500 includes memory 2530 coupled to processor 2504 via memory interface 2534. Memory 2530 includes memory devices for storing information within device 2500. Memory may include non-volatile (state does not change when power to the memory device is interrupted) and / or volatile (state is indeterminate when power to the memory device is interrupted) memory devices. Memory device 2530 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for functioning as process memory. In one embodiment, memory 2530 may operate as system memory for device 2500 for storing data and instructions used when one or more processors 2504 execute applications or processes. Memory 2530 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of device 2500.

[0060] Elements of various embodiments and examples may also be provided as a machine-readable medium (e.g., memory 2530) that stores computer-executable instructions (e.g., instructions for performing any other process described herein). The machine-readable medium (e.g., memory 2530) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, the disclosed embodiments may be downloaded as a computer program (e.g., BIOS) that may be transferred by data signal from a remote computer (e.g., server) to a requesting computer (e.g., client) over a communications link (e.g., modem or network connection).

[0061] In some embodiments, device 2500 includes temperature measurement circuitry 2540, for example, to measure the temperatures of various components of device 2500. In one example, temperature measurement circuitry 2540 may be built into, coupled to, or attached to the various components whose temperatures are to be measured and monitored. For example, temperature measurement circuitry 2540 may measure the temperatures of (or temperatures within) one or more of cores 2508a, 2508b, 2508c, voltage regulator 2514, memory 2530, a motherboard of SoC 2501, and / or any suitable component of device 2500.

[0062] In some embodiments, device 2500 includes power measurement circuitry 2542, for example, to measure power consumed by one or more components of device 2500. In one example, in addition to or instead of measuring power, power measurement circuitry 2542 may measure voltage and / or current. In one example, power measurement circuitry 2542 may be built into, coupled to, or attached to various components whose power, voltage, and / or current should be measured and monitored. For example, power measurement circuitry 2542 may measure power, current, and / or voltage supplied by one or more voltage regulators 2514, power supplied to SoC 2501, power supplied to device 2500, power consumed by processor 2504 (or other components) of device 2500, etc.

[0063] In some embodiments, device 2500 includes one or more voltage regulator circuits, generally referred to as voltage regulators (VRs) 2514, having high-bandwidth and low-power differential-to-single-ended Type III compensators. VRs 2514 generate signals at appropriate voltage levels that can be provided to operate any appropriate components of device 2500. By way of example only, VRs 2514 are shown providing signals to processor 2504 of device 2500. In some embodiments, VRs 2514 receive one or more voltage identification (VID) signals and generate voltage signals at appropriate levels based on the VID signals. Various types of VRs can be used for VRs 2514. For example, VRs 2514 can include "buck" VRs, "boost" VRs, combinations of buck and boost VRs, low-dropout (LDO) regulators, switching DC-DC regulators, etc. Buck VRs are typically used in power delivery applications that require converting an input voltage to an output voltage by a ratio less than one. Boost VRs are commonly used in power delivery applications that require an input voltage to be converted to an output voltage by a ratio greater than one. In some embodiments, each processor core has its own VR, which is controlled by the PCU 2510a / b and / or PMIC 2512. In some embodiments, each core has a distributed network of LDOs to provide efficient control for power management. The LDOs can be digital LDOs, analog LDOs, or a combination of digital and analog LDOs. The VR is an adaptive VR that can provide an adaptive voltage output as described with reference to various embodiments.

[0064] In some embodiments, device 2500 includes one or more clock generator circuits, generally referred to as clock generator 2516. Clock generator 2516 generates a clock signal at an appropriate frequency level that may be provided to any appropriate component of device 2500. By way of example only, clock generator 2516 is shown providing a clock signal to processor 2504 of device 2500. In some embodiments, clock generator 2516 receives one or more Frequency Identification (FID) signals and generates a clock signal at an appropriate frequency based on the FID signals. Clock generator 2516 is an adaptive clock source capable of providing an adaptive frequency output as described with reference to various embodiments.

[0065] In some embodiments, device 2500 includes a battery 2518 that powers various components of device 2500. By way of example only, battery 2518 is shown powering processor 2504. Although not shown, device 2500 may include charging circuitry for, for example, recharging the battery based on alternating current (AC) power received from an AC adapter.

[0066] In some embodiments, device 2500 includes a power control unit (PCU) 2510 (also referred to as a power management unit (PMU), power controller, etc.). In one example, some sections of PCU 2510 may be implemented by one or more processing cores 2508, and these sections of PCU 2510 are symbolically illustrated using dotted boxes and labeled PCU 2510a. In one example, some other sections of PCU 2510 may be implemented external to processing core(s) 2508, and these sections of PCU 2510 are symbolically illustrated using dotted boxes and labeled PCU 2510b. PCU 2510 may implement various power management operations for device 2500. PCU 2510 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) for implementing various power management operations for device 2500.

[0067] In some embodiments, device 2500 includes a power management integrated circuit (PMIC) 2512, for example, to implement various power management operations for device 2500. In some embodiments, PMIC 2512 is a reconfigurable power management IC (RPMIC) and / or IMVP (Intel® Mobile Voltage Positioning). In one example, the PMIC is in an IC chip separate from processor 2504. It may implement various power management operations for device 2500. PMIC 2512 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2500.

[0068] In one example, device 2500 includes one or both of a PCU 2510 or a PMIC 2512. In one example, either PCU 2510 or PMIC 2512 may not be present in device 2500, and therefore, these components are illustrated using dashed lines.

[0069] Various power management operations of device 2500 may be performed by PCU 2510, by PMIC 2512, or by a combination of PCU 2510 and PMIC 2512. For example, PCU 2510 and / or PMIC 2512 may select a power state (e.g., a P-state) for various components of device 2500. For example, PCU 2510 and / or PMIC 2512 may select a power state (e.g., in accordance with the Advanced Configuration and Power Interface (ACPI) specification) for various components of device 2500. By way of example only, PCU 2510 and / or PMIC 2512 may transition various components of device 2500 into a sleep state, an active state, an appropriate C-state (e.g., a C0 state or other appropriate C-state in accordance with the ACPI specification), etc. In one example, the PCU 2510 and / or the PMIC 2512 may control the voltage output by the VR 2514 (e.g., SCVR) and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In one example, the PCU 2510 and / or the PMIC 2512 may control functions related to battery power usage, charging of the battery 2518, and power saving operations.

[0070] The clock generator 2516 may include a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2504 has its own clock source. As such, each core can operate at a frequency independent of the operating frequencies of the other cores. In some embodiments, the PCU 2510 and / or PMIC 2512 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if that core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2510 and / or PMIC 2512 determines the operating conditions of each core of the processor, and when the PCU 2510 and / or PMIC 2512 determines that a core is operating below its target performance level, it opportunistically adjusts the frequency and / or power supply voltage of that core without the core's clock source (e.g., its PLL) losing lock. For example, if a core is drawing less current from the power supply rails than the total current allocated to that core or processor 2504, the PCU 2510 and / or PMIC 2512 may temporarily increase the power draw for that core or processor 2504 (e.g., by increasing the clock frequency and / or power supply voltage level) so that the core or processor 2504 can achieve a higher performance level. In this manner, the voltage and / or frequency can be temporarily increased for the processor 2504 without compromising product reliability.

[0071] In one example, the PCU 2510 and / or the PMIC 2512 may perform power management operations based, at least in part, on receiving measurements from the power measurement circuit 2542, the temperature measurement circuit 2540, the charge level of the battery 2518, and / or other suitable information that can be used for power management. To this end, the PMIC 2512 is communicatively coupled to one or more sensors to sense / detect various values / variations in one or more factors that have an impact on the power / thermal behavior of the system / platform. Examples of the one or more factors include current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity to (and / or in thermal contact / coupled with) one or more components or logic / IP blocks of the computing system. Additionally, in at least one embodiment, coupling one or more sensors directly to the PCU2510 and / or PMIC2512 may enable the PCU2510 and / or PMIC2512 to manage processor core energy based at least in part on the value(s) detected by one or more of those sensors.

[0072] An example software stack for device 2500 is also illustrated (although not all elements of the software stack are shown). By way of example only, processor 2504 may execute application program 2550, operating system 2552, one or more power management (PM) application programs (e.g., generally referred to as PM applications 2558), and / or the like. PM applications 2558 may also be executed by PCU 2510 and / or PMIC 2512. OS 2552 may also include one or more PM applications 2556a, 2556b, 2556c. OS 2552 may also include various drivers 2554a, 2554b, 2554c, etc., some of which may be specific to power management purposes. In some embodiments, device 2500 may further include basic input / output system (BIOS) 2520. The BIOS 2520 may communicate with the OS 2552 (eg, via one or more drivers 2554), communicate with the processor 2504, and so on.

[0073] For example, one or more of PM applications 2558, 2556, drivers 2554, BIOS 2520, etc. may be used to implement power management tasks, such as, for example, to control the voltage and / or frequency of various components of device 2500, to control the wake-up state, sleep state, and / or other suitable power state of various components of device 2500, to control battery power usage, charging of battery 2518, functions related to power saving operations, etc.

[0074] References in the specification to "one embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or feature described in connection with those embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "one embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, feature, structure, or feature "may," "could," or "can" be included, that particular component, feature, structure, or feature need not be included. When the specification or claims refer to an element with "a" or "an," it does not mean that there is only one of that element. When the specification or claims refer to an element with "an additional," it does not exclude there being more than one of that additional element.

[0075] Furthermore, particular features, structures, functions, or characteristics may be combined as desired in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0076] While the disclosure has been described with respect to specific embodiments thereof, numerous modifications, variations, and variations of these embodiments will become apparent to those skilled in the art in light of the foregoing description. The disclosed embodiments are intended to encompass all such modifications, variations, and variations that fall within the broad scope of the appended claims.

[0077] Additionally, for ease of illustration and description, and to avoid obscuring the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Also, configurations may be shown in block diagram form to avoid obscuring the disclosure and in light of the fact that details regarding the implementation of such block diagram configurations will depend heavily on the platform in which the disclosure will be implemented (i.e., such details should be well within the purview of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe example embodiments of the disclosure, it will be apparent to one skilled in the art that the disclosure may be practiced without those specific details or with variations thereon. This description is therefore to be regarded as illustrative and not limiting.

[0078] To illustrate various embodiments, the following examples are provided, which may be dependent upon one another as appropriate.

[0079] Example 1. An apparatus comprising: a multiplexer controllable to select one of scan data or data as an output; a tri-state inverter coupled to the output of the multiplexer, the tri-state inverter controllable by a clock and an inverse of the clock, the clock and the inverse of the clock routed on a poly line aligned between a p-type active region and an n-type active region; a first memory coupled to the output of the tri-state inverter; a pass gate coupled to the first memory, the pass gate controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; and an inverter coupled to the output of the second memory.

[0080] Example 2. The apparatus of Example 1, wherein the inverter is a first inverter and the first memory includes a second inverter, the second inverter having legs spanning at least two devices such that each leg is a leg of a minimum device size.

[0081] Example 3. The apparatus of Example 2, wherein the tri-state inverter is a first tri-state inverter, and the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inverse of the clock.

[0082] Example 4. The apparatus of example 1, wherein the tri-state inverter is directly coupled to the output of the multiplexer.

[0083] Example 5. The apparatus of example 1, wherein the multiplexer is controllable by a scan select.

[0084] Example 6. The apparatus of example 1, wherein the second memory includes a third tri-state inverter coupled to a third inverter.

[0085] Example 7. An apparatus comprising: a pair of inverters providing a clock and an inverse of the clock; a plurality of flip-flops each coupled to the pair of inverters, each of the plurality of flip-flops being a tri-state inverter controllable by the clock and the inverse of the clock, the clock and the inverse of the clock being routed on poly lines aligned between p-type and n-type active regions; a first memory coupled to the output of the tri-state inverter; a pass gate coupled to the first memory, the pass gate controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; and an inverter coupled to the output of the second memory.

[0086] Example 8. The apparatus of Example 7, wherein the inverter is a first inverter and the first memory includes a second inverter, the second inverter having legs spanning at least two devices such that each leg is a leg of a minimum device size.

[0087] Example 9. The apparatus of Example 8, wherein the tri-state inverter is a first tri-state inverter, and the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inverse of the clock.

[0088] Example 10. The apparatus of example 7, wherein the tri-state inverter is directly coupled to the output of the multiplexer.

[0089] Example 11. The apparatus of Example 7, wherein the second memory includes a third tri-state inverter coupled to a third inverter.

[0090] Example 12. A device comprising: a tri-state inverter controllable by a clock and an inverse of the clock; a first memory coupled to an output of the tri-state inverter, the first memory having a uniform layout and no notches in a diffusion region associated with the first memory; a pass gate coupled to the first memory, the pass gate controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; and an inverter coupled to an output of the second memory.

[0091] Example 13. The device of Example 12, wherein the clock and the inverse of the clock are routed on poly lines aligned between p-type and n-type active regions.

[0092] Example 14. The apparatus of Example 12, wherein the inverter is a first inverter and the first memory includes a second inverter, the second inverter having legs spanning at least two devices such that each leg is a leg of a minimum device size.

[0093] Example 15. The apparatus of any one of Examples 12-14, wherein the tri-state inverter is a first tri-state inverter, and the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inverse of the clock.

[0094] Example 16. A system having a memory; a processor coupled to the memory, the processor including a flip-flop having: a tri-state inverter coupled to an output of a multiplexer, the tri-state inverter controllable by a clock and an inverse of the clock; a first memory coupled to the output of the tri-state inverter, the first memory having a uniform layout and no notches in a diffusion region associated with the first memory; a pass gate coupled to the first memory, the pass gate controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; and an inverter coupled to the output of the second memory; and a wireless interface that enables the processor to communicate with another device.

[0095] Example 17. The system of Example 16, wherein the clock and the inverse of the clock are routed on poly lines aligned between p-type and n-type active regions.

[0096] Example 18. The system of Example 16, wherein the inverter is a first inverter and the first memory includes a second inverter, the second inverter having legs spanning at least two devices such that each leg is a leg of a minimum device size.

[0097] Example 19. The system of Example 16, wherein the tri-state inverter is a first tri-state inverter, and the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inverse of the clock.

[0098] Example 20. The system of example 16, wherein the FF has a multiplexer controllable to select one of the scan data or the data as output.

[0099] An Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. a multiplexer controllable to select either the scan data or the data as an output; a first tri-state inverter coupled to the output of the multiplexer, the first tri-state inverter being controllable by a clock and an inverse of the clock, the clock and the inverse of the clock being routed on poly lines aligned along a first direction between p-type and n-type active regions; a first memory coupled to the output of the first tri-state inverter; a pass gate coupled to the first memory, the pass gate being controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; a first inverter coupled to an output of the second memory; and source / drain diffusion regions of all transistors included in the first tri-state inverter, the first memory, and the pass gate have the same width along the first direction; the first memory includes a second inverter, the second inverter including at least two transistors electrically connected in parallel to each other and not aligned with each other in the first direction; Device.

2. The device described in claim 1, wherein the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, and the second tri-state inverter is controllable by the clock and the inversion of the clock.

3. 3. The apparatus of claim 1, wherein the first tri-state inverter is directly coupled to the output of the multiplexer.

4. 4. The apparatus of claim 1, wherein the multiplexer is controllable by a scan select.

5. The apparatus of claim 1 , wherein the second memory includes a third tri-state inverter coupled to a third inverter.

6. a pair of inverters providing a clock and an inverse of the clock; a plurality of flip-flops, each coupled to the pair of inverters, each of the plurality of flip-flops comprising: a first tri-state inverter controllable by the clock and the inverse of the clock, the clock and the inverse of the clock being routed on poly lines aligned along a first direction between p-type and n-type active regions; a first memory coupled to the output of the first tri-state inverter; a pass gate coupled to the first memory, the pass gate being controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; a first inverter coupled to an output of the second memory; a plurality of flip-flops, and source / drain diffusion regions of all transistors included in the first tri-state inverter, the first memory, and the pass gate have the same width along the first direction; the first memory includes a second inverter, the second inverter including at least two transistors electrically connected in parallel to each other and not aligned with each other in the first direction; Device.

7. The device described in claim 6, wherein the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, and the second tri-state inverter is controllable by the clock and the inversion of the clock.

8. 8. The apparatus of claim 6 or 7, wherein the first tri-state inverter is directly coupled to the output of a multiplexer controllable to select one of scan data or data as an output.

9. 9. The apparatus of claim 6, wherein the second memory includes a third tri-state inverter coupled to a third inverter.

10. a first tri-state inverter controllable by a clock and an inverse of the clock, the clock and the inverse of the clock being routed on a poly line aligned along a first direction between a p-type active region and an n-type active region; a first memory coupled to the output of the first tri-state inverter; a pass gate coupled to the first memory, the pass gate being controllable by the clock and the inverse of the clock; a second memory coupled to the pass gate; a first inverter coupled to an output of the second memory; and source / drain diffusion regions of all transistors included in the first tri-state inverter, the first memory, and the pass gate have the same width along the first direction; the first memory includes a second inverter, the second inverter including at least two transistors electrically connected in parallel to each other and not aligned with each other in the first direction; Device.

11. The device described in claim 10, wherein the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inversion of the clock.

12. Memory and a processor coupled to said memory, said processor including a flip-flop having the device of any one of claims 1 to 5; a wireless interface that enables the processor to communicate with another device; A system having:

13. Memory and a processor coupled to said memory, said processor including a flip-flop having the device of any one of claims 6 to 9; a wireless interface that enables the processor to communicate with another device; A system having:

14. Memory and a processor coupled to said memory, said processor including a flip-flop having the device of claim 10 or 11; a wireless interface that enables the processor to communicate with another device; A system having:

15. controlling a multiplexer to select one of the scan data or the data as an output; controlling a first tri-state inverter coupled to the output of the multiplexer by a clock and an inverse of the clock, the clock and the inverse of the clock being routed on a poly line aligned along a first direction between a p-type active region and an n-type active region; providing an output of the first tri-state inverter to a first memory; controlling a pass gate coupled to the first memory by the clock and the inverse of the clock; providing an output of the pass gate to a second memory; providing an output of the second memory to a first inverter; Having that, source / drain diffusion regions of all transistors included in the first tri-state inverter, the first memory, and the pass gate have the same width along the first direction; the first memory includes a second inverter, the second inverter including at least two transistors electrically connected in parallel to each other and not aligned with each other in the first direction; method.

16. The method of claim 15, wherein the first memory includes a second tri-state inverter coupled to the second inverter and the first tri-state inverter, the second tri-state inverter being controllable by the clock and the inversion of the clock.

17. 17. The method of claim 15 or 16, wherein the first tri-state inverter is directly coupled to the output of the multiplexer.

18. 18. The method of any one of claims 15 to 17, wherein the multiplexer is controllable by a scan select.

19. 19. The method of claim 15, wherein the second memory includes a third tri-state inverter coupled to a third inverter.

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