Solid-state imaging device, manufacturing method, and electronic device

Abstract

The present disclosure pertains to a solid-state imaging element with which it is possible to manufacture better goods, a manufacturing method, and an electronic instrument. On a first semiconductor substrate, apart from a dedicated pad used for inspection in the manufacturing process, a first pad used for connection to the outside is provided, and on a second semiconductor substrate, a second pad used for inspection in the manufacturing process is provided. After inspection to guarantee KGD for each of the first semiconductor substrate and the second semiconductor substrate is performed, when the first semiconductor substrate and the second semiconductor substrate are stacked in chip units, the first pad is electrically connected to the second pad via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. The present invention can be applied, for example, to a stacked CMOS image sensor.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device, a manufacturing method, and an electronic device, and more particularly to a solid-state imaging device, a manufacturing method, and an electronic device that enable the manufacturing of better quality products. [Background technology]

[0002] 2. Description of the Related Art Conventionally, in a solid-state imaging device having a stacked structure in which a plurality of semiconductor substrates are stacked, pads made of aluminum or the like are provided for electrical connection to the outside.

[0003] For example, Patent Document 1 discloses a solid-state imaging element with a three-layer structure, showing a structure in which pads are arranged on the first and third layers, or a structure in which pads are arranged on the second and third layers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 186192 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventionally, a manufacturing method has been adopted in which each semiconductor substrate is inspected to ensure KGD (Known Good Die) before being stacked, and only non-defective products are bonded together, but for example, some semiconductor substrates do not have inspection pads. Therefore, KGD inspection cannot be performed on such semiconductor substrates, and there has been a demand for a method to manufacture better quality products.

[0006] The present disclosure has been made in view of such circumstances, and aims to enable the production of better quality products. [Means for solving the problem]

[0007] A solid-state imaging device according to one aspect of the present disclosure comprises a first semiconductor substrate on which a first pad used for connection to the outside is provided, in addition to a dedicated pad used for inspection during the manufacturing process, and a second semiconductor substrate on which a second pad used for inspection during the manufacturing process is provided, and the first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate.

[0008] A manufacturing method according to one aspect of the present disclosure is a method for manufacturing a solid-state imaging device that includes a first semiconductor substrate on which a first pad used for connection to the outside is provided, in addition to a dedicated pad used for inspection during the manufacturing process, and a second semiconductor substrate on which a second pad used for inspection during the manufacturing process is provided, and includes a step of electrically connecting the first pad and the second pad via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate.

[0009] An electronic device according to one aspect of the present disclosure has a first semiconductor substrate on which a first pad used for connection to the outside is provided, in addition to a dedicated pad used for inspection during the manufacturing process, and a second semiconductor substrate on which a second pad used for inspection during the manufacturing process is provided, and the electronic device is equipped with a solid-state imaging element in which the first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate.

[0010] In one aspect of the present disclosure, a first semiconductor substrate is provided with a first pad used for connection to an external device, separate from a dedicated pad used for testing during the manufacturing process, and a second semiconductor substrate is provided with a second pad used for testing during the manufacturing process, and the first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration example of a first embodiment of a solid-state imaging device to which the present technology is applied. [Figure 2] FIG. 1 is a diagram illustrating an example of the overall planar configuration of a solid-state imaging device. [Figure 3] 1A to 1C are diagrams illustrating a method for manufacturing a solid-state imaging device. [Figure 4] FIG. 10 is a block diagram showing a configuration example of a second embodiment of a solid-state imaging device to which the present technology is applied. [Figure 5] FIG. 1 is a block diagram illustrating an example of the configuration of an imaging device. [Figure 6] FIG. 1 is a diagram illustrating an example of use of an image sensor. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0013] <First Configuration Example of Solid-State Imaging Device> FIG. 1 is a diagram showing a configuration example of a first embodiment of a solid-state imaging device to which the present technology is applied.

[0014] 1 is a semiconductor device (e.g., a CMOS (Complementary Metal Oxide Semiconductor) image sensor) having a two-layer structure in which a sensor chip 12, which is a first semiconductor substrate, and a logic chip 13, which is a second semiconductor substrate, are stacked. Fig. 1 shows an example of a partial cross-sectional configuration of a junction portion that electrically connects the sensor chip 12 and the logic chip 13.

[0015] The sensor chip 12 is provided with, for example, a plurality of pixels (not shown) for the solid-state imaging element 11 to capture an image, as well as aluminum pads 21 and contact electrodes 22.

[0016] The aluminum pad 21 is used for wire bonding to electrically connect the solid-state imaging element 11 to the outside, and an opening 23 is formed in the sensor chip 12 so as to expose the aluminum pad 21. When the sensor chip 12 is dug to form the opening 23, a recess 24 corresponding to the shape of the opening 23 is formed in the aluminum pad 21. The recess 24 has a depth sufficient to remove the barrier metal of the aluminum pad 21, for example.

[0017] The contact electrodes 22 are electrodes for electrically connecting the aluminum pad 21 to the logic chip 13, and are provided at multiple locations (12 locations in the example shown in FIG. 1) on the outer periphery of the aluminum pad 21, which is outside the opening 23. For example, the contact electrodes 22 have an exposed surface on the surface of the sensor chip 12 that will be bonded to the logic chip 13, and are formed by filling a trench dug from the exposed surface to the aluminum pad 21 with a conductive material (for example, Cu).

[0018] The logic chip 13 is provided with, for example, a logic circuit (not shown) for performing the signal processing required for the solid-state imaging element 11 to perform imaging, as well as aluminum pads 31, contact electrodes 32, dummy patterns 33, and an I / O circuit 34.

[0019] The aluminum pad 31 is used for testing to ensure KGD for the logic chip 13. For example, during the testing, an opening is formed to make an electrical connection to the aluminum pad 31, and after the testing, the opening is backfilled to form a backfilled portion 35. Furthermore, when the logic chip 13 is dug to form an opening (not shown), a recess 36 corresponding to the shape of the opening is formed in the aluminum pad 31.

[0020] The aluminum pad 31 is also used for electrical connection with the sensor chip 12. For example, the aluminum pad 31 has an opening region formed in a plan view so as to correspond to the opening 23 formed in the sensor chip 12, and contact electrodes 32 are connected to a plurality of locations (12 locations in the example shown in FIG. 1) around the periphery of the opening region.

[0021] The contact electrodes 32 are electrodes for electrically connecting the aluminum pads 31 to the sensor chip 12, and are provided at a plurality of locations corresponding to the contact electrodes 22 of the sensor chip 12. For example, the contact electrodes 32 are formed from the same material as the contact electrodes 22, and are electrically and mechanically connected to each other by bonding the same materials together on their exposed surfaces (Cu-Cu direct bonding).

[0022] The dummy pattern 33 is made of the same aluminum material as the aluminum pad 31 so as to partially fill the opening area (i.e., the area corresponding to the opening 23 of the sensor chip 12) formed in the aluminum pad 31. For example, the dummy pattern 33 is not electrically connected and does not function as a wiring.

[0023] The I / O circuit 34 is a semiconductor circuit configured with transistors, wiring, etc. for controlling the input and output of signals to and from the solid-state imaging element 11. For example, the I / O circuit 34 is disposed in a position other than the area corresponding to the opening 23 of the sensor chip 12, and in the example shown in Fig. 1, is disposed so as to overlap the area where the recess 36 is formed in the aluminum pad 31 in plan view. In other words, it is preferable to dispose the I / O circuit 34 so as not to be directly below the wire bonding performed on the aluminum pad 21.

[0024] The solid-state imaging element 11 has a structure in which the aluminum pad 21 of the sensor chip 12 and the aluminum pad 31 of the logic chip 13 are connected by direct Cu-Cu bonding between the contact electrodes 22 and 32, but bump bonding via solder may also be used.

[0025] FIG. 2 shows an example of the overall planar configuration of the solid-state imaging device 11.

[0026] 2, the solid-state imaging element 11 is configured such that a plurality of aluminum pads 21 provided along the outer periphery of the sensor chip 12 and a plurality of aluminum pads 31 provided along the outer periphery of the logic chip 13 are arranged in corresponding positions. In other words, the solid-state imaging element 11 is configured such that when the sensor chip 12 and the logic chip 13 are aligned and bonded on a chip-by-chip basis, the aluminum pads 21 and the aluminum pads 31 are bonded as shown in FIG.

[0027] A pixel region 41 in which a plurality of pixels are arranged in an array is provided in the center of the sensor chip 12, and a plurality of KGD dedicated pads 42 are provided near the pixel region 41. After an inspection to assure KGD of the sensor chip 12 is performed, the openings of the KGD dedicated pads 42 are backfilled.

[0028] The solid-state imaging device 11 is configured in this manner, and KGD inspection is performed on the sensor chip 12 using dedicated KGD pads 42, and KGD inspection is performed on the logic chip 13 using aluminum pads 31. Then, sensor chips 12 and logic chips 13 that have passed inspection are selected, and bonding is performed on a chip-by-chip basis using contact electrodes 22 and contact electrodes 32. By inspecting both the sensor chip 12 and the logic chip 13 for KGD in this manner, it becomes possible to manufacture solid-state imaging devices 11 that are of better quality than ever before.

[0029] In the solid-state imaging element 11, by providing the aluminum pads 21 for connection to the outside on the sensor chip 12, the depth of the openings 23 can be made shallower than in a configuration in which the aluminum pads for connection to the outside are provided on the second or third layer, for example. This allows the solid-state imaging element 11 to have a structure that allows wire bonding to the aluminum pads 21 to be easily performed.

[0030] In the solid-state imaging element 11, the opening 23 that exposes the aluminum pad 21 of the sensor chip 12 and the backfilled portion 35 of the logic chip 13 (i.e., the opening during KGD inspection of the logic chip 13) are arranged so as not to overlap in a planar view. For example, the solid-state imaging element 11 is configured so that the opening 23 and the backfilled portion 35 are adjacent to each other in a planar view. This allows the solid-state imaging element 11 to reduce, for example, parasitic resistance and parasitic capacitance.

[0031] The solid-state imaging element 11 is laid out so that the I / O circuit 34 is positioned so as not to overlap the opening 23 when viewed in plan, for example, so as to overlap the backfilled portion 35 adjacent to the opening 23. This prevents the I / O circuit 34 from being affected by wire bonding to the aluminum pad 21, and prevents damage to the I / O circuit 34.

[0032] The solid-state imaging element 11 has a layout in which a dummy pattern 33 is arranged in an opening region formed in the aluminum pad 31 so that, in a plan view, an area overlapping the opening 23 is open. By providing the dummy pattern 33 directly below the opening 23 in this way, the solid-state imaging element 11 can improve wire bond resistance compared to a structure in which the dummy pattern 33 is not provided, and it becomes possible to manufacture a better product.

[0033] <Method of manufacturing a solid-state imaging device> A method for manufacturing the solid-state imaging device 11 will be described with reference to FIG.

[0034] In the first step, as shown in the first row of FIG. 3, aluminum pads 31 and dummy patterns 33 are formed on the wiring layer of the logic chip 13.

[0035] 3, in the second step, the wiring layer of the logic chip 13 is dug to form an opening 37 for KGD, thereby partially opening the aluminum pad 31. At this time, as the opening 37 is dug, a recess 36 is formed in the aluminum pad 31. Then, the aluminum pad 31 is used to perform a KGD inspection on the logic chip 13.

[0036] For example, if the logic chip 13 is determined to be a non-defective product as a result of the KGD inspection, in the third step, an insulating material similar to the interlayer film of the wiring layer is backfilled into the opening 37 to form a backfilled portion 35, as shown in the third row of Figure 3. Furthermore, to form a contact electrode 32, a trench is dug and filled with a conductive material.

[0037] 3, in the fourth step, the sensor chip 12, on which aluminum pads 21 and contact electrodes 22 have been formed and KGD inspection has been carried out in a separate process from the logic chip 13, is stacked chip by chip on the logic chip 13. At this time, the contact electrodes 22 and contact electrodes 32 are directly bonded to each other by Cu-Cu, thereby electrically and mechanically connecting the sensor chip 12 and the logic chip 13.

[0038] Thereafter, for example, a process is performed in which the wiring layer of the sensor chip 12 is dug to form an opening 23 for wire bonding, and the aluminum pad 21 is partially opened, and the solid-state imaging element 11 is manufactured.

[0039] By using the manufacturing method described above, a better quality solid-state imaging device 11 can be manufactured.

[0040] <Second Configuration Example of Solid-State Imaging Device> Fig. 4 is a diagram showing a configuration example of a second embodiment of a solid-state imaging device to which the present technology is applied. In the solid-state imaging device 11A shown in Fig. 4, components common to those of the solid-state imaging device 11 in Fig. 1 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0041] 4, the solid-state imaging device 11A is a semiconductor device having a three-layer structure in which a sensor chip 12, which is a first semiconductor substrate, a logic chip 13A, which is a second semiconductor substrate, and a memory chip 14, which is a third semiconductor substrate, are stacked. Fig. 4 shows an example of a partial cross-sectional configuration of a joint portion that electrically joins the sensor chip 12, the logic chip 13A, and the memory chip 14.

[0042] 4, in logic chip 13A, backfilled portion 35A is formed on the memory chip 14 side, and accordingly, recessed portion 36A is formed on aluminum pad 31A on the logic chip 13A side. Also, two-tiered contact electrodes 38 and 39 for electrical connection with memory chip 14 are formed in multiple locations on logic chip 13A, and contact electrode 39 has an exposed surface that is exposed on the surface of logic chip 13A on the memory chip 14 side.

[0043] The memory chip 14 is provided with, for example, a memory (not shown) that temporarily stores pixel data acquired by the sensor chip 12, as well as aluminum pads 51, contact electrodes 52, and an I / O circuit 53.

[0044] The aluminum pad 51 is used for testing to ensure KGD for the memory chip 14. For example, during the testing, an opening is formed to make an electrical connection to the aluminum pad 51, and after the testing, the opening is backfilled to form a backfilled portion 54. When the memory chip 14 is dug to form an opening (not shown), a recess 55 corresponding to the shape of the opening is formed in the aluminum pad 51.

[0045] The aluminum pad 51 is also used for electrical connection with the logic chip 13A. For example, contact electrodes 52 are connected to the aluminum pad 51 at a plurality of locations so as to correspond to the contact electrodes 39 of the logic chip 13A in plan view.

[0046] Contact electrodes 52 are electrodes for electrically connecting memory chip 14 to logic chip 13A, and electrical and mechanical bonding is achieved by utilizing bonding between the same materials (Cu-Cu direct bonding) on the respective exposed surfaces.

[0047] The I / O circuit 53 is a circuit configured with transistors and wiring for controlling input and output of signals to and from the solid-state imaging device 11A, and is preferably arranged so as not to be directly below the wire bonding performed on the aluminum pad 21.

[0048] The solid-state imaging device 11A is configured as described above, and like the solid-state imaging device 11, a better quality product can be manufactured.

[0049] <Example of electronic device configuration> The solid-state imaging device 11 as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0050] FIG. 5 is a block diagram showing an example of the configuration of an imaging device mounted on an electronic device.

[0051] As shown in FIG. 5, the imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

[0052] The optical system 102 is configured to have one or more lenses, and guides image light (incident light) from a subject to the image sensor 103, forming an image on the light receiving surface (sensor section) of the image sensor 103.

[0053] The above-described solid-state image sensor 11 is applied as the image sensor 103. Electrons are accumulated in the image sensor 103 for a certain period of time in accordance with an image formed on the light receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to a signal processing circuit 104.

[0054] The signal processing circuit 104 performs various types of signal processing on the pixel signals output from the image sensor 103. The image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 to be displayed, or supplied to a memory 106 to be stored (recorded).

[0055] In the imaging device 101 configured in this manner, by applying the above-described solid-state imaging element 11, for example, a better quality solid-state imaging element 11 can be used, and images can be captured reliably.

[0056] <Examples of using image sensors> FIG. 6 is a diagram showing an example of using the image sensor (imaging element) described above.

[0057] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0058] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as in-vehicle sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognizing the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Security devices such as surveillance cameras for crime prevention and cameras for person authentication Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports purposes Agricultural equipment such as cameras for monitoring the condition of fields and crops

[0059] <Configuration combination example> The present technology can also be configured as follows. (1) a first semiconductor substrate provided with a first pad used for connection to an external device, separate from a dedicated pad used for testing in a manufacturing process; a second semiconductor substrate provided with a second pad used for testing in the manufacturing process; Equipped with The first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. Solid-state imaging element. (2) After an inspection is performed to ensure that the first semiconductor substrate and the second semiconductor substrate are KGD (Known Good Die), the first semiconductor substrate and the second semiconductor substrate are stacked on each other in chip units. The solid-state imaging device according to (1) above. (3) an opening for connecting the first pad to an external device is provided in the first semiconductor substrate; the second semiconductor substrate is provided with a backfilled portion that backfills a portion that was opened during testing using the second pad, The opening and the backfilled portion are disposed at positions where they do not overlap each other in a plan view. The solid-state imaging device according to (1) or (2) above. (4) an opening region is formed in the second pad, the opening region being open in a range that overlaps with the opening when viewed in a plane; A dummy pattern is provided in which the opening is partially filled with the same material as the second pad. The solid-state imaging device according to (3) above. (5) a semiconductor circuit for controlling input and output of signals is provided on the second semiconductor substrate; The semiconductor circuit is disposed at a position that does not overlap with the opening in a plan view. The solid-state imaging device according to (3) or (4) above. (6) The semiconductor circuit is disposed at a position overlapping the backfilled portion in a plan view. The solid-state imaging device according to (5) above. (7) The first electrode and the second electrode are electrically and mechanically connected by using a joint between the same materials. The solid-state imaging device according to any one of (1) to (6) above. (8) a third semiconductor substrate provided with a third pad used for testing in the manufacturing process; The second pad and the third pad are electrically connected via a second electrode provided on the second semiconductor substrate and a third electrode provided on the third semiconductor substrate. The solid-state imaging device according to any one of (1) to (7) above. (9) A method for manufacturing a solid-state imaging device including a first semiconductor substrate provided with first pads used for connection to an external device in addition to dedicated pads used for inspection in a manufacturing process, and a second semiconductor substrate provided with second pads used for inspection in a manufacturing process, a step of electrically connecting the first pad and the second pad via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate; A manufacturing method comprising: (10) a first semiconductor substrate provided with a first pad used for connection to an external device, separate from a dedicated pad used for testing in a manufacturing process; a second semiconductor substrate provided with a second pad used for testing in the manufacturing process; and The first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. An electronic device equipped with a solid-state imaging device.

[0060] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained. [Explanation of symbols]

[0061] 11 solid-state imaging element, 12 sensor chip, 13 logic chip, 14 memory chip, 21 aluminum pad, 22 contact electrode, 23 opening, 24 recess, 31 aluminum pad, 32 contact electrode, 33 dummy pattern, 34 I / O circuit, 35 backfilled portion, 36 recess, 37 opening, 38 and 39 contact electrodes, 41 pixel area, 42 dedicated pad for KGD, 51 aluminum pad, 52 contact electrode, 53 I / O circuit, 54 backfilled portion, 55 recess

Claims

1. a first semiconductor substrate provided with a first pad used for connection to an external device, separate from a dedicated pad used for testing in a manufacturing process; a second semiconductor substrate provided with a second pad used for testing in the manufacturing process; Equipped with The first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. Solid-state imaging element.

2. an opening for connecting the first pad to an external device is provided in the first semiconductor substrate; the second semiconductor substrate is provided with a backfilled portion that backfills a portion where the second semiconductor substrate has been dug so that the second pad is exposed during testing using the second pad; The opening and the backfilled portion are disposed at positions where they do not overlap each other in a plan view. The solid-state imaging device according to claim 1 .

3. an opening region is formed in the second pad, the opening region being open in a range that overlaps with the opening when viewed from above; A dummy pattern is provided in which the opening is partially filled with the same material as the second pad. The solid-state imaging device according to claim 2 .

4. a semiconductor circuit for controlling input and output of signals is provided on the second semiconductor substrate; The semiconductor circuit is disposed at a position that does not overlap with the opening in a plan view. The solid-state imaging device according to claim 2 .

5. The semiconductor circuit is disposed at a position overlapping the backfilled portion in a plan view.

5. The solid-state imaging device according to claim 4.

6. The first electrode and the second electrode are electrically and mechanically connected by using a joint between the same materials. The solid-state imaging device according to claim 1 .

7. a third semiconductor substrate provided with a third pad used for testing in the manufacturing process; The second pad and the third pad are electrically connected via a fourth electrode provided separately from the second electrode on the second semiconductor substrate and a third electrode provided on the third semiconductor substrate. The solid-state imaging device according to claim 1 .

8. A method for manufacturing a solid-state imaging device including a first semiconductor substrate provided with first pads used for connection to an external device in addition to dedicated pads used for inspection in a manufacturing process, and a second semiconductor substrate provided with second pads used for inspection in a manufacturing process, a step of electrically connecting the first pad and the second pad via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate; A manufacturing method comprising:

9. After an inspection is performed to ensure that each of the first semiconductor substrate and the second semiconductor substrate is a known good die (KGD), the first semiconductor substrate and the second semiconductor substrate are stacked on each other in chip units. The method of claim 8.

10. a first semiconductor substrate provided with a first pad used for connection to an external device, separate from a dedicated pad used for testing in a manufacturing process; a second semiconductor substrate provided with a second pad used for testing in the manufacturing process; and The first pad and the second pad are electrically connected via a first electrode provided on the first semiconductor substrate and a second electrode provided on the second semiconductor substrate. An electronic device equipped with a solid-state imaging device.

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