Semiconductor Devices

Abstract

To provide a semiconductor device with smaller variation in transistor characteristic.SOLUTION: A memory device 202 includes a transistor 200 and a capacitor element 201. The transistor includes an oxide 230. An insulator 211, an insulator 212, an insulator 214, an insulator 280, an insulator 282, an insulator 283, an insulator 284, and an insulator 274 function as interlayer films. Additionally, a conductor 240a, a conductor 240b, and a conductor 240c that are electrically connected to the transistor and function as a plug are provided. Moreover, an insulator 241a, an insulator 241b, and an insulator 241c are provided in contact with a side surface of the conductor functioning as the plug. Furthermore, a conductor 246a and a conductor 246b that are electrically connected to the conductors and function as wires are provided on the insulator 274 and a conductor 240. An insulator 286 is provided on the conductor 246 and the insulator 274.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU has a semiconductor integrated circuit (including at least transistors and memories) separated from a semiconductor wafer, and has multiple semiconductor elements on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor integrated circuits (IC chips) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0006] In addition, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current in a non-conducting state. For example, a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 1). Also, for example, a memory device that can retain data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, first and second conductors, and first to third insulators, in which the transistor and the first conductor are disposed over the first insulator, the transistor includes an oxide semiconductor, the second insulator is disposed over the transistor, the first conductor has a region that does not overlap with the second insulator, the third insulator is disposed to cover the first conductor, the transistor, and the second insulator, and the second conductor is disposed over the third insulator and at least a portion of the second conductor overlaps with the first conductor.

[0013] Another embodiment of the present invention includes first and second oxides, first to sixth conductors, and first to sixth insulators, in which the first conductor is disposed over the first insulator, the second insulator is disposed over the first conductor, the first oxide is disposed over the second insulator, the second conductor and a third conductor are disposed over the first oxide, the third insulator is disposed over the second conductor and the third conductor, and the second oxide is disposed over the first oxide. a fourth insulator is disposed on the second oxide, the fourth conductor is disposed on the fourth insulator, a fifth conductor is disposed on the first insulator and has an area that does not overlap with the third insulator, the fifth insulator is disposed covering the second insulator, the third insulator, and the fifth conductor, and a sixth conductor is disposed on the fifth insulator and at least a portion of the sixth conductor overlaps with the fifth conductor.

[0014] In the above, it is preferable that the fifth insulator contacts the first insulator in a region that does not overlap with the second insulator, the third insulator, and the fifth conductor, and that at least a portion of the sixth conductor overlaps with a region where the fifth insulator contacts the first insulator. Also, in the above, it is preferable that the height of the upper surface of the sixth conductor and the height of the upper surface of the region of the fifth insulator that overlaps with the second insulator are approximately the same.

[0015] In the above, the fifth insulator preferably contacts the side surface of the third insulator, the side surface of the second insulator, and the top surface and side surface of the fifth conductor. Also, in the above, the first insulator and the fifth insulator are preferably nitrides containing silicon. Also, in the above, the fifth insulator preferably has a stacked structure.

[0016] In the above, it is preferable that the height of the upper surface of the third insulator, the height of the upper surface of the second oxide, the height of the upper surface of the fourth insulator, and the height of the upper surface of the fourth conductor are approximately the same.

[0017] In the above, it is preferable that at least a portion of the fifth conductor overlaps with the third insulator.

[0018] In the above, it is preferable that the first conductor and the fifth conductor are integrated into an island shape.

[0019] In the above, it is preferable that the fifth conductor does not overlap the third insulator, and that the fifth insulator contacts one side surface of the fifth conductor and also contacts a side surface opposite to the one side surface.

[0020] In the above, it is preferable that the third conductor is electrically connected to the sixth conductor.

[0021] In the above, it is preferable that an opening reaching the fifth conductor is formed in the second insulator and the first oxide, and the third conductor is in contact with the fifth conductor through the opening. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0024] [Figure 1]1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] 2A and 2B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] 3A and 3B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4A is a diagram explaining the classification of IGZO crystal structures, Figure 4B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 4C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 5] 5A and 5B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A and 6B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A and 7B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A and 8B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A and 9B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A and 10B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A and 11B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12]12A and 12B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A and 13B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A and 14B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A and 15B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A and 16B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A and 17B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A and 18B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A and 19B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A and 20B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A and 21B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A and 22B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A and 23B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A and 24B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A and 25B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A and 26B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A and 27B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 30 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 32] 32A and 32B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 33] 33A to 33C are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 34] FIG. 34 is a diagram showing various storage devices by hierarchy. [Figure 35] 35A and 35B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 36] 36A and 36B are diagrams illustrating an example of an electronic component. [Figure 37] 37A to 37E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 38] 38A to 38H are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatching pattern may be used and no particular symbols may be assigned.

[0027] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0028] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0029] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] For example, if it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0032] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0033] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0035] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0036] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0037] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0038] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0039] In this specification and the like, silicon oxynitride is a substance whose composition contains more oxygen than nitrogen, and silicon nitride oxide is a substance whose composition contains more nitrogen than oxygen.

[0040] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0041] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0043] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0044] (Embodiment 1) In this embodiment, an example of a semiconductor device including a memory device 202 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0045] <Configuration example of semiconductor device> The configuration of a memory device 202 including a transistor 200 and a capacitor 201 will be described using FIGS. 1A, 1B, 2A, and 2B. FIG. 1A is a top view of the memory device 202. FIGS. 1B, 2A, and 2B are cross-sectional views of the memory device 202. FIG. 1B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 2A is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 2B is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0046] A semiconductor device of one embodiment of the present invention includes an insulator 211 over a substrate (not shown), an insulator 212 over the insulator 211, an insulator 214 over the insulator 212, a transistor 200 and a capacitor 201 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 284 over the insulator 283, and an insulator 274 over the insulator 284. The transistor 200 includes an oxide 230 (oxide 230a, oxide 230b, oxide 230c, and oxide 230d). The insulators 211, 212, 214, 280, 282, 283, 284, and 274 function as interlayer films. The transistor 200 also includes a conductor 240 (conductor 240a, conductor 240b, and conductor 240c) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a, insulator 241b, and insulator 241c) is provided in contact with the side surface of the conductor 240 that functions as a plug. Further, a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as a wiring is provided on the insulator 274 and the conductor 240. Further, an insulator 286 is provided on the conductor 246 and the insulator 274.

[0047] The transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) and an oxide 230c on the oxide 230b, a conductor 242a on the oxide 243a, and a conductor 242b on the oxide 243b. The oxide 230c includes an oxide 230d on the oxide 230c, an insulator 250 on the oxide 230d, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping the oxide 230c, an insulator 272 in contact with a portion of the top surface of the insulator 224, a portion of the side surface of the oxide 230a, a portion of the side surface of the oxide 230b, a side surface of the oxide 243a, a side surface of the oxide 243b, a side surface of the conductor 242a, a top surface of the conductor 242a, a side surface of the conductor 242b, and a top surface of the conductor 242b, and an insulator 273 on the insulator 272. The insulator 280 is disposed on the insulator 273. The oxide 230c is in contact with a side surface of the oxide 243a, a side surface of the oxide 243b, a side surface of the conductor 242a, and a side surface of the conductor 242b, respectively. 1B and 2A, the height of the upper surface of the conductor 260 is arranged to be approximately the same as the height of the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the oxide 230c. Furthermore, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and the insulator 280. Furthermore, hereinafter, the conductors 242a and 242b may be collectively referred to as the conductor 242.

[0048] Openings reaching the oxide 230b are provided in the insulator 280, the insulator 273, and the insulator 272. Here, the openings may include, for example, grooves and slits. The region where the openings are formed may also be referred to as an opening. The oxide 230d, the oxide 230c, the insulator 250, and the conductor 260 are disposed within the openings. In addition, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are provided between the conductor 242a and the oxide 243a and between the conductor 242b and the oxide 243b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. In addition, in the region overlapping with oxide 230b, oxide 230c has a portion in contact with oxide 230b, a portion facing the side of conductor 260 via insulator 250, and a portion overlapping with the bottom surface of conductor 260 via insulator 250.

[0049] 1A and 1B, an opening 270 reaching the insulator 211 is formed in the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282. The opening 270 is formed to surround the transistor 200. The capacitor 201 is formed in a region inside the opening 270 that overlaps with the conductor 206 (conductor 206a and conductor 206b). Note that in this specification and the like, the space inside the opening 270 may be referred to as "inside the opening 270." Furthermore, in this specification and the like, the region surrounded by the opening 270 in a top view, such as the insulator 280 shown in FIG. 1A, may be referred to as "inside the region surrounded by the opening 270."

[0050] The capacitor 201 includes a conductor 206 on an insulator 214, an insulator 283 covering the insulators 282, 280, the transistor 200, and the conductor 206, an insulator 284 on the insulator 283, and a conductor 248 disposed on the insulator 284 and at least partially overlapping with the conductor 206. Here, the conductor 206 functions as a lower electrode of the capacitor 201, the insulators 283 and 284 function as dielectrics of the capacitor 201, and the conductor 248 functions as an upper electrode of the capacitor 201. In other words, the capacitor 201 constitutes a metal-insulator-metal (MIM) capacitor.

[0051] Conductor 206 is a conductor formed in the same layer as conductor 205, and at least its side surface is in contact with insulator 216. Conductor 206 has a region that does not overlap with insulators 222, 224, and 280, and this region overlaps with opening 270. Also, as shown in FIG. 1B , conductor 206 may be configured so that at least a portion thereof overlaps with insulators 222, 224, and 280.

[0052] Insulator 283 contacts insulator 211 in a region where it does not overlap with insulators 222, 224, 280, and conductor 206, i.e., at the bottom of opening 270. Furthermore, insulator 283 is preferably provided in contact with the top surface of insulator 211, the side surface of insulator 212, the side surface of insulator 214, the side surface of insulator 216, the side surface of insulator 222, the side surface of insulator 224, the side surface of insulator 272, the side surface of insulator 273, the side surface of insulator 280, the side surface of insulator 282, and the top surface of insulator 282. Furthermore, as shown in FIG. 1B , insulator 283 preferably contacts the top surface and side surface of conductor 206 in opening 270. Here, insulator 283 is provided in contact with the bottom surface and inner wall of opening 270, and insulator 284 is provided further inside.

[0053] The conductor 248 is provided further inside the insulator 284. In other words, the conductor 248 is provided so as to be embedded inside the opening 270. Here, it is preferable that at least a portion of the conductor 248 overlaps with the region where the insulator 283 contacts the insulator 211. It is also preferable that the height of the upper surface of the conductor 248 and the height of the upper surface of the region of the insulator 284 that overlaps with the insulator 280 are approximately the same.

[0054] As shown in Figures 1A and 1B, inside opening 270, capacitive element 201 is formed in a region where conductor 248 overlaps the upper surface of conductor 206 via insulators 283 and 284, and in a region where conductor 248 faces the side surface of conductor 206 via insulators 283 and 284.

[0055] 1A, 1B, 2A, and 2B, inside opening 270 formed to surround transistor 200, insulator 283 contacts insulator 211 in a region that does not overlap with conductor 206. Insulator 283 also contacts the side surface of insulator 212. As a result, components of transistor 200, including oxide 230 and the like, insulators 214, 216, 222, 224, 272, 273, 280, and 282, are isolated from the outside by insulators 283 and 284 and insulators 211 and 212. In other words, transistor 200 is disposed within a region sealed by insulators 283 and 284 and insulators 211 and 212. Furthermore, on the upper and lower surfaces of the transistor 200, an insulator 214 and an insulator 282 are further disposed inside the insulator 283.

[0056] Here, the insulators 211, 212, 214, 282, 283, and 284 preferably do not easily diffuse impurities such as hydrogen. For example, the insulators 211, 212, 214, 282, 283, and 284 preferably do not easily diffuse impurities such as hydrogen as the insulators 280 or 274. For example, the insulators 211, 212, 283, and 284 are preferably formed using a material that has the function of suppressing the diffusion of hydrogen and oxygen. Furthermore, the insulators 214 and 282 are preferably formed using a material that has the function of capturing and fixing hydrogen. Typically, the insulators 211, 212, 283, and 284 can be made of silicon nitride. Typically, the insulators 214 and 282 can be made of aluminum oxide.

[0057] In this way, it can be said that transistor 200 is disposed in a region sealed by an insulator that does not easily diffuse impurities such as hydrogen, which reduces the diffusion of impurities such as hydrogen into transistor 200, insulator 280, insulator 216, insulator 224, etc., and reduces the incorporation of impurities into oxide 230.

[0058] Insulator 241a is provided in contact with the inner walls of the openings of insulators 272, 273, 280, 282, 283, and 284, and insulator 274, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Also, insulator 241b is provided in contact with the inner walls of the openings of insulators 272, 273, 280, 282, 283, and 284, and insulator 274, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Furthermore, an insulator 241c is provided in contact with the inner wall of the opening of the insulator 274, a first conductor of the conductor 240c is provided in contact with the side surface of the insulator 241c, and a second conductor of the conductor 240c is provided further inward. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 274 can be made approximately the same. Note that in the transistor 200, the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may have a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0059] In the transistor 200, the conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0060] The transistor 200 preferably uses a metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 including the channel formation region. The oxide 230 preferably includes an oxide 230a disposed over the insulator 224, an oxide 230b disposed over the oxide 230a, an oxide 230c disposed over the oxide 230b and at least a portion of which is in contact with the oxide 230b, and an oxide 230d disposed over the oxide 230c.

[0061] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0062] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0063] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b or oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d.

[0064] In this way, by placing oxide 230a below oxide 230b or oxide 230c, it is possible to suppress the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b or oxide 230c.

[0065] Furthermore, by disposing the oxide 230d on the oxide 230b or the oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230d to the oxide 230b or the oxide 230c. Furthermore, by disposing the oxide 230d on the oxide 230b or the oxide 230c, it is possible to suppress the upward diffusion of oxygen from the oxide 230b or the oxide 230c.

[0066] Furthermore, since the oxides 230a to 230d contain a common element other than oxygen as a main component, the defect state density at each interface between the oxides 230a, 230b, 230c, and 230d can be reduced. In this case, the main carrier path is the oxide 230b, the oxide 230c, or the vicinity thereof, for example, the interface between the oxide 230b and the oxide 230c. Because the defect state density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0067] The oxide 230b and the oxide 230c preferably have crystallinity. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b and the oxide 230c. Alternatively, the oxide 230d may have crystallinity.

[0068] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., V OCAAC-OS is a metal oxide with few crystal grains. On the other hand, it is difficult to identify clear crystal grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable. Furthermore, after the formation of the metal oxide, heat treatment at a temperature at which the metal oxide does not become polycrystalline (for example, 400°C to 600°C) can give the CAAC-OS a more crystalline and dense structure.

[0069] The oxide 230 (e.g., the oxide 230b) is preferably an oxide semiconductor with a low carrier concentration. To reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0070] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water, so V O Furthermore, defects where hydrogen enters oxygen vacancies (hereinafter referred to as V O Hydrogen atoms (sometimes referred to as H) function as donors and generate electrons, which serve as carriers. Some hydrogen atoms may bond with oxygen atoms, which are bonded to metal atoms, to generate electrons, which serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Furthermore, variations in the in-plane distribution of hydrogen concentration can lead to variations in the electrical characteristics of the transistor. Furthermore, hydrogen in an oxide semiconductor is easily transported by stresses such as heat and an electric field. Therefore, the reliability of a transistor may be reduced if the oxide semiconductor contains a large amount of hydrogen.

[0071] From the above, when an oxide semiconductor is used for the oxide 230, V in the oxide 230 OIt is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0072] However, even if an oxide semiconductor is formed so as to reduce the hydrogen concentration, hydrogen may be absorbed from an insulating film that functions as an interlayer film and is in contact with the oxide semiconductor. For example, when an insulating film that functions as an interlayer film is formed, a large amount of highly reactive hydrogen (e.g., hydrogen radicals) is generated during film formation, and a large amount of hydrogen may be absorbed into the insulating film that functions as an interlayer film. Part of the large amount of hydrogen absorbed into the insulating film that functions as an interlayer film may diffuse to the oxide 230 through the conductor 240 that functions as a via due to heat treatment or the like during the manufacturing process of the transistor 200. Thus, the hydrogen concentration in the oxide semiconductor may increase due to hydrogen contained in the insulating film that functions as an interlayer film.

[0073] In contrast, in this embodiment, the transistor 200 including the insulator 280 is sealed with insulating films (such as the insulators 211, 212, 283, and 284) that do not easily diffuse hydrogen, thereby preventing hydrogen from entering the insulator 280 and the transistor 200. The insulators 211, 212, 283, and 284 have a function of preventing hydrogen from diffusing (for example, at least one of hydrogen atoms and hydrogen molecules). The insulators 211, 212, 283, and 284 are formed between a block including the transistor 200 and the insulator 280 and an interlayer film such as the insulator 274, which can prevent hydrogen contained in the interlayer film from entering the block including the transistor 200 and the insulator 280. Therefore, the amount of hydrogen diffusing into the conductor 242, the oxide 230, or the like can be reduced.

[0074] In this manner, by sealing the block including the transistor 200 and the insulator 280 with the insulators 211, 212, 283, and 284, the hydrogen concentration in the oxide 230 can be reduced. For example, when the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) of the oxide 230b is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 The oxide 230, in which impurities such as hydrogen are sufficiently reduced, is used for the channel formation region of the transistor 200, thereby enabling the transistor 200 to have normally-off characteristics, stable electrical characteristics, and improved reliability. Furthermore, by suppressing the diffusion of hydrogen into the transistor 200, variation in the electrical characteristics of the transistor due to the in-plane distribution of the hydrogen concentration can be suppressed.

[0075] Furthermore, the capacitor 201 can be manufactured without using an additional mask in the manufacturing process of the transistor 200 having the above-described sealed structure. In other words, part of the manufacturing process of the capacitor 201 can be shared with part of the manufacturing process of the transistor 200. Therefore, the memory device 202 according to one embodiment of the present invention can be manufactured with high productivity.

[0076] By adopting the above-described structure, it is possible to provide a semiconductor device with little variation in transistor characteristics, a highly reliable semiconductor device, a semiconductor device with excellent electrical characteristics, or a semiconductor device with high productivity.

[0077] In addition, in a cross-sectional view of the transistor in the channel length direction, a groove is preferably formed in the oxide 230b, and the oxide 230c is preferably embedded in the groove. In this case, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the groove. In addition, the thickness of the oxide 230c is preferably approximately the same as the depth of the groove.

[0078] With this configuration, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming the opening for embedding the conductor 260, the damaged region can be removed, thereby suppressing poor electrical characteristics of the transistor 200 due to the damaged region.

[0079] 1A and 1B, the side of the opening in which the conductor 260 and the like are embedded, including the groove in the oxide 230b, is generally perpendicular to the surface on which the oxide 230b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped, with a gently curved surface. Furthermore, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0080] 2A, in the cross-sectional view of the transistor 200 in the channel width direction, the oxide 230b may have a curved surface between the side surface and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (such a shape is also called a rounded shape). Here, as shown in FIG. 2A, in the region where the oxide 230b overlaps with the oxide 230c, the oxide 230c is provided in contact with the top surface and side surface of the oxide 230b and the side surface of the oxide 230a.

[0081] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape improves the coverage of the groove with the insulator 250 and conductor 260 formed in a later process. Furthermore, it is possible to prevent a decrease in the length of the region without the curved surface and suppress a decrease in the on-current and mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0082] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0083] To make the oxide 230c the main carrier path, the atomic ratio of indium to the main metal element in the oxide 230c is preferably larger than the atomic ratio of indium to the main metal element in the oxide 230b. Using a metal oxide with a high indium content for the channel formation region can increase the on-state current of the transistor. Therefore, by making the atomic ratio of indium to the main metal element in the oxide 230c larger than the atomic ratio of indium to the main metal element in the oxide 230b, the oxide 230c can be made the main carrier path.

[0084] Furthermore, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a and 230b. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxides 230a and 230b. In this case, the oxide 230c serves as the main carrier path.

[0085] Specifically, the oxide 230c may be a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=5:1:3 (atomic ratio) or a composition close thereto, or In:M:Zn=10:1:3 (atomic ratio) or a composition close thereto.

[0086] One parameter used to evaluate transistor reliability is the shift voltage (Vsh), measured in a +GBT (Gate Bias Temperature) stress test. The shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the transistor's drain current (Id)-gate voltage (Vg) curve intersects with the line at Id = 1 pA. The amount of change in Vsh is expressed as ΔVsh.

[0087] In a +GBT stress test of a transistor, ΔVsh may shift in the negative direction over time. Also, ΔVsh may exhibit behavior in which it fluctuates in both the negative and positive directions rather than fluctuating in a negative direction (e.g., the negative direction). Note that in this specification and elsewhere, this behavior may be referred to as the jagged behavior of ΔVsh in a +GBT stress test.

[0088] By using a metal oxide that does not contain element M as a main component or a metal oxide with a low ratio of element M as oxide 230c, for example, it is possible to reduce ΔVsh, suppress the jagged behavior of ΔVsh, and improve the reliability of the transistor.

[0089] Furthermore, the oxide 230b and the oxide 230c are preferably crystalline oxides such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This prevents oxygen from being extracted from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0090] The oxide 230c is preferably a CAAC-OS, and the c-axis of the crystal of the oxide 230c is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. The CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0091] Furthermore, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be an In-M-Zn oxide, an In-Zn oxide, or an indium oxide, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0092] Furthermore, the conduction band minimum of the oxide 230d is preferably closer to the vacuum level than the conduction band minimum of the oxide 230c. In other words, the electron affinity of the oxide 230d is preferably smaller than that of the oxide 230c. In this case, the oxide 230d is preferably made of a metal oxide that can be used for the oxide 230a or the oxide 230b. In this case, the main carrier path is the oxide 230c.

[0093] Specifically, the oxide 230c may be a metal oxide or indium oxide having an atomic ratio of In:M:Zn=4:2:3 or a similar composition, an atomic ratio of In:M:Zn=5:1:3 or a similar composition, or an atomic ratio of In:M:Zn=10:1:3 or a similar composition. The oxide 230d may be a metal oxide or oxide of element M having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, an atomic ratio of M:Zn=2:1 or a similar composition, or an atomic ratio of M:Zn=2:5 or a similar composition.

[0094] Furthermore, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0095] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. Because the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, it will cause poor transistor characteristics. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0096] Here, the conduction band minimum changes smoothly at the junctions between the oxides 230a, 230b, 230c, and 230d. In other words, the conduction band minimum at the junctions between the oxides 230a, 230b, 230c, and 230d changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b, between the oxides 230b and 230c, and between the oxides 230c and 230d.

[0097] Specifically, when the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a, the oxide 230c, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0098] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. The oxide 230c may be a metal oxide having an atomic ratio of In:M:Zn=4:2:3 or a similar composition, an atomic ratio of In:M:Zn=5:1:3 or a similar composition, or an atomic ratio of In:M:Zn=10:1:3 or a similar composition, or an indium oxide. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, as the oxide 230d, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, a composition of M:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of the element M may be used.

[0099] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0100] By configuring the oxides 230a, 230b, 230c, and 230d as described above, the defect state density can be reduced at the interface between the oxides 230a and 230b, the interface between the oxides 230b and 230c, and the interface between the oxides 230c and 230d, which reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a large on-state current and high frequency characteristics.

[0101] Note that in the transistor 200, the oxide 230 has four stacked layers of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, or a stacked structure of five or more layers may be used. Alternatively, each of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a stacked structure.

[0102] The insulators 211, 212, 214, 272, 273, 282, 283, 284, and 286 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, the insulators 211, 212, 214, 272, 273, 282, 283, 284, and 286 are preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., is less permeable to the above impurities). Alternatively ... oxygen (i.e., is less permeable to the above oxygen).

[0103] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property refers to a function of suppressing the diffusion of a specific substance (also referred to as low permeability of the substance) or a function of capturing and fixing a specific substance (also referred to as gettering).

[0104] For example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used for the insulators 211, 212, 214, 272, 273, 282, 283, 284, and 286. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulators 211, 212, 283, 284, and 286. For example, aluminum oxide, which has a high hydrogen capture and fixation function, is preferably used for the insulators 214, 272, 273, and 282. This can prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 211, 212, and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the insulator 274, the conductor 246, and the like, which are arranged outside the insulator 284, toward the transistor 200. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the insulator 280, the conductor 246, and the like, which are arranged above the insulator 273, toward the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 and the like toward the substrate through the insulators 211, 212, and 214. In this way, it is preferable to surround the transistor 200 with the insulators 211, 212, 214, 272, 273, 282, 283, and 284, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0105] It may also be preferable to reduce the resistivity of the insulators 211, 284, and 286. For example, it may be preferable to reduce the resistivity of the insulators 211, 284, and 286 to approximately 1×10 13By setting the resistivity to Ωcm, the insulator 211, the insulator 284, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 211, the insulator 284, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0106] Note that it is not necessary to provide either the insulator 211 or the insulator 212. It is also not necessary to provide either the insulator 283 or the insulator 284. For example, when the insulator 212 and the insulator 284 are formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content, it is not necessary to provide the insulator 211 and the insulator 283.

[0107] 1A, 1B, 2A, and 2B, the opening 270 is formed in the insulator 212, but the present invention is not limited to this. For example, the opening 270 does not have to be formed in the insulator 212. In this case, the opening 270 is formed above the insulator 214, and the bottom surface of the opening 270 becomes the insulator 212. Therefore, the insulator 283 contacts the top surface of the insulator 212 at the bottom surface of the opening 270.

[0108] Although the insulators 211, 212, 283, and 284 are each provided as a single layer in the transistor 200, the present invention is not limited to this. For example, each of the insulators 211, 212, 283, and 284 may have a stacked structure of two or more layers.

[0109] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like, as appropriate.

[0110] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0111] Furthermore, when reading data from the memory device 202, a higher potential than that used when data is retained is applied to the conductor 205 to lower the Vth of the transistor 200, thereby making it possible to easily read charge corresponding to the data retained in the capacitor 201. In the memory device 202 described in this embodiment, the capacitor 201 is formed to match the sealing structure of the transistor 200, which may reduce the capacitance of the capacitor 201. However, by increasing the potential applied to the conductor 205 when data is read, the data read speed of the memory device 202 can be sufficiently increased.

[0112] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0113] As shown in FIG. 1A, the conductor 205 is preferably larger than the region of the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 2A, the conductor 205 preferably extends to a region outside the end of the oxide 230 that intersects with the channel width direction. That is, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0114] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0115] Furthermore, it is not necessary to provide one conductor 205 for each transistor, and for example, the conductor 205 may be shared by a plurality of transistors.

[0116] Note that in the transistor 200, the conductor 205 has a stack of the conductor 205a and the conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0117] Here, the conductor 205a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0118] By using a conductive material capable of suppressing oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0119] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the conductive material.

[0120] Conductor 206 has a region that does not overlap with insulators 222, 224, and 280, and this region overlaps with opening 270. Also, as shown in FIG. 1B , one side of conductor 206 may contact insulator 216, and the other side may coincide with the sides of insulators 212 and 214.

[0121] 1B, the conductor 206 may be configured so that at least a portion thereof overlaps with the insulators 222, 224, and 280. This configuration allows the conductor 206 and the conductor 205 to be disposed in close proximity to each other. This reduces the area occupied by the memory device 202 and increases the storage capacity per unit area.

[0122] The conductor 206 is preferably formed in the same process as the conductor 205. Therefore, it is preferable that the conductor 206a has the same structure as the conductor 205a, and the conductor 206b has the same structure as the conductor 205b. The conductor 206 functions as a lower electrode of the capacitor 201.

[0123] By providing the conductor 205 and the conductor 206 in an island shape inside the region surrounded by the opening 270, the insulator 283 contacts the insulator 211 outside the transistor 200 and the conductor 206. This makes it possible to more reliably seal the transistor 200 and the conductor 206. Furthermore, by providing the conductor 260, the insulator 250, the oxide 230c, and the oxide 230d in an island shape inside the region surrounded by the opening 270, it is possible to more reliably seal the transistor 200 and the conductor 206.

[0124] Insulator 222 and insulator 224 function as gate insulators.

[0125] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0126] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0127] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0128] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0129] The insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0130] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0131] Alternatively, the oxide 230 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF (Radio Frequency) treatment. By performing one or more of these treatments, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, V O A reaction occurs in which the bond of H is broken, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 230 or an insulator near the oxide 230. Some of the hydrogen may also be diffused or gettered into the conductor 242.

[0132] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230 by applying RF to the substrate side. The microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0133] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 600°C or lower, more preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby increasing the V O The heat treatment can be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, followed by a subsequent heat treatment in a nitrogen gas or inert gas atmosphere.

[0134] In addition, by subjecting the oxide 230 to oxygen addition treatment, V in the oxide 230 O The oxygen supplied repairs the damaged cells. OFurthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). This allows the hydrogen remaining in the oxide 230 to be converted to V O recombines to V O The formation of H can be suppressed.

[0135] Each of the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the insulators 222 and 224 are not limited to having a laminated structure made of the same material, and may have a laminated structure made of different materials.

[0136] Oxide 243 (oxide 243a and oxide 243b) may be provided on oxide 230b.

[0137] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. Such a structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 does not need to be provided.

[0138] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0139] The conductor 242a is provided over the oxide 243a, and the conductor 242b is provided over the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0140] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0141] If the oxide 243 is not provided, contact between the conductor 242 and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 242, resulting in oxidation of the conductor 242. The oxidation of the conductor 242 is likely to result in a decrease in the conductivity of the conductor 242. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230b or the oxide 230c.

[0142] Furthermore, oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, which may form layers between the conductor 242a and the oxide 230b, between the conductor 242b and the oxide 230b, or between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Because these layers contain more oxygen than the conductor 242a or the conductor 242b, they are presumed to have insulating properties. In this case, the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and can be regarded as a metal-insulator-semiconductor (MIS) structure or a diode junction structure primarily based on the MIS structure.

[0143] Note that hydrogen contained in the oxide 230b, the oxide 230c, and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b, the oxide 230c, and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 240a or the conductor 242b.

[0144] Furthermore, as shown in FIG. 2B, a curved surface may exist between the side surface of the conductor 242b and the top surface of the conductor 242b. In other words, the end of the side surface and the end of the top surface may be curved. The curved surface may have a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductor 242b, for example. The lack of corners at the end improves the film coverage in the film formation process after the formation of the conductor 242. Although not shown in FIG. 2B, the same applies to the conductor 242a as to the conductor 242b.

[0145] The insulator 272 preferably covers the top and side surfaces of the conductor 242 and functions as a barrier insulating film. This structure can prevent the conductor 242 from absorbing excess oxygen contained in the insulator 280. Furthermore, by preventing oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and wiring can be suppressed. Therefore, the transistor 200 can have high electrical characteristics and reliability.

[0146] Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Alternatively, as the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0147] It is also preferable to provide an insulator 273 on the insulator 272. For example, the insulator 272 may be an aluminum oxide film formed by a sputtering method, and the insulator 273 may be an aluminum oxide film formed by an atomic layer deposition (ALD) method. By forming the insulator 273 using the ALD method, it is possible to form a film with reduced dense defects such as cracks and pinholes or with a uniform thickness.

[0148] In addition, oxygen may be supplied to the insulator 224 during the formation of the insulator 272. The insulator 224 is sealed by the insulators 272 and 273, which suppresses outward diffusion of oxygen supplied to the insulator 224 and allows oxygen to be efficiently supplied to the oxide 230. In addition, hydrogen in the insulator 224 may be absorbed by the insulator 273, which is preferable.

[0149] Note that instead of providing the insulators 272 and 273, an insulator functioning as a barrier insulating film may be provided between the top surface of the conductor 242 and the insulator 280. This structure can suppress the absorption of excess oxygen from the insulator 280 by the conductor 242. Furthermore, suppressing oxidation of the conductor 242 can suppress an increase in contact resistance between the transistor 200 and the wiring. This can provide the transistor 200 with high electrical characteristics and reliability. Therefore, the insulator functioning as the barrier insulating film preferably has a function of suppressing oxygen diffusion. For example, the insulator functioning as the barrier insulating film preferably has a function of suppressing oxygen diffusion more than the insulator 280. For example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed as the insulator functioning as the barrier insulating film. In particular, aluminum oxide is preferably formed by an ALD method.

[0150] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0151] The insulator 250 is preferably formed using an insulator that releases oxygen upon heating, similar to the insulator 224. By providing the insulator that releases oxygen upon heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, the concentrations of impurities such as water and hydrogen in the insulator 250 are preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0152] Although the insulator 250 is shown as a single layer in FIGS. 1B and 2A, it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0153] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure consisting of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, it also allows the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator to be made thinner.

[0154] Specifically, the upper layer of the insulator 250 can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0155] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0156] It is preferable that the metal oxide functions as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by a sputtering method, the electrical resistance of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0157] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0158] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 2A, the top surface of the conductor 260 is generally flush with the top surfaces of the insulator 250 and the oxide 230c. While the conductor 260 has a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 1B and 2A, it may have a single-layer structure or a stacked structure of three or more layers.

[0159] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0160] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0161] Furthermore, it is preferable to use a conductor with high conductivity for the conductor 260. For example, the conductor 260b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0162] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0163] 2A, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0164] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 242, and the insulator 273. The top surface of the insulator 280 may be planarized.

[0165] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0166] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. The insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using, for example, the same material as the insulator 216. The insulator 280 may also be a stack of the above materials, for example, a stack structure of silicon oxide formed by sputtering and silicon oxynitride formed thereon by CVD. Silicon nitride may also be stacked on the stack structure.

[0167] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses the permeation of oxygen. For example, an insulator such as aluminum oxide may be used as the insulator 282. By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sealed by the insulators 211, 212, 283, and 284, the impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in the sealed region can be kept constant.

[0168] The insulator 282 preferably has a structure in contact with the top surfaces of the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260. This structure can prevent oxygen contained in the insulator 280 from diffusing toward the conductor 260. Furthermore, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b via the oxide 230c, thereby reducing oxygen vacancies in the oxide 230a and the oxide 230b and improving the electrical characteristics and reliability of the transistor.

[0169] The insulators 283 and 284 function as a barrier insulating film that seals the transistor 200 and also function as a dielectric film for the capacitor 201. The insulator 283 is disposed to cover the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282. The insulator 284 is disposed on and in contact with the insulator 283. As the barrier insulating film used for the insulators 283 and 284, a nitride containing silicon, such as silicon nitride or silicon nitride oxide, is preferably used.

[0170] For example, silicon nitride formed by sputtering may be used as the insulator 283, and silicon nitride formed by CVD may be used as the insulator 284. By forming the insulator 283 by sputtering, a silicon nitride film with high density and low void formation can be formed. Furthermore, by forming the insulator 284 by CVD, a silicon nitride film can be formed at a high film formation rate.

[0171] The conductor 248 may be any conductor that can be used for the conductor 260. Although the conductor 248 has a single-layer structure in FIG. 1B and other figures, the conductor 248 is not limited to this and may have a laminated structure of two or more layers. For example, the conductor 248 may have the same laminated structure as the conductor 260a and the conductor 260b on the conductor 260a.

[0172] Conductor 248 is disposed inside opening 270 so as to be embedded further inside insulator 284. Here, it is preferable that a portion of conductor 248 overlaps with conductor 206, and another portion overlaps with the region where insulator 283 contacts insulator 211. With this configuration, capacitive elements are formed in the region where conductor 248 overlaps with conductor 206 and in the region where conductor 248 faces the side surface of conductor 206, thereby increasing the electrostatic capacitance.

[0173] Furthermore, since the conductor 248 is formed so as to be embedded inside the opening 270, it is arranged so as to surround the transistor 200, as shown in Fig. 1A. This allows the capacitive element 201 to be formed in a hook shape, as shown in Fig. 1A, and the capacitance can be increased.

[0174] The conductors 240a, 240b, and 240c are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a, 240b, and 240c may have a layered structure.

[0175] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 274, 284, 283, 282, 280, 273, and 272. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a, 240b, and 240c. Furthermore, it is possible to prevent impurities such as water and hydrogen contained in the insulator 274 from being mixed into the oxide 230 through the conductors 240a, 240b, and 240c.

[0176] The insulators 241a, 241b, and 241c may be, for example, insulators such as silicon nitride, aluminum oxide, and silicon nitride oxide. The insulators 241a, 241b, and 241c are provided in contact with the insulators 283 and 284, respectively, and thus can prevent impurities such as water and hydrogen contained in the insulator 274 from entering the oxide 230 through the conductors 240a, 240b, and 240c. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a, 240b, and 240c.

[0177] The insulator 274 functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be formed using, for example, a material similar to that of the insulator 280.

[0178] A conductor 246a is arranged in contact with the top surface of the conductor 240a, and functions as a wiring connected to one of the source electrode and drain electrode of the transistor 200. A conductor 246b is arranged in contact with the top surfaces of the conductors 240b and 240c, and electrically connects the other of the source electrode and drain electrode of the transistor 200 to the upper electrode of the capacitor 201. The conductors 246a and 246b are not limited thereto and may be arranged as appropriate depending on the circuit configuration of the semiconductor device including the memory device 202.

[0179] The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0180] The insulator 286 is provided on the conductor 246 and on the insulator 274. As a result, the top surface and side surfaces of the conductor 246 are in contact with the insulator 286. In other words, the conductor 246 can be wrapped in the insulator 286. This configuration can suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 246. This is also preferable because it can prevent impurities such as water and hydrogen from diffusing from the conductor 246 to the outside.

[0181] Alternatively, conductors functioning as wirings may be provided in the same layer as the conductors 246a and 246b or in a layer above the conductors 246a and 246b, and connected to the electrodes of the transistor 200 or the capacitor 201. FIGS. 3A and 3B show an example in which wirings are provided to lead out the conductor 260 functioning as the first gate of the transistor 200, the conductor 205 functioning as the second gate electrode of the transistor 200, and the conductor 206 functioning as the bottom electrode of the capacitor 201. FIG. 3A shows a top view of the memory device 202. FIG. 3B is a cross-sectional view of the portion indicated by the dashed dotted line A7-A8 in FIG. 3A. Some elements are omitted from the top view of FIG. 3A for clarity.

[0182] 3A and 3B, conductor 246d is disposed in the same layer as conductor 246a and conductor 246b, insulator 288 is disposed on insulator 286, conductor 246e and conductor 246f are disposed on insulator 288, and insulator 289 is disposed covering conductor 246e and conductor 246f. An opening reaching conductor 260 is provided below conductor 246d, conductor 240d is provided so as to be embedded in the opening, and insulator 241d is provided in contact with a side surface of conductor 240d. An opening reaching conductor 205 is provided below conductor 246e, conductor 240e is provided so as to be embedded in the opening, and insulator 241e is provided in contact with a side surface of conductor 240e. An opening reaching the conductor 206 is provided below the conductor 246f, the conductor 240f is provided so as to be embedded in the opening, and the insulator 241f is provided in contact with the side surface of the conductor 240f.

[0183] Here, the conductors 246d, 246e, and 246f can have the same structure as the conductor 246 described above. Furthermore, the conductors 240d, 240e, and 240f can have the same structure as the conductor 240. Furthermore, the insulators 241d, 241e, and 241f can have the same structure as the insulator 241. Furthermore, the insulator 288 can have the same structure as the insulator 274 described above. Furthermore, the insulator 289 can have the same structure as the insulator 286 described above.

[0184] With this configuration, conductor 246d functions as wiring connected to conductor 260, conductor 246e functions as wiring connected to conductor 205, and conductor 246f functions as wiring connected to conductor 206.

[0185] Here, since insulators 241d, 241e, and 241f are arranged in contact with insulators 283 and 284, impurities such as water and hydrogen contained in insulators 274 and 288 can be prevented from entering the area sealed by insulators 283 and 284 through conductors 240d, 240e, and conductor 240f.

[0186] 3A, the conductors 246d to 246f extend in the channel width direction of the transistor 200. However, the present invention is not limited to this example and may be arranged as appropriate according to the circuit configuration of the semiconductor device. Furthermore, the conductor 246d is arranged in a lower layer, and the conductors 246e and 246f are arranged in an upper layer. However, the present invention is not limited to this example and may be arranged as appropriate according to the circuit configuration of the semiconductor device. Furthermore, the conductors 246d to 246f are provided over the insulator 284. However, the present invention is not limited to this example and may be provided under the insulator 211, for example. Furthermore, the semiconductor devices described in this embodiment or other embodiments may also be provided with conductors that function as wirings in a similar manner to the above.

[0187] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0188] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0189] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0190] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0191] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0192] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0193] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0194] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced.

[0195] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, for example, a silicide such as nickel silicide, may be used.

[0196] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0197] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0198] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0199] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0200] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to indium and zinc. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0201] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0202] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0203] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be explained using Fig. 4A. Fig. 4A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0204] As shown in FIG. 4A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0205] The structure within the bold frame in Figure 4A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" or "Crystal."

[0206] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0207] As shown in Figure 4B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 4B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0208] The crystalline structure of a film or substrate can be evaluated using a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 4C shows the diffraction pattern of a CAAC-IGZO film. Figure 4C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0209] As shown in Figure 4C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0210] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from that shown in FIG. 4A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0211] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0212] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0213] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0214] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0215] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0216] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0217] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0218] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in a transistor semiconductor layer. Zn is preferably included in the CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0219] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, because the crystallinity of oxide semiconductors can be reduced by impurities or defects, CAAC-OS can also be said to be an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable against thermal budgets. Therefore, using CAAC-OS for OS transistors enables greater flexibility in manufacturing processes.

[0220] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0221] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0222] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with a focus on the material composition of the CAC-OS.

[0223] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0224] Furthermore, CAC-OS is a composite metal oxide in which the first and second regions are separated into a mosaic structure, with the first regions distributed throughout the film (also called a cloud structure).

[0225] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0226] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0227] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0228] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0229] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (the ability to switch on / off). In other words, CAC-OS has a conductive function in one part of the material, an insulating function in another part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and high-speed switching operation can be achieved.

[0230] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0231] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0232] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0233] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9cm -3 The carrier concentration of an oxide semiconductor film can be reduced by reducing the impurity concentration in the oxide semiconductor film and thereby reducing the density of defect states. An oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0234] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0235] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0236] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0237] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0238] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0239] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0240] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0241] It is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is reduced to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0242] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0243] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material or a two-dimensional material) that functions as a semiconductor as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0244] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0245] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0246] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0247] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 1A and 1B, which is one embodiment of the present invention, will be described with reference to FIGS. 5A to 19A and 5B to 19B.

[0248] 5A to 19A are top views. 5B to 19B are cross-sectional views of the portion indicated by the dashed dotted line A1-A2 in FIGS. 5A to 19A, and are also cross-sectional views in the channel length direction of the transistor 200. Note that some elements are omitted from the top views in FIGS. 5A to 19A for clarity.

[0249] First, a substrate (not shown) is prepared, and then a film of the insulator 211 is formed on the substrate. The insulator 211 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0250] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0251] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0252] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0253] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0254] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and achieve good step coverage. In particular, ALD has excellent step coverage and excellent film thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0255] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0256] In this embodiment, the insulator 211 is formed by depositing silicon nitride by the CVD method.

[0257] Next, the insulator 212 is deposited on the insulator 211. The insulator 212 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is deposited as the insulator 212 by a sputtering method.

[0258] In this way, by using an insulator that is impermeable to copper, such as silicon nitride, as insulators 211 and 212, even if a metal that easily diffuses, such as copper, is used in a conductor in a layer (not shown) below insulator 211, it is possible to prevent the metal from diffusing upward through insulators 211 and 212. Furthermore, by using an insulator that is impermeable to impurities, such as water and hydrogen, such as silicon nitride, it is possible to prevent the diffusion of impurities, such as water and hydrogen, contained in layers below insulator 211.

[0259] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0260] It is preferable that the hydrogen concentration of the insulator 212 is lower than that of the insulator 211, and that the hydrogen concentration of the insulator 214 is lower than that of the insulator 212. By forming a silicon nitride film as the insulator 212 by a sputtering method, it is possible to form silicon nitride having a lower hydrogen concentration than the insulator 211 formed by forming a silicon nitride film by a CVD method. Furthermore, by using aluminum oxide as the insulator 214, it is possible to make the hydrogen concentration lower than that of the insulator 212.

[0261] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration be placed away from the transistor 200.

[0262] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0263] Next, openings are formed in the insulator 216 down to the insulator 214. The conductors 205 and 206 are filled in the openings in a later process. The openings may be formed by wet etching, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 214 that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214. Alternatively, for example, the insulators 212, 214, and 216 may be formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used.

[0264] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0265] After the openings are formed, a conductive film that will become the conductors 205a and 206a is formed. The conductive film preferably contains a conductor that suppresses oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film may be a stacked film of a conductor that suppresses oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0266] In this embodiment, the conductive film that becomes conductor 205a and conductor 206a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of conductor 205b and conductor 206b, even if a metal that easily diffuses, such as copper, is used for the conductive film that becomes conductor 205b and conductor 206b (described later), the metal can be prevented from diffusing out of conductor 205a and conductor 206a.

[0267] Next, a conductive film that will become the conductors 205b and 206b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film that will become the conductors 205b and 206b.

[0268] Next, chemical mechanical polishing (CMP) is performed to remove the conductive film that will become conductors 205a and 206a, and a portion of the conductive film that will become conductors 205b and 206b, thereby exposing the insulator 216. As a result, the conductors 205a and 205b, and the conductors 206a and 206b remain only in the openings. This allows the formation of conductors 205 and 206 with flat upper surfaces (see FIGS. 5A and 5B). Note that the CMP process may remove a portion of the insulator 216.

[0269] In this way, the conductor 206 is formed simultaneously with the conductor 205, and therefore the conductor 206 that functions as the lower electrode of the capacitor element 201 can be formed without an additional mask.

[0270] Next, the insulator 222 is formed over the insulator 216, the conductor 205, and the conductor 206. The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222's barrier properties against hydrogen and water prevent hydrogen and water contained in structures around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0271] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0272] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0273] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0274] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, this heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0275] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is deposited by CVD as the insulator 224. The insulator 224 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will be the insulator 224 that comes into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0276] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF to the substrate side may be used. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not necessary.

[0277] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the insulator 224 is reached. This CMP processing can planarize and smooth the surface of the insulator 224. Placing aluminum oxide on the insulator 224 and performing CMP processing facilitates detection of the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film thickness of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0278] Next, oxide film 230A and oxide film 230B are sequentially formed on insulator 224 (see FIGS. 5A and 5B). Preferably, oxide film 230A and oxide film 230B are formed successively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0279] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0280] For example, when the oxide films 230A and 230B are formed by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide films are formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0281] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0282] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0283] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the characteristics required for oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0284] Next, oxide film 243A is formed on oxide film 230B (see FIGS. 5A and 5B). Oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in oxide film 243A is preferably greater than the atomic ratio of Ga to In in oxide film 230B. In this embodiment, oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0285] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A without exposing them to the atmosphere, for example, by using a multi-chamber film forming apparatus.

[0286] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not polycrystallize, i.e., 250°C to 650°C, preferably 300°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0287] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other contaminants from being absorbed into oxide film 230A, oxide film 230B, oxide film 243A, and the like as much as possible.

[0288] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550°C for one hour, followed by another heat treatment in an oxygen atmosphere at 550°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure.

[0289] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 5A and 5B). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The heat treatment temperature is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is set to 200° C.

[0290] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 6A and 6B). This processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A may be processed under different conditions. During this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be reduced.

[0291] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Instead of the light described above, an electron beam or an ion beam may also be used. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0292] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched, thereby forming a hard mask with a desired shape. The conductive film 242A may be etched after removing the resist mask, or may be etched while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0293] Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a portion of them overlaps with the conductor 205. In addition, at least a portion of the conductor 206b does not overlap with the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B.

[0294] Furthermore, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are preferably approximately perpendicular to the top surface of the insulator 222. Having the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B approximately perpendicular to the top surface of the insulator 222 enables a smaller area and higher density when providing multiple transistors 200. Alternatively, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B may be configured to form a small angle with the top surface of the insulator 222. In this case, the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B and the top surface of the insulator 222 is preferably 60 degrees or greater and less than 70 degrees. Such a shape improves coverage of the insulator 272 and the like in subsequent processes, thereby reducing defects such as voids.

[0295] Furthermore, a curved surface is present between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. In other words, it is preferable that the end of the side surface and the end of the top surface are curved. For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductive layer 242B. The absence of corners at the end of the side surface of the conductive layer 242B and the top surface of the conductive layer 242B improves film coverage in the subsequent film formation process.

[0296] Next, the insulator 272 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIGS. 7A and 7B). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed as the insulator 272 by a sputtering method. By forming aluminum oxide by a sputtering method, oxygen can be injected into the insulator 224.

[0297] Next, the insulator 273 is deposited on the insulator 272 (see FIGS. 7A and 7B). The insulator 273 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, aluminum oxide is deposited as the insulator 273 by ALD. Alternatively, silicon nitride may be deposited as the insulator 273 by sputtering.

[0298] Next, an insulating film to be the insulator 280 is formed on the insulator 273. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed by a sputtering method, and a silicon oxide film can be formed thereon by a PEALD method or a thermal ALD method. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulator 280. Heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 273 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used.

[0299] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIGS. 7A and 7B). As with the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0300] Here, microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and V in the oxide 230b and the oxide 230a is increased.O H to V O and hydrogen (H). At this time, some of the hydrogen that has been split may combine with oxygen contained in the insulator 280 and be removed as water molecules. Also, some of the hydrogen may be gettered to the conductor 242 via the insulators 272 and 273.

[0301] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0302] Furthermore, by performing microwave treatment to modify the film quality of the insulator 280, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 via the insulator 280 in post-processing steps after the formation of the insulator 280 or by heat treatment, etc.

[0303] Next, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 8A and 8B).

[0304] When forming the opening, the upper portion of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0305] Furthermore, dry etching or wet etching can be used to process a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 273 and a portion of the insulator 272 may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. The processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0306] Here, when a part of the oxide 230b is removed by dry etching to form the groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.02 W / cm. 2 It should be more than 0.03W / cm 2 It is preferable to set it to 0.06W / cm or more. 2 The dry etching time may be appropriately set in accordance with the depth of the groove.

[0307] Here, it is preferable to remove impurities attached to the surfaces of or diffused into the oxides 230a and 230b. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. Examples of such impurities include those derived from components contained in the insulators 280, 273, and 272, and the conductive layer 242B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0308] In particular, impurities such as aluminum and silicon inhibit the formation of a CAAC-OS oxide in the oxide 230b or the oxide 230c. Therefore, it is preferable to reduce or eliminate impurity elements such as aluminum and silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0309] The region of the metal oxide where the CAAC-OS transformation is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC regions of the oxide 230b and the oxide 230c are reduced or eliminated.

[0310] In contrast, the oxide 230b and the oxide 230c preferably have a layered CAAC structure. In particular, it is preferable that the CAAC structure be formed up to the lower end of the drain of the oxide 230b and the oxide 230c. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. That is, it is preferable that either or both of the oxide 230b and the oxide 230c near the lower end of the conductor 242a (conductor 242b) have a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having a CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0311] In order to remove the impurities, a cleaning process is performed. The cleaning method may be wet cleaning using a cleaning solution, plasma treatment, or heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0312] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0313] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0314] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0315] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0316] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process can remove impurities that have adhered to the surfaces of or diffused into the oxides 230a and 230b. Furthermore, it can improve the crystallinity of the oxide 230c formed on the oxide 230b.

[0317] Due to previous processes such as dry etching or the above-mentioned cleaning process, the film thickness of insulator 224 in the area that overlaps with the opening but does not overlap with oxide 230b may become thinner than the film thickness of insulator 224 in the area that overlaps with oxide 230b.

[0318] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O This heat treatment can reduce the crystallinity of the oxide 230b and also improve the crystallinity of the oxide 230c formed in the grooves of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0319] Next, the oxide film 230C is formed (see FIGS. 9A and 9B). A heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the heat treatment without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be further reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0320] Here, it is preferable that oxide film 230C is provided so as to be in contact with at least the inner wall of the groove formed in oxide 230b, part of the side surface of oxide 243, part of the side surface of conductor 242, part of the side surface of insulator 272, part of the side surface of insulator 273, and part of the side surface of insulator 280. By being surrounded by oxide 243, insulator 272, insulator 273, and oxide film 230C, conductor 242 can be prevented from decreasing in conductivity due to oxidation of conductor 242 in subsequent steps.

[0321] The oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using a film formation method similar to that used for the oxide film 230A or the oxide film 230B, depending on the characteristics required for the oxide film 230C. In this embodiment, the oxide film 230C is formed by a sputtering method using an oxide target having an In:Ga:Zn=4:2:3 (atomic ratio), an oxide target having an In:Ga:Zn=5:1:3 (atomic ratio), an oxide target having an In:Ga:Zn=10:1:3 (atomic ratio), or an indium oxide target.

[0322] During the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, during the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, by forming the oxide film 230C in such an oxygen-rich atmosphere, the oxide film 230C is more likely to become a CAAC-OS.

[0323] The oxide film 230C is preferably formed while the substrate is heated. At this time, by setting the substrate temperature to 200°C or higher, oxygen vacancies in the oxide film 230C and the oxide 230b can be reduced. By forming the oxide film 230C while heating the substrate, the crystallinity of the oxide film 230C and the oxide 230b can be improved.

[0324] Next, oxide film 230D is formed (see FIGS. 10A and 10B). Oxide film 230D may be formed continuously from oxide film 230C without exposure to the atmosphere.

[0325] The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230D may be formed by the same film formation method as that for the oxide film 230A or 230B, depending on the characteristics required for the oxide film 230D. In this embodiment, the oxide film 230D is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=In:Ga:Zn=1:3:4.

[0326] When forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the oxide film 230C. Alternatively, when forming the oxide film 230D, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.

[0327] Next, the insulating film 250A is formed (see FIGS. 10A and 10B). A heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately after the formation of the insulating film 250A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0328] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 that contacts the oxide 230d in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0329] When the insulator 250 has a two-layer laminated structure, it is preferable to successively deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmosphere. Depositing the films without exposing them to the atmosphere can prevent impurities or moisture from the atmosphere from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and can keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0330] Here, after the insulating film 250A is formed, a microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. By performing the microwave treatment, an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and V in the oxide film 230C, the oxide 230b, and the oxide 230a is increased. O H to V Oand hydrogen. At this time, some of the hydrogen separated may combine with oxygen to form H2O, which may be removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Also, some of the hydrogen may be gettered by the conductor 242. In this way, by performing microwave treatment, the hydrogen concentrations in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced. Also, V in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O can be repaired or compensated for.

[0331] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered by the conductor 242. Alternatively, a heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0332] Furthermore, by performing microwave processing to modify the film quality of the insulating film 250A, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment.

[0333] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 11A and 11B). The conductive film 260A and the conductive film 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed using an ALD method, and the conductive film 260B is formed using a CVD method.

[0334] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (see FIGS. 12A and 12B). As a result, the oxide 230c is arranged to cover the inner walls (side walls and bottom surface) of the opening that reaches the oxide 230b and the groove of the oxide 230b. The oxide 230d is arranged to cover the inner walls of the opening and the groove via the oxide 230c. The insulator 250 is arranged to cover the inner walls of the opening and the groove via the oxide 230d. The conductor 260 is arranged to be embedded in the opening and the groove via the oxide 230c, the oxide 230d, and the insulator 250.

[0335] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0336] Next, the insulator 282 is formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 13A and 13B). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form an aluminum oxide film by a sputtering method as the insulator 282. By forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during film formation. At this time, it is preferable to form the insulator 282 while heating the substrate. Furthermore, it is preferable to form the insulator 282 in contact with the top surface of the conductor 260, because this can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0337] Next, a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, a portion of the insulator 214, and a portion of the insulator 212 are processed to form an opening 270 that reaches the insulator 211 (see FIGS. 14A and 14B ). Thus, a portion of the side surface of the insulator 282, a portion of the side surface of the insulator 280, a portion of the side surface of the insulator 273, a portion of the side surface of the insulator 272, a portion of the side surface of the insulator 224, a portion of the side surface of the insulator 222, a portion of the side surface of the insulator 216, a portion of the side surface of the insulator 214, and a portion of the side surface of the insulator 212 are exposed inside the opening 270. Note that the opening 270 may be formed so as to surround the transistor 200 in a top view. Alternatively, the opening 270 may be formed so as to surround a plurality of transistors 200.

[0338] The capacitor element 201, which will be formed in a later process, is formed in a region where the conductor 206 overlaps with the opening 270. Therefore, the opening 270 is formed so as to expose at least a portion of the conductor 206. In other words, the conductor 206 has a region where at least a portion of the conductor 206 does not overlap with the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212.

[0339] Furthermore, it is preferable that at least a part of the side surface of the conductor 206 is exposed inside the opening 270. With this configuration, the conductor 248 can be provided facing the side surface of the conductor 206 in a later process, and therefore the capacitor element 201 can be formed up to the side surface of the conductor 206.

[0340] A dry etching method or a wet etching method can be used to process a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, a portion of the insulator 214, and a portion of the insulator 212. Processing by the dry etching method is suitable for fine processing. Furthermore, the processing may be performed under different conditions.

[0341] Next, an insulator 283 is formed to cover the insulators 282, 280, 273, 272, 224, 222, 216, 214, 212, and conductor 206 (see FIGS. 15A and 15B). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon nitride film may be formed by a sputtering method. As shown in FIG. 15B, the insulator 283 contacts the insulator 211 at the bottom of the opening 270. That is, the upper and side surfaces of the transistor 200 are surrounded by the insulator 283, and the lower surface is surrounded by the insulator 211. In this way, by surrounding the transistor 200 with the insulators 283 and 211, which have high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

[0342] Next, it is preferable to form a film of insulator 284 on insulator 283 (see FIGS. 16A and 16B). For example, the film of insulator 284 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is also preferable to use the same material for insulator 284 as insulator 212 and insulator 283.

[0343] The insulator 284 is preferably formed using a film formation method with high film-forming properties. Specifically, a silicon nitride film is preferably formed using a CVD method. In particular, the insulator 284 is preferably formed by a CVD method using a compound gas that does not contain hydrogen atoms or that contains only a small amount of hydrogen atoms.

[0344] The insulators 283 and 284 function as a barrier insulating film that seals the transistor 200 and also function as a dielectric film of the capacitor 201. Therefore, by forming the insulators 283 and 284 as described above, the dielectric film of the capacitor 201 can be provided without adding any additional steps.

[0345] Next, a conductive film 248A is formed on the insulator 284 (see FIGS. 17A and 17B). The conductive film 248A is formed so as to fill the opening 270 in which the insulators 283 and 284 have been formed. The conductive film 248A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film 248A is not limited to a single-layer structure, and may also have a multilayer structure. For example, the conductive film 248A may be configured such that titanium nitride is formed using an ALD method, and tungsten is formed on the titanium nitride using a CVD method.

[0346] Next, the conductive film 248A is polished by CMP until the insulator 284 is exposed, thereby forming the conductor 248 (see FIGS. 18A and 18B). As a result, the conductor 248 is disposed so as to be embedded in the opening 270. By forming the conductor 248 by CMP, the height of the upper surface of the conductor 248 and the height of the upper surface of the insulator 284 become roughly the same.

[0347] In this way, the conductor 248 is formed so as to be embedded in the opening 270, and therefore the conductor 248 that functions as the upper electrode of the capacitor element 201 can be formed without an additional mask.

[0348] Next, the insulator 274 is formed on the insulator 284 and the conductor 248 (see FIGS. 19A and 19B). The insulator 274 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed using a CVD method. The insulator 274 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulating film that becomes the insulator 274 to be reduced. The insulator 274 is preferably subjected to a CMP process to flatten the upper surface.

[0349] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and to be further supplied to the oxide 230a and the oxide 230b via the oxide 230c. Note that this heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282 or the insulator 284.

[0350] Next, openings are formed in insulators 272, 273, 280, 282, 283, 284, and 274, reaching conductors 242a, 242b, and 248 (see FIGS. 19A and 19B). The openings may be formed using lithography. Note that although the shape of the openings is circular in the top view in FIG. 19A, the shape is not limited to this. For example, the openings may have a roughly circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in the top view.

[0351] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIGS. 19A and 19B). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0352] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 240 that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240 to the outside.

[0353] Next, a conductive film that will become the conductor 240 is formed. The conductive film that will become the conductor 240 preferably has a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0354] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 240, exposing the upper surfaces of the insulators 284 and 274. As a result, the conductive film remains only in the openings, forming conductors 240a, 240b, and 240c with flat upper surfaces (see FIGS. 19A and 19B). Note that the CMP process may remove a portion of the upper surface of the insulator 274.

[0355] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0356] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a, and the conductor 246b that contacts the upper surfaces of the conductors 240b and 240c (see FIGS. 1A and 1B). At this time, part of the insulator 274 may be removed in areas where the conductors 246a and 246b do not overlap with the insulator 274.

[0357] Next, an insulator 286 is formed on the conductor 246 and the insulator 274 (see FIGS. 1A and 1B). The insulator 286 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 286 may also be multi-layered. For example, a silicon nitride film may be formed by sputtering, and another silicon nitride film may be formed on the silicon nitride by CVD.

[0358] 1A and 1B can be manufactured. As shown in FIGS. 5A to 19A and 5B to 19B, a memory device 202 including the transistor 200 and the capacitor 201 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

[0359] As described above, the conductor 206, the insulator 283, the insulator 284, and the conductor 248, which are included in the capacitor 201, can be formed without using an additional mask in the process of manufacturing the transistor 200. In this manner, part of the process of manufacturing the capacitor 201 can be shared with part of the process of manufacturing the transistor 200. Therefore, by manufacturing the memory device 202 according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0360] <Modification of Semiconductor Device> 20 to 25 , an example of a semiconductor device according to one embodiment of the present invention will be described. In the semiconductor device including the memory device 202 shown in FIGS. 20 to 25 , structures having the same functions as those of the semiconductor device including the memory device 202 shown in <Structural Example of Semiconductor Device> are denoted by the same reference numerals. Also in this section, the materials described in detail in <Structural Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device including the memory device 202.

[0361] <<Semiconductor Device Variation 1>> The memory device 202 shown in FIGS. 20A and 20B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. FIG. 20A shows a top view of the memory device 202. FIG. 20B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 20A. Some elements are omitted from the top view of FIG. 20A for clarity. The memory device 202 shown in FIGS. 20A and 20B differs from the memory device 202 shown in FIGS. 1A and 1B in that a portion of the conductor 205 overlaps with the conductor 248 via the insulators 283 and 284.

[0362] 1A and 1B, the conductor 205 and the conductor 206 are provided separately, but in the memory device 202 shown in Figures 20A and 20B, they are integrated into the conductor 205. The conductor 205 functions as the back gate of the transistor 200 and also as the lower electrode of the capacitor 201.

[0363] 20A and 20B, the conductor 205 is provided in an island shape and is in a floating state. With this structure, charges held in the conductor 248 induce charges in the conductor 205, thereby reducing the Vth of the transistor 200. This allows charges corresponding to the data held in the capacitor 201 to be easily read, thereby enabling the data read speed of the memory device 202 to be sufficiently increased.

[0364] <<Semiconductor Device Modification Example 2>> The memory device 202 shown in FIGS. 21A and 21B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. FIG. 21A shows a top view of the memory device 202. FIG. 21B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 21A. Some elements are omitted from the top view of FIG. 21A for clarity. The memory device 202 shown in FIGS. 21A and 21B differs from the memory device 202 shown in FIGS. 1A and 1B in that the conductor 206 does not overlap with the insulator 280. Therefore, in the memory device 202 shown in FIGS. 21A and 21B, the conductor 206 does not overlap with the transistor 200.

[0365] 21B, it is preferable that the insulator 283 contacts one side surface (the side surface on the A1 side) of the conductor 206 and also contacts the side surface opposite to the one side surface (the side surface on the A2 side). That is, in the memory device 202 shown in FIGS. 21A and 21B, the conductor 206 is provided so as to be covered with the conductor 248.

[0366] With this configuration, the capacitive element 201 can be formed also on the side surface of the conductor 206 on the A1 side, thereby increasing the capacitance.

[0367] <<Semiconductor Device Modification Example 3>> The memory device 202 shown in FIGS. 22A and 22B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. FIG. 22A shows a top view of the memory device 202. FIG. 22B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 22A. Some elements are omitted from the top view of FIG. 22A for clarity. The memory device 202 shown in FIGS. 22A and 22B differs from the memory device 202 shown in FIGS. 1A and 1B in that an opening 251 reaching the conductor 206 is formed in the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b, and the conductor 242b contacts the conductor 206 through the opening 251.

[0368] With this structure, one of the source and the drain of the transistor 200 can be electrically connected to the conductor 206 which functions as a lower electrode of the capacitor 201 .

[0369] In addition, the conductor 246b electrically connected to the conductor 248 via the conductor 240c functions as a capacitance wiring. Note that since there is no need to extract and route the conductor 242b onto the insulator 274, there is no need to provide the conductor 240b and the insulator 241b shown in FIG. 1B.

[0370] 5, the oxide film 243A is formed, and then the opening 251 reaching the conductor 206 is formed. Thereafter, the conductive film 242A is formed, so that the conductive film 242A is formed in contact with the upper surface of the conductor 206.

[0371] <<Semiconductor Device Variation 4>> The memory device 202 shown in FIGS. 23A and 23B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. The memory device 202 shown in FIGS. 23A and 23B has a layout similar to that of the memory device 202 shown in FIG. 1A. FIG. 23A is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 1A, and FIG. 23B is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in FIG. 1A. The memory device 202 shown in FIGS. 23A and 23B differs from the memory device 202 shown in FIGS. 1A and 1B in that the ends where the side surfaces and top surfaces of the conductors 242a and 242b intersect are angular.

[0372] The corner-shaped end where the side surface and top surface of the conductor 242 intersect increases the cross-sectional area of the conductor 242 compared to when the end has a curved surface. This reduces the resistance of the conductor 242, allowing the on-current of the transistor 200 to be increased.

[0373] In this way, when the edge where the side surface and the top surface of the conductor 242 intersect is made angular, a hard mask may be formed on the conductive layer 242B when forming the conductive layer 242B into an island shape in the process shown in Fig. 6. This makes it possible to prevent the edge where the side surface and the top surface of the conductive layer 242B intersect from being etched.

[0374] Alternatively, the hard mask may be made of an insulator similar to the insulator 272. In this case, if the manufacturing process is continued while the hard mask remains, the insulator 272a can be formed on the conductor 242a, and the insulator 272b can be formed on the conductor 242b, as shown in Figures 23A and 23B. When the insulators 272a and 272b are formed in this manner, the insulators 272 and 273 shown in Figure 1B do not need to be formed.

[0375] <<Modification 5 of the semiconductor device>> The memory device 202 shown in FIGS. 24A and 24B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. FIG. 24A shows a top view of the memory device 202. FIG. 24B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 24A. Some elements are omitted from the top view of FIG. 24A for clarity. The memory device 202 shown in FIGS. 24A and 24B differs from the memory device 202 shown in FIGS. 1A and 1B in that the side surfaces of the conductors 205 and 206 are tapered.

[0376] 5, the insulator 214 is formed, and then the conductors 205 and 206 are patterned on the insulator 214. At this time, the side surfaces of the conductors 205 and 206 are tapered. After that, the insulator 216 is formed to cover the conductors 205 and 206, and a CMP process is performed on the insulator 216 to remove part of the insulator 216 and expose the surfaces of the conductors 205 and 206.

[0377] <<Sixth Modification of Semiconductor Device>> The memory device 202 shown in FIGS. 25A and 25B is a modified example of the memory device 202 shown in FIGS. 1A and 1B. The memory device 202 shown in FIGS. 25A and 25B has a layout similar to that of the memory device 202 shown in FIG. 1A. FIG. 25A is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and FIG. 25B is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 1A. The memory device 202 shown in FIGS. 25A and 25B differs from the memory device 202 shown in FIGS. 1A and 1B in that an insulator 287 is arranged in contact with the side surfaces of the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282, and the conductor 206.

[0378] The insulator 287 is preferably formed using a material that has the function of capturing and fixing hydrogen, similar to the insulator 282 or the insulator 214. Typically, the insulator 287 can be made of aluminum oxide.

[0379] 25A and 25B, insulator 283 is provided to cover insulator 282 and insulator 287. That is, insulators 214, 287, and 282, which have the function of capturing and fixing hydrogen, are provided in contact with insulators 216, 280, etc., within the area sealed with insulator 283 and insulator 211. Therefore, insulators 214, 287, and 282 capture or fix hydrogen contained in insulators 216, 280, etc., and the amount of hydrogen within the sealed area can be kept constant.

[0380] 14, an insulating film such as aluminum oxide is formed by sputtering or the like, and then an anisotropic etching process is performed on the insulating film to form the insulator 287 in contact with the side surfaces of the insulators 211, 212, 214, 216, 222, 224, 272, 273, 280, 282, and conductor 206. Dry etching is preferably used as the anisotropic etching process. This allows the insulating film formed on a surface roughly parallel to the substrate surface to be removed, forming the insulator 287 in a self-aligned manner.

[0381] <<Seventh Modification of Semiconductor Device>> The memory device 202 shown in FIGS. 26A, 26B, 27A, and 27B is a modified example of the memory device 202 shown in FIGS. 1A, 1B, 2A, and 2B. FIG. 26A shows a top view of the memory device 202. FIG. 26B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 26A. FIG. 27A is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 26A. FIG. 27B is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 26A. Some elements have been omitted from the top view of FIG. 26A for clarity. 26A, 26B, 27A, and 27B differs from memory device 202 shown in FIGS. 1A, 1B, 2A, and 2B in that conductors 260, 205, and 206 are extended to function as wiring. Memory device 202 shown in FIGS. 26A, 26B, 27A, and 27B also differs from memory device 202 shown in FIGS. 1A, 1B, 2A, and 2B in that openings 270a and 270b are formed to surround transistor 200, conductor 248a is embedded in opening 270a, and conductor 248b is embedded in opening 270b. It is preferable that the distance between openings 270a and 270b and oxide 230c be as short as possible.

[0382] In opening 270b, similarly to opening 270, conductor 206 is exposed, and capacitive element 201 is formed therein. Also, similarly to opening 270, insulator 283 is provided in contact with the bottom surface and inner wall of opening 270b, and insulator 284 is provided further inside. Furthermore, similarly to conductor 248 in opening 270, conductor 248b is provided inside opening 270b so as to fill in the further inside of insulator 284. Also, it is preferable that the height of the top surface of conductor 248b and the height of the top surface of the region of insulator 284 that overlaps with insulator 280 are approximately the same.

[0383] Furthermore, in opening 270a, no conductor is provided in the same layer as conductor 206, but similar to opening 270, insulator 283 is provided in contact with the bottom surface and inner wall of opening 270a, and insulator 284 is provided further inside. Furthermore, similar to conductor 248 in opening 270, conductor 248a is provided inside opening 270a so as to embed the area further inside insulator 284. Furthermore, it is preferable that the height of the upper surface of conductor 248a and the height of the upper surface of the region of insulator 284 that overlaps with insulator 280 are approximately the same.

[0384] 26A, the conductor 260 functions as a wiring including a first gate electrode, the conductor 205 functions as a wiring including a second gate electrode, and the conductor 206 functions as a wiring including a lower electrode of the capacitive element 201. Note that, although the conductors 260, 205, and 206 are arranged extending in the A3-A4 direction in FIG. 26A, the present invention is not limited to this, and the conductors 260, 205, and 206 can be arranged as appropriate in accordance with the circuit configuration of the semiconductor device including the memory device 202.

[0385] In addition, the insulator 250, the oxide 230c, and the oxide 230d may also be arranged to extend in the channel width direction in accordance with the conductor 260.

[0386] 26A and 27A, the oxide 230c may be provided in an island shape for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Also, the oxide 230c of one transistor 200 may be separated from the oxide 230c of another transistor 200 adjacent to the transistor 200. In other words, the oxide 230c may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0387] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, the above structure allows the oxide 230c to be independently provided in each transistor 200. This can prevent a parasitic transistor from being formed between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing a leakage path from being formed. This makes it possible to provide a semiconductor device that has excellent electrical characteristics and can be miniaturized or highly integrated.

[0388] 27A, the oxide 230d has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200. Note that the oxide 230c and the oxide 230d of the transistor 200 may be separated from the oxide 230c and the oxide 230d of the transistor 200 adjacent to the transistor 200, respectively.

[0389] <Application examples of semiconductor devices> 28 to 30 , an example of a semiconductor device including a memory device 202 according to one embodiment of the present invention, which is different from those shown in the above <Structural Example of Semiconductor Device> and the above <Modified Example of Semiconductor Device>, will be described. Note that in the semiconductor device shown in FIGS. 28 to 30 , structures having the same functions as those of the structures constituting the semiconductor device shown in <<Structural Example of Semiconductor Device>> are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural Example of Semiconductor Device> and <Modified Example of Semiconductor Device> can be used as materials for constituting the transistor 200.

[0390] 28 is a cross-sectional view in the channel length direction of a semiconductor device 600 having a memory device 202a including a transistor 200a and a capacitor 201a, and a memory device 202b including a transistor 200b and a capacitor 201b. As shown in FIG. 28, the semiconductor device 600 has an axisymmetric configuration with the conductor 240a and the conductor 246a as the axis of symmetry. For this reason, in FIG. 28, reference numerals are attached to the components of the memory device 202a, and the same reference numerals can be used to refer to the components of the memory device 202b.

[0391] The conductor 242a serves as both a source electrode or a drain electrode of the transistor 200a and a source electrode or a drain electrode of the transistor 200b. The conductor 246a functions as a wiring, and the conductor 240a functions as a plug. In this way, by configuring the two transistors, the two capacitors, and the wiring and the plug in the above-described manner, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0392] The configurations and effects of the memory device 202a including the transistor 200a and the capacitor 201a and the memory device 202b including the transistor 200b and the capacitor 201b can be understood from the configuration examples of the semiconductor devices described above.

[0393] In the above, the memory device 202a and the memory device 202b are given as examples of the configuration of the semiconductor device, but the semiconductor device described in this embodiment is not limited to this. For example, as shown in Fig. 29, a semiconductor device 600_1 and a semiconductor device 600_2 having a configuration similar to that of the semiconductor device 600_1 may be connected via a conductor 206 that functions as a lower electrode of a capacitor element. In this specification, a semiconductor device having the memory device 202a and the memory device 202b may be referred to as a cell.

[0394] Figure 29 is a cross-sectional view in which a semiconductor device 600_1 having a memory device 202a_1 consisting of a transistor 200a_1 and a capacitance element 201a_1, and a memory device 202b_1 consisting of a transistor 200b_1 and a capacitance element 201b_1 (not shown), and a semiconductor device 600_2 having a memory device 202a_2 consisting of a transistor 200a_2 and a capacitance element 201a_2, and a memory device 202b_2 consisting of a transistor 200b_2 and a capacitance element 201b_2 (not shown) are connected via a conductor 206 that functions as the lower electrode of the capacitance element.

[0395] As shown in FIG. 29, the conductor 206 functioning as one electrode of the capacitor 201a_1 of the semiconductor device 600_1 also serves as one electrode of the capacitor 201a_2 of the semiconductor device 600_2. Although not shown, the conductor 206 functioning as one electrode of the capacitor 201b_1 of the semiconductor device 600_1 also serves as one electrode of the capacitor of the cell adjacent to the left side of the semiconductor device 600_1. The same configuration is also applied to the cell on the right side of the semiconductor device 600_2. In other words, a cell array (also referred to as a memory device layer) can be configured. Such a cell array configuration can reduce the spacing between adjacent cells, thereby reducing the projected area of the cell array and enabling higher integration. Furthermore, by arranging the cell arrays shown in FIG. 29 in a matrix, a matrix cell array can be configured.

[0396] As described above, by forming the semiconductor device 600_1 and the semiconductor device 600_2 with the configuration shown in this embodiment, the area of the cell can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0397] Furthermore, the cell arrays may be stacked instead of being arranged in a matrix. Fig. 30 shows a cross-sectional view of a configuration in which n layers of cell arrays 610 are stacked. As shown in Fig. 30, by stacking multiple cell arrays (cell arrays 610_1 to 610_n), the cells can be integrated and arranged without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be configured.

[0398] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0399] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or with structures, methods, and the like described in other embodiments.

[0400] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0401] [Storage device] 31 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a memory device 202 is provided above a transistor 300. As in the above embodiment, the memory device 202 includes a transistor 200 and a capacitor 201. Note that the memory device 202, the transistor 200, and the capacitor 201 described in the above embodiment can be used as the memory device 202, the transistor 200, and the capacitor 201.

[0402] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the transistor 200 can retain data for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced. Furthermore, as shown in Embodiment 1, the transistor 200 is sealed with the insulators 283, 284, 211, and 212; therefore, variation in electrical characteristics of the memory device can be suppressed, and the reliability can be improved.

[0403] 31 , a wiring 1001 is electrically connected to the source of a transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. A wiring 1005 is electrically connected to one of the electrodes of a capacitor 201.

[0404] Moreover, the memory device shown in FIG. 31 can be arranged in a matrix to form a memory cell array.

[0405] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel type.

[0406] Here, in the transistor 300 shown in FIG. 31, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0407] Note that the transistor 300 shown in FIG. 31 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0408] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, multiple conductors that function as plugs or wiring may be collectively given the same reference numeral. Furthermore, in this specification and the like, wiring and a plug electrically connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as wiring, and cases where a part of a conductor functions as a plug.

[0409] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. The capacitor 201 or a conductor 328, a conductor 330, and the like electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0410] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to enhance flatness.

[0411] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 31 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

[0412] Similarly, a conductor 218, a conductor (conductor 205) constituting the transistor 200, a conductor (conductor 206) constituting the capacitor 201, and the like are embedded in the insulators 210, 211, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring that electrically connects the transistor 300 to an upper wiring.

[0413] As described in Embodiment 1, the conductor 240, the transistor 200, the capacitor 201, and the like are embedded in the insulator 222, the insulator 224, the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, and the insulator 284. As described in Embodiment 1, the conductor 246 is provided over the conductor 240, and the insulators 286 and 288 are provided over the conductor 246.

[0414] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductors 205 and 206 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surfaces of the conductors 205 and 206.

[0415] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0416] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0417] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0418] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0419] For example, it is preferable to use an insulator with a low dielectric constant for insulators 210, 352, and 354. For example, it is preferable to use silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin for the insulator. Alternatively, it is preferable to use a laminate structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide with resin. Silicon oxide and silicon oxynitride are thermally stable, so by combining them with resin, a thermally stable laminate structure with a low dielectric constant can be achieved. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0420] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 211, 212, 350, and 324 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0421] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0422] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0423] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, conductor 218, and conductor 246, either in a single layer or a multilayer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum and copper are preferably used. Using low-resistance conductive materials can reduce wiring resistance.

[0424] When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0425] 31, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 272, the insulator 273, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0426] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0427] The insulator 241 may be an insulating material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. For example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide may be used. Silicon nitride is particularly preferable because of its high blocking properties against hydrogen. Alternatively, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0428] As in Embodiment 1, the transistor 200 is preferably sealed with the insulators 211, 212, 214, 282, 283, and 284. This structure can reduce the intrusion of hydrogen contained in the insulator 274 and the like into the insulator 280 and the like.

[0429] Here, the conductor 240 penetrates the insulators 284, 283, and 282, and the conductor 218 penetrates the insulators 214, 212, and 211, but as described above, the insulator 241 is provided in contact with the conductor 240. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 211, 212, 214, 282, 283, and 284 via the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 211, 212, 214, 282, 283, 284, and 241, and it is possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside.

[0430] Furthermore, the insulators 216, 224, 280, 250, and 274 are preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0431] In this way, the hydrogen concentration in the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0432] Furthermore, dicing lines (which may be called scribe lines, dividing lines, or cutting lines) that are provided when cutting a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form are preferably designed so that the insulator 283 and the insulator 211 are in contact with each other and overlap with an area where the capacitive element 201 is not formed. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (segment) the semiconductor devices into multiple semiconductor devices.

[0433] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0434] (Embodiment 3) In this embodiment, a memory device (hereinafter also referred to as an OS memory device) including a memory device (hereinafter also referred to as a memory cell) according to one embodiment of the present invention will be described with reference to FIGS. 32A, 32B, and 33A to 33C. The memory cell includes an OS transistor and a capacitor. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely small, the OS memory device has excellent data retention characteristics and can function as a nonvolatile memory. Furthermore, as shown in the above embodiment, the OS transistor is sealed with a barrier insulating film that has a barrier property against hydrogen. This suppresses variations in the electrical characteristics of the OS memory device, thereby improving its reliability.

[0435] <Storage device configuration example> 32A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0436] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to access.

[0437] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0438] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0439] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0440] 32A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 32B, the memory cell array 1470 may be provided so as to overlap a portion of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0441] 33A to 33C illustrate examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0442] [DOSRAM] 33A to 33C show circuit configuration examples of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor element may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 33A includes a transistor M1 and a capacitor element CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0443] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0444] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be controlled by applying an arbitrary potential to the wiring BGL.

[0445] 33A corresponds to the memory device 202 shown in the above embodiment. That is, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 201.

[0446] Furthermore, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a back gate of the transistor M1 connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 33B. Furthermore, for example, the memory cell MC may be a memory cell configured with a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 33C.

[0447] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 201 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0448] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, and the storage capacitance of the memory cells can be reduced.

[0449] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.

[0450] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 34 shows various storage devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the storage capacity and recording density required. Figure 34 shows, from the top layer, memories embedded as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM, and 3D NAND memory.

[0451] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0452] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0453] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0454] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0455] A storage device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0456] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0457] (Fourth embodiment) 35A and 35B, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0458] As shown in FIG. 35A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0459] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 35B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0460] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be the DOSRAM described in the previous embodiment.

[0461] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. NOSRAM or DOSRAM may be used for this memory. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0462] Furthermore, since the CPU 1211 and GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0463] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0464] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0465] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. A controller refers to a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0466] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0467] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0468] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0469] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its high image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0470] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0471] (Embodiment 5) This embodiment mode will describe examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment mode is incorporated.

[0472] <Electronic components> First, an example of an electronic component incorporating memory device 720 will be described with reference to FIGS. 36A and 36B.

[0473] FIG. 36A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 36A has memory device 720 inside mold 711. FIG. 36A omits a portion of the interior of electronic component 700 to show it. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0474] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0475] 36B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0476] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0477] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0478] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, with a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0479] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0480] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0481] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0482] A heat sink (heat dissipation plate) may be provided over the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0483] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 36B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0484] The electronic component 730 can be mounted on other substrates using various mounting methods other than BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0485] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0486] (Sixth embodiment) In this embodiment, application examples of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIGS. 37A to 37E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0487] 37A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0488] FIG. 37B is a schematic diagram of the appearance of an SD card, and FIG. 37C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0489] FIG. 37D is a schematic diagram of the appearance of an SSD, and FIG. 37E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0490] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0491] (Embodiment 7) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in Figures 38A to 38H.

[0492] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an electronic device with a GPU or chip according to one embodiment of the present invention, it is possible to equip the electronic device with artificial intelligence.

[0493] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0494] An electronic device according to one embodiment of the present invention may have a sensor (a sensor having the function of measuring force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0495] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 38A to 38H.

[0496] [Information terminal] 38A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0497] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display portion 5102 and displays them on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0498] 38B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0499] The notebook information terminal 5200 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the information terminal 5100. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0500] 38A and 38B are respectively an example of a smartphone and a notebook type information terminal as electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0501] [Game consoles] FIG. 38C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), the video displayed on the display unit 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation unit. This allows multiple players to play a game simultaneously. The chips described in the above embodiments can be incorporated into the substrates of the housings 5301, 5302, and 5303.

[0502] 38D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0503] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, the reduction in power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0504] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0505] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in questions from the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0506] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0507] 38C and 38D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0508] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0509] 38E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 38F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0510] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.

[0511] The supercomputer 5500 is a large-scale computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by the chip. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, the reduction in power consumption can reduce heat generated by a circuit, thereby reducing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0512] 38E and 38F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the GPU or chip of one embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0513] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0514] Fig. 38G is a diagram showing the area around the windshield inside the interior of an automobile, which is an example of a moving body, showing display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0515] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0516] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0517] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0518] Although an automobile is described as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can also include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0519] [electric appliances] 38H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0520] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0521] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0522] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0523] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples. [Explanation of symbols]

[0524] BGL: wiring, BIL: wiring, CA: capacitance element, CAL: wiring, MC: memory cell, M1: transistor, WOL: wiring, 200: transistor, 200a: transistor, 200a_1: transistor, 200a_2: transistor, 200b: transistor, 200b_1: transistor, 200b_2: transistor, 201: capacitance element, 201a: capacitance element, 201a_1: capacitance element, 201a_2: capacitance element, 201b: capacitance element, 201b_1: capacitance element, 201b_2: capacitance element, 202: memory device, 202a: memory device, 2 02a_1: memory device, 202a_2: memory device, 202b: memory device, 202b_1: memory device, 202b_2: memory device, 205: conductor, 205a: conductor, 205b: conductor, 206: conductor, 206a: conductor, 206b: conductor, 210: insulator, 211: insulator, 212: insulator, 214: insulator, 216: insulator, 217: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 2 30C: oxide film, 230d: oxide, 230D: oxide film, 240: conductor, 240a: conductor, 240b: conductor, 240c: conductor, 240d: conductor, 240e: conductor, 240f: conductor, 241: insulator, 241a: insulator, 241b: insulator, 241c: insulator, 241d: insulator, 241e: insulator, 241f: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 243: oxide, 243a: oxide, 243A: oxide film, 243b: oxide, 243B: oxide layer, 246: conductor, 246 a: conductor, 246b: conductor, 246d: conductor, 246e: conductor, 246f: conductor, 248: conductor, 248a: conductor, 248A: conductive film, 248b: conductor, 250: insulator, 250A: insulating film, 251: opening, 260: conductor, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 270: opening, 270a: opening, 270b: opening, 272: insulator, 272a: insulator, 272b: insulator, 273: insulator, 274: insulator, 280: insulator, 282: insulator, 283: insulator, 284: insulator, 286: insulator,287: insulator, 288: insulator, 289: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 600: semiconductor device, 600_1: semiconductor device, 600_2: semiconductor device, 610: cell array, 610_n: cell array, 610_1: cell array, 700: electronic component, 7 02: printed circuit board, 704: mounting substrate, 711: mold, 712: land, 713: electrode pad, 714: wire, 720: memory device, 721: drive circuit layer, 722: memory circuit layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 901: boundary area, 902: boundary area, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector , 1104: Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Housing, 1152: Connector, 1153: Board, 1154: Memory chip, 1155: Memory chip, 1156: Controller chip, 1200: Chip, 1201: PCB, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 12 13: Analog calculation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1470: Memory cell array, 1471: Memory cell, 1472: Memory cell, 1473: Memory cell, 5100: Information terminal, 5101: Housing, 5102: Display unit, 5200: Notebook information terminal, 5201: Main body, 5202: Display unit,5203: keyboard, 5300: portable game console, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection unit, 5306: operation keys, 5400: stationary game console, 5402: controller, 5500: supercomputer, 5501: rack, 5502: calculator, 5504: circuit board, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door,

Claims

1. A semiconductor device having a transistor, a first insulator; and a first conductor having a region located above the first insulator; a second insulator having a region located above the first conductor; a first oxide having a region overlying the second insulator; a second conductor having a region located above the first oxide; a third conductor having a region located above the first oxide; a third insulator having a region located above the second conductor and a region located above the third conductor; a second oxide having a region located above the first oxide; a fourth insulator having a region located above the second oxide; a fourth conductor having a region located above the fourth insulator; a fifth conductor having a region located above the first insulator and below the second insulator, and having a region not overlapping with the second insulator; a fifth insulator having a region in contact with an inner wall of an opening formed in the second insulator, a region in contact with an inner wall of an opening formed in the third insulator, a region in contact with an upper surface and a side surface of the fifth conductor, and a region located above the fourth conductor; a sixth conductor having a region located above the fifth insulator and a region overlapping an upper surface and a side surface of the fifth conductor via the fifth insulator; each of the first conductor and the fifth conductor has a region in contact with an upper surface of the first insulator; In a cross-sectional view of the transistor in a channel length direction, a length of the fifth conductor in the channel length direction is greater than a length of the first conductor in the channel length direction; In the cross-sectional view, the second oxide has a region disposed between the second conductor and the third conductor.

2. In claim 1, The semiconductor device, wherein each of the first oxide and the second oxide is an oxide semiconductor containing In, Ga, and Zn.

3. In claim 1 or 2, A semiconductor device, wherein the third insulator has a region in contact with an upper surface of the second conductor, a region in contact with an upper surface of the third conductor, and a region in contact with a side surface of the first oxide.

4. In any one of claims 1 to 3, a sixth insulator having a region located above the third insulator and below the fifth insulator; a semiconductor device, wherein the second oxide, the fourth insulator, and the fourth conductor each have a region located within an opening provided in the sixth insulator;

5. In claim 4, The fifth insulator has a region in contact with an inner wall of an opening formed in the sixth insulator.

6. In any one of claims 1 to 5, The semiconductor device, wherein the third conductor is electrically connected to the sixth conductor.

Images