Semiconductor Devices

Abstract

To provide a transistor employing an oxide semiconductor film of a self-aligned structure, having high electric characteristics, and imparted with stable electric characteristics.SOLUTION: A semiconductor device comprises a transistor including an oxide semiconductor film on an oxide insulation film, a gate insulation film in contact with the oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film via the gate insulation film, a nitride insulation film in contact with the oxide semiconductor film, and a pair of conductive films in contact with the oxide semiconductor film. The oxide semiconductor film comprises a first region and a second region. The first region is in contact with the gate insulation film, and the second region is in contact with the nitride insulation film and the pair of conductive films. At least the second region includes an impurity element, and has different impurity element concentration than the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these. In particular, one aspect of the present invention relates to a field effect transistor, a driving method thereof, and a manufacturing method thereof. The present invention relates to a semiconductor device having a transistor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called thin-film transistors) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor materials, such as silicon, are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as another material.

[0004] As a transistor using an oxide semiconductor, For example, the channel formation region of a transistor is A gate electrode and a gate insulating film are formed on a part of the oxide semiconductor film. The resistance of the gate electrode of the semiconductor film and the area not covered by the gate insulating film is reduced. The transistor has a self-aligned structure that forms the source region and the drain region. It has been reported (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-220817 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-228622 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, a low-resistance source region and a drain region are formed in a self-aligned manner. In order to achieve this, an interlayer insulating film is formed in a region of the oxide semiconductor film that is not covered with the gate electrode and the gate insulating film. A silicon nitride film is formed as an insulating film by plasma CVD, and the silicon nitride film contains The hydrogen contained in the oxide semiconductor film is introduced into the oxide semiconductor film to form a low-resistance region. In this method, hydrogen may diffuse into the channel formation region, and stable semiconductor characteristics may not be obtained. There was a problem of difficulty in obtaining sex.

[0007] In view of this, one embodiment of the present invention is a transistor using a self-aligned oxide semiconductor film. An object of the present invention is to provide a transistor having excellent electrical characteristics. One embodiment of the present invention provides a method for manufacturing a transistor with little variation in electrical characteristics. Another object of one embodiment of the present invention is to fabricate a display device with reduced power consumption. Another embodiment of the present invention provides a manufacturing method of a novel display device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a method for forming an oxide semiconductor film over an insulating film and a first region of the oxide semiconductor film. a gate electrode overlapping the oxide semiconductor film via the gate insulating film; a nitride insulating film in contact with the second region of the semiconductor film; and a first insulating film in contact with the second region of the oxide semiconductor film. a pair of conductive films, the first region and the second region having different impurity element concentrations; The semiconductor device has a higher impurity element concentration in the second region than in the first region. .

[0010] The impurity element is a rare gas element, and the impurity element is contained in the first region and the second region. Alternatively, the impurity element may be hydrogen, boron, nitrogen, fluorine, aluminum, or lithium. It is included in the second region.

[0011] The nitride insulating film may be a silicon nitride film.

[0012] An oxide insulating film may be provided between the gate electrode and the nitride insulating film. The gate electrode may have the same metal element as the oxide semiconductor film. The insulating film is formed using an oxide semiconductor film having electrical conductivity. [Effects of the Invention]

[0013] According to one embodiment of the present invention, a transistor including a self-aligned oxide semiconductor film can be In the present invention, a transistor having excellent electrical characteristics can be provided. According to one embodiment, a method for manufacturing the transistor with little variation in electrical characteristics is provided. Another embodiment of the present invention provides a method for manufacturing a display device with reduced power consumption. Another embodiment of the present invention is to provide a method for manufacturing a novel display device. This can be done.

[0014] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 7]1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A and 1B are a cross-sectional view and an enlarged view illustrating one embodiment of a semiconductor device. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 14] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; [Figure 15] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 16] 1A and 1B are a block diagram and a circuit diagram of a display device according to an embodiment. [Figure 17] 1. An electronic device according to an embodiment. [Figure 18] FIG. 1 is a diagram illustrating a model used in calculations. [Figure 19] FIG. 10 is a graph for explaining the relationship between donor density and Id-Vg characteristics in the Loff region. [Figure 20] FIG. 1 is a graph for explaining the relationship between the on-state current and the field-effect mobility with respect to the donor density in the Loff region. [Figure 21] FIG. 10 is a graph for explaining the relationship between donor density and Id-Vg characteristics in the Loff region. [Figure 22] FIG. 10 is a diagram illustrating the temperature dependence of resistivity. [Figure 23] 1A and 1B are a cross-sectional view and an enlarged view illustrating a structure of a transistor. [Figure 24] 1A and 1B are a cross-sectional view and an enlarged view illustrating a structure of a transistor. [Figure 25] 1A and 1B are a cross-sectional view and an enlarged view illustrating a structure of a transistor. [Figure 26] A diagram explaining the InGaZnO4 crystal structure. [Figure 27] FIG. 1 is a diagram illustrating the formation energy of hydrogen-related defects. [Figure 28] A diagram explaining the relative energy with respect to the V-O-H distance. [Figure 29] A diagram explaining the pathway and energy changes involved in the escape of hydrogen from VO. [Figure 30] 1 is a diagram illustrating the diffusion path and energy change of hydrogen. [Figure 31] FIG. 1 is a diagram illustrating the formation energy of hydrogen-related defects. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and any deviation from the spirit and scope of the present invention is not permitted. It will be readily understood by those skilled in the art that various modifications can be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the following description of the embodiments. .

[0017] In addition, the position, size, range, etc. of each component shown in the drawings etc. are not necessarily shown in order to facilitate understanding. It may not represent the actual position, size, range, etc. Therefore, the disclosed invention The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0018] In this specification, ordinal numbers such as "first," "second," and "third" refer to the order of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0019] In this specification, the terms "above" and "below" are used to indicate whether the positional relationship of a component is "directly above" or "below." For example, the term "gate electrode on the gate insulating film" does not necessarily mean "directly under" the gate insulating film. If the expression "electrode" is used, it excludes those that include other components between the gate insulating film and the gate electrode. do not.

[0020] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0021] Also, the functions of "source" and "drain" can be changed by using transistors with different polarities. Or, when the direction of the current changes during circuit operation, the positions may be swapped. Therefore, in this specification and the like, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0022] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0023] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. This will be used to explain.

[0024] FIG. 1 shows a top-gate self-aligned transistor as an example of a transistor included in a semiconductor device. 1 shows a cross-sectional view of a transistor having an in-structure.

[0025] The transistor shown in FIG. 1 includes an insulating film 53 formed on a substrate 51 and a gate insulating film 54 formed on the insulating film 53. The oxide semiconductor film 55 is formed on the gate insulating film 57 in contact with the oxide semiconductor film 55. a gate electrode 59 in contact with the oxide semiconductor film 57 and overlapping with the oxide semiconductor film 55 . The oxide semiconductor film 55 has a first region 55a and a second region sandwiching the first region 55a. The gate electrode 59 has the first region 55b and the second region 55c of the oxide semiconductor film 55. In the transistor, the nitride insulating layer in contact with the second regions 55b and 55c overlaps with the nitride insulating layer 55a. A veneer 65 is provided.

[0026] An insulating film 67 in contact with the nitride insulating film 65 may be provided in the transistor. In the openings of the nitride insulating film 65 and the insulating film 67, the second region of the oxide semiconductor film 55 is A pair of conductive films 68 and 69 in contact with the transistors 55b and 55c may be provided in the transistor.

[0027] In the oxide semiconductor film 55, the first region 55a and the second regions 55b and 55c are The concentration of impurity elements varies. Typical examples of impurity elements are hydrogen, boron, nitrogen, and fluorine. , aluminum, phosphorus, and rare gas elements. Representative examples of rare gas elements include helium, These include neon, argon, krypton, and xenon.

[0028] The impurity element is a rare gas element, and the oxide semiconductor film 55 is formed by a sputtering method. In this case, the first region 55a and the second regions 55b and 55c each contain a rare gas element. Furthermore, the second regions 55b and 55c have a higher concentration of rare gas elements than the first region 55a. This is because when the oxide semiconductor film 55 is formed by a sputtering method, the sputtering Since a rare gas is used as the ring gas, the rare gas is contained in the oxide semiconductor film 55. In order to form oxygen vacancies in the first and second regions 55b and 55c, a rare gas is intentionally added. This is because the second regions 55b and 55c are larger than the first region 55a. A rare gas element different from the above may be added.

[0029] If the impurity element is hydrogen, boron, nitrogen, fluorine, aluminum, or phosphorus, the second Therefore, the impurity element is contained only in the first region 55b and the second region 55c. Therefore, the second regions 55b and 55c have a higher concentration of the impurity element.

[0030] In the oxide semiconductor film 55, the first region 55a and the second regions 55b and 55c Specifically, the second region 55a has a higher hydrogen concentration than the first region 55b. b and 55c have a higher concentration of hydrogen.

[0031] The oxide semiconductor film 55 is in contact with the nitride insulating film 65, and thus the oxide semiconductor film 55 is The contained hydrogen diffuses into the second regions 55b and 55c of the oxide semiconductor film 55. As a result, Compared to the first region 55a, the second regions 55b and 55c have a higher concentration of hydrogen.

[0032] Secondary ion mass spectrometry (SIMS) of the second regions 55b and 55c The hydrogen concentration obtained by ion mass spectrometry was 8×10 1 9 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 Above, preferably is 5 x 10 20 atoms / cm 3 The above is the case. The secondary ion mass in the first region 55a The hydrogen concentration obtained by quantitative analysis is 5×10 19 atoms / cm 3 Below, preferably 1×10 19 atoms / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 below , preferably 1 x 10 18 atoms / cm 3 Less than or equal to 5 x 10 17 atoms / cm 3 Less than 1 × 10 16 atoms / cm 3 The following is the result.

[0033] By setting the hydrogen concentration in the first region 55a within the above range, the capacitance in the first region 55a can be reduced. As a result, the transistor can suppress the generation of electrons at the threshold voltage. It has electrical characteristics in which the value voltage is positive (also called normally-off characteristics).

[0034] The resistivity of the oxide semiconductor film increases due to the interaction between oxygen vacancies and hydrogen contained in the oxide semiconductor film. Specifically, hydrogen enters oxygen vacancies in the oxide semiconductor film, and the capacitance is reduced. As a result, the conductivity of the oxide semiconductor film 55 increases. The second regions 55b and 55c have a higher hydrogen concentration than the first region 55a. The amount of oxygen deficiency due to the addition of impurity elements is large. Therefore, typically, the second region 55b, The resistivity of 55c is 1×10 -3 Ωcm or more 1×10 4 less than Ωcm, more preferably Resistivity is 1×10 -3Ωcm or more 1×10 -1 It is less than Ωcm.

[0035] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, oxygen Hydrogen enters the vacancy site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. The oxide semiconductor that has become a conductor is called an oxide conductor. Generally, oxide semiconductors have a large energy gap, so they are sensitive to visible light. On the other hand, oxide conductors are oxides that have a donor level near the conduction band. Therefore, the influence of absorption due to the donor level is small, and the oxide is not sensitive to visible light. It has the same level of transparency as nitride semiconductors.

[0036] Therefore, in the transistor, the second regions 55b and 55c are formed of an oxide conductor. The second regions 55b and 55c function as low resistance regions. The transistor having the structure shown in FIG. 1 has a high on-state current.

[0037] In addition, in the transistor described in this embodiment, an impurity element is added to the second regions 55b and 55c. By adding hydrogen, oxygen vacancies are formed and hydrogen is added. It is possible to reduce the resistivity of 55b and 55c and to Therefore, it is possible to reduce the variation in resistivity of the second regions 55b and 55c. By adding an impurity element to the second region, the resistivity of the second regions 55b and 55c can be controlled. is possible.

[0038] The configuration shown in FIG. 1 will be described in detail below.

[0039] The substrate 51 can be made of various substrates and is not limited to a specific one. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI Substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, Stainless steel foil substrate, tungsten substrate, tungsten foil substrates, flexible substrates, laminated films, papers containing fibrous materials, or substrate films Examples of glass substrates include barium borosilicate glass and aluminoboron. Silicate glass or soda lime glass, etc. Flexible substrates, laminated films Examples of the base film include the following: Polyethylene naphthalate (PET), polyethylene naphthalate (PEN), polyether sulfonate Plastics such as acrylic are also used. Examples include polypropylene, polyester, and polyfluoride. vinyl, or polyvinyl chloride. Alternatively, for example, polyamide, polyimide, These include materials such as amide, aramid, epoxy, inorganic vapor deposition film, and paper. By manufacturing transistors using a silicon substrate, single crystal substrate, or SOI substrate, Small size, high current capability, and low variation in characteristics, size, or shape. When a circuit is constructed using such transistors, This makes it possible to reduce the power consumption of the circuit or to increase the integration density of the circuit.

[0040] In addition, a flexible substrate is used as the substrate 51, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 51 and the transistor. After a semiconductor device is partially or entirely completed on it, it is separated from the substrate 51 and mounted on another substrate. In this case, the transistors are mounted on substrates with poor heat resistance or flexible substrates. The above-mentioned peeling layer may be formed of, for example, a tungsten film and a silicon oxide film. A laminated structure of an inorganic film and a substrate, or a structure in which an organic resin film such as polyimide is formed on a substrate etc. can be used.

[0041] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Lum substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It can be used to create devices that are less prone to breakage, heat resistant, lightweight, or thin. .

[0042] The insulating film 53 can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 55, At least a region in contact with the oxide semiconductor film 55 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 53, This allows oxygen contained in the insulating film 53 to move to the oxide semiconductor film 55. Therefore, it is preferable.

[0043] The insulating film 53 may be, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. , silicon nitride film, aluminum oxide film, hafnium oxide film, gallium oxide film or Ga A Zn oxide film or the like may be used, and may be provided as a laminated layer or a single layer.

[0044] The oxide semiconductor film 55 is typically an In—Ga oxide film, an In—Zn oxide film, or an In -M-Zn oxide film (M is Al, Ga, Y, Zr, Sn, La, Ce, or Nd), etc. The oxide semiconductor film 55 is formed using a metal oxide film. Note that the oxide semiconductor film 55 has a light-transmitting property.

[0045] When the oxide semiconductor film 55 is an In-M-Zn oxide, the atomic ratio of In to M is When the sum of In and M is 100 atomic %, In is less than 25 atomic %. More preferably, M is less than 75 atomic %, and more preferably In is more than 34 atomic %. and M is less than 66 atomic %.

[0046] The oxide semiconductor film 55 has an energy gap of 2 eV or more, preferably 2.5 eV or more. , and more preferably 3 eV or more.

[0047] The thickness of the oxide semiconductor film 55 is 3 nm to 200 nm, preferably 3 nm to 100 nm. 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0048] The oxide semiconductor film 55 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, Sn, L In the case of In-Zn-Mn oxide films, the sputtering agent used to deposit the In-Mn-Zn oxide film is The atomic ratio of the metal elements in the plating target preferably satisfies In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn. =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, I n:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1 The atomic ratio of the oxide semiconductor film 55 to be formed is preferably 0.01:2. The atomic ratio of the metal elements contained in the sputtering target is plus or minus 4. Includes 0% variation.

[0049] In addition, the oxide semiconductor film 55 contains silicon or carbon, which is one of the Group 14 elements. If the oxide semiconductor film 55 is exposed to the oxygen, oxygen vacancies increase in the oxide semiconductor film 55, causing the oxide semiconductor film 55 to become n-type. The concentrations of silicon and carbon in the oxide semiconductor film 55 (obtained by secondary ion mass spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 As a result, the transistor has electrical characteristics in which the threshold voltage is positive. (also called normally-off characteristics).

[0050] In addition, in the oxide semiconductor film 55, alkali metals obtained by secondary ion mass spectrometry The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 Alkali metals and alkaline earth metals are When bonded to a carbide semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal of the oxide semiconductor film 55 may It is preferable to reduce the concentration of the metalloid. As a result, the transistor has a threshold voltage that is higher than that of the transistor. It has a low electrical characteristic (also called a normally-off characteristic).

[0051] Furthermore, when nitrogen is contained in the oxide semiconductor film 55, electrons serving as carriers are generated. As a result, the nitride semiconductor containing nitrogen is used. Therefore, the transistor having the oxide semiconductor film tends to be normally on. Therefore, it is preferable that nitrogen is reduced as much as possible. For example, in secondary ion mass spectrometry, The resulting nitrogen concentration is 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0052] By reducing impurities in the oxide semiconductor film 55, the carrier density of the oxide semiconductor film is reduced. Therefore, the oxide semiconductor film 17 can have a carrier density of 1×10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 Less than 1 × 10 13 pieces / cm 3 Less than 1 × 10 11 pieces / cm 3 The following is the result.

[0053] The oxide semiconductor film 55 is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using this, a transistor with even better electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (low oxygen vacancy) are considered to be high purity pure silicon. High purity intrinsic or substantially high purity intrinsic oxides In semiconductors, the carrier density can be reduced in some cases because there are few carrier sources. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a threshold voltage of 100 V. The electrical characteristics tend to be such that the voltage is positive (also called normally-off characteristics). An oxide semiconductor film that is intrinsic or substantially highly purified and intrinsic has a low density of defect states; The trap level density may also be lower. A certain oxide semiconductor film has a significantly small off-state current and a low voltage ( In the drain voltage range of 1V to 10V, the off-state current is Below the measurement limit of the isa, i.e., 1 × 10 -13 A characteristic of less than A can be obtained. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has fluctuations in electrical characteristics. This may result in a highly reliable transistor.

[0054] The oxide semiconductor film 55 may have a non-single crystal structure, for example. , CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure (described below), or Among non-single crystal structures, the amorphous structure has the highest defect level density and CA AC-OS has the lowest defect level density.

[0055] Note that the oxide semiconductor film 55 has an amorphous structure region, a microcrystalline structure region, and a polycrystalline structure region. The film may be a mixed film having two or more of the following: a CAAC-OS region, a single crystal structure region, and a single crystal structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA region, or the like. In the case of a single-layer structure having two or more regions, either a C-OS region or a single-crystal structure region, The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a polycrystalline structure region. The layer structure has two or more types of regions, namely, a CAAC-OS region, a single crystal structure region, and a This may occur.

[0056] The gate insulating film 57 is formed by forming a single layer or a laminate of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 55, the gate insulating film At least a region of the insulating film 57 that is in contact with the oxide semiconductor film 55 is formed of an oxide insulating film. The gate insulating film 57 is preferably a silicon oxide film, a silicon oxynitride film, a nitride film, or the like. Silicon oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, gallium oxide film A Ga-Zn oxide film or a Ga-Zn oxide film may be used, and the film may be formed as a laminated layer or a single layer. Cut.

[0057] The gate insulating film 57 is an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating film 54, oxygen can be diffused from the oxide semiconductor film 55 to the outside, and oxygen can be diffused from the outside to the oxide semiconductor film 55. It is possible to prevent the intrusion of hydrogen, water, etc. into the membrane 55. Examples of insulating films having such effects include aluminum oxide films, aluminum oxynitride films, and gallium oxide films. gallium oxide film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide film Examples of suitable oxide films include hafnium oxide nitride films and hafnium oxide nitride films.

[0058] The gate insulating film 57 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAlx O y N z ), hafnium oxide, yttrium oxide, etc. The use of k-materials can reduce gate leakage of transistors.

[0059] The thickness of the gate insulating film 57 is 5 nm or more and 400 nm or less, and more preferably 10 nm or more. It is preferable to set the thickness to 300 nm or less, and more preferably to set the thickness to 50 nm or more and 250 nm or less.

[0060] The gate electrode 59 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or nickel. A metal element selected from the group consisting of nickel, iron, cobalt, and tungsten, or a metal element containing the above-mentioned metal elements. The metal layer can be formed by using an alloy containing the metal elements or an alloy combining the above-mentioned metal elements. In addition, the present invention uses a metal element selected from one or more of manganese and zirconium. The gate electrode 13 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, a single layer structure of copper film containing manganese, Two-layer structure with titanium film stacked on aluminum film, two-layer structure with titanium film stacked on titanium nitride film Layer structure, two-layer structure with tungsten film laminated on titanium nitride film, tantalum nitride film or nitride film Two-layer structure with tungsten film laminated on tungsten oxide film, copper film on copper film containing manganese A two-layer structure in which a titanium film is laminated, and an aluminum film is laminated on top of the titanium film. A three-layer structure in which a titanium film is formed on top of the copper film containing manganese, and a copper film is laminated on top of the copper film. There are three-layer structures, such as a copper film containing manganese on top. Elements selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium An alloy film made of one or a combination of elements, or a nitride film may also be used.

[0061] The gate electrode 59 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal element may also be used.

[0062] The nitride insulating film 65 may be silicon nitride, silicon nitride oxide, aluminum nitride, or nitride. The nitride insulating film 65 can be formed using aluminum oxide or the like. Degrees are 1 x 10 22 atoms / cm 3 It is preferable that this is equal to or greater than this.

[0063] The pair of conductive films 68 and 69 may be made of aluminum, titanium, chromium, nickel, copper, yttrium, or the like. aluminum, zirconium, molybdenum, iron, cobalt, silver, tantalum, or tungsten Any metal or alloy containing this metal as its main component is used as a single layer or laminated structure. For example, a single layer structure of aluminum film containing silicon, a single layer structure of copper film containing manganese, a titanium Two-layer structure with aluminum film stacked on top of tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film; Two-layer structure with copper film laminated on tungsten film, two-layer structure with copper film laminated on tungsten film, manganese film Two-layer structure in which a copper film is laminated on a copper film containing titanium or titanium nitride, and An aluminum film or a copper film is laminated on the titanium nitride film or the titanium nitride film, and then a titanium film or a copper film is laminated on the aluminum film or the copper film. A three-layer structure in which a titanium film or titanium nitride film is formed, a molybdenum film or molybdenum nitride film, and Then, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. A three-layer structure in which a molybdenum film or molybdenum nitride film is formed on top of the manganese film. a three-layer structure in which a copper film is laminated on a copper film containing manganese, and a copper film containing manganese is further formed on the copper film It should be noted that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used. stomach.

[0064] The insulating film 67 can be made of the same material as the insulating film 53 or the gate insulating film 57, as appropriate.

[0065] Next, a manufacturing method of the transistor illustrated in FIG. 1 will be described with reference to FIGS.

[0066] Films constituting the transistor 10 (insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) The methods include sputtering, chemical vapor deposition (CVD), vacuum evaporation, and pulsed laser deposition ( Alternatively, it can be formed by a coating method or a printing method. The film formation methods include sputtering and plasma enhanced chemical vapor deposition (PECVD). is a typical example, but thermal CVD may also be used. An example of thermal CVD is MOCVD (metal organic CVD). Chemical vapor deposition (CVD) and atomic layer deposition (ALD) may also be used.

[0067] In the thermal CVD method, the pressure in the chamber is atmospheric or reduced, and the source gas and oxidant are simultaneously mixed. The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0068] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating this gas introduction sequence. By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Simultaneously with or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. Introduce the source gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0069] This gas introduction sequence is repeated multiple times while controlling it until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0070] As shown in FIG. 2A, an insulating film 53 and an oxide semiconductor film 54 are formed on a substrate 51. do.

[0071] The insulating film 53 can be formed by a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD) method, or the like. The insulating film can be formed by using a suitable method such as a printing method or a coating method. After the formation, oxygen is added to the insulating film to form the insulating film 53. The oxygen to be added may be oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The addition method may be an ion doping method, an ion implantation method, a plasma treatment method, etc. There is.

[0072] A method for forming the oxide semiconductor film 54 will be described below. by coating method, coating method, pulsed laser deposition method, laser ablation method, thermal CVD method, etc. An oxide semiconductor film is formed. Next, a mask is formed on the oxide semiconductor film by a lithography process. After the formation, part of the oxide semiconductor film is etched using the mask. ) the oxide semiconductor film 54 can be formed. After that, the mask is removed. do.

[0073] In addition, by using a printing method for the oxide semiconductor film 54, the oxide semiconductor The membrane 54 can be formed directly.

[0074] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma is used. The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like.

[0075] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of the oxygen gas to the rare gas is A higher ratio is preferred.

[0076] The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. .

[0077] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, The temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200°C or higher and 350°C or lower. S film can be formed.

[0078] In addition, in order to form a CAAC-OS film described later, the following conditions are preferably applied: It's nice.

[0079] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0080] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0081] After the oxide semiconductor film is formed, heat treatment is performed to dehydrogenate or The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point. Preferably, the temperature is 250°C or higher and 450°C or lower, and more preferably, 300°C or higher and 450°C or lower. .

[0082] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It is carried out in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. It should be noted that the inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0083] The heat treatment can be carried out using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. The processing time can be reduced.

[0084] The oxide semiconductor film is formed while being heated, and after the oxide semiconductor film is formed, By performing heat treatment, the hydrogen concentration in the oxide semiconductor film is increased to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 at oms / cm 3 Less than 1 x 10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 It can be as follows:

[0085] The film formation equipment using ALD is used to form oxide semiconductor films, such as In-Ga-Zn-O films. When depositing an In-O layer, In(CH3)3 gas and O3 gas are introduced repeatedly in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a Ga-O layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a Zn-O layer. The order of these layers is not limited to this example. In addition, by mixing these gases, an In-Ga-O layer Alternatively, a mixed compound layer such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. Instead of the gas 3, H2O gas bubbled with an inert gas such as Ar may be used. It is preferable to use O3 gas that does not contain In(CH3)3. Alternatively, Ga(CH)3 gas may be used instead of Ga(CH). 5)3 gas may be used. Zn(CH3)2 gas may also be used.

[0086] Here, a 35-nm-thick oxide semiconductor film is formed by a sputtering method. A mask is formed over the oxide semiconductor film, and part of the oxide semiconductor film is selectively etched. Next, after removing the mask, a heat treatment is performed in a mixed gas atmosphere containing nitrogen and oxygen. Then, the oxide semiconductor film 54 is formed.

[0087] The heat treatment is carried out at a temperature higher than 350°C and lower than 650°C, preferably higher than 450°C and lower than 600°C. By carrying out the following, the CAAC conversion rate described below is 60% or more but less than 100%, preferably 80% % or more and less than 100%, preferably 90% or more and less than 100%, more preferably 95% or more and less than 90%. In addition, the oxide semiconductor film can be obtained with a hydrogen content of 8% or less. That is, it is possible to obtain an oxide semiconductor film having a low impurity concentration and a low defect level density. An oxide semiconductor film with a low conductivity can be formed.

[0088] Next, as shown in FIG. 2(B), an insulating film 56 is formed, and then a gate electrode 59 is formed. .

[0089] The insulating film 56 is an insulating film that will become a gate insulating film in a later process. Sputtering method, CVD method, vacuum evaporation method, pulsed laser deposition (PLD) method, thermal CVD method etc. are formed.

[0090] When a silicon oxide film or a silicon oxynitride film is formed as the insulating film 56, the source gas As the gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorinated silane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0091] When a gallium oxide film is formed as the insulating film 56, MOCVD (Metal O Formed using the Organic Chemical Vapor Deposition method It is possible.

[0092] The insulating film 56 is formed by a thermal CVD method such as MOCVD or ALD. To form a hafnium film, a solvent and a liquid containing a hafnium precursor compound (hafnium Alkoxide solution, typically tetrakisdimethylamidohafnium (TDMAH) Two types of gases are used: vaporized raw material gas and ozone (O3) as an oxidizing agent. The chemical formula for thoraxdimethylamidohafnium is Hf[N(CH3)2]4. Other liquid materials include tetrakis(ethylmethylamido)hafnium.

[0093] The insulating film 56 is formed by using a thermal CVD method such as MOCVD or ALD. When forming an aluminum film, a liquid containing a solvent and an aluminum precursor compound (trimethylsilyl) is used. Two types of gases are used: vaporized methylaluminum (TMA, etc.) and H2O as an oxidizer. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionato) In addition, by forming it using the ALD method, it is possible to obtain an insulating film with a high coverage and a thin film thickness. 56 can be formed.

[0094] The insulating film 56 is formed by using a thermal CVD method such as MOCVD or ALD. When forming a silicon film, hexachlorodisilane is adsorbed onto the surface to be filmed, and the adsorbed material contains It removes the chlorine contained in the adsorbent and supplies radicals of oxidizing gases (O2, nitrous oxide). Make it react.

[0095] Here, a silicon oxynitride film is formed as the insulating film 56 by plasma CVD. .

[0096] The gate electrode 59 is formed by the following methods. First, sputtering, vacuum evaporation, A conductive film is formed by pulsed laser deposition (PLD) or thermal CVD, and then lithography is performed on the conductive film. A mask is formed by a lithography process. Then, a part of the conductive film is etched using the mask. This forms the gate electrode 59. After this, the mask is removed.

[0097] The gate electrode 59 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may also be formed by a jet method or the like.

[0098] In addition, a tungsten film can be formed as a conductive film using a film formation device that uses ALD. In this case, WF6 gas and B2H6 gas are introduced repeatedly in sequence to obtain the initial tungsten content. A tungsten film is formed, and then WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. It should be noted that SiH4 gas may be used instead of B2H6 gas.

[0099] Next, as shown in FIG. 2(C), the insulating film 56 is etched using the gate electrode 59 as a mask. Then, the gate insulating film 57 is formed.

[0100] Next, as shown in FIG. 2(D), the oxide semiconductor film 54 is formed using the gate electrode 59 as a mask. As a result, the impurity element 62 is added to the oxide semiconductor film covered with the gate electrode 59. The impurity element 62 is added to the undoped region. When the oxide semiconductor film is subjected to the stress, defects, typically oxygen vacancies, are formed in the oxide semiconductor film.

[0101] The impurity element 62 can be added by ion doping, ion implantation, plasma treatment, or the like. There are principles, laws, etc.

[0102] The addition of the impurity element 62 can be controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when argon is added by ion implantation, the acceleration voltage is 10 kV and the dose is 10 kV. The amount is 1 x 10 13 ions / cm 2 More than 1×10 16 ions / cm 2 The following would suffice: , e.g., 1 x 10 14 ions / cm 2 In addition, phosphorus ions can be implanted by ion implantation. When adding ions, the acceleration voltage is 30 kV and the dose is 1 × 10 13 ions / cm 2 End 5×10 16 ions / cm2 For example, 1×10 15 ions / cm 2 This can be done as follows.

[0103] Note that instead of the impurity element 62, an oxide semiconductor film 54 is irradiated with ultraviolet light or the like to form an oxide Oxygen vacancies may be formed in the semiconductor film 54. Alternatively, the oxide semiconductor film 54 may be irradiated with laser light. By irradiating the oxide semiconductor film 54 with oxygen, oxygen vacancies may be formed in the oxide semiconductor film 54.

[0104] Next, as shown in FIG. 3A, the oxide semiconductor film 54, the gate insulating film 57, and the gate A nitride insulating film 64 is formed on the electrode 59. The nitride insulating film 64 is formed by a method such as These include the sputtering method, CVD method, vacuum evaporation method, and pulsed laser deposition (PLD) method.

[0105] Since the nitride insulating film 64 contains hydrogen, the impurities in the oxide semiconductor film 54 When the region to which the element is added comes into contact with the nitride insulating film 64, the element contained in the nitride insulating film 64 The hydrogen moves to a region of the oxide semiconductor film to which the impurity element is added. As a result, the first region 55a to which no impurity element is added and the second region 55b to which the impurity element and hydrogen are added are formed. The oxide semiconductor film 55 having the regions 55b and 55c is formed. Since the hydrogen contained in the second regions 55b and 55c is partially diffused, a part of the second regions 55b and 55c is in contact with the gate electrode. It may overlap with the insulating film 57 .

[0106] The second regions 55b and 55c sandwich the first region 55a.

[0107] The second regions 55b and 55c are formed by oxygen deficiency and water deficiency caused by the addition of impurity elements. The interaction between oxygen vacancies and hydrogen makes the second regions 55b and 55c conductive. That is, the second regions 55b and 55c become low resistance regions.

[0108] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher. Less than the strain point, preferably 200°C or more and 450°C or less, more preferably 300°C or more and 450°C or less ° C. or less. This step further increases the conductivity of the second regions 55b and 55c.

[0109] Next, as shown in Fig. 3(B), an insulating film 66 may be formed. This reduces the parasitic capacitance between the pair of conductive films to be formed later and the gate electrode 59. It can be reduced.

[0110] Next, openings are formed in the nitride insulating film 64 and the insulating film 66, and the second regions 55b and 55c are After exposing a part of the conductive film 68, 69, a pair of conductive films 68 and 69 are formed (see FIG. 3(C)).

[0111] The pair of conductive films 68 and 69 can be formed by the same method as that for the gate electrode 59. do.

[0112] Through the above steps, a transistor can be manufactured.

[0113] In the transistor described in this embodiment, a gate electrode 59 and a pair of conductive films 68 and 69 are overlapped. Since there is no region where the parasitic capacitance is reduced, the on-current is large. The transistor described in this embodiment can stably form a region with low resistivity; Compared to the above, the on-state current is improved and the variation in electrical characteristics is reduced.

[0114] <Transistor Id-Vg characteristics and donor density in the offset region> Here, we calculate the Id-Vg characteristics of the transistor and the donor density in the offset region. The results are explained below.

[0115] The model used for the calculation is shown in Figure 18. The transistor shown in Figure 18 is made up of a substrate 51 and a An insulating film 52 formed on a plate 51, an insulating film 53 formed on the insulating film 52, and an insulating film 5 3 and a gate insulating film 57 in contact with the oxide semiconductor film 55. and a gate electrode 59 in contact with the gate insulating film 57. has a first region 55a and second regions 55b and 55c sandwiching the first region 55a. The gate electrode 59 overlaps with the first region 55a of the oxide semiconductor film 55. 5b denotes a source region or a drain region (hereinafter referred to as an S / D region) that is in contact with the conductive film 68. ) 55b_2 and an offset region (hereinafter referred to as The lower region is called the Loff region.) 55b_1 and the region 55b_3. The region 55c includes an S / D region 55c_2 in contact with the conductive film 69, and a first region 55a and an S / D region 55c_2 in contact with the conductive film 69. The Loff region 55c_1 between the regions 55c_2 and 55c_3. The regions 55b_1 and 55c_1 do not overlap with the gate electrode 59. A nitride insulating film 65 is provided in contact with the second region 55b and the second region 55c.

[0116] An insulating film 67 in contact with the nitride insulating film 65 is provided on the transistor. In the openings of the film 65 and the insulating film 67, the second regions 55b and 55c of the oxide semiconductor film 55 are exposed. A pair of conductive films 68 and 69 in contact with the transistor c are provided in the transistor.

[0117] Next, the parameters used in the calculation are shown in Table 1.

[0118] [Table 1]

[0119] The transistor has Loff regions 55b_1 and 55c_1. When the donor density of _1, 55c_1 is small, the Loff regions 55b_1, 55c_1 become parasitic. This becomes a resistance, which causes a decrease in the on-state current. Using the parameters shown in 1, the donor densities of the Loff regions 55b_1 and 55c_1 are calculated as follows: The relationship between the Id-Vg characteristics of the transistor was calculated. The donor density in the Loff region was set to 1×10 14 [1 / cm 3 ], 1×10 15 [1 / cm 3 ], 1×10 16 [1 / cm 3 ], 1× 10 17 [1 / cm 3 ], 1×10 18 [1 / cm 3 ], 1×10 19 [1 / cm 3 ]and FIG. 19 shows the results of calculating the Id-Vg characteristics of the transistor.

[0120] As can be seen from the graph in Figure 19, when the donor density in the Loff region is low, On the other hand, when the donor density in the Loff region is high, No degradation in on-current or mobility was observed, and excellent Id-Vg characteristics were obtained.

[0121] Next, in Figure 20, the on-current and mobility (maximum saturated mobility) are plotted against the donor density. In FIG. 20, the left vertical axis represents the on-state current, the right vertical axis represents the mobility, The horizontal axis represents the index of donor density in the Loff region. indicates the on-state current when the gate voltage is 10V, and the triangles indicate the on-state current when the gate voltage is 20V. The on-state current is shown, and the diamonds indicate the mobility when the gate voltage is 10V.

[0122] As can be seen from Figure 20, in order to obtain excellent on-current and mobility, the following conditions must be met in an ideal transistor: is at least 1×10 18 [1 / cm 3 ] donor must be added to the Loff region. It can be seen that:

[0123] Next, to investigate the saturation characteristics of the transistor, the Id-Vd characteristics were calculated as shown in Figure 2. 1. In FIG. 21, the scale of the vertical axis differs for each graph.

[0124] In the Id-Vd characteristics shown in Figure 21, the donor density in the Loff region is 1×10 17 [ 1 / cm 3 In the following model, the shape of the Id-Vd curve in the linear region is similar to that of a normal FET. On the other hand, the donor density in the Loff region is 1×10 18 [1 / cm 3 ]The above models show excellent characteristics in both the linear and saturated regions.

[0125] From the above calculation results, it is at least 1 × 10 18 [1 / cm 3 ] donor in the Loff region By introducing this material, it is possible to fabricate transistors with excellent Id-Vd characteristics. I understand.

[0126] <Oxide conductor film> Here, the resistance in a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film) The temperature dependency of resistivity will be explained with reference to FIG.

[0127] Here, a sample having an oxide conductor film was fabricated. The oxide conductor film (OC_SiN) formed by the semiconductor film contacting the silicon nitride film x ) In the doping device, argon is added to the oxide semiconductor film, and the silicon nitride film is The oxide conductive film (OC_Ar doped + SiN x ), or In the plasma processing device, the oxide semiconductor film is exposed to argon plasma and silicon nitride is The oxide conductive film formed by contacting with the film (OC_Ar plasma + SiN x )of The silicon nitride film contains hydrogen.

[0128] Oxide conductor film (OC_SiN x The method for preparing a sample containing the SiO2 film is as follows: After forming a silicon oxynitride film with a thickness of 400 nm by plasma CVD, By exposing the silicon oxynitride film to plasma and adding oxygen ions to it, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. On the silicon film, an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1.2 was deposited. The sputtering method used for the sputtering target produced a 100 nm thick In-Ga -Zn oxide film was formed, and then heat-treated in a nitrogen atmosphere at 450 °C. The film was then heat-treated in a mixed gas atmosphere of oxygen and nitrogen. Next, a 100 nm thick film of nitrogen was deposited on the film by plasma CVD. Next, a heat treatment was performed in a mixed gas atmosphere of nitrogen and oxygen at 350°C. Ta.

[0129] Oxide conductor film (OC_Ar doped + SiN x The preparation method of the sample containing A 400 nm thick silicon oxynitride film was formed on a glass substrate by plasma CVD. After the formation, the silicon oxynitride film is exposed to oxygen plasma to add oxygen ions to the film. A silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, an In-Ga layer with an atomic ratio of In:Ga:Zn=1:1:1.2 was formed. -Zn oxide was used as the sputtering target to form a 100 mm thick film. After forming an In-Ga-Zn oxide film with a thickness of 4 nm, the film was heat-treated in a nitrogen atmosphere at 450°C. The substrate was then heat-treated at 50°C in a mixed gas atmosphere of nitrogen and oxygen. , the In-Ga-Zn oxide film was subjected to irradiation at an acceleration voltage of 10 kV and a dose of 5 × 10 14 / c m 2 Argon was added to form oxygen vacancies in the In-Ga-Zn oxide film. A silicon nitride film with a thickness of 100 nm was formed by plasma CVD. The heat treatment was carried out in a mixed gas atmosphere of SiO 2 and oxygen.

[0130] Oxide conductor film (OC_Ar plasma + SiN x The sample preparation method including A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. After forming the silicon oxynitride film, it is exposed to oxygen plasma to release oxygen when heated. Next, a silicon oxynitride film with an atomic ratio of I was formed on the silicon oxynitride film, which releases oxygen when heated. Sputtering target: In-Ga-Zn oxide with n:Ga:Zn=1:1:1.2 A 100 nm thick In-Ga-Zn oxide film was formed by the sputtering method used in After heat treatment in a nitrogen atmosphere at 450°C, Next, argon plasma was generated in a plasma processing device and accelerated. Oxygen vacancies were formed by bombarding the In-Ga-Zn oxide film with argon ions. Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen at 0°C.

[0131] Next, the resistivity of each sample was measured and the results are shown in Figure 22. Here, the resistivity was measured using a four-terminal In FIG. 22, the horizontal axis indicates the measurement temperature, and the vertical axis indicates the indicates the resistivity. x ) measurement results are indicated by square marks, Oxide conductor film (OC_Ar doped + SiN x The measurement results of oxide conductors are shown by circles. Electrical film (OC_Ar plasma+SiN x ) measurement results are indicated by triangles.

[0132] Although not shown, the oxide semiconductor film that is not in contact with the silicon nitride film has a high resistivity. Therefore, it is considered that the oxide conductor film has a higher resistivity than the oxide semiconductor film. It is clear that it is low.

[0133] As can be seen from FIG. 22, the oxide conductor film (OC_Ar doped+SiN x ) and acid Compound conductor film (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen The resistivity fluctuation is small. Typically, the resistivity fluctuation is small between 80K and 290K. The resistivity fluctuation is less than ±20%. Or, the resistivity fluctuation is less than ±20% between 150K and 250K. The coefficient is less than ±10%. Therefore, it is assumed that the oxide conductor film is By using it as the source and drain regions of a transistor, the oxide conductor film and the source The contact with the conductive film that functions as the electrode and drain electrode is an ohmic contact, and the oxide conductive The contact resistance between the conductive film and the conductive film that functions as the source electrode and the drain electrode can be reduced. In addition, since the resistivity of the oxide conductor has low temperature dependency, the oxide conductor film and the source electrode and drain electrode can be easily formed. The amount of change in contact resistance with the conductive film that functions as the drain electrode is small, resulting in highly reliable transistors. It is possible to create a star.

[0134] <Variation 1> Here, modifications of the transistor described in this embodiment will be described with reference to FIGS. 23 to 25. The transistor shown in FIG. 23 is formed on an insulating film 824 on a substrate 821. the oxide semiconductor film 828, the insulating film 837 in contact with the oxide semiconductor film 828, and the insulating film 83 and a conductive film 840 which is in contact with the insulating film 7 and overlaps with the oxide semiconductor film 828. The conductive film 837 functions as a gate insulating film. It has all the functions.

[0135] The insulating film 846 in contact with the oxide semiconductor film 828 and the insulating film 846 The transistor is provided with an insulating film 846 and an insulating film 847. In the portion, conductive films 856 and 857 in contact with the oxide semiconductor film 828 are provided in the transistor. The conductive films 856 and 857 function as a source electrode and a drain electrode. In addition, an insulating film 862 in contact with the insulating film 847 and the conductive films 856 and 857 is provided. It is being done.

[0136] Note that components of the transistor described in this embodiment, conductive films and The insulating film and the conductive film may be formed in contact with the transistor structure shown in other embodiments. and insulating films can be used as appropriate.

[0137] In the transistor illustrated in FIG. 23A, the oxide semiconductor film 828 is A region 828a formed in the overlapping region and a region containing an impurity element sandwiching the region 828a The conductive films 856 and 857 have the regions 828b and 828c. The region 828a functions as a channel region. The regions 828b and 828c , the resistivity is lower than that of the region 828a, and it can be said that the region 828b and 828c function as a source region and a drain region.

[0138] Alternatively, in the transistor illustrated in FIG. 23B, in the oxide semiconductor film 828, The regions 828d and 828e in contact with the conductive films 856 and 857 are not doped with impurity elements. In this case, the regions 828d and 828e in contact with the conductive films 856 and 857 and the region 8 Between the region 82 and the region 82a, regions 828b and 828c containing impurity elements are provided. When a voltage is applied to the conductive films 856 and 857, the conductive films 828d and 828e become conductive. It functions as a source region and a drain region.

[0139] Note that the transistor shown in FIG. 23B is formed by forming the conductive films 856 and 857. The film 840 and the conductive films 856 and 857 are used as masks to add an impurity element to the oxide semiconductor film. By doing so, it can be formed.

[0140] The conductive film 840 may have a tapered edge. The angle θ1 between the surface where the film 837 and the conductive film 840 come into contact and the side surface of the conductive film 840 is 90°. or 10° or more and 85° or less, or 15° or more and 85° or less, or 30° or more and 8 It may be 5° or less, or 45° to 85°, or 60° to 85°. The angle θ1 is set to less than 90°, or 10° or more and 85° or less, or 15° or more and 85° or less, Or 30° to 85°, or 45° to 85°, or 60° to 85° By setting the insulating film 837 and the conductive film 840 at the lower side, the insulating film 846 can cover the side surfaces of the insulating film 837 and the conductive film 840. It is possible to increase it.

[0141] Next, modified examples of the regions 828b and 828c will be described. 23(F) is an enlarged view of the oxide semiconductor film 828 and its vicinity shown in FIG. The channel length L is the distance between the regions containing a pair of impurity elements.

[0142] As shown in FIG. 23C, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is aligned with the edge of the conductive film 840 via the insulating film 837. That is, in the top view, the area 828a and the area 828b are the same or substantially the same. The boundary of c coincides or almost coincides with the edge of the conductive film 840.

[0143] Alternatively, as shown in FIG. 23(D), in the cross section in the channel length direction, a region 828 a has a region that does not overlap with the edge of the conductive film 840. The region is an offset region. The length of the offset region in the channel length direction is L off It is shown as follows. If there are multiple offset areas, the length of each offset area is L off That is said. o ff is included in the channel length L. Also, L off is less than 20% of the channel length L, and is less than 10%, or less than 5%, or less than 2%.

[0144] Alternatively, as shown in FIG. 23(E), in the cross section in the channel length direction, a region 828 b and 828c have a region overlapping with the conductive film 840 with the insulating film 837 interposed therebetween. Functions as an overlap region. Overlap region in the channel length direction The length of L ov L ov is less than 20% of the channel length L, or less than 10%, or is less than 5% or less than 2%.

[0145] Alternatively, as shown in FIG. 23(F), in the cross section in the channel length direction, a region 828 and region 828f between region 828a and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap with the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0146] 23C to 23F, the transistor shown in FIG. As explained above, the transistor shown in FIG. 23(B) can also be used in the same manner as in FIGS. The structure of F) can be applied as appropriate.

[0147] In the transistor shown in FIG. 24A, the edge of the insulating film 837 is closer to the edge of the conductive film 840 than the edge of the insulating film 837. That is, the insulating film 837 has a shape that protrudes from the conductive film 840. Since the insulating film 846 can be separated from the region 828a, Preventing nitrogen, hydrogen, etc. from entering the region 828a that functions as the channel region can be done.

[0148] In the transistor shown in FIG. 24B, the insulating film 837 and the conductive film 840 have tapered shapes. The angles of the tapered portions are different. The angle θ1 between the surface of the oxide semiconductor film 828 and the side surface of the conductive film 840 and the insulating film 83 The angle θ2 between the surface where 9 contacts and the side surface of the insulating film 837 is different. It may be less than 0°, or between 30° and 85°, or between 45° and 70°. For example, if the angle θ2 is greater than the angle θ1, the insulating film 846 can be moved away from the region 828a. Therefore, nitrogen, hydrogen, etc. contained in the insulating film 846 function as a channel region. In addition, the insulating film 846 can be prevented from entering the region 828a. Furthermore, if the angle θ2 is smaller than the angle θ1, the transistor can be miniaturized.

[0149] Next, regarding the modified examples of the regions 828b and 828c, FIGS. 24(C) to 24(F) are used. 24(C) to 24(F) are diagrams showing the oxide semiconductor shown in FIG. 8 is an enlarged view of the vicinity of the membrane 828. FIG.

[0150] As shown in FIG. 24C, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is aligned with the end of the conductive film 840 via the insulating film 837. That is, in the top view, the area 828a and the area 828b are the same or substantially the same. The boundary of 8c coincides or almost coincides with the edge of the conductive film 840.

[0151] Alternatively, as shown in FIG. 24(D), in the cross section in the channel length direction, a region 828 a has a region that does not overlap with the conductive film 840. This region functions as an offset region. That is, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating film 837. The conductive film 840 is aligned or substantially aligned with the end of the conductive film 840 and does not overlap the end of the conductive film 840.

[0152] Alternatively, as shown in FIG. 24(E), in the cross section in the channel length direction, a region 828 b and 828c have regions that overlap with the conductive film 840 with the insulating film 837 interposed therebetween. In other words, in the top view, the ends of the regions 828b and 828c are called overlapping regions. , overlapping the conductive film 840.

[0153] Alternatively, as shown in FIG. 24(F), in the cross section in the channel length direction, a region 828 and region 828f between region 828a and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap with the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0154] 24C to 24F, the transistor shown in FIG. As explained above, the transistor shown in FIG. 24(B) can also be used in the same manner as in FIGS. The structure of F) can be applied as appropriate.

[0155] In the transistor shown in FIG. 25A, the conductive film 840 has a stacked structure, and the insulating film 837 The conductive film 840b is in contact with the conductive film 840a. The end of the conductive film 840a is located outside the end of the conductive film 840b. a has a shape that protrudes from the conductive film 840b.

[0156] Next, modified examples of the regions 828b and 828c will be described. 25(E) is an enlarged view of the vicinity of the oxide semiconductor film 828 shown in FIG. 25(A).

[0157] As shown in FIG. 25B, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is the end of the conductive film 840a included in the conductive film 840 and the insulating film 840b. The film 837 is aligned or substantially aligned with the region 828a. The boundaries of the regions 828b and 828c coincide or substantially coincide with the edges of the conductive film 840. do.

[0158] Alternatively, as shown in FIG. 25C, in the cross section in the channel length direction, a region 828 a has a region that does not overlap with the conductive film 840. This region functions as an offset region. That is, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the conductive film 840. Does not overlap with the department.

[0159] Alternatively, as shown in FIG. 25(D), in the cross section in the channel length direction, a region 828 The regions 828b and 828c overlap with the conductive film 840, here the conductive film 840a. In other words, in the top view, the ends of the regions 828b and 828c are called overlap regions. However, it overlaps with the conductive film 840a.

[0160] Alternatively, as shown in FIG. 25(E), in the cross section in the channel length direction, a region 828 and region 828f between region 828a and region 828c. The impurity element passes through the conductive film 840a and is added to the regions 828f and 828g. Therefore, the regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g have a low conductivity and a high resistivity. However, the conductive film 840a and the conductive film 840b may overlap with each other.

[0161] Note that the edge of the insulating film 837 may be located outside the edge of the conductive film 840a.

[0162] Alternatively, the side surface of the insulating film 837 may be curved.

[0163] Alternatively, the insulating film 837 may have a tapered shape. The angle between the surface of the insulating film 837 and the side of the insulating film 837 is less than 90°, preferably 3 It may be greater than or equal to 0° and less than 90°.

[0164] As shown in FIG. 25E, the oxide semiconductor film 828 is By having regions 828f and 828g with low impurity element concentrations and high resistivity, Therefore, the electric field in the drain region can be reduced. It is possible to reduce degradation such as fluctuations in threshold voltage.

[0165] <Variation 2> In this embodiment, the gate electrode 59 is formed using a conductive film. Similarly to the second regions 55b and 55c, a conductive oxide semiconductor film is used to form the gate. An electrode 59a may be formed (see FIG. 4). Since the semiconductor film 55 has a light-transmitting property, a light-transmitting transistor can be manufactured. can be done.

[0166] Note that a conductive oxide semiconductor film has a higher resistivity than a conductive film formed of a metal. Therefore, when a large-area substrate is used as the substrate 51, the conductive layer connected to the gate electrode 59a Preferably, the film 77 is provided on the insulating film 67 .

[0167] A manufacturing method of the transistor shown in FIG. 4 will be described with reference to FIGS.

[0168] In the step of FIG. 2B, an oxide semiconductor film is formed instead of the gate electrode 59.

[0169] Next, as shown in FIG. 2C, after forming the gate insulating film 57, the oxide semiconductor film 54 An impurity element 62 is added to the oxide semiconductor film over the gate insulating film 57 .

[0170] Next, as shown in FIG. 3A, a nitride insulating film 64 is formed to form the oxide semiconductor film. Similar to the second regions 55b and 55c included in the second region 55, the second region 55b has a conductive oxide semiconductor film. A gate electrode 59a (see FIG. 4) can be formed.

[0171] Next, an insulating film 67 having an opening is formed, and then, similarly to the pair of conductive films 68 and 69, a gate electrode is formed. A conductive film 77 (see FIG. 4) is formed to be connected to the port electrode 59a.

[0172] Through the above steps, a transistor with a self-aligned structure can be manufactured.

[0173] <Variation 3> In this embodiment, the nitride insulating film 65 is in contact with the oxide semiconductor film 55. As shown in Fig. 1B, even if an insulating film 56 is provided between the nitride insulating film 64 and the oxide semiconductor film 55, The insulating film 56 shown in FIG. 5B functions as a gate insulating film. In this case, the thickness of the nitride insulating film 64 is preferably such that hydrogen contained in the nitride insulating film 64 diffuses into the oxide semiconductor film 55. Typically, the thickness is 1 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less, or The thickness can be set to 10 nm or more and 30 nm. The manufacturing method will be explained below.

[0174] After the steps of FIG. 2(A) and FIG. 2(B), an insulating film is formed on a substrate 51 as shown in FIG. 5(A). The oxide semiconductor film 53, the oxide semiconductor film 55, the insulating film 56, and the gate electrode 59 are formed. The impurity element 62 is added to the compound semiconductor film 55. At this time, the concentration profile of the impurity element 62 is It is preferable to add the impurity element 62 so that the peak of the peak is located in the oxide semiconductor film 55. Desirable.

[0175] Next, as shown in FIG. 5B, a nitride insulating film 64 is formed to add impurity elements. The first region 55a is not doped with impurity elements, and the second region 55b contains impurity elements and hydrogen. The oxide semiconductor film 55 having the structure c can be formed.

[0176] After that, similarly to the first embodiment, an insulating film 67 and a pair of conductive films 68 and 69 are formed. You may do so.

[0177] <Variation 4> A method for manufacturing a transistor using a method different from that of this embodiment will be described. In this example, the timing of doping impurities is different from the manufacturing method shown in FIGS. do.

[0178] After the steps of FIGS. 2A and 2B, an insulating film is formed on a substrate 51 as shown in FIG. 6A. The oxide semiconductor film 53, the oxide semiconductor film 54, the insulating film 56, and the gate electrode 59 are then formed. The impurity element 62 is added to the compound semiconductor film 54. At this time, the concentration profile of the impurity element is It is preferable to add the impurity element 62 so that the peak is located in the oxide semiconductor film 54. stomach.

[0179] Next, as shown in FIG. 6(B), the insulating film 56 is etched using the gate electrode 59 as a mask. Then, the gate insulating film 57 is formed.

[0180] Next, as shown in FIG. 6(C), a nitride insulating film 64 is formed to add impurity elements. The first region 55a is not doped with impurity elements, and the second region 55b contains impurity elements and hydrogen. The oxide semiconductor film 55 having the structure c can be formed.

[0181] After that, similarly to the first embodiment, an insulating film 67 and a pair of conductive films 68 and 69 are formed. You may do so.

[0182] <Variation 5> A method for manufacturing a transistor using a method different from that of this embodiment will be described. In this example, the timing of doping impurities is shorter than that of the fabrication methods shown in FIGS. The processing is different.

[0183] After the steps of FIGS. 2(A) to 2(C), an insulating film is formed on the substrate 51 as shown in FIG. 7(A). An insulating film 53, an oxide semiconductor film 54, a gate insulating film 57, and a gate electrode 59 are formed.

[0184] Next, as shown in FIG. 7B, a nitride insulating film 64 is formed. As a result, an oxide semiconductor Hydrogen migrates to a part of the membrane 54 .

[0185] Next, as shown in FIG. 7C, an impurity element 62 is added to the oxide semiconductor film 54. At this time, the peak of the concentration profile of the impurity element is positioned in the oxide semiconductor film 54. It is preferable to add the impurity element 62. By the above steps, the impurity element is not added. The first region 55a contains impurity elements and hydrogen, and the second regions 55b and 55c contain impurity elements and hydrogen. An oxide semiconductor film 55 can be formed.

[0186] After that, similarly to the first embodiment, an insulating film 67 and a pair of conductive films 68 and 69 are formed. You may do so.

[0187] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0188] (Embodiment 2) In this embodiment, a transistor having a structure different from that in Embodiment 1 and a manufacturing method thereof will be described. This will be explained with reference to FIGS. 8 to 10.

[0189] FIG. 8 is a cross-sectional view of the transistor according to this embodiment, in which a gate electrode 59b is formed on a side surface thereof. The transistor differs from the transistor described in Embodiment 1 in that it has a sidewall insulating film 61 .

[0190] The transistor shown in FIG. 8 includes a substrate 51, an insulating film 53 formed on the substrate 51, and an insulating An oxide semiconductor film 55 formed on the film 53 and a gate insulating film in contact with the oxide semiconductor film 55 The gate insulating film 57a and the gate electrode 59b are in contact with each other. The conductive film 55 is made up of a first region 55a and a second region 55b, 55b sandwiching the first region 55a. The gate electrode 59b overlaps with the first region 55a of the oxide semiconductor film 55. In the transistor, a nitride insulating film 65 is provided in contact with the second regions 55b and 55c. In addition, in the cross section in the channel length direction, the side surface of the gate electrode 59b and the nitride insulating film 65 A sidewall insulating film 61 is formed between the first and second insulating films.

[0191] The angle formed by the bottom surface (the surface in contact with the gate insulating film 57a) and the side surface of the gate electrode 59b is 7 As a result, the sidewall insulation of the gate electrode 59b is formed on the side surface of the gate electrode 59b. In addition, it is possible to manufacture a transistor with a small structure having a small channel length. It is possible.

[0192] The gate electrode 59b is made of the same material as the gate electrodes 59 and 59a shown in the first embodiment. It is possible.

[0193] The sidewall insulating film 61 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. It can be formed using a silicon film or the like.

[0194] Transistors using oxide semiconductors have the following advantages compared to transistors using silicon semiconductors: It is known that the off-state current is small at room temperature. This is thought to be due to the small number of carriers, that is, the low carrier density. Even in transistors using materials with low carrier density, by shortening the channel length, Threshold voltage fluctuations may occur.

[0195] Therefore, by providing the sidewall insulating film 61 as in the transistor described in this embodiment, In the first region 55a, a region that does not overlap with the gate electrode 59b can be provided. That is, the channel region 55d in the first region 55a and the second region 55b, which is a low resistance region, Offset regions 55e and 55f can be provided between the first and second electrodes 55b and 55c. The oxide semiconductor regions 55e and 55f are provided on both ends of the channel region 55d. The electric field applied between the second regions 55b and 55c of the film 55, particularly the second region in contact with the drain electrode, This can mitigate the electric field concentration near the region, thereby suppressing fluctuations in the threshold voltage. In addition, the concentration of electric field can be alleviated, preventing the transistor from being damaged by the concentration of electric field. In other words, the breakdown voltage of the transistor is improved, The offset regions 55e and 55f are transistors in which deterioration of electrical characteristics is suppressed. By having this, deterioration in a voltage-temperature stress test in which a voltage is applied to the drain electrode, Degradation under current stress can be reduced.

[0196] A manufacturing method of the transistor shown in FIG. 8 will be described with reference to FIGS.

[0197] As in the first embodiment, as shown in FIG. 9(A), an insulating film 53, an oxide film, and a A semiconductor film 54, an insulating film 56, and a gate electrode 59b are formed.

[0198] Next, an insulating film is formed on the insulating film 56 and the gate electrode 59b, and then the insulating film is formed by the RIE method. (Reactive ion etching) method By processing the gate electrode 59b by reactive etching, the sidewall insulating film 61 in contact with the side surface of the gate electrode 59b is It can be formed in a self-aligned manner (see FIG. 9(B)). The film 56 is etched to form a gate insulating film 57a.

[0199] Next, as shown in FIG. 9C, using the gate electrode 59b and the sidewall insulating film 61 as a mask, The impurity element 62 is added to the oxide semiconductor film 54, and oxygen vacancies are formed in part of the oxide semiconductor film 54. A region having the following structure is formed:

[0200] Next, as shown in FIG. 10A, the oxide semiconductor film 54, the gate insulating film 57a, and the gate insulating film 57b are A nitride insulating film 64 is formed on the gate electrode 59b. As a result, the nitride insulating film 64 is not doped with an impurity element. The oxide film has a first region 55a containing no impurity element and a second region 55b, 55c containing hydrogen. A compound semiconductor film 55 is formed. After this, a heat treatment may be performed.

[0201] Next, as shown in FIG. 10(B), an insulating film 66 may be formed.

[0202] Next, openings are formed in the nitride insulating film 64 and the insulating film 66, and the second regions 55b and 55c are After exposing a part of the conductive film 68, 69, a pair of conductive films 68 and 69 are formed (see FIG. 10(C)).

[0203] Through the above steps, a transistor with a self-aligned structure can be manufactured.

[0204] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0205] (Embodiment 3) In this embodiment, a structure of an oxide semiconductor film applicable to Embodiments 1 and 2 will be described. 11. Note that the transistor described in Embodiment 1 However, this embodiment can be applied to the transistor described in Embodiment 2 as appropriate. It is possible to do this.

[0206] The transistor illustrated in FIG. 11A has the same structure as the transistor illustrated in FIG. 1 of Embodiment 1. The structure is the same as that of the oxide semiconductor film 55, but the structure of the oxide semiconductor film 55 is different. Enlarged views of 1 are shown in Figs. 11(B) to 11(D).

[0207] As shown in FIG. 11B, the oxide semiconductor film 55 is formed by the first oxide film in contact with the insulating film 53. The second oxide semiconductor film 55_1 is in contact with the first oxide semiconductor film 55_1 and the gate insulating film 57. The oxide semiconductor film 55_2 is formed of the oxide semiconductor film 55_1.

[0208] Alternatively, as shown in FIG. 11C, the oxide semiconductor film 55 is formed on the second insulating film 53. The first oxide semiconductor film 55_2 is connected to the second oxide semiconductor film 55_2 and the gate insulating film 57. The third oxide semiconductor film 55_3 is formed on the first oxide semiconductor layer 55_1.

[0209] Alternatively, as shown in FIG. 11D, the oxide semiconductor film 55 is formed on the first insulating film 53. the first oxide semiconductor film 55_1 and the second oxide semiconductor film 55_2 in contact with the first oxide semiconductor film 55_1. a third oxide semiconductor film 55_2 in contact with the second oxide semiconductor film 55_2 and the gate insulating film 57; The semiconductor film 55_3 is a nitride semiconductor film.

[0210] The first oxide semiconductor film 55_1, the second oxide semiconductor film 55_2, and the third oxide semiconductor film 55_3 are The conductor film 55_3 is an In-M-Zn oxide film (M is Al, Ti, Ga, Y, Zr, Sn, In the case of La, Ce, Nd or Hf, the first oxide semiconductor film 55_1 and the third oxide semiconductor film The semiconductor film 55_3 is In:M:Zn=x1:y1:z1 [atomic ratio], and the second oxide semiconductor If the film 55_2 is In:M:Zn=x2:y2:z2 [atomic ratio], then y1 / x1 is It is larger than y2 / x2, and preferably, y1 / x1 is 1.5 times or more larger than y2 / x2. More preferably, y1 / x1 is at least twice as large as y2 / x2, and even more preferably In this case, y1 / x1 is three times or more larger than y2 / x2. In the second oxide semiconductor film 55_1 and the third oxide semiconductor film 55_3, when y1 is equal to or greater than x1, This is preferable because stable electrical characteristics can be imparted to a transistor including the oxide semiconductor film 55_2. On the other hand, when y1 is three times or more of x1, the second oxide semiconductor film 55_2 is used. Therefore, y1 should be less than three times x1. preferable.

[0211] The second oxide semiconductor film 55_2 is an In-M-Zn oxide film (M is Ga, Y, Zr, L a, Ce, or Nd), the second oxide semiconductor film 55_2 is formed by In the target, if the atomic ratio of metal elements is In:M:Zn=x1:y1:z1, 、 x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 It is preferable that z1 / y1 is 1 or more and 6 or less, and more preferably 1 or more and 6 or less. By setting the upper 6 or lower, a CAAC-OS film is formed as the second oxide semiconductor film 55_2. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1. :1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In: M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2 etc.

[0212] The first oxide semiconductor film 55_1 and the third oxide semiconductor film 55_3 are made of In-M-Zn oxide. In the case of an oxide film (where M is Ga, Y, Zr, La, Ce, or Nd), the first oxide semiconductor In the target used for depositing the film 55_1 and the third oxide semiconductor film 55_3, If the atomic ratio of metal elements is In:M:Zn=x2:y2:z2, 、 x2 / y2 <x 1 / y1, and z2 / y2 is 1 / 3 or more and 6 or less, or even 1 or more and 6 or less. Note that when z2 / y2 is set to 1 or more and 6 or less, the first oxide semiconductor film 55 Therefore, CAAC-OS films are likely to be formed as the first and third oxide semiconductor films 55_1 and 55_3. Typical examples of the atomic ratio of the metal elements in the target are In:M:Zn=1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn=1:4:4, In:M:Zn=1:4: 5, In:M:Zn=1:4:6, In:M:Zn=1:6:3, In:M:Zn=1: 6:4, In:M:Zn=1:6:5, In:M:Zn=1:6:6, In:M:Zn= Examples include In:M:Zn=1:6:7, In:M:Zn=1:6:8, and In:M:Zn=1:6:9.

[0213] Note that the first oxide semiconductor film 55_1, the second oxide semiconductor film 55_2, and the third oxide semiconductor film 55_3 are The atomic ratio of the compound semiconductor film 55_3 is plus or minus the above atomic ratio as an error. Including a 40% variation.

[0214] The atomic ratio is not limited to these, and an appropriate atomic ratio may be selected depending on the required semiconductor characteristics. Just use something.

[0215] In addition, in FIG. 11D, the first oxide semiconductor film 55_1 and the third oxide semiconductor The film 55_3 may have the same metal atomic ratio. The oxide semiconductor film 55_3 of No. 3 is formed by using a compound in which In:Ga:Zn=1:3:2, 1:3:4, or An In-Ga-Zn oxide with an atomic ratio of 1:4:5 may also be used.

[0216] Alternatively, in FIG. 11D, the first oxide semiconductor film 55_1 and the third oxide semiconductor film The first oxide semiconductor film 55_1 and the second oxide semiconductor film 55_2 may have a different metal atomic ratio. As the third layer, an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2 was used. The oxide semiconductor film 55_3 is made of In:Ga:Zn=1:3:4 or 1:4:5 atoms. A numerical ratio of In-Ga-Zn oxide may also be used.

[0217] The thickness of the first oxide semiconductor film 55_1 and the third oxide semiconductor film 55_3 is 3 nm or more. The thickness of the second oxide semiconductor film 5 is set to 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of 5_2 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably The thickness is more preferably 3 nm to 50 nm. The second oxide semiconductor film 55_2 and the third oxide semiconductor film 55_3 are thinner than the second oxide semiconductor film 55_2. By reducing the temperature, it is possible to reduce the amount of fluctuation in the threshold voltage of the transistor. Oxygen contained in the third oxide semiconductor film 55_3 diffuses into the pair of conductive films 68 and 69, In order to prevent the pair of conductive films 68 and 69 from being oxidized, the thickness of the third oxide semiconductor film 55_3 is Thinner is preferable.

[0218] The first oxide semiconductor film 55_1, the second oxide semiconductor film 55_2, and the third oxide semiconductor film 55_3 are The interfaces of the conductive films 55_3 are measured by STEM (Scanning Transmission It can be observed using electron microscopy.

[0219] The first oxide semiconductor film 55_1, the second oxide semiconductor film 55_2, and the third oxide semiconductor film 55_3 are The conductive film 55_3 may have the same crystal structure as the oxide semiconductor film 55 described in Embodiment 1. can be done.

[0220] The oxide semiconductor film in which oxygen vacancies are less likely to occur than the second oxide semiconductor film 55_2 is By providing the second oxide semiconductor film 55_2 above and / or below the second oxide semiconductor film 55_2, The oxygen vacancies in the second oxide semiconductor film 55_2 can be reduced. 5_2 is a first oxide semiconductor film having one or more metal elements constituting the second oxide semiconductor film 55_2. The first oxide semiconductor film 55_1 and / or the third oxide semiconductor film 55_3 are in contact with each other. The interface between the oxide semiconductor film 55_1 and the second oxide semiconductor film 55_2, The interface state density at the interface between the oxide semiconductor film 55_2 and the third oxide semiconductor film 55_3 is extremely low. Therefore, oxygen vacancies in the second oxide semiconductor film 55_2 can be reduced. be.

[0221] In addition, the second oxide semiconductor film 55_2 may be an insulating film having a different constituent element (for example, silicon oxide). When the gate insulating film including the silicon film is in contact with the silicon dioxide film, an interface state is formed, and the interface state In such a case, a second transistor with a different threshold voltage may appear. This may cause the apparent threshold voltage of the transistor to fluctuate. The first oxide semiconductor film 55_2 includes one or more metal elements. Since the oxide semiconductor film 55_1 is in contact with the second oxide semiconductor film 55_2, the first oxide semiconductor film 55_1 and the The interface state is less likely to be formed at the interface of the second oxide semiconductor film 55_2. By providing the compound semiconductor film 55_1, the electrical characteristics such as the threshold voltage of the transistor can be controlled. Variation can be reduced.

[0222] In addition, a channel is formed at the interface between the gate insulating film 57 and the second oxide semiconductor film 55_2. If the interface is too thick, interfacial scattering occurs at the interface, resulting in a decrease in the field-effect mobility of the transistor. While the second oxide semiconductor film 55_2 is being heated, a third oxide semiconductor film containing one or more metal elements is Since the oxide semiconductor film 55_3 is provided in contact with the second oxide semiconductor film 55_2, At the interface between the oxide semiconductor film 55_2 and the third oxide semiconductor film 55_3, scattering of carriers occurs. This makes it difficult for the oxide to break down, and the field effect mobility of the transistor can be increased.

[0223] The first oxide semiconductor film 55_1 and the third oxide semiconductor film 55_3 are formed on the insulating film 5 The constituent elements of the second oxide semiconductor film 55_2 and the gate insulating film 57 are mixed into the second oxide semiconductor film 55_2 and become impurities. It also functions as a barrier film for suppressing the formation of levels due to the ion beam.

[0224] For example, when the insulating film 53 and the gate insulating film 57 are made of insulating films containing silicon, , silicon in the insulating film 53 and the gate insulating film 57, or silicon in the insulating film 53 and the gate insulating film 5 The carbon that may be mixed into the first oxide semiconductor film 55_1 and / or the third oxide semiconductor film 55_2 is mixed into the first oxide semiconductor film 55_3 and / or the third oxide semiconductor film 55_4. Silicon, carbon, etc. may be mixed into the conductive film 55_3 from the interface to a depth of several nm. When the impurities enter the second oxide semiconductor film 55_2, an impurity level is formed. It can become n-type by becoming a donor and generating electrons.

[0225] However, the first oxide semiconductor film 55_1 and the third oxide semiconductor film 55_3 If the thickness is greater than a few nm, impurities such as silicon and carbon may be present in the second oxide semiconductor. Since the impurity does not reach the film 55_2, the influence of the impurity level is reduced.

[0226] From the above, the transistor described in this embodiment has electrical characteristics such as threshold voltage. This is a transistor with reduced variation.

[0227] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0228] (Fourth embodiment) In this embodiment, a structure of an oxide semiconductor film applicable to any of Embodiments 1 to 3 will be described. 12. Note that the transistor described in Embodiment 1 The transistors shown in Embodiment 2 or 3 will be used in the present embodiment. It is possible to apply the following form.

[0229] The transistor described in this embodiment is formed by forming an oxide film with an insulating film 53 interposed therebetween as shown in FIG. It is characterized by having a gate electrode 73 overlapping the semiconductor film 55 .

[0230] By setting the potential of the gate electrode 73 to a potential different from that of the gate electrode 59, the transistor It is possible to control the threshold voltage and fabricate a normally-off transistor. Alternatively, the potential of the gate electrode 73 can be set to the same potential as that of the gate electrode 59. The on-current of the transistor can be increased.

[0231] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0232] (Embodiment 5) In this embodiment, in the transistor described in the above embodiment, an oxide semiconductor film An embodiment applicable to the above will be described.

[0233] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single-crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), a microcrystalline oxide semiconductor oxide semiconductors (hereinafter referred to as microcrystalline oxide semiconductors) and amorphous oxide semiconductors (hereinafter referred to as amorphous oxide semiconductors) The oxide semiconductor film may be formed of one or more of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The oxide semiconductor may be made of a conductor and a crystal grain. The CAAC-OS and a microcrystalline oxide semiconductor will be described.

[0234] <caac-os> First, the CAAC-OS film will be described.

[0235] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0236] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron microscope, clear boundaries between the crystals are observed. It is difficult to identify the grain boundaries. It can be said that the CAAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0237] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0238] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0239] FIG. 13(a) is a cross-sectional TEM image of the CAAC-OS film. This is a cross-sectional TEM image of 13(a) enlarged, with the atomic arrangement emphasized for easier understanding. The key is displayed.

[0240] Figure 13(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 13(a). The local Fourier transform image of the c-axis orientation in each region is shown in Figure 13(c). In addition, the c-axis orientation is different between A-O and O-A', so different graphs are formed. The c-axis angles between the A and A crystals are 14.3° and 16. 6°, 26.4°, and so on. Between these, the angle of the c-axis gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0241] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm on the top surface of the CAAC-OS film is observed. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See FIG. 14(A)).

[0242] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0243] Most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 Over 5μm 2 More than or equal to 1000 μm 2 Crystal regions with more than this size may be observed.

[0244] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0245] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0246] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0247] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0248] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high percentage of impurities. The region where the ZnO was added was transformed, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0249] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0250] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0251] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0252] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0253] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0254] Furthermore, a semiconductor device including a transistor using the CAAC-OS film does not break even when bent. Therefore, a transistor using a CAAC-OS film can be used in a flexible semiconductor device. It is preferable to use

[0255] <nc-os> Next, a microcrystalline oxide semiconductor film will be described.

[0256] It is difficult to clearly identify the crystal parts of a microcrystalline oxide semiconductor film in a TEM image. The crystal part contained in the microcrystalline oxide semiconductor film has a thickness of 1 nm to 100 nm. The size is often less than 1 nm or 10 nm. Nanocrystals (nc) are microcrystals of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having stal is The nc-OS film is called an Oxide Semiconductor film. In TEM images, it is sometimes difficult to clearly identify grain boundaries.

[0257] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron diffraction (also called selected area electron diffraction) is performed using an electron beam (for example, 50 nm or larger). On the other hand, for the nc-OS film, Nanobeam electron circuit using an electron beam with a probe diameter close to or smaller than the size of the crystal part. When the nc-OS film was subjected to nanobeam electron diffraction, spots were observed. When the image is taken, a circular (ring-shaped) area of high brightness may be observed. When nanobeam electron diffraction was performed on the c-OS film, multiple spots were observed within the ring-shaped region. It may be observed (see FIG. 14(B)).

[0258] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0259] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0260] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0261] FIG. 14C shows an electron gun chamber 70, an optical system 72 below the electron gun chamber 70, and a a sample chamber 74, an optical system 76 below the sample chamber 74, an observation chamber 80 below the optical system 76, and an observation A transillumination system having a camera 78 installed in a chamber 80 and a film chamber 82 below the observation chamber 80. The electron diffraction measurement device is shown. The camera 78 is installed facing the inside of the observation chamber 80. The room chamber 82 may not be provided.

[0262] FIG. 14(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 14(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 70 is irradiated onto a substance 88 placed in the sample chamber 74 via the optical system 72. The electrons are incident on a fluorescent screen 92 installed inside the observation chamber 80 via the optical system 76. On the light plate 92, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. It is possible to measure the

[0263] The camera 78 is installed facing the fluorescent screen 92 and captures the pattern that appears on the fluorescent screen 92. A straight line passing through the center of the lens of the camera 78 and the center of the fluorescent screen 92 is The angle between the line and the upper surface of the fluorescent screen 92 is, for example, 15° or more and 80° or less, or 30° or more. The angle is set to 75° or less, or 45° to 70°. The smaller the angle, the more accurate the image captured by the camera 78. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be distorted. If the data is corrected, it is possible to correct distortions in the obtained transmission electron diffraction pattern. In some cases, it may be acceptable to install the camera 78 in the film chamber 82. The fluorescent screen may be installed in the room chamber 82 so as to face the direction of incidence of the electrons 84. A transmission electron diffraction pattern with little distortion can be taken from the backside of 92.

[0264] A holder for fixing a substance 88, which is a sample, is installed in the sample chamber 74. The holder is structured to be transparent to electrons passing through the material 88. The holder may have a function to move the object 88 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range of movement is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance88. That's fine.

[0265] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0266] For example, as shown in FIG. 14(D), the irradiation position of the electron 84, which is a nanobeam, in the material By changing (scanning) the In this case, if the substance 88 is a CAAC-OS film, the structure shown in FIG. Alternatively, if the material 88 is an nc-OS film, the diffraction pattern shown in Figure 14(B) is The diffraction pattern shown is observed.

[0267] By the way, even if material 88 is a CAAC-OS film, it may be partially composed of nc-OS films. Therefore, the quality of the CAAC-OS film can be determined by the diffraction pattern. , the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAA For example, in a high-quality CAAC-OS film, If present, the CAAC conversion rate is 50% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern is different from that of the CAAC-OS film. The percentage of the area where this is observed is denoted as the non-CAAC rate.

[0268] As an example, immediately after film formation (denoted as as-sputtered), or in an atmosphere containing oxygen The top surface of each sample with the CAAC-OS film after the heat treatment at 450°C in air was scanned. Transmission electron diffraction patterns were acquired while scanning at a speed of 5 nm / s for 60 seconds. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the probe diameter of 1n. The same measurement was carried out on six samples. The rate was calculated using the average value of six samples.

[0269] The CAAC conversion rate for each sample is shown in Figure 15(A). The AAC conversion rate was 75.7% (non-CAAC conversion rate was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC rate is reduced by heat treatment at a high temperature (for example, 400°C or higher). It can be seen that the CAAC conversion rate increases (the CAAC conversion rate increases). It can be seen that a CAAC-OS film with a high CAAC content can be obtained even with the SiO2 solution.

[0270] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The amorphous oxide semiconductor film was not observed in the measurement area. Therefore, it is possible that the heat treatment could produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the adjacent region influences the rearrangement and formation of CAAC. .

[0271] 15(B) and 15(C) show the CAAC- 15(B) and 15(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the heat treatment at 50°C has a more uniform film quality. It can be seen that the film quality of the CAAC-OS film is improved by heat treatment at a low temperature.

[0272] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0273] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination.

[0274] (Embodiment 6) In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0275] <Configuration example> FIG. 16A is a top view of a display device according to one embodiment of the present invention, and FIG. 16B is a top view of a display device according to one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device according to one embodiment of the present invention is described. 16C is a circuit diagram for explaining a pixel of a display device according to one embodiment of the present invention. FIG. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. do.

[0276] The transistors disposed in the pixel portion can be formed according to the above-described embodiment modes. In addition, since the transistor can be easily made into an n-channel type, the n-channel transistor in the driver circuit can be easily made into an n-channel type. A part of the driver circuit can be configured with a panel-type transistor, and the transistors in the pixel section can be In this way, the transistor shown in the above embodiment mode is formed in the pixel portion and the driver circuit. By using the capacitor, a highly reliable display device can be provided.

[0277] An example of a block diagram of an active matrix display device is shown in FIG. On this substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 has a signal line driver circuit 703 and a signal line driver circuit 704. A plurality of scanning lines are arranged extending from a first scanning line driving circuit 702 and a second scanning line driving circuit 704. The scanning lines are arranged extending from the second scanning line driving circuit 703. In the area, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a connection board such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via a connection. do.

[0278] In FIG. 16A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components such as drive circuits to be provided is reduced, which contributes to cost reduction. 700 If an external drive circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0279] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in FIG. 16(B). 1 shows a pixel circuit that can be applied to the pixel.

[0280] This pixel circuit can be applied to a configuration in which one pixel has a plurality of pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0281] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be applied. The source or drain electrode 714, which functions as a transistor 716, is connected to the transistor The transistors 716 and 717 are used in common. The transistors described in the embodiments can be appropriately used. A display device can be provided.

[0282] A first pixel electrode electrically connected to the transistor 716 and a second pixel electrode electrically connected to the transistor 717 The shape of the second pixel electrode that is electrically connected to the first pixel electrode and the second pixel electrode will be described. The first pixel electrode has a V-shaped shape and is separated by a slit. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0283] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 712. The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the voltage, the orientation of the liquid crystal can be controlled.

[0284] Also, a capacitance wiring 710, a gate insulating film functioning as a dielectric, and a first pixel electrode or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0285] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0286] Note that the pixel circuit shown in FIG. 16(B) is not limited to this. For example, The pixel shown has a new switch, resistor, capacitor, transistor, sensor, or logic circuit. You can also add roads etc.

[0287] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in FIG. 16(C). 1 shows the pixel structure of the display device.

[0288] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of the pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0289] FIG. 16C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. The film can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0290] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0291] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting element. The switching transistor 721 has a gate element 724 and a capacitor element 723. The gate electrode is connected to the scanning line 726, and the first electrode (one of the source electrode and the drain electrode) is connected to a signal line 725, and the second electrode (the other of the source electrode and the drain electrode) is connected to a driving The driving transistor 722 is connected to the gate electrode of the driving transistor 722. The first electrode is connected to the power supply line 727 via the capacitor element 723. The first electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the optical element 724 corresponds to a common electrode 728. The common electrode 728 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed on the substrate.

[0292] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. This allows for the development of highly reliable organic EL devices. A display device can be provided.

[0293] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, ND, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. 24, a current flows through the light emitting element 724, causing it to emit light. The forward voltage of 724 refers to the voltage required to achieve the desired brightness, and Includes threshold voltage.

[0294] The capacitor 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode and the electrode.

[0295] Next, a description will be given of the signal input to the driving transistor 722. Voltage input voltage driving In this method, the driving transistor 722 is in two states: fully on or off. A video signal that becomes a pixel value is input to the driving transistor 722. In order to operate the motor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A signal line 725 is applied to the gate electrode of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0296] When analog gradation driving is performed, the gate electrode of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 724. , analog gray scale driving can be performed.

[0297] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 6(C) is connected to a pixel circuit including a switch, a resistor, a capacitor, a sensor, a transistor, or A logic circuit or the like may be added.

[0298] When the transistors exemplified in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0299] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or in various A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. For example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc. etc.), transistors (transistors that emit light according to the current), electron-emitting elements, liquid crystal elements, Electronic ink, electrophoretic element, grating light valve (GLV), plasma display ray (PDP), MEMS (Micro-Electro-Mechanical Systems) based display Display element, Digital Micromirror Device (DMD), DMS (Digital Micromirror Scatter), MIRASOL (registered trademark), IMOD (Interference Module shutter-type MEMS display element, optical interference-type MEMS display element, Electrowetting elements, piezoelectric ceramic displays, and carbon nanotubes In addition to these, it has at least one electric or magnetic display element. The display medium has a contrast, brightness, reflectance, transmittance, etc. that change due to the thermal effect. An example of a display device using an EL element is an EL display. An example of a display device using electron emission elements is a field emission display (F ED) or SED type flat panel display (SED: Surface-conduct ion electron-emitter display). An example of the display device used is a liquid crystal display (transmissive liquid crystal display, semi-transmissive LCD display, reflective LCD display, direct-view LCD display, projection LCD display Display devices using electronic ink, electronic liquid powder, or electrophoretic elements An example of this is electronic paper. When realizing a liquid crystal display, part or all of the pixel electrodes are used as reflective electrodes. For example, a part or all of the pixel electrodes may be made of aluminum. In this case, the SRA may be provided under the reflective electrode. It is also possible to provide a memory circuit such as M. This further reduces power consumption. It is possible.

[0300] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0301] (Embodiment 7) In this embodiment, the oxide semiconductor film contains oxygen vacancies and hydrogen, and thus the resistivity is reduced. Specifically, the second oxide semiconductor film 55 V formed in regions 55b and 55c O Here, oxygen vacancy V O The state where there is a hydrogen atom H in O It is written as H.

[0302] <1-a calculation method> Here, oxygen vacancies (hereinafter referred to as V) in In-Ga-Zn oxide (hereinafter referred to as IGZO) O The effects of the simultaneous presence of ZnO and hydrogen were investigated using first-principles calculations. Introduction, V O We investigated the oxygen sites where V is likely to form and the state of existence of hydrogen atoms. O We investigated the stability of hydrogen atoms inside or outside the nucleus. The transition level of pancreatic defects was calculated.

[0303] For first-principles calculations, Vienna Ab initio Simulation Park ckage (VASP) was used. Also, the Heyd-Scu hybrid functional was used. The seria-Ernzerhof (HSE) functional is used, and the exchange-correlation potential is Generalized Perdew-Burke-Ernzerhof (PBE) type -Gradient-Approximation (GGA) is used to generate pseudopotentials. The projector augmented-wave (PAW) method was used. O Of The calculation of the stability of hydrogen atoms on the side or outside uses GGA, and the formation energy The HSE functional is used to calculate the band gap and transition levels because the band gap accuracy is required. When GGA was used, the energy cutoff was 500 eV and the k-point was Mo. The sampling was 2x2x3 on the Khorst-Pack mesh. When using the number, the energy cutoff is 800 eV, and the k-point sampling The screening parameter in the HSE functional is set to 2 nm. -1 The ratio of the Hartree-Fock exchange term was set to 0.25.

[0304] <1-b Defect formation energy> The defect concentration c is determined by the formation energy of the defect D (E form (D)) and calculated from formula (1) will be done.

[0305]

number

[0306] where N sites is the number of sites where defects D can form, k B is the Boltzmann constant, T is the temperature. In other words, the smaller the formation energy, the easier it is for defect D to form. Therefore, the formation energy was calculated using formula (2).

[0307]

number

[0308] where E tot (D q ) is the total energy of a cell with a defect D of charge q, E tot (b ulk) is the total energy of the perfect crystal, Δn i is the number of atom i to be increased or decreased, μ i is the chemical potential of atom i potential, ε VBM is the energy of the top of the valence band (VBM), ΔV q is the reference potential Correction term for E F is the Fermi energy. In this case, the Fermi energy is 0 The position of eV corresponds to the VBM. The chemical potential depends on the environment. Chemical potential (μ O ) (oxygen-rich condition) is set as half of the total energy of the oxygen molecule. At this time, the chemical potential of hydrogen (μ H ) is the total energy of the water molecule minus the amount of oxygen The value was set to half of the value obtained by subtracting the electrochemical potential.

[0309] The oxygen-rich condition is, for example, a condition in which oxygen is introduced into the oxygen vacancy when oxygen vacancy occurs. These are conditions under which the formation of oxygen vacancies is easily achieved, that is, conditions under which the formation of oxygen vacancies is suppressed.

[0310] On the other hand, the hydrogen chemical potential (μ H ) is the total energy of the hydrogen molecule The chemical potential of oxygen at this time is the lower limit (oxygen-poor condition), but the moisture From the total energy of the child μ H The value was calculated by subtracting twice the value.

[0311] The oxygen-poor condition is a condition in which the formation of oxygen vacancies is promoted when oxygen vacancies occur. is.

[0312] <1-c Defect transition level> Depending on the type of defect, there are levels (also called transition levels) that accompany transitions to different charge states. exists in the band gap, and the carrier capture depends on the depth of the level and the position of the Fermi level. Therefore, the transition level (ε(q / q')) of the defect D is calculated using the following formula ( Calculated from 3).

[0313]

number

[0314] The value obtained from equation (3) is the position of the transition level when the top of the valence band is set to 0.0 eV. In other words, the value obtained by subtracting the transition level from the band gap is the conduction band edge (CB M), and the Fermi level is higher than ε(q / q'). If it is in the electron band, the defect is stable in the charge state q. If it is in the conduction band, the defect is stable in the charge state q. It can be said that the charge state q' is stable.

[0315] <1-d atomic diffusion> Next, the Nudged Elastic Band (NEB) method was used to measure the atomic diffusion rate. The NEB method is a method for determining the activation barrier between the initial and final states. This is a method to find the state where the required energy is lowest. The calculation was carried out by relaxing the atomic coordinates to less than eV / nm.

[0316] <1-e calculation structure> Typically, cells with defects are fabricated so that there is one defect per perfect crystal. However, in order to set three-dimensional periodic boundary conditions, it is necessary to minimize the interaction between defects. It is necessary to widen the spacing between the atoms, that is, to increase the lattice size. InGaO3(ZnO) m In a crystal, the lattice constants a (and b) are very small relative to c. Therefore, if we try to make the lattice size in the a and b axes approximately the same as c, the number of atoms will be Therefore, at m=1, the lattice vectors are (420) and (040 ), (211), and then the lattice constant c is multiplied by 1 / 3 to obtain the 112-atom superstructure. A cell (InGaZnO4) was prepared (see Figure 26). This resulted in the distance between defects being Even in the direction of the shortest axis, it is 0.8 nm or more.

[0317] In addition, InGaO3(ZnO) m In (m=1), Ga, Zn, and There are two layers ((Ga,Zn)O layers) composed of Ga and O. The arrangement of Zn and O was chosen to have the lowest energy. From the combination of the nearest metal atoms, the oxygen site is O (1) From O (4) to Specifically, there are four types of O sites (O (1 ) ), O site bonded to three In and one Ga (O (2) ), one G in the ab plane direction a and two Zn-binding O sites (O (3) ), two Ga and one Zn in the ab-plane direction O site (O (4) )

[0318] First, the lattice constants and atomic coordinates are optimized for the perfect crystal using GGA or HS. The E functional was used. The lattice constants and band gaps obtained are shown in Table 2. For this purpose, the lattice constant and band gap obtained experimentally are also listed. In this case, the lattice constant is overestimated compared to the experimental value, and the band gap is underestimated. On the other hand, when the HSE functional is used, the lattice constant and band gap are close to the measured values. The reason why the calculated lattice constants a and b are slightly different is that Ga and This is due to the arrangement of Zn and Zn.

[0319] [Table 2]

[0320] <2-a V O Easy to create site> V O To investigate the effect of the simultaneous presence of V and hydrogen, first O and hydrogen You need to get it.

[0321] Introduction, V O I investigated the sites where this is likely to occur. I removed one oxygen atom from a perfect crystal. By doing this, V O A cell with the following structure was created, and the atomic configuration was relaxed using the HSE functional. V calculated under oxygen-rich conditions O The formation energies of are shown in Table 3.

[0322] [Table 3] In Table 3, n M indicates the coordination number of the metal atom M (=In, Ga, Zn) adjacent to oxygen. vinegar.

[0323] Oxygen site O (1) V in O The formation energy of the oxygen site O (2) Less than Oxygen site O (1) and oxygen sites O (2) The oxygen in each of the The remaining binding partner is the oxygen site O (1) In the case of Zn, Raw Site O (2) Then, Ga. If we consider this difference to be the main cause of the difference in formation energy, It is presumed that Ga has a stronger bond with oxygen than Zn. (3) To Keruv V O The formation energy of the oxygen site O (4) Oxygen site O (3) teeth The number of Ga atoms bonded in the ab-plane direction is determined by the oxygen site O (4) is less than. Therefore, It can be said that the bond between Ga and O is strong. O is an acid with a low coordination number with Ga. Raw Site O (1) Or oxygen site O (3) It is thought that it is easy to form.

[0324] Also, V O The transition levels of the oxygen site O are shown in Table 3. (3) and oxygen sites O (4) Well then, V O The transition level of ε(2+ / +) is closer to the conduction band than the transition level of ε(+ / 0). Also, oxygen sites O (1) V O Transition of ε(2+ / +) and ε(+ / 0) Therefore, the Fermi level is shifted from the valence band to the conduction band. When you do, V O + Without going through V O 2+ From V O 0 That is, V O shows negative-U behavior, similar to that of ZnO. Oxygen site O (1) and oxygen site O (3) V in O The transition level of ε(2+ / 0) is , located approximately 0.8 eV below the conduction band bottom (Fermi energy 3.15 eV) This indicates that V in IGZO O This suggests that the donor is a deep donor. Crystalline InGaO3(ZnO) m This is consistent with the results for (m=3).

[0325] <2-b Hydrogen Forms> Next, we investigated the form of hydrogen. Hydrogen in IGZO exists as interstitial hydrogen atoms or It can exist as a hydrogen molecule or bonded to oxygen. The octahedral interstitial lattice between the nO2 layer and the (Ga,Zn)O layer (Int (5) ) with a hydrogen atom (H oct ) or molecular hydrogen ((H2) oct ) and Ga In the oxygen of the -O bond, the hydrogen atom bonded to the oxygen atom on the opposite side to Ga (bond Atomic relaxation was performed for each cell using the HSE functional. Ta.

[0326] The change in formation energy with respect to the Fermi energy is shown in Figure 27. The formation energy calculated under oxygen-rich conditions is shown in Figure 27(B), and the formation energy calculated under oxygen-poor conditions is shown in Figure 27(C). Here, we compare the formation energies per hydrogen atom. Therefore, (H2) in Figure 27 oct The formation energies of are shown at half the value. , Fermi energy 0 eV corresponds to VBM, Fermi energy 3.15 eV corresponds to CBM. In addition, in Fig. 27(A) and Fig. 27(B), the slope of the line is 0 If the slope of the line is negative, each defect is negatively charged. A positive slope of the line indicates a positively charged state.

[0327] Hydrogen molecule (H2) oct exists in a charge-neutral state from the VBM to 2.82 eV, It was found that from 2.82 eV to the CBM, it exists in a negatively charged state. .

[0328] Also, hydrogen atom H oct The charge-neutral state exists between the VBM and 2.17 eV. Between 2.17 eV and CBM, it exists in a negatively charged state. H oct + could not be confirmed.

[0329] The hydrogen atom bonded to the oxygen atom (bonded-H) is 2.82e from the VBM. Up to V, it exists in a positively charged state, and from 2.82 eV to CBM, it exists in a neutral state. It was found that it exists in this state.

[0330] Comparing the formation energies of each configuration, hydrogen in IGZO is in the region within the band gap. In all regions, regardless of the oxygen condition, the hydrogen atoms bonded to the oxygen atoms (bonded-H ) and found to be stable.

[0331] <2-c V O Stable structure when and H exist simultaneously> In the above-mentioned <2-a> and <2-b>, V O The stability of V and hydrogen was evaluated separately. O and When hydrogen atoms are present in a single cell, the hydrogen atoms and V O and V O Inside A state in which a hydrogen atom is inserted into (V O H) is considered. We investigated whether it was stable.

[0332] V O is the oxygen site O (1) A cell that exists in and has one hydrogen atom at any position And, V O is the oxygen site O (3) and one hydrogen atom is present at any position. Atomic relaxation was carried out for each cell. Here, the exchange-correlation potential GGA was used for the sharu. V O The phase of the total energy versus the distance from the center of the atom to the hydrogen atom The plot of the values is shown in Figure 28. O The center of the bonded oxygen atom is released. This is the position that existed before V O When a hydrogen atom enters the O H) is set to 0 nm This was the energy reference point. In Figure 28, the square marks indicate oxygen sites O (1) to V O If there is oxygen, the triangle indicates the oxygen site O (3) V to O In addition, The dashed line A indicates one hydrogen atom is V O The relative value of the energy in the cell enclosed by the dashed line B is the relative energy in cells with one hydrogen atom near various oxygen atoms As a result of the calculation, the plots within dashed line A are more prominent than those within dashed line B at both oxygen sites. is low in energy, so V O and hydrogen atoms exist farther apart than V O H is more stable It was found that...

[0333] Hydrogen atom and V O and V O A state in which a hydrogen atom is inserted inside (V O H ), which of the two states is stable is determined by a method different from the calculation using the GGA. To investigate, the formation energy (E form ) defined as the bond energy (E b )of , was calculated using Equation (4). Here, the HSE functional was used for the exchange-correlation potential. Ta.

[0334]

number

[0335] In addition, in the formula (4), E form (V o )+E form (bonded-H) , hydrogen atoms and V O is the formation energy of the state where the atoms are separated, and E form (V O H) is V O A state in which a hydrogen atom is inserted inside (V O H).

[0336] Figure 31 shows the oxygen site O (3) V present in O Formation energy of (shown by thin solid line), The formation energy of a hydrogen atom bonded to an oxygen atom (bonded-H) (shown by the dashed-dotted line). ), oxygen site O (3) V formed in O The formation energy of H (shown as a dashed line), and Binding energy (E b ) (shown by the thick solid line) as a function of the Fermi energy. Figure 31(A) and Figure 31(B) show the results of oxygen-rich conditions and oxygen-promoted conditions, respectively. These are the calculation results under the above conditions.

[0337] From equation (4), the bond energy E b When is positive, V O A hydrogen atom has entered the V O H) is stable. In Figure 31, when the Fermi level is 1.85 eV or higher, E b When the carrier concentration is high, the Fermi level is close to the bottom of the conduction band. The Elmi level is 1.85 eV or higher. Therefore, V O A state in which a hydrogen atom is inserted inside (V O H) is a hydrogen atom and V O This is more stable than the state where the two atoms are separated.

[0338] From Figure 28, V O and hydrogen atoms are present, V O It is more stable in H I understand. But V O H hydrogen atom is V O If it is easy to escape from inside, The child is V O Therefore, V O H hydrogen atom is V O Get out from within, V O The diffusion process of hydrogen until it bonds with nearby oxygen and its activity at that time The barrier was investigated by the NEB method, where the GGA exchange-correlation potential was used.

[0339] Here, the initial state is V O The cell with H, the final state is V O and V O Nearby oxygen atoms Cells with hydrogen atoms bonded to V (i.e., in the calculation of Figure 28, O away Then, the initial state or the final state is determined from the maximum energy in the path. The activation barrier was calculated by subtracting the energy of the V O The route for hydrogen to escape from inside The energy change is shown in Figure 29. (1) In V O Hydrogen escapes from Routes A and B were assumed as the diffusion routes for the ion beam (Fig. 29(A)). The calculation revealed that the activation barrier for route A was smaller, at 1.52 eV. Ta.

[0340] Also, oxygen sites O (3) In V O The diffusion path for hydrogen to escape from , D were assumed (Fig. 29(B)). When these routes were calculated, route C was found to be the better. The activation barrier was small, being 1.61 eV.

[0341] V O After escaping from the hydrogen, O The hydrogen diffuses back into the oxygen or into another oxygen. and V in the opposite direction to C (respectively denoted as A' and C'). O The hydrogen goes back inside. For paths E and F that diffuse to the NEB, set the final states of paths A and C to the initial states. The hydrogen diffusion path and energy change are shown in Figure 30.

[0342] The activation barriers for paths A', C', E, and F are 0.46 eV, 0.34 eV, and 0.38 eV, respectively. eV, 0.03 eV.

[0343] Next, from the activation barrier obtained above, the reaction frequency Γ at which hydrogen diffusion occurs is calculated using the following formula (5 ) was estimated using the formula.

[0344]

number

[0345] where ν is the frequency factor, E a is the activation barrier.

[0346] ν is 1.0×10 13 / sec, V at 350°C O The hydrogen inside Frequency of release, V O Table 4 shows the frequency with which hydrogen enters the oxygen sintering layer and diffuses into other oxygen sintering layers.

[0347] [Table 4]

[0348] From Table 4, oxygen site O (1) and O (3) So, hydrogen is frequently V O Go inside , V at 350℃ O Therefore, once hydrogen is released from the V O Within Once inside, it's difficult to get out, so V O H is stable.

[0349] <2-d V O H transition level > The above-mentioned <2-c V O From the stable structure when and H exist simultaneously, V O and hydrogen are the same When there is time, V O It was found that V exists stably as H. O H transition level The V O The ε(+ / 0) transition level of H is the oxygen site O (1) V to O There is H 3.03 eV for oxygen site O (3) V to O When H was present, it was 2.97 eV. Any V O Since the ε(+ / 0) transition level of H is also located near the bottom of the conduction band, s It is thought to be a hollow donor. O H acts as a donor, so V O It was revealed that IGZO containing H has low resistivity and is conductive.

[0350] (Embodiment 8) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) navigation systems, audio playback devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 17. .

[0351] FIG. 17A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 17(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0352] FIG. 17B shows a portable data terminal, which is made up of a first housing 911, a second housing 912, a first table The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 is determined by the connection 915. The image on the first display unit 913 can be displayed on the first housing at the connection unit 915. The switching may be performed according to the angle between the main body 911 and the second body 912. At least one of the first display unit 913 and the second display unit 914 is provided with a position input device. A display device with additional functions may be used. This can be added by providing a touch panel on the display device. The function of the device is to provide a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. This can also be added.

[0353] FIG. 17C shows a notebook personal computer, which includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0354] FIG. 17(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a It has 33 etc.

[0355] FIG. 17E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 9 43, operation keys 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected to each other by a connection portion 946. The angle between the first housing 941 and the second housing 942 is determined by the connection portion 946. The image on the display unit 943 is displayed on the first housing at the connection unit 946. The switch may be configured to be switched according to the angle between the first housing 941 and the second housing 942.

[0356] FIG. 17(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0357] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

Claims

1. a first oxide insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film; a gate insulating film having a region in contact with an upper surface of the oxide semiconductor film; a first gate electrode having a region overlapping with the oxide semiconductor film via the gate insulating film; a nitride insulating film having a region located above the first gate electrode and a region in contact with the oxide semiconductor film; a pair of conductive films each having a region located above the nitride insulating film and a region in contact with the oxide semiconductor film; a lower end of the gate insulating film is located on an upper surface of the oxide semiconductor film in a cross-sectional view of the transistor including the oxide semiconductor film in a channel length direction; a lower end of the first gate electrode is located on an upper surface of the gate insulating film in the cross-sectional view; the nitride insulating film has a region in contact with a side surface of the first gate electrode, a region in contact with an upper surface of the gate insulating film, a region in contact with a side surface of the gate insulating film, and a region in contact with an upper surface of the oxide semiconductor film; the oxide semiconductor film has a first region and a second region, the first region is in contact with the gate insulating film, the second region has a region in contact with the nitride insulating film and a region in contact with one of the pair of conductive films, At least the second region contains an impurity element, the second region has a region having a higher concentration of the impurity element than the first region, The semiconductor device, wherein the variation rate of the resistivity of the second region is less than ±20% at a temperature of 80K or higher and 290K or lower.

2. a first oxide insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first oxide insulating film; a gate insulating film having a region in contact with an upper surface of the oxide semiconductor film; a first gate electrode having a region overlapping with the oxide semiconductor film via the gate insulating film; a second oxide insulating film having a region located above the first gate electrode and in contact with the oxide semiconductor film; a nitride insulating film having a region located above the second oxide insulating film; a pair of conductive films each having a region located above the nitride insulating film and a region in contact with the oxide semiconductor film; a lower end of the gate insulating film is located on an upper surface of the oxide semiconductor film in a cross-sectional view of the transistor including the oxide semiconductor film in a channel length direction; a lower end of the first gate electrode is located on an upper surface of the gate insulating film in the cross-sectional view; the second oxide insulating film has a region in contact with a side surface of the first gate electrode, a region in contact with an upper surface of the gate insulating film, a region in contact with a side surface of the gate insulating film, and a region in contact with an upper surface of the oxide semiconductor film; the oxide semiconductor film has a first region and a second region, the first region is in contact with the gate insulating film, the second region has a region in contact with the second oxide insulating film and a region in contact with one of the pair of conductive films, At least the second region contains an impurity element, the second region has a region having a higher concentration of the impurity element than the first region, The semiconductor device, wherein the variation rate of the resistivity of the second region is less than ±20% at a temperature of 80K or higher and 290K or lower.

3. In claim 1 or 2, The semiconductor device according to claim 1, wherein the oxide semiconductor film has a crystalline portion in which a plurality of spots are observed within a ring-shaped region in nanobeam electron diffraction.

4. In any one of claims 1 to 3, a second gate electrode having a region located below the first oxide insulating film; the first gate electrode has a region overlapping with the second gate electrode with the gate insulating film, the oxide semiconductor film, and the first oxide insulating film interposed therebetween; In the cross-sectional view, the length of a lower surface of the second gate electrode is greater than the length of a lower surface of the first gate electrode.

5. In claim 4, In the cross-sectional view, an angle formed between a side surface of the first gate electrode and an upper surface of the gate insulating film is larger than an angle formed between a side surface of the second gate electrode and an upper surface of the substrate.

Images