Multilayer wiring board

Abstract

To provide a multilayer wiring board which is excellent in insulation reliability.SOLUTION: A multilayer wiring board has two or more layers 126 laminated with each other, wherein each of the two or more layers 126 includes: an insulating resin layer 1263 that has a first surface and a second surface as a back face of the first surface and is provided with a groove part G opened in the first surface; an inorganic insulating layer 1264 including a part covering a bottom surface of the groove part G; a conductor layer 1262 including a wiring part 1262W embedded with the groove part G in the insulating resin layer 1263; a first metal-containing layer 1261a which does not cover the side face of the wiring part 1262W and covers the surface on the first surface side of the wiring part 1262W; and a second metal-containing layer 1261b which includes a part interposed between the first metal-containing layer 1261a and the wiring part 1262W and a part covering the side face of the wiring part 1262W, and is made of a metal material different from a material of the first metal-containing layer 1261a.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer wiring board. [Background technology]

[0002] In recent years, as semiconductor devices have become faster and more highly integrated, there has been a demand for narrower pitches of the bonding terminals used to bond semiconductor chips and finer wiring within the substrate for wiring substrates for flip chip ball grid arrays (FC-BGA) that mount semiconductor chips. Meanwhile, bonding between FC-BGA substrates and motherboards requires bonding terminals arranged at roughly the same pitch as conventional bonding terminals. To meet these demands, a technology has been adopted in which a multilayer wiring substrate containing fine wiring, also known as an interposer, is provided between the FC-BGA substrate and the semiconductor chip.

[0003] One of these is silicon interposer technology, which manufactures interposers by forming a multilayer wiring structure, each layer of which contains fine wiring, on a silicon wafer using semiconductor circuit manufacturing technology.

[0004] Furthermore, a method has been developed in which the above-mentioned multilayer wiring structure is directly fabricated on an FC-BGA substrate, rather than being formed on a silicon wafer. This method involves forming the above-mentioned multilayer wiring structure using chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate whose core layer is made of, for example, a glass epoxy substrate. This method is disclosed in Patent Document 1.

[0005] Furthermore, there is also a method (hereinafter referred to as a transfer method) in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to an FC-BGA substrate, and then the support is peeled off from the interposer to provide the above-mentioned multilayer wiring structure on the FC-BGA substrate. This method is disclosed in Patent Document 2.

[0006] The wiring included in the multilayer wiring structure can be fabricated by a semi-additive method, as disclosed in Patent Document 3. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-225671 [Patent Document 2] International Publication No. 2018 / 047861 [Patent Document 3] Japanese Patent Application Publication No. 2018-022894 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a multilayer wiring board with excellent insulation reliability. [Means for solving the problem]

[0009] According to one aspect of the present invention, there is provided a semiconductor device comprising two or more layers stacked on top of each other, each of the two or more layers being an insulating resin layer having a first surface and a second surface opposite to the first surface, the insulating resin layer having a groove portion that opens on the first surface, an inorganic insulating layer including a portion that covers the bottom surface of the groove, a conductor layer including a wiring portion that fills the groove portion of the insulating resin layer, a first metal-containing layer that covers the surface of the wiring portion on the first surface side without covering the side surface of the wiring portion, and a second metal-containing layer that includes a portion interposed between the first metal-containing layer and the wiring portion and a portion that covers the side surface of the wiring portion, and that is made of a metal material different from the material of the first metal-containing layer. and a width D1 of the portion of the first metal-containing layer covering the surface of the wiring portion on the first surface side is smaller than a width D2 of a region of the surface of the second metal-containing layer facing a plane including the first surface. A multilayer wiring substrate is provided.

[0010] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to the above aspect, wherein the inorganic insulating layer further includes a portion that covers a connection portion between the bottom surface of the groove and a side wall of the groove.

[0011] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the inorganic insulating layer further includes a portion covering a side wall of the groove portion.

[0012] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the inorganic insulating layer further includes a portion covering the first surface.

[0013] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, tantalum oxide, tantalum nitride, and aluminum oxide.

[0014] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein the insulating resin layer is formed integrally in the thickness direction, the insulating resin layer further has a first recess that opens on the first surface and a second recess that opens on the second surface and is connected to one or more of the first recesses, the inorganic insulating layer further includes a portion that covers the bottom surface of the first recess, the conductor layer further includes a land portion that fills the first recess of the insulating resin layer and a via portion that protrudes from the first surface at the position of the land portion, the via portion fills the second recess of the insulating resin layer adjacent on the first surface side, and the first metal-containing layer further covers the surface of the land portion on the first surface side and the side surface of the via portion without covering the side surface of the land portion.

[0015] Here, the insulating resin layer being "integrally formed in the thickness direction" means that there are no internal interfaces that intersect with the thickness direction of the insulating resin layer, i.e., the insulating resin layer has a single-layer structure. Even if multiple insulating layers stacked on top of each other are made of the same material, their interfaces can be confirmed by observing the cross section with an electron microscope such as a scanning electron microscope.

[0016] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to the above aspect, wherein the inorganic insulating layer further includes a portion covering a side wall of the first recess.

[0018] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium, and the second metal-containing layer contains copper.

[0019] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein the arithmetic mean roughness Ra of the portion of the second metal-containing layer that covers the side surface of the wiring portion is 10 nm or less.

[0020] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the groove has a cross section perpendicular to its length direction that is inversely tapered.

[0021] According to yet another aspect of the present invention, there is provided a composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being a multilayer wiring board according to any of the above aspects.

[0022] According to yet another aspect of the present invention, there is provided a composite wiring board according to the above aspect, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[0023] According to yet another aspect of the present invention, there is provided a packaged device comprising a composite wiring board according to any of the above aspects and a functional device mounted on the surface of the second wiring board opposite the first wiring board.

[0024] Here, a "functional device" refers to a device that operates when supplied with at least one of power and an electrical signal, a device that outputs at least one of power and an electrical signal in response to an external stimulus, or a device that operates when supplied with at least one of power and an electrical signal and outputs at least one of power and an electrical signal in response to an external stimulus. The functional device may be in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device may include, for example, one or more of a large-scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a MEMS (Micro Electro Mechanical Systems). The MEMS may include, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0025] According to yet another aspect of the present invention, a method for manufacturing a semiconductor device includes forming two or more laminated layers, and forming each of the two or more layers by forming a dummy layer having a groove and at least one through hole communicating with the recess on an insulating resin layer having a recess; forming a first metal-containing layer covering an upper surface of the dummy layer and inner surfaces of the recess, the groove, and the through hole; forming a second metal-containing layer made of a metal material different from that of the first metal-containing layer on the first metal-containing layer; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, and removing the recess from the conductor layer. a portion where the first metal-containing layer is filled, a portion where the through hole is filled, and a portion where the groove is filled are obtained as a via portion, a land portion, and a wiring portion, respectively; thereafter, removing the dummy layer; removing the exposed portion of the first metal-containing layer; forming an inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the inorganic insulating layer, fills the gap between the land portion and the wiring portion, and has recesses provided at one or more positions of the land portion; and removing exposed portions of the inorganic insulating layer at the positions of the recesses provided in the insulating resin layer that covers the inorganic insulating layer.

[0026] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer is formed so as to further cover side surfaces of the land portion and side surfaces of the wiring portion.

[0027] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any of the above aspects, in which the inorganic insulating layer is formed so as to further cover the insulating resin layer exposed by removing the dummy layer.

[0028] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any of the above aspects, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, tantalum oxide, tantalum nitride, and aluminum oxide.

[0029] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any one of the above aspects, wherein the dummy layer is made of a photosensitive resin. [Effects of the Invention]

[0030] According to the present invention, a multilayer wiring board with excellent insulation reliability is provided. [Brief explanation of the drawings]

[0031] [Figure 1] 1 is a cross-sectional view of a packaged device according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view schematically showing a multilayer wiring substrate included in the packaged device shown in FIG. 1; [Figure 3] 3 is an enlarged cross-sectional view showing a part of the multilayer wiring board shown in FIG. 2. [Figure 4] FIG. 10 is an enlarged cross-sectional view showing a portion of a multilayer wiring board according to another embodiment of the present invention. [Figure 5] FIG. 10 is an enlarged cross-sectional view showing a portion of a multilayer wiring board according to still another embodiment of the present invention. [Figure 6] 1 is a cross-sectional view schematically showing a step in a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 7] 10A and 10B are cross-sectional views schematically showing another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 8] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 9] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 10] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 11] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 12] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 13] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 14] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 15] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 16] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 17] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 18] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 19] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 20] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 21] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 22] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 23] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 24]10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 25] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 26] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 27] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 28] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 29] 10 is a cross-sectional view schematically showing still another step in the method for manufacturing a multilayer wiring board according to one embodiment of the present invention. [Figure 30] 1A-1C are cross-sectional views illustrating a process for manufacturing a packaged device according to an embodiment of the present invention. [Figure 31] 5A to 5C are cross-sectional views schematically illustrating other steps in the method for manufacturing a packaged device according to an embodiment of the present invention. [Figure 32] 5A-5C are cross-sectional views schematically illustrating still other steps in a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Figure 33] FIG. 10 is a cross-sectional view schematically showing a multilayer wiring board according to a comparative example. [Figure 34] 34 is an enlarged cross-sectional view of a portion of the multilayer wiring board shown in FIG. 33. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are more specific embodiments of any of the above aspects. The embodiments described below are examples that embody the technical idea of the present invention, and the technical idea of the present invention is not limited to the materials, shapes, structures, arrangements, etc. of the components described below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

[0033] In the drawings referred to in the following description, components having the same or similar functions are denoted by the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions of multiple layers in the thickness direction may differ from the actual dimensions. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings. Furthermore, it should be noted that the same structure is depicted upside down in some drawings.

[0034] In this disclosure, the terms "top surface" and "bottom surface" refer to the two main surfaces of a plate-like member or a layer contained therein, i.e., the surface perpendicular to the thickness direction and having the largest area, and the back surface thereof, respectively, the surface shown at the top and the surface shown at the bottom in the drawings. Also, the term "side surface" refers to a surface that is perpendicular to or inclined with respect to the main surface.

[0035] Furthermore, in this disclosure, the expression "AA on BB" is used regardless of the direction of gravity. The state specified by the expression "AA on BB" includes a state in which AA is in contact with BB. The expression "AA on BB" does not exclude the presence of one or more other components between AA and BB.

[0036] <Structure> FIG. 1 is a cross-sectional view that schematically illustrates a packaged device according to one embodiment of the present invention.

[0037] The packaged device 1 shown in FIG. 1 includes a composite wiring board 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40.

[0038] The functional device 20 is, for example, a semiconductor chip, or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is a semiconductor chip. That is, here, the packaged device 1 is a semiconductor package.

[0039] The packaged device 1 includes a plurality of functional devices 20. The packaged device 1 may include only one functional device 20.

[0040] The functional devices 20 are bonded to the composite wiring substrate 10 via bonding electrodes 40. Here, the functional devices 20 are bonded to the composite wiring substrate 10 by flip-chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring substrate 10 by other bonding methods such as wire bonding.

[0041] The bonding electrodes 40 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The bonding electrodes 40 are made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, gold wires can be used to electrically connect the functional device 20 and the composite wiring board.

[0042] The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surface of the functional device 20. The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10.

[0043] The composite wiring board 10 includes an FC-BGA substrate 11, a multilayer wiring board 12, a sealing resin layer 13, and a bonding electrode 14.

[0044] The FC-BGA substrate 11 is an example of a first wiring substrate. The FC-BGA substrate 11 is bonded to, for example, a motherboard (not shown).

[0045] The FC-BGA substrate 11 includes a core layer 111 , an insulating layer 112 , a conductor layer 113 , an insulating layer 114 , and a joining conductor 115 .

[0046] The core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate made of woven or nonwoven fabric impregnated with a thermosetting insulating resin. The woven or nonwoven fabric may be made of, for example, glass fiber, carbon fiber, or aramid fiber. The insulating resin may be, for example, epoxy resin.

[0047] Through holes are provided in the core layer 111. Part of the conductor layer 113 covers the side walls of the through holes. Here, part of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 so as to produce through holes with side walls made of a conductor. These through holes with side walls made of a conductor may be filled with an insulator.

[0048] The remainder of the conductor layers 113 and the insulating layers 112 form multi-layer wiring structures on both major surfaces of the core layer 111. Each multi-layer wiring structure includes conductor layers 113 and insulating layers 112 stacked alternately.

[0049] Each insulating layer 112 included in the multilayer wiring structure is, for example, an insulating resin layer. The insulating layer 112 has a through hole formed therein.

[0050] The conductor layer 113 is made of a metal such as copper or an alloy, and may have a single-layer structure or a multi-layer structure.

[0051] Each conductor layer 113 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 sandwiched therebetween further includes a via portion covering the sidewall of a through hole provided in the insulating layer 112.

[0052] An insulating layer 114 is provided on the multilayer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 has a through hole that communicates with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

[0053] The joining conductor 115 is a metal bump provided on a portion of the conductor layer 113 that is exposed at the position of the through-hole in the insulating layer 114. The joining conductor is also called a joining terminal. The joining conductor 115 is made of, for example, solder.

[0054] The multilayer wiring board 12 is a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via bonding electrodes 40, and is also bonded to the FC-BGA substrate 11 via bonding electrodes 14. In other words, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA substrate 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

[0055] The bonding electrodes 14 are arranged between the multilayer wiring substrate 12 and the functional device 20. The pitch of the bonding electrodes 14 is wider than the pitch of the bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the underside of the FC-BGA substrate 11. The bonding electrodes 14 are made of, for example, solder.

[0056] The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12. The sealing resin layer is also called an underfill layer. The sealing resin layer 13 fixes the second wiring substrate 12 to the FC-BGA substrate 11.

[0057] The multilayer wiring board 12 will be described in more detail with reference to FIGS. Fig. 2 is a cross-sectional view schematically showing multilayer wiring board 12 included in packaged device 1 shown in Fig. 1. Fig. 3 is an enlarged cross-sectional view showing a part of multilayer wiring board 12 shown in Fig. 2.

[0058] The multilayer wiring board 12 shown in Figures 2 and 3 includes two or more layers 126, an insulating resin layer 124, an insulating resin layer 123, a conductor layer 122, an adhesion layer 127a, a seed layer 127b, a conductor layer 129, an insulating resin layer 130, and a surface treatment layer 131, as shown in Figure 2.

[0059] Two or more layers 126 are stacked on top of each other. Here, two layers 126 are stacked. The number of layers 126 may be three or more.

[0060] Each of these layers 126 includes an insulating resin layer 1263, an inorganic insulating layer 1264, a conductor layer 1262, a first metal-containing layer 1261a, and a second metal-containing layer 1261b.

[0061] The insulating resin layer 1263 is, for example, formed integrally in the thickness direction. The insulating resin layer 1263 is preferably made of an insulating resin that does not contain a filler.

[0062] 2 and 3, the insulating resin layer 1263 has a first surface S1 and a second surface S2 that is the rear surface of the first surface S1. The insulating resin layer 1263 is provided with a plurality of first recesses R1, a plurality of grooves G, and a plurality of second recesses R2.

[0063] The first recess R1 is open to the first surface S1. The first recess R1 is a land recess filled with a land portion 1262L, which will be described later.

[0064] The first recesses R1 have the same depth, which is smaller than the thickness of the insulating resin layer 1263.

[0065] One or more of the first recesses R1 communicate with one of the grooves G. In addition, one or more of the first recesses R1 communicate with a second recess R2 included in the insulating resin layer 1263 in which the first recesses R1 are provided.

[0066] The first recess R1 has an opening, a sidewall, and a bottom surface. The bottom surface of the first recess R1 is a plane perpendicular to the thickness direction. According to one example, the first recess R1 has a circular bottom surface, and the bottom surface of the first recess R1 that communicates with the second recess R2 has a circular opening.

[0067] Here, the first recess R1 has a shape in which the dimension in a direction perpendicular to the thickness direction gradually increases from the opening to the bottom. That is, the cross section of the first recess R1 perpendicular to the thickness direction is inversely tapered. According to one example, the first recess R1 has a truncated cone shape. The cross section of the first recess R1 parallel to the thickness direction may be rectangular. That is, the first recess R1 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

[0068] The groove G is open to the first surface S1. The groove G is filled with a wiring portion 1262W, which will be described later. The depth of the groove G is equal to the depth of the first recess R1.

[0069] The groove G has an opening, a sidewall, and a bottom surface, which is a flat surface perpendicular to the thickness direction.

[0070] The groove G has a shape in which the width gradually increases from the opening toward the bottom. That is, the groove G has an inversely tapered cross section perpendicular to the length direction. The groove G may have a rectangular cross section perpendicular to the length direction.

[0071] The second recess R2 is open to the second surface S2. The second recess R2 is a via recess filled with a via portion 1262V, which will be described later.

[0072] The second recesses R2 communicate with one or more of the first recesses R1. Specifically, each of the second recesses R2 communicates with one of the first recesses R1.

[0073] The second recess R2 has an opening and a sidewall. The second recess R2 communicates with the first recess R1 at its bottom. The orthogonal projection of the second recess R2 onto a plane perpendicular to the thickness direction is surrounded by the contour of the orthogonal projection onto the plane of the bottom surface of the first recess R1 communicating with the second recess R2.

[0074] The second recess R2 has a shape in which the dimension in a direction perpendicular to the thickness direction gradually increases from the opening to the bottom. That is, the cross section of the second recess R2 perpendicular to the thickness direction is inversely tapered. According to one example, the second recess R2 has a truncated cone shape. The cross section of the second recess R2 parallel to the thickness direction may be rectangular. That is, the second recess R2 may have a prismatic or cylindrical shape with its height parallel to the thickness direction. The first recess R1, the groove G, and the second recess R2 will be described in more detail later.

[0075] The inorganic insulating layer 1264 includes a portion covering the bottom surface and side walls of the groove portion G, a portion covering the first surface S1 of the insulating resin layer 1263, and a portion covering the bottom surface and side walls of the first recess portion R1.

[0076] As shown in FIG. 2, the inorganic insulating layer 1264 has a through-hole at the position of the second recess R2 of the insulating resin layer 1263 of the layer 126 containing the inorganic insulating layer 1264.

[0077] The conductor layer 1262 includes a land portion 1262L and a wiring portion 1262W that respectively fill the first recessed portion R1 and the groove portion G of the insulating resin layer 1263, and a via portion 1262V that protrudes from the first surface S1 at the position of the land portion 1262L. In each conductor layer 1262, each of the via portions 1262V is formed integrally with one of the lands 1262L included in that conductor layer 1262. The via portion 1262V of each conductor layer 1262 fills the second recessed portion R2 of the insulating resin layer 1263 in which the first recessed portion R1 and the groove portion G are respectively filled by the land portion 1262L and the wiring portion 1262W of that conductor layer 1262, and of another insulating resin layer adjacent to that insulating resin layer on the first surface S1 side.

[0078] The conductor layer 1262 is made of a metal such as copper or an alloy. The conductor layer 1262 may have a single-layer structure or a multi-layer structure. According to one example, the conductor layer 1262 is made of copper.

[0079] 2 and 3, first metal-containing layer 1261a covers the surface of wiring portion 1262W on the first surface S1 side without covering the side surface of wiring portion 1262W. Also, first metal-containing layer 1261a covers the surface of land portion 1262L on the first surface S1 side without covering the side surface of land portion 1262L. Also, first metal-containing layer 1261a covers the side surface and bottom surface of via portion 1262V in FIG. 2.

[0080] First metal-containing layer 1261a is an adhesion layer or seed adhesion layer that improves adhesion of second metal-containing layer 1261b to dummy layer 125 and insulating resin layer 124 (described later) to prevent peeling of second metal-containing layer 1261b. First metal-containing layer 1261a also serves as a barrier layer that prevents diffusion of metal from conductor layer 1262 to insulating resin layer 1263. According to one example, first metal-containing layer 1261a is a layer containing titanium, such as a titanium oxide layer.

[0081] Second metal-containing layer 1261b includes a portion interposed between first metal-containing layer 1261a and wiring portion 1262W and a portion covering the side surface of wiring portion 1262W. Second metal-containing layer 1261b also includes a portion interposed between first metal-containing layer 1261a and land portion 1262L and a portion covering the side surface of land portion 1262L. Second metal-containing layer 1261b also includes a portion interposed between first metal-containing layer 1261a and via portion 1262V. Second metal-containing layer 1261b is a seed layer that serves as a power supply layer when conductor layer 1262 is formed by electroplating.

[0082] Second metal-containing layer 1261b is made of a metal material different from the material of first metal-containing layer 1261a. Second metal-containing layer 1261b may be made of the same material as conductor layer 1262. Alternatively, second metal-containing layer 1261b may be made of a metal material with a lower ionization tendency than the material of conductor layer 1262. Second metal-containing layer 1261b contains, for example, copper. When second metal-containing layer 1261b contains copper, delamination is less likely to occur between insulating resin layer 1263 and second metal-containing layer 1261b. Even when two stacked layers are made of the same material, the interface between the layers can be confirmed by observing a cross section parallel to the stacking direction using, for example, a scanning electron microscope.

[0083] The portion of second metal-containing layer 1261b covering the side surface of wiring portion 1262W preferably has an arithmetic mean roughness Ra of 10 nm or less. When the arithmetic mean roughness Ra of the portion is 10 nm or less, the electrons travel a short distance along the surface of the portion, achieving high transmission characteristics. Furthermore, when the arithmetic mean roughness Ra of the portion is 10 nm or less, pinholes are less likely to occur in inorganic insulating layer 1264. The arithmetic mean roughness Ra is obtained by a method in accordance with JIS B 0601:2013.

[0084] 2, the insulating resin layer 124 is provided on one main surface of the multilayer wiring structure made up of the layer 126. The material of the insulating resin layer 124 may be the same as or different from the material of the insulating resin layer 1263.

[0085] The insulating resin layer 124 has a through hole at the position of the via portion 1262V included in the adjacent layer 126. The through hole of the insulating resin layer 124 is filled with the via portion 1262V included in the adjacent layer 126.

[0086] The through holes in the insulating resin layer 124 are recesses that open on the layer 126 side. These recesses have a shape in which the dimension in a direction perpendicular to the thickness direction gradually increases from bottom to top. That is, the recesses in the insulating resin layer 124 have an inversely tapered cross section perpendicular to the thickness direction. In one example, these through holes have a truncated cone shape. These through holes may have a rectangular cross section parallel to the thickness direction. That is, these through holes may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

[0087] The insulating resin layer 123 is provided on the insulating resin layer 124. The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124 and 1263. The insulating resin layer 123 has through holes at the positions of the through holes of the insulating resin layer 124.

[0088] The conductor layer 122 fills the through holes of the insulating resin layer 123. The conductor layer 122 is an electrode for joining the multilayer wiring board 12 and the functional device 20. The conductor layer 122 is made of, for example, copper.

[0089] The conductor layer 129 fills the second recess R2 of the insulating resin layer 1263 included in the layer 126 located above, and covers the opening of the second recess R2 and the surrounding area on the second surface S2 of the insulating resin layer 1263. The conductor layer 129 is made of a metal such as copper or an alloy.

[0090] The adhesion layer 127a includes a portion that covers the inner surface of the second recess R2 of the insulating resin layer 1263 included in the layer 126 located above, and a portion that covers the area around the opening of the second recess R2 on the second surface S2 of the insulating resin layer 1263. The adhesion layer 127a is a layer that improves the adhesion of the seed layer 127b to the insulating resin layer 1263 and makes it less likely for the seed layer 127b to peel off.

[0091] The seed layer 127b is provided on the adhesion layer 127a and serves as a power supply layer when the conductor layer 129 is formed by electrolytic plating.

[0092] The insulating resin layer 130 is provided on the insulating resin layer 1263 included in the layer 126 located above and the conductor layer 129. The insulating resin layer 130 has a through hole at the position of the conductor layer 129.

[0093] The surface treatment layer 131 is provided on the portion of the conductor layer 129 that is exposed in the through-hole of the insulating resin layer 130. The surface treatment layer 131 is provided to prevent oxidation of the surface of the conductor layer 129 and to improve wettability with solder.

[0094] In FIG. 3, length t1 is the distance between the first surface S1 of one layer 126 and the bottom surface of the groove G included in the other layer 126 between two adjacent layers 126. Length t2 is the depth of the groove G in the layer 126. Length t3 is the distance between the bottom surface of the groove G included in the layer 126 and the second surface S2 of this layer 126. Length t4 is the width of the bottom surface of the groove G included in the layer 126. Length t5 is the distance between the bottom surfaces of adjacent grooves G in the width direction of the groove G.

[0095] FIG. 4 is an enlarged cross-sectional view showing a portion of multilayer wiring board 12 according to another embodiment of the present invention. Multilayer wiring board 12 according to this embodiment is the same as multilayer wiring board 12 described above, except that width D1 shown in FIG. 4 is smaller than width D2 shown in FIG. 4. Width D1 is the width of a portion of first metal-containing layer 1261a that covers the surface of wiring portion 1262W on the first surface S1 side. In other words, width D1 is the width of first metal-containing layer 1261a in a direction perpendicular to the length direction of wiring portion 1262W and perpendicular to the thickness direction of wiring portion 1262W. Width D2 is the width of a region of the surface of second metal-containing layer 1261b that faces a plane including first surface S1.

[0096] When width D1 is smaller than width D2, the contact area between inorganic insulating layer 1264 and second metal-containing layer 1261b is large, and therefore delamination is less likely to occur between inorganic insulating layer 1264 and second metal-containing layer 1261b.

[0097] 5 is an enlarged cross-sectional view showing a portion of multilayer wiring board 12 according to yet another embodiment of the present invention. In multilayer wiring board 12 according to this embodiment, inorganic insulating layer 1264 covers the bottom surfaces and corners of the side surfaces of grooves G. That is, in multilayer wiring board 12 according to this embodiment, inorganic insulating layer 1264 includes a portion covering the bottom surfaces of grooves G, a portion covering the connection portions between the bottom surfaces of grooves G and the side walls of grooves G, and a portion covering first surface S1 of insulating resin layer 1263. The inorganic insulating layer 1264 is the same as the multilayer wiring board 12 described above, except that instead of including a portion covering the bottom surface and side walls of the groove portion G, a portion covering the first surface S1 of the insulating resin layer 1263, and a portion covering the bottom surface and side walls of the first recess R1, the inorganic insulating layer 1264 includes a portion covering the bottom surface of the groove portion G, a portion covering the connection portion between the bottom surface of the groove portion G and the side wall of the groove portion G, and a portion covering the first surface S1 of the insulating resin layer 1263.

[0098] As shown in FIG. 5, on the first surface S1 of the insulating resin layer 1263, the inorganic insulating layer 1264 is not provided directly below the portion of the inorganic insulating layer 1264 that covers the bottom surface of the groove G.

[0099] According to this embodiment, for example, when the line / space of the wiring is about 5 μm / 5 μm, high insulation reliability can be achieved even if the inorganic insulating layer 1264 does not cover the entire side surface of the groove G.

[0100] <Manufacturing method> The multilayer wiring substrate 12 included in this packaged device 1 can be manufactured, for example, by the following method.

[0101] 6 to 29 are cross-sectional views that schematically show a method for manufacturing a multilayer wiring board according to one embodiment of the present invention.

[0102] In this method, first, a release layer 3 is formed on one surface of a support 2 as shown in FIG.

[0103] Since light may be irradiated onto the release layer 3 through the support 2, it is advantageous for the support 2 to be light-transmitting. For example, a glass plate can be used as the support 2. A rectangular glass plate is suitable for large sizes. Furthermore, a glass plate can achieve excellent flatness and high rigidity. Therefore, a glass plate as the support 2 is suitable for forming a fine pattern thereon.

[0104] Furthermore, a glass plate has a small coefficient of thermal expansion (CTE) and is therefore less susceptible to distortion, making it excellent for ensuring pattern placement accuracy and flatness. When a glass plate is used as the support 2, the thickness of the glass plate is preferably thicker in order to prevent warping during the manufacturing process, and is, for example, 0.5 mm or more, preferably 1.2 mm or more.

[0105] The CTE of the glass plate is preferably 3 ppm or more and 16 ppm or less, and from the viewpoint of compatibility with the CTE of the FC-BGA substrate 11 and the functional device 20, it is more preferably about 10 ppm.

[0106] As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used.

[0107] On the other hand, if the support 2 does not require optical transparency when peeling it off, such as when the peeling layer 3 is made of a resin that foams when heated, the support 2 can be made of a material with little distortion, such as metal or ceramics.

[0108] Hereinafter, as an example, it is assumed that the material of the release layer 3 is a resin that absorbs ultraviolet light (UV light) and becomes peelable, and the support 2 is a glass plate.

[0109] The release layer 3 may be made of a resin that becomes peelable by absorbing light such as UV light and generating heat or changing its properties, or a resin that becomes peelable by foaming when heated. The material of the release layer 3 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, as well as inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. The release layer 3 may further contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0110] The release layer 3 may have a single-layer structure or a multilayer structure. For example, a protective layer may be provided on the release layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and a layer for improving adhesion between the support 2 and the release layer 3 may be further provided. A laser light reflective layer or a metal layer may further be provided between the release layer 3 and the multilayer wiring structure.

[0111] In addition, when a resin that can be peeled off by light such as UV light, for example laser light, is used as the material for the peeling layer 3, if the support 2 is translucent, the peeling layer 3 may be irradiated with light through the support 2.

[0112] 7, an adhesion layer 4a and a seed layer 4b are formed in a vacuum. The adhesion layer 4a improves the adhesion of the seed layer 4b to the release layer 3 and prevents peeling of the seed layer 4b in subsequent steps. The seed layer 4b also serves as a power supply layer in electrolytic plating for forming the conductor layer 122.

[0113] The adhesion layer 4a and the seed layer 4b can be formed by, for example, sputtering or vapor deposition. Materials for the adhesion layer 4a and the seed layer 4b include, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, Cu alloys, and combinations thereof. Here, as an example, considering electrical properties, ease of manufacturing, and cost, a titanium layer and a copper layer are used for the adhesion layer 4a and the seed layer 4b, respectively, and they are formed by sputtering.

[0114] The total thickness of the adhesion layer 4a and the seed layer 4b is preferably 1 μm or less. Here, as an example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 4a, and a copper layer with a thickness of 300 nm is formed as the seed layer 4b.

[0115] Next, as shown in FIG. 8, a resist layer 121 is formed on the seed layer 4b. The resist layer 121 is made of a photosensitive resin. As the photosensitive resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used. The photosensitive resin may be in a liquid form or a film form.

[0116] When a liquid photosensitive resin is used as the material of the resist layer 121, the resist layer 121 can be formed on the seed layer 4b by any of methods such as slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like resist is used as the resist layer 121, the resist layer 121 can be provided on the seed layer 4b by any of methods such as lamination, vacuum lamination, and vacuum pressing.

[0117] Next, through holes are formed in the resist layer 121 by photolithography. The shape of the through holes in a plan view is set according to the pitch and shape of the bonding electrodes of the functional device 20. Here, as an example, the through holes have circular openings with a diameter of 25 μm and are spaced at a pitch of 55 μm. Here, plan view means observing the object in the thickness direction, that is, observing the orthogonal projection of the object onto a plane perpendicular to the thickness direction.

[0118] The thickness of the resist layer 121 is set according to the thickness of the conductor layer 122 to be formed next. Here, as an example, the thickness of the resist layer 121 is set to 8 μm.

[0119] After forming these through holes, plasma treatment may be carried out to remove residues left behind during development.

[0120] 9, a conductor layer 122 is formed on the seed layer 4b by electrolytic plating. The conductor layer 122 constitutes an electrode for bonding to the functional device 20. Examples of electrolytic plating for forming the conductor layer 122 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Among these, electrolytic copper plating is preferable because it is simple, inexpensive, and can achieve good electrical conductivity.

[0121] As described above, the conductor layer 122 serves as an electrode for bonding to the functional device 20. Therefore, the thickness of the conductor layer 122 is preferably 1 μm or more from the viewpoint of solder bonding, and is preferably 30 μm or less from the viewpoint of productivity.

[0122] 10, the resist layer 121 is removed. The resist layer 121 is removed by, for example, a dry etching method, or is dissolved or peeled off by immersion in an alkaline solution or solvent.

[0123] 11, an insulating resin layer 123 is formed so as to encapsulate the conductor layer 122. The material of the insulating resin layer 123 may be a photosensitive resin or a non-photosensitive resin. The material of the insulating resin layer 123 may be the same as or different from the material of the insulating resin layers 124, 130, and 1263 described below.

[0124] 12, the upper surface of the conductor layer 122 is exposed by physical polishing, or by physical polishing and chemical mechanical polishing (CMP). The structure obtained in this manner can also be obtained by a damascene process.

[0125] 13, an insulating resin layer 124 having a through hole at the position of the conductor layer 122 is provided on the conductor layer 122 and the insulating resin layer 123. The through hole in the insulating resin layer 124 is a second recess R2 that opens on the second surface of the insulating resin layer 124, in this case, the top surface of the insulating resin layer 124. The second recess R2 may be formed so that its cross section has a rectangular shape, but is preferably formed in a forward tapered shape. Forming the second recess R2 in a forward tapered shape makes it easier to form the first metal-containing layer 1261a and the second metal-containing layer 1261b without creating discontinuities within the second recess R2.

[0126] The insulating resin layer 124 is made of, for example, a photosensitive resin. For example, the same material as that described above for the resist layer 121 can be used as the photosensitive resin. The insulating resin layer 124 having through holes can be formed by, for example, the same method as that described above for the resist layer 121.

[0127] Alternatively, the insulating resin layer 124 is made of a non-photosensitive resin. Examples of the non-photosensitive resin that can be used include polyimide resin, benzocyclobutene resin, epoxy resin, and modified versions of these. Non-photosensitive resins such as polyimide have excellent insulating and mechanical properties, and can also achieve high heat resistance. Furthermore, inorganic particles such as silica, alumina, and zirconia may be added to the non-photosensitive resin as a filler. Here, as an example, a non-photosensitive polyimide resin is used as the non-photosensitive resin.

[0128] The non-photosensitive resin may be in the form of a liquid or a film.

[0129] When a liquid non-photosensitive resin is used, the insulating resin layer 124 can be formed by a method selected from, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

[0130] When a film-like non-photosensitive resin is provided as the insulating resin layer 124, lamination, vacuum lamination, vacuum pressing, or the like can be applied.

[0131] Here, as an example, a photosensitive epoxy resin is applied onto the conductor layer 122 and the insulating resin layer 123 by spin coating. The photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little as it hardens, which is advantageous for the subsequent formation of fine patterns. Also, here, as an example, the insulating resin layer 124 is formed to a thickness of 2 μm.

[0132] After forming the insulating resin layer 124, the surface may be subjected to physical polishing or may be subjected to physical polishing and polishing such as CMP in order to flatten the surface. When a non-photosensitive resin is used as the material for the insulating resin layer 124, the through holes can be formed by, for example, laser light irradiation.

[0133] 14, a dummy layer 125 having grooves G' and through holes R1', one or more of which communicate with the second recesses R2, is formed on the insulating resin layer 124 and the conductor layer 122. The grooves G' and through holes R1' of the dummy layer 125 correspond to the grooves G and first recesses R1 of the insulating resin layer 1263, respectively.

[0134] The dummy layer 125 is made of a photosensitive resin. For example, the same material as that described above for the resist layer 121 can be used as the photosensitive resin. The dummy layer 125 having the groove G' and the through hole R1' can be formed by the same method as that described above for the resist layer 121.

[0135] The through hole R1' in the dummy layer 125 is formed so that the opening diameter at its upper surface is larger than the opening diameter at its upper surface of the through hole in the insulating resin layer 124. The through hole R1' is formed to have a forward tapered shape. The groove G' is also formed so that the cross section perpendicular to the length direction has a forward tapered shape.

[0136] Groove G' and through hole R1' may be formed to have a rectangular cross section, but forming them in a forward tapered shape makes it easier to form first metal-containing layer 1261a and second metal-containing layer 1261b without creating discontinuities within groove G' and through hole R1'.

[0137] Furthermore, when the groove G' and the through hole R1' are formed so that their cross sections have a forward tapered shape, the contact area between the insulating resin layer 1263 and the inorganic insulating layer 1264 is larger than when the cross sections are rectangular without changing their cross-sectional areas. This makes it possible to improve the adhesion between the insulating resin layer 1263 and the inorganic insulating layer 1264. Similarly, it is possible to improve the adhesion between the insulating resin layer 1263 and the conductor layer 1262. This makes it possible to reduce the likelihood of delamination.

[0138] Next, in a vacuum, a first metal-containing layer 1261a is formed to cover the upper surface of dummy layer 125, the inner surface of second recess R2, the inner surface of groove G', and the inner surface of through-hole R1', as shown in Fig. 15. Subsequently, a second metal-containing layer 1261b made of a metal material different from that of first metal-containing layer 1261a is formed on first metal-containing layer 1261a.

[0139] The first metal-containing layer 1261a and the second metal-containing layer 1261b are a seed adhesion layer (or adhesion layer) and a seed layer, respectively. The first metal-containing layer 1261a and the second metal-containing layer 1261b can be made of the same materials as those described above for the adhesion layer 4a and the seed layer 4b, respectively. The first metal-containing layer 1261a and the second metal-containing layer 1261b can be formed by the same methods as those described above for the adhesion layer 4a and the seed layer 4b, respectively.

[0140] The material of second metal-containing layer (1261b) is preferably the same as that of conductor layer (1262).

[0141] The sum of the thickness of first metal-containing layer (1261a) and the thickness of second metal-containing layer (1261b) is preferably 1 μm or less, which is preferable as a power supply layer for electrolytic plating.

[0142] The thickness of first metal-containing layer 1261a is preferably in the range of 10 nm to 100 nm, and more preferably in the range of 30 nm to 80 nm.

[0143] The thickness of second metal-containing layer 1261b is preferably in the range of 40 nm to 400 nm, and more preferably in the range of 100 nm to 350 nm.

[0144] Here, as an example, a titanium-containing layer is used as first metal-containing layer 1261a, taking into consideration electrical properties, ease of manufacturing, and cost, as well as improving adhesion between insulating resin layer 1263 and second metal-containing layer 1261b. A copper-containing layer is used as second metal-containing layer 1261b, taking into consideration electrical properties, ease of manufacturing, and cost. First metal-containing layer 1261a and second metal-containing layer 1261b are formed sequentially by sputtering. The thickness of first metal-containing layer 1261a is 50 nm, and the thickness of second metal-containing layer 1261b is 300 nm.

[0145] Note that, in the etching of first metal-containing layer 1261a described below, a material other than titanium can be used as first metal-containing layer 1261a as long as the etching rate is sufficiently higher than that of copper. Furthermore, a layer made of a metal material different from the material of first metal-containing layer 1261a and the material of second metal-containing layer 1261b may be provided between first metal-containing layer 1261a and second metal-containing layer 1261b.

[0146] Next, as shown in FIG. 16, a conductor layer 1262' is formed on the second metal-containing layer 1261b. The conductor layer 1262' is formed so as to fill the second recess R2, the groove G', and the through-hole R1'. The conductor layer 1262' can be made of the same material as described above for the conductor layer 122. The conductor layer 1262' can be formed by the same method as described above for the conductor layer 122. Here, as an example, the conductor layer 1262 is assumed to be a copper layer formed by electrolytic plating.

[0147] 17, the conductor layer 1262′, the first metal-containing layer 1261a, and the second metal-containing layer 1261b are subjected to polishing such as physical polishing and CMP to remove portions of the conductor layer 1262′, the first metal-containing layer 1261a, and the second metal-containing layer 1261b that are located outside the second recess R2, the groove G′, or the through hole R1′. Note that this polishing may also remove portions near the top surface of the dummy layer 125.

[0148] Of the conductor layer 1262' shown in FIG. 16, the portion that remains after the polishing is the conductor layer 1262 shown in FIG. In this manner, the portions of the conductor layer 1262 where the second recesses R2 are filled, the portions where the through holes R1' are filled, and the portions where the grooves G' are filled are obtained as the via portions 1262V, the land portions 1262L, and the wiring portions 1262W, respectively. According to this method, the via portions 1262V, the land portions 1262L, and the wiring portions 1262W are obtained by polishing, and therefore a smoother conductor surface can be obtained compared to the semi-additive method.

[0149] 18, the dummy layer 125 is removed. The dummy layer 125 can be removed by dry etching or by immersion in an alkaline solution or solvent.

[0150] Next, as shown in Fig. 19, the exposed portions of first metal-containing layer 1261a are removed by an etching agent in the structure shown in Fig. 18. By removing the exposed portions of first metal-containing layer 1261a, second metal-containing layer 1261b covering the side surfaces of land portion 1262L and wiring portion 1262W is exposed.

[0151] The etching agent used is a chemical solution that selectively etches first metal-containing layer (1261a) relative to second metal-containing layer (1261b). This etching maintains the smoothness of the portions of second metal-containing layer (1261b) that cover the side surfaces of wiring portion (1262W) and land portion (1262L). It is preferable to use an etching solution whose etching rate for first metal-containing layer (1261a) is 10 times or more higher than that for second metal-containing layer (1261b).

[0152] For example, after this etching, the portions of second metal-containing layer 1261b that cover the side surfaces of wiring portion 1262W and land portion 1262L have an arithmetic mean roughness Ra of 10 nm or less.

[0153] 4 may be smaller than width D2. When width D1 and width D2 are approximately the same and the adhesion between inorganic insulating layer 1264 and second metal-containing layer 1261b is insufficient, the contact area between inorganic insulating layer 1264 and second metal-containing layer 1261b can be increased by making width D1 smaller than width D2. This can improve the adhesion between inorganic insulating layer 1264 and second metal-containing layer 1261b.

[0154] 20, an inorganic insulating layer 1264 is formed on the insulating resin layer 124 and the conductor layer 1262. The inorganic insulating layer 1264 is formed so as to cover the upper surface of the insulating resin layer 124, the upper and side surfaces of the wiring portion 1262W, and the upper and side surfaces of the land portion 1262L.

[0155] The inorganic insulating layer 1264 is formed by, for example, plasma CVD (Chemical Vapor Deposition) and is made of one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, tantalum oxide, tantalum nitride, and aluminum oxide.

[0156] The thickness of the inorganic insulating layer 1264 is preferably 0.05 μm or more, and more preferably 0.1 μm or more. If the inorganic insulating layer 1264 is too thin, discontinuities such as pinholes are likely to occur. The thickness of the inorganic insulating layer 1264 is preferably less than 1 μm, and more preferably 0.5 μm or less. If the inorganic insulating layer 1264 is made thicker, for example, its deposition or partial removal by etching requires longer time. Furthermore, if the inorganic insulating layer 1264 is too thick, delamination is likely to occur between the inorganic insulating layer 1264 and the insulating resin layer 1263 or between the inorganic insulating layer 1264 and the second metal-containing layer 1261b.

[0157] In order to improve the adhesion between the inorganic insulating layer 1264 and the insulating resin layer 1263, the inorganic insulating layer 1264 may be treated with a silane coupling agent.

[0158] Next, as shown in FIG. 21, an insulating resin layer 1263 is provided to cover the inorganic insulating layer 1264 and fill the gap between the land portion 1262L and the wiring portion 1262W. A through hole is formed in the insulating resin layer 1263 as the second recess R2. The lower and upper surfaces of the insulating resin layer 1263 are the first surface S1 and the second surface S2, respectively. The recess of the insulating resin layer 1263 filled with the land portion 1262L is the first recess R1 described above. The recess of the insulating resin layer 1263 filled with the wiring portion 1262W is the groove G described above.

[0159] The insulating resin layer 1263 is made of a photosensitive resin or a non-photosensitive resin. For example, the same materials as those described above for the resist layer 121 and the insulating resin layer 124 can be used as the photosensitive resin or non-photosensitive resin. The insulating resin layer 1263 having the first recess R1, the second recess R2, and the groove G can be formed by the same method as those described above for the resist layer 121 and the insulating resin layer 124.

[0160] The thickness of the insulating resin layer 1263 is, for example, in the range of 1.5 μm to 5 μm. Here, as an example, the insulating resin layer 1263 is formed to a thickness of 2 μm.

[0161] 22, the portion of the inorganic insulating layer 1264 exposed in the second recess R2 is removed by, for example, dry etching using the insulating resin layer 1263 as a mask.

[0162] In this manner, layer 126 including first metal-containing layer 1261a, second metal-containing layer 1261b, conductor layer 1262, insulating resin layer 1263, and inorganic insulating layer 1264 is obtained.

[0163] 14 to 22 is then repeated, resulting in a multilayer wiring structure including two layers 126. By repeating the above sequence two or more times, the number of layers 126 included in the multilayer wiring structure can be increased to three or more.

[0164] 23, an adhesion layer 127a is formed to cover the upper surface of the insulating resin layer 1263 included in the upper layer 126 and the inner surface of the second recess R2. Subsequently, a seed layer 127b made of a metal material different from the material of the adhesion layer 127a is formed on the adhesion layer 127a. The seed layer 127b is preferably made of the same material as the conductor layer 129 or a metal material with a lower ionization tendency than the material of the conductor layer 129.

[0165] The adhesion layer 127a and the seed layer 127b can be made of the same materials as those described above for the adhesion layer 4a and the seed layer 4b, respectively, and can be formed by the same methods as those described above for the adhesion layer 4a and the seed layer 4b, respectively.

[0166] 24, a resist layer 128 having through holes is formed on the seed layer 127b. Each of the through holes in the resist layer 128 communicates with a second recess R2 provided in the insulating resin layer 1263 included in the upper layer 126.

[0167] The resist layer 128 is made of a photosensitive resin. The same materials as those described above for the resist layer 121 can be used for the resist layer 128. The resist layer 128 can be formed by the same method as that described above for the resist layer 121.

[0168] 25, a conductor layer 129 is formed on the seed layer 127b. The conductor layer 129 can be made of the same material as described above for the conductor layer 122. The conductor layer 129 can be formed by the same method as described above for the conductor layer 122.

[0169] 26, the resist layer 128 is removed. The resist layer 128 can be removed in the same manner as described above for the resist layer 121.

[0170] 27, the exposed portions of the adhesion layer 127a and the seed layer 127b are removed. The adhesion layer 127a and the seed layer 127b can be removed by, for example, immersing them in a chemical solution. The chemical solution may, for example, contain hydrogen peroxide.

[0171] 28, an insulating resin layer 130 is formed on the insulating resin layer 1263 and the conductor layer 129. The insulating resin layer 130 has through holes at the positions of the conductor layer 129. The insulating resin layer 130 can be formed, for example, by providing a solder resist on the insulating resin layer 1263 and the conductor layer 129, and then exposing and developing the solder resist. An insulating layer obtained from the solder resist is also called a solder resist layer.

[0172] The solder resist may be made of insulating resin such as epoxy resin, acrylic resin, etc. Here, as an example, a photosensitive epoxy resin containing filler is used as the solder resist.

[0173] 29, a surface treatment layer 131 is provided on the conductor layer 129. The surface treatment layer 131 is provided for the purposes of preventing oxidation of the surface of the conductor layer 129 and improving wettability to solder. Here, as an example, an electroless Ni / Pd / Au plating layer is formed as the surface treatment layer 131.

[0174] An OSP (Organic Solderability Preservative) film, i.e., a surface treatment layer made of a water-soluble preflux, may be formed as the surface treatment layer 131. Alternatively, an electroless tin plating layer or an electroless Ni / Au plating layer may be formed as the surface treatment layer 131.

[0175] Next, the bonding conductors 132 are formed on the surface treatment layer 131. The bonding conductors 132 are, for example, metal bumps such as solder bumps. The bonding conductors 132 can be formed, for example, by placing solder material such as solder balls on the surface treatment layer 131, melting them, and then cooling them to adhere them to the surface treatment layer 131.

[0176] In this manner, a multilayer wiring board 12 supported by the support 2, that is, a multilayer wiring board with a support, is obtained.

[0177] By using the multilayer wiring board with a support thus obtained, the packaged device 1 shown in FIG. 1 can be manufactured, for example, by the following method.

[0178] Figure 30 is a cross-sectional view schematically illustrating a step in a method for manufacturing a packaged device according to an embodiment of the present invention, Figure 31 is a cross-sectional view schematically illustrating another step in a method for manufacturing a packaged device according to an embodiment of the present invention, and Figure 32 is a cross-sectional view schematically illustrating yet another step in a method for manufacturing a packaged device according to an embodiment of the present invention.

[0179] 30, the multilayer wiring board 12 supported by the support member 2 is bonded to the FC-BGA substrate 11. Then, the bonded portion is sealed with a sealing resin layer 13.

[0180] The material for the encapsulating resin layer 13 can be, for example, a mixture of a resin and a filler. The resin can be, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins. The filler can be, for example, one of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide, or two or more of these. The encapsulating resin layer 13 can be formed, for example, by filling a liquid material between the FC-BGA substrate 11 and the multilayer wiring substrate 12.

[0181] In this manner, a composite wiring board 10 is obtained that includes the FC-BGA substrate 11 and the multilayer wiring board 12. At this point, the support body 2 remains provided on the multilayer wiring board 12.

[0182] Next, as shown in Fig. 31, laser light 50 is irradiated onto release layer 3 from the support 2 side, and as shown in Fig. 32, support 2 and composite wiring board 10 are peeled from each other. As described above, the material of release layer 3 is a resin that absorbs ultraviolet light (UV light) and becomes peelable, so that it is possible to peel support 2 from composite wiring board 10 by irradiating with laser light 50. If release layer 3 remains on composite wiring board 10, it is removed by, for example, etching. In addition, adhesion layer 4a and seed layer 4b are also removed by, for example, etching.

[0183] Thereafter, the functional device 20 shown in FIG. Prior to bonding of the functional device 20, a surface treatment layer such as an electroless Ni / Pd / Au plating layer, an OSP film, an electroless tin plating layer, or an electroless Ni / Au plating layer may be provided on the conductor layer 122 exposed on the surface in order to prevent oxidation and improve wettability to solder.

[0184] Next, the joints are sealed with a sealing resin layer 30 . As the material of the encapsulating resin layer 30, for example, the materials exemplified as the material of the encapsulating resin layer 13 can be used. The encapsulating resin layer 30 can be formed, for example, by the same method as that described above for the encapsulating resin layer 13. In this manner, the packaged device 1 shown in FIG. 1 is completed.

[0185] In the above method, the multilayer wiring substrate 12 is bonded to the FC-BGA substrate 11, and then the functional device 20 is bonded to the multilayer wiring substrate 12. Alternatively, the functional device 20 may be bonded to the multilayer wiring substrate 12, and then the multilayer wiring substrate 12 may be bonded to the FC-BGA substrate 11.

[0186] According to the above-mentioned method, the surfaces of the conductor layers 122 and 129 have an arithmetic mean roughness Ra of 100 nm or more, for example. If these surfaces are rough, the connection reliability between the components is high.

[0187] <Effects> Interposers obtained using silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and semiconductor front-end process equipment. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from a single wafer is not necessarily large. Furthermore, the manufacturing equipment is expensive. Therefore, silicon interposers are expensive. Furthermore, because silicon wafers are semiconductors, the use of silicon interposers also presents the problem of degradation of transmission characteristics.

[0188] No silicon wafers are required to manufacture the multilayer wiring board 12. Furthermore, in the multilayer wiring board 12, many of the insulating layers can be insulating resin layers. Therefore, the multilayer wiring board 12 can be manufactured using inexpensive materials and equipment, enabling cost reductions and achieving excellent transmission characteristics.

[0189] The technique of directly fabricating a multilayer wiring structure containing a conductor layer with a fine wiring pattern on an FC-BGA substrate minimizes the degradation of transmission characteristics seen with silicon interposers. However, this method has issues with the manufacturing yield of the FC-BGA substrate itself and the difficulty of forming a multilayer wiring structure containing a conductor layer with a fine wiring pattern on a core layer such as a glass epoxy substrate, resulting in low overall manufacturing yield. Furthermore, it is difficult to achieve high symmetry with this FC-BGA substrate across a plane that bisects its thickness. Therefore, such FC-BGA substrates are prone to warping and distortion when heated.

[0190] In manufacturing the above-described composite wiring board 10 and packaged device 1, multilayer wiring board 12 is manufactured separately from FC-BGA substrate 11, and then they are bonded together. A multilayer wiring structure including conductor layer 1262 having a fine wiring pattern is not formed in FC-BGA substrate 11, but is formed in multilayer wiring board 12. Therefore, the above-described composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

[0191] Furthermore, in manufacturing the composite wiring board 10, the multilayer wiring structure including the conductor layer 1262 having a fine wiring pattern is formed on the support 2, rather than on a core layer such as a glass epoxy substrate. Because a material with excellent smoothness can be used as the support 2, the fine patterns formed thereon can be formed with high shape accuracy. For these reasons as well, the above-described composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

[0192] Furthermore, in the above-described composite wiring board 10 and packaged device 1, it is easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of the FC-BGA substrate 11, and it is also easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of the multilayer wiring board 12. Therefore, the above-described composite wiring board 10 and packaged device 1 is less likely to warp or distort when heated.

[0193] Semi-additive methods are also available for forming fine wiring. In the semi-additive method, a base layer is first prepared, and a first metal-containing layer and a second metal-containing layer are formed on the base layer. Next, a resist layer is formed in a pattern on the second metal-containing layer, and a conductor layer including a wiring portion is formed on the second metal-containing layer by electrolytic copper plating. The resist is then removed, and then unnecessary portions of the first metal-containing layer and the second metal-containing layer are further removed. Specifically, after removing the resist, portions of the first metal-containing layer and the second metal-containing layer that are not covered by the conductor layer are removed by etching. The base layer and the conductor layer are then covered with an insulating resin layer. In this manner, fine wiring and the like are formed on the base layer.

[0194] According to this method, when the unnecessary layer is etched, the surface of the conductor layer is also etched. As a result, the surface of the conductor layer becomes rough. In this case, the arithmetic mean roughness Ra of the surface of the conductor layer is about 100 nm. When the surface of the conductor layer is rough, especially when the surface of the wiring portion is rough, the electrons travel a long distance through the surface, making it impossible to achieve high transmission characteristics.

[0195] In the semi-additive method, an inorganic insulating layer may be provided on the surface of the wiring portion after removing the unnecessary first and second metal-containing layers to prevent the conductor layer material, such as copper, from diffusing into the insulating resin layer. However, as described above, the surface of the conductor layer formed by the semi-additive method is rough, and pinholes are likely to occur in the inorganic insulating layer when the inorganic insulating layer is thin, for example, less than 1 μm. If pinholes occur, the conductor layer material diffuses through the pinholes into the insulating resin layer, making it impossible to achieve high insulation reliability.

[0196] Furthermore, if the inorganic insulating layer is thickened, it takes longer to form the layer and to partially remove it by etching. Furthermore, in this case, peeling is likely to occur between the conductor layer and the inorganic insulating layer due to the difference in the linear expansion coefficient between the copper contained in the conductor layer and the material of the inorganic insulating layer. In particular, in vias with a large conductor area, disconnection due to interlayer peeling is likely to occur. In the above case, peeling is also likely to occur between the inorganic insulating layer and the insulating resin layer due to the difference in the linear expansion coefficient between the material of the inorganic insulating layer and the material of the insulating resin layer.

[0197] On the other hand, according to the above-described method for manufacturing the multilayer wiring substrate 12, the side surfaces of the wiring portion 1262W are covered with the second metal-containing layer 1261b. Furthermore, according to the above-described method, the upper surfaces of the wiring portion and the portions of the second metal-containing layer 1261b that cover the side surfaces of the wiring portion 1262W are hardly etched. Therefore, the upper surface of the wiring portion 1262W and the above-described portions of the second metal-containing layer 1261b are smooth. When the upper surface of the wiring portion 1262W and the above-described portions of the second metal-containing layer 1261b are smooth, the electrons travel a short distance through the upper surface of the wiring portion 1262W and the above-described portions of the second metal-containing layer 1261b, thereby achieving high transmission characteristics. Furthermore, when the upper surface of the wiring portion 1262W and the above-described portions of the second metal-containing layer 1261b are smooth, pinholes are less likely to occur in the inorganic insulating layer 1264, thereby achieving high insulation reliability without increasing the thickness of the inorganic insulating layer 1264.

[0198] 2 to 5, in the above-described multilayer wiring board 12, the first metal-containing layer 1261a covers the surface of the wiring portion 1262W on the first surface S1 side. Therefore, in two adjacent layers 126, metal is unlikely to diffuse from the wiring portion 1262W included in one layer 126 to the insulating resin layer 1263 included in the other layer 126. Therefore, the above-described multilayer wiring board 12 can achieve excellent insulation reliability.

[0199] 2 to 5, in the above-described multilayer wiring board 12, first metal-containing layer 1261a covers the surface of wiring portion 1262W on the first surface S1 side without covering the side surfaces of wiring portion 1262W. Therefore, for example, when a material having a lower conductivity than the material of wiring portion 1262W is used as first metal-containing layer 1261a, the above-described multilayer wiring board 12 can achieve a lower wiring resistivity than a multilayer wiring board including first metal-containing layer 1261a that also covers the side surfaces of wiring portion 1262W. [Example]

[0200] Next, the effects of using the multilayer wiring board 12 and the manufacturing method thereof described above will be described.

[0201] (Example) The multilayer wiring board 12 described with reference to Figures 2 and 3 was manufactured by the method described with reference to Figures 6 to 29. The lengths t1, t2, t3, t4, and t5 of the multilayer wiring board 12 were set to 2 µm. The thickness of the inorganic insulating layer 1264 was set to 0.05 µm. The arithmetic mean roughness Ra of the portion of the second metal-containing layer 1261b covering the side surface of the wiring portion 1262W was about 10 nm.

[0202] (Comparative Example 1) Fig. 33 is a cross-sectional view schematically showing a multilayer wiring board 12'. Fig. 34 is an enlarged cross-sectional view showing a part of the multilayer wiring board 12' shown in Fig. 33.

[0203] The multilayer wiring board 12' shown in FIGS. 33 and 34 is similar to the multilayer wiring board 12 according to the embodiment, except for the following points.

[0204] That is, the multilayer wiring board 12′ includes a layer 126′ instead of the layer 126. Each layer 126′ includes an insulating resin layer 1263, a first metal-containing layer 1261a′, a second metal-containing layer 1261b′, a conductor layer 1262′, and an inorganic insulating layer 1264′. Because the conventional semi-additive method was used to form the first metal-containing layer 1261a′, the second metal-containing layer 1261b′, and the conductor layer 1262′, the side surfaces of the wiring portion 1262W′ are not covered by the second metal-containing layer 1261b′. Furthermore, the cross section of the wiring portion 1262W has a substantially rectangular shape. Apart from these points, the multilayer wiring board 12′ according to the comparative example is similar to the multilayer wiring board 12 according to the example.

[0205] In FIG. 34, length t1' is the distance between the first surface S1 of one layer 126' and the bottom surface of the groove included in the other layer 126' between two adjacent layers 126'. Length t2' is the depth of the groove in the layer 126'. Length t3' is the shortest distance between the bottom surface of the groove included in the layer 126' and the second surface S2 of this layer 126'. Length t4' is the width of the bottom surface of the groove included in the layer 126'. Length t5' is the distance between the bottom surfaces of adjacent grooves in the width direction of the groove.

[0206] The lengths t1', t2', t3', t4', and t5' of the multilayer wiring board 12' were set to 2 μm, and the thickness of the inorganic insulating layer 1264' was set to 0.05 μm.

[0207] (Comparative Example 2) The multilayer wiring board according to Comparative Example 2 is similar to the multilayer wiring board according to Comparative Example 1, except that the thickness of the inorganic insulating layer 1264' is changed from 0.05 μm to 0.5 μm.

[0208] (Comparative Example 3) The multilayer wiring board according to Comparative Example 3 is similar to the multilayer wiring board according to Comparative Example 1, except that the thickness of the inorganic insulating layer 1264' is changed from 0.05 μm to 1 μm.

[0209] (Confirmation of action and effect) The multilayer wiring board 12 according to the example and the multilayer wiring boards 12' according to the comparative examples 1 to 3 were evaluated as follows.

[0210] (Evaluation method) The inter-wire insulation reliability was evaluated by applying a 3.3V bias between the wires in an environment of 130°C and 85% RH, and the pass criterion was a resistance of 1MΩ or more for 192 hours.

[0211] (Evaluation results) The multilayer wiring board 12 according to the example met the above-mentioned pass criteria. On the other hand, the multilayer wiring boards 12' according to comparative examples 1 and 2 did not meet the above-mentioned pass criteria. Furthermore, the multilayer wiring board 12' according to comparative example 3 could not be evaluated for insulation reliability because peeling occurred between the inorganic insulating layer 1264' and the insulating resin layer 1263, and between the inorganic insulating layer 1264' and the insulating resin layer 124. The invention as originally claimed is set forth below. [1] Two or more layers laminated together, each of the two or more layers comprising: an insulating resin layer having a first surface and a second surface that is the back surface of the first surface, the insulating resin layer having a groove portion that opens in the first surface; an inorganic insulating layer including a portion covering the bottom surface of the groove; a conductor layer including a wiring portion embedded in the groove portion of the insulating resin layer; a first metal-containing layer that covers the surface of the wiring portion on the first surface side without covering the side surface of the wiring portion; a second metal-containing layer including a portion interposed between the first metal-containing layer and the wiring portion and a portion covering a side surface of the wiring portion, the second metal-containing layer being made of a metal material different from that of the first metal-containing layer; A multilayer wiring board including: [2] 2. The multilayer wiring board according to item 1, wherein the inorganic insulating layer further includes a portion covering a connection between the bottom surface of the groove and a side wall of the groove. [3] Item 2. The multilayer wiring board according to item 1, wherein the inorganic insulating layer further includes a portion covering the side wall of the groove. [4] 4. The multilayer wiring board according to any one of items 1 to 3, wherein the inorganic insulating layer further includes a portion covering the first surface. [5] 5. The multilayer wiring board according to any one of items 1 to 4, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, tantalum oxide, tantalum nitride, and aluminum oxide. [6] The insulating resin layer is integrally formed in the thickness direction, the insulating resin layer is further provided with a first recess that opens on the first surface and a second recess that opens on the second surface and communicates with one or more of the first recesses; the inorganic insulating layer further includes a portion covering a bottom surface of the first recess, the conductor layer further includes a land portion that fills the first recess of the insulating resin layer, and a via portion that protrudes from the first surface at a position of the land portion, the via portion fills the second recess of the insulating resin layer adjacent to the first surface side, 6. A multilayer wiring board according to any one of items 1 to 5, wherein the first metal-containing layer further covers the first surface of the land portion and the side surface of the via portion without covering the side surface of the land portion. [7] 7. The multilayer wiring board according to item 6, wherein the inorganic insulating layer further includes a portion covering the sidewall of the first recess. [8] 8. A multilayer wiring board according to any one of items 1 to 7, wherein the width D1 of the portion of the first metal-containing layer covering the surface of the wiring portion on the first surface side is smaller than the width D2 of the region of the surface of the second metal-containing layer facing a plane including the first surface. [9] Item 9. The multilayer wiring board according to any one of items 1 to 8, wherein the first metal-containing layer contains titanium and the second metal-containing layer contains copper.

[10] 10. The multilayer wiring board according to any one of items 1 to 9, wherein the arithmetic mean roughness Ra of the portion of the second metal-containing layer that covers the side surface of the wiring portion is 10 nm or less.

[11] 11. The multilayer wiring board according to any one of items 1 to 10, wherein the groove has a cross section perpendicular to its length direction that is inversely tapered.

[12] A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being the multilayer wiring board according to any one of items 1 to 11.

[13] Item 13. The composite wiring board according to item 12, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[14] Item 12 or 13, and the composite wiring board according to item 12 or 13; a functional device mounted on the surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

[15] forming two or more stacked layers, wherein forming each of the two or more layers comprises: forming a dummy layer having a groove and at least one through hole communicating with the recess on an insulating resin layer having a recess; forming a first metal-containing layer that covers an upper surface of the dummy layer and inner surfaces of the recess, the groove, and the through hole; forming a second metal-containing layer on the first metal-containing layer, the second metal-containing layer being made of a metal material different from that of the first metal-containing layer; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess, the through hole, and the groove are filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; removing the exposed portion of the first metal-containing layer; forming an inorganic insulating layer so as to cover at least the upper surfaces of the land portions and the wiring portions; forming an insulating resin layer that covers the inorganic insulating layer, fills gaps between the land portion and the wiring portion, and has recesses at one or more positions of the land portion; removing a portion of the inorganic insulating layer that is exposed at the position of the recess provided in the insulating resin layer that covers the inorganic insulating layer; A method for manufacturing a multilayer wiring board comprising the steps of:

[16] Item 16. The method for manufacturing a multilayer wiring board according to item 15, wherein the inorganic insulating layer is formed so as to further cover the side surfaces of the land portion and the wiring portion.

[17] Item 17. The method for manufacturing a multilayer wiring board according to item 15 or 16, wherein the inorganic insulating layer is formed so as to further cover the insulating resin layer exposed by removing the dummy layer.

[18] Item 18. The method for manufacturing a multilayer wiring board according to any one of Items 15 to 17, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, tantalum oxide, tantalum nitride, and aluminum oxide.

[19] 19. The method for manufacturing a multilayer wiring board according to any one of items 15 to 18, wherein the dummy layer is made of a photosensitive resin. [Explanation of symbols]

[0212] 1...packaged device, 2...support, 3...peeling layer, 4a...adhesion layer, 4b...seed layer, 10...composite wiring board, 11...FC-BGA board, 12...multilayer wiring board, 12'...multilayer wiring board, 13...encapsulating resin layer, 14...bonding electrode, 20...functional device, 30...encapsulating resin layer, 40...bonding electrode, 50...laser light, 111...core layer, 112...insulating layer, 113...conductor layer, 114...insulating layer, 115...bonding conductor, 121...resist layer, 122...conductor layer, 123...insulating resin layer, 124...insulating resin layer, 125...dummy layer, 126...layer, 126'...layer, 1261a...first metal-containing layer, 1261a' ...first metal-containing layer, 1261b...second metal-containing layer, 1261b'...second metal-containing layer, 1262...conductor layer, 1262'...conductor layer, 1262L...land portion, 1262L'...land portion, 1262V...via portion, 1262V'...via portion, 1262W...wiring portion, 1262W'...wiring portion, 1263...insulating resin layer, 1264...inorganic insulating layer, 127a...adhesion layer, 127b...seed layer, 128...resist layer, 129...conductor layer, 130...insulating resin layer, 131...surface treatment layer, 132...joining conductor, G...groove portion, G'...groove portion, R1...first recess, R1'...through hole, R2...second recess, S1...first surface, S2...second surface.

Claims

1. Two or more layers laminated together, each of the two or more layers comprising: an insulating resin layer having a first surface and a second surface that is the back surface of the first surface, the insulating resin layer having a groove portion that opens on the first surface; an inorganic insulating layer including a portion covering the bottom surface of the groove; a conductor layer including a wiring portion embedded in the groove portion of the insulating resin layer; a first metal-containing layer that covers the surface of the wiring portion on the first surface side without covering the side surface of the wiring portion; a second metal-containing layer including a portion interposed between the first metal-containing layer and the wiring portion and a portion covering a side surface of the wiring portion, the second metal-containing layer being made of a metal material different from the material of the first metal-containing layer; Including, A multilayer wiring board in which the width D1 of the portion of the first metal-containing layer that covers the surface of the wiring portion on the first surface side is smaller than the width D2 of the area of the surface of the second metal-containing layer that faces a plane including the first surface.

2. 2. The multilayer wiring board according to claim 1, wherein the inorganic insulating layer further includes a portion that covers a connection between the bottom surface of the groove and a side wall of the groove.

3. 2. The multilayer wiring board according to claim 1, wherein the inorganic insulating layer further includes a portion covering a side wall of the groove.

4. The multilayer wiring board according to claim 1 , wherein the inorganic insulating layer further includes a portion covering the first surface.

5. 5. The multilayer wiring board according to claim 1, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, tantalum oxide, tantalum nitride, and aluminum oxide.

6. The insulating resin layer is integrally formed in the thickness direction, the insulating resin layer is further provided with a first recess that opens on the first surface and a second recess that opens on the second surface and communicates with one or more of the first recesses, the inorganic insulating layer further includes a portion covering a bottom surface of the first recess, the conductor layer further includes a land portion that fills the first recess of the insulating resin layer, and a via portion that protrudes from the first surface at a position of the land portion, the via portion fills the second recess of the insulating resin layer adjacent to the first surface side, A multilayer wiring board as described in any one of claims 1 to 5, wherein the first metal-containing layer further covers the surface of the land portion on the first surface side and the side of the via portion without covering the side of the land portion.

7. The multilayer wiring board according to claim 6 , wherein the inorganic insulating layer further includes a portion covering a side wall of the first recess.

8. 8. The multilayer wiring board according to claim 1, wherein the first metal-containing layer contains titanium, and the second metal-containing layer contains copper.

9. 9. The multilayer wiring board according to claim 1, wherein the portion of the second metal-containing layer that covers the side surface of the wiring portion has an arithmetic mean roughness Ra of 10 nm or less.

10. 10. The multilayer wiring board according to claim 1, wherein the groove has a cross section perpendicular to its length direction that is inversely tapered.

11. A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being a multilayer wiring board according to any one of claims 1 to 10.

12. 12. The composite wiring board according to claim 11, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

13. The composite wiring board according to claim 11 or 12, a functional device mounted on the surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

14. forming two or more stacked layers, wherein forming each of the two or more layers comprises: forming a dummy layer having a groove and at least one through hole communicating with the recess on an insulating resin layer having a recess; forming a first metal-containing layer that covers an upper surface of the dummy layer and inner surfaces of the recess, the groove, and the through hole; forming a second metal-containing layer on the first metal-containing layer, the second metal-containing layer being made of a metal material different from that of the first metal-containing layer; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess, the through hole, and the groove are filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; removing the exposed portion of the first metal-containing layer; forming an inorganic insulating layer so as to cover at least the upper surfaces of the land portions and the wiring portions; forming an insulating resin layer that covers the inorganic insulating layer, fills gaps between the land portion and the wiring portion, and has recesses at one or more positions of the land portion; removing a portion of the inorganic insulating layer that is exposed at the position of the recess provided in the insulating resin layer that covers the inorganic insulating layer; A method for manufacturing a multilayer wiring board comprising the steps of:

15. The method for manufacturing a multilayer wiring board according to claim 14, wherein the inorganic insulating layer is formed so as to further cover the side surfaces of the land portion and the wiring portion.

16. 16. The method for manufacturing a multilayer wiring board according to claim 14, wherein the inorganic insulating layer is formed so as to further cover the insulating resin layer exposed by removing the dummy layer.

17. 17. The method for manufacturing a multilayer wiring board according to claim 14, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, tantalum oxide, tantalum nitride, and aluminum oxide.

18. 18. The method for manufacturing a multilayer wiring board according to claim 14, wherein the dummy layer is made of a photosensitive resin.

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