Semiconductor Devices

Abstract

To provide a semiconductor device that can reduce the parasitic inductance of wiring in a semiconductor device that mounts a power semiconductor element.SOLUTION: A semiconductor device includes an insulating circuit board 1 having conductive plates 12a and 12b on the upper surface side, semiconductor chips 2a and 2b mounted on the conductive plates 12a and 12b, a printed circuit board 4 provided above the semiconductor chips 2a and 2b and electrically connected to the semiconductor chips 2a and 2b, first external connection terminals 6a and 6b electrically connected to the conductive plates 12a and 12b and extending upward from the conductive plates 12a and 12b, a first conductive block 7 provided to surround the outer periphery of the first external connection terminals 6a and 6b and to be insulated from the first external connection terminals 6a and 6b, and a sealing member 8 that seals the semiconductor chips 2a and 2b, the printed circuit board 4, and the first conductive block 7.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device (semiconductor module) incorporating a power semiconductor element. [Background technology]

[0002] Power semiconductor elements are used, for example, as switching elements for power conversion. A known conventional semiconductor device incorporating a power semiconductor element has a structure in which a power semiconductor chip (hereinafter simply referred to as a "semiconductor chip") constituting the power semiconductor element is disposed on an insulating circuit board, and a printed circuit board is disposed above the semiconductor chip.

[0003] FIG. 1C of Patent Document 1 discloses a semiconductor power module in which an annular magnetic member is arranged so as to surround terminals connected to power semiconductor elements in a module package. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-11734 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional semiconductor devices incorporating power semiconductor elements have a problem in that surge voltages occur due to parasitic inductance during switching operations of the power semiconductor elements.

[0006] In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device in which the parasitic inductance of wiring within the semiconductor device on which a power semiconductor element is mounted is reduced. [Means for solving the problem]

[0007] One aspect of the present invention includes: (a) an insulating circuit board having a conductive plate on an upper surface thereof; (b) a semiconductor chip mounted on the conductive plate; (c) a printed circuit board provided above the semiconductor chip and electrically connected to the semiconductor chip; (d) a first external connection terminal electrically connected to the conductive plate and extending above the conductive plate; (e) a first conductive block surrounding the outer periphery of the first external connection terminal and provided insulated from the first external connection terminal; and (f) an encapsulating member for encapsulating the semiconductor chip, the printed circuit board, and the first conductive block. Materials The gist of the present invention is that the semiconductor device comprises: [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor device in which the parasitic inductance of wiring within the semiconductor device on which a power semiconductor element is mounted is reduced. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a side view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a plan view of a portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along the AA direction in FIG. 2. [Figure 4] 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 5] FIG. 10 is a side view of a semiconductor device according to a comparative example. [Figure 6] 10 is a graph showing the relationship between the analytical frequency and the inductance between P and P terminals when the thickness of the conductive member of the semiconductor device according to the first embodiment is changed. [Figure 7] 10 is a graph showing the relationship between the analysis frequency and the inductance between P and P terminals when the width of the conductive member of the semiconductor device according to the first embodiment is changed. [Figure 8] 10 is a graph showing the relationship between the analytical frequency and the inductance between P and P terminals when the gap between the conductive members of the semiconductor device according to the first embodiment is changed. [Figure 9]10 is a graph showing the relationship between the analytical frequency and the inductance between P and N terminals when the material of the conductive member of the semiconductor device according to the first embodiment is changed. [Figure 10] FIG. 10 is a side view of the semiconductor device according to the second embodiment. [Figure 11] FIG. 10 is a side view of the semiconductor device according to the third embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a portion of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a portion of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 10 is a plan view of a portion of a semiconductor device according to a sixth embodiment. [Figure 15] FIG. 13 is a cross-sectional view of a portion of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, first to seventh embodiments will be described with reference to the drawings. In the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to seventh embodiments shown below are intended to exemplify devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0011] In the following description, the "first main electrode" of a semiconductor chip refers to either the source electrode or the drain electrode for a field-effect transistor (FET) or a static induction transistor (SIT). It refers to either the emitter electrode or the collector electrode for an insulated gate bipolar transistor (IGBT). It refers to either the anode electrode or the cathode electrode for a static induction thyristor (SI thyristor), a gate turn-off thyristor (GTO), or a diode. Furthermore, the "second main electrode" of a semiconductor element refers to either the source electrode or the drain electrode, which is not the first main electrode, for a FET or SIT. It refers to either the emitter electrode or the collector electrode, which is not the first main electrode, for an IGBT. It refers to either the anode electrode or the cathode electrode, which is not the first main electrode, for a SI thyristor, a GTO, or a diode. That is, if the "first main electrode" is the source electrode, the "second main electrode" refers to the drain electrode. If the "first main electrode" is the emitter electrode, the "second main electrode" refers to the collector electrode. If the "first main electrode" is an anode electrode, the "second main electrode" means a cathode electrode.

[0012] In addition, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following explanation are merely definitions for the convenience of explanation and do not limit the technical idea of the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if it is rotated 180 degrees and observed, "up and down" is read in reverse.

[0013] (First embodiment) The semiconductor device according to the first embodiment is a semiconductor module known as a "2-in-1" that has the functions of two power semiconductor elements. As shown in FIG. 1, the semiconductor device according to the first embodiment includes an insulating circuit board 1 and semiconductor chips 2a and 2b mounted on the insulating circuit board 1. A printed circuit board 4 is disposed above the semiconductor chips 2a and 2b at a distance from the semiconductor chips 2a and 2b. The peripheries of the semiconductor chips 2a and 2b and the printed circuit board 4 are sealed with a sealing member 8, and the semiconductor chips 2a and 2b and the printed circuit board 4 are electrically insulated from the surroundings.

[0014] The insulating circuit board 1 includes an insulating substrate 11, upper conductor layers (conductive plates) 12a and 12b arranged on the upper surface (circuit surface side) of the insulating substrate 11, and a lower conductor layer (heat sink) 13 arranged on the lower surface (cooling surface side) of the insulating substrate 11. Although not shown in Fig. 1, a predetermined circuit pattern is formed on the upper conductor layers 12a and 12b.

[0015] The insulating circuit board 1 may be, for example, a direct copper bonded (DCB) board or an active metal brazing (AMB) board. The insulating substrate 11 is composed of a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or the like, or a resin insulating substrate using a polymer material, etc. The upper conductor layers 12a and 12b and the lower conductor layer 13 are composed of conductor foil made of, for example, copper (Cu), aluminum (Al), or the like.

[0016] The semiconductor chips 2a and 2b are bonded to the upper conductor layers 12a and 12b via a bonding material (not shown), such as solder or a sintered material, or by direct bonding. The semiconductor chips 2a and 2b may be made of, for example, silicon (Si) or wide-bandgap semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (GaO). The semiconductor chips 2a and 2b vary in type depending on the application. Examples of suitable semiconductor chips include power semiconductor elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs), field-effect transistors (FETs), insulated-gate bipolar transistors (IGBTs), static induction (SI) thyristors, and gate turn-off (GTO) thyristors, as well as rectifier elements such as free wheel diodes (FWDs). Here, we will describe the case where the semiconductor chips 2a and 2b are SiC MOSFETs.

[0017] Each of the semiconductor chips 2a and 2b has a first main electrode (drain electrode) on its underside and a control electrode (gate electrode) and a second main electrode (source electrode) on its upper side. The drain electrode on the underside of the semiconductor chip 2a is joined to the upper conductor layer 12a of the insulating circuit board 1 via a bonding material such as solder or a sintered material. The drain electrode on the underside of the semiconductor chip 2b is joined to the upper conductor layer 12b of the insulating circuit board 1 via a bonding material such as solder or a sintered material.

[0018] 1 shows two semiconductor chips 2a and 2b as an example, the number of semiconductor chips is not particularly limited and can be selected appropriately depending on the rated current, etc. For example, one semiconductor chip may be included, or three or more semiconductor chips may be included.

[0019] The semiconductor chips 2a and 2b are connected to a printed circuit board 4 via a plurality of post electrodes (bumps) 3a and 3b. The source electrode of the semiconductor chip 2a is joined to the lower ends of some of the plurality of post electrodes 3a via a bonding material (not shown) such as solder or a sintered material. The gate electrode of the semiconductor chip 2a is joined to the lower ends of other parts of the plurality of post electrodes 3a via a bonding material (not shown) such as solder or a sintered material. The source electrode of the semiconductor chip 2b is joined to the lower ends of some of the plurality of post electrodes 3b via a bonding material (not shown) such as solder or a sintered material. The gate electrode of the semiconductor chip 2b is joined to the lower ends of other parts of the plurality of post electrodes 3b via a bonding material (not shown) such as solder or a sintered material.

[0020] The post electrodes 3a, 3b are, for example, rod-shaped (pin-shaped) or column-shaped, and may specifically be polygonal prisms such as circular cylinders, elliptical cylinders, triangular prisms, or square prisms. Metal materials such as copper (Cu) can be used as the material for the post electrodes 3a, 3b. The post electrodes 3a, 3b may be bonded to a lower wiring layer 43 on the lower surface of the printed circuit board 4, or may extend through to an upper wiring layer 42 on the upper surface of the printed circuit board 4.

[0021] The printed circuit board 4 includes an insulating layer 41, an upper wiring layer 42 disposed on the upper surface of the insulating layer 41, and a lower wiring layer 43 disposed on the lower surface of the insulating layer 41. For example, the insulating layer 41 is made of a resin substrate made of polyimide resin or a combination of glass fiber and polyimide resin.

[0022] The upper wiring layer 42 and the lower wiring layer 43 are made of a conductor foil made of, for example, copper (Cu) or aluminum (Al). Although not shown in FIG. 1, a predetermined circuit pattern is formed on the upper wiring layer 42 and the lower wiring layer 43. For example, the same circuit pattern may be formed on the upper wiring layer 42 and the lower wiring layer 43. The upper wiring layer 42 and the lower wiring layer 43 may be electrically connected via a through hole that penetrates the insulating layer 41.

[0023] The lower end of a high-potential external connection terminal (drain-side connection terminal) 6a is connected to the upper conductor layer 12a of the insulating circuit board 1 via a bonding material (not shown) such as solder or a sintered material. The drain-side connection terminal 6a extends upward toward the insulating circuit board 1. The upper end of the drain-side connection terminal 6a protrudes from the upper surface of the sealing member 8 and is connected to an external circuit. The drain-side connection terminal 6a is made of a metal material such as copper (Cu). The drain-side connection terminal 6a supplies current to the drain electrode of the semiconductor chip 2a via the upper conductor layer 12a of the insulating circuit board 1.

[0024] A low-potential side external connection terminal (source side connection terminal) 6b and an output side external connection terminal (output terminal) 6c are connected to the upper wiring layer 42 of the printed circuit board 4. The source side connection terminal 6b extends upwards on the printed circuit board 4. The upper end of the source side connection terminal 6b protrudes from the upper surface of the sealing member 8 and is connected to an external circuit. The source side connection terminal 6b is made of a metal material such as copper (Cu). The source side connection terminal 6b passes a current from the source electrode of the semiconductor chip 2b to the external circuit via the post electrode 3b and the printed circuit board 4.

[0025] The lower end of output terminal 6c is connected to upper conductor layer 12b of insulating circuit board 1. Output terminal 6c extends upward from insulating circuit board 1. The upper end of output terminal 6c protrudes from the upper surface of sealing member 8 and is connected to an external circuit. Output terminal 6c is made of a metal material such as copper (Cu). When semiconductor chip 2a is in the ON state, output terminal 6c passes current from the source electrode of semiconductor chip 2a to the external circuit via post electrode 3a and printed circuit board 4. When semiconductor chip 2b is in the ON state, output terminal 6c supplies current from the external circuit to the drain electrode of semiconductor chip 2b via upper conductor layer 12b of insulating circuit board 1.

[0026] Although not shown, multiple gate control terminals (external connection terminals) and multiple auxiliary source terminals (external connection terminals) are connected to the printed circuit board 4. Each gate control terminal applies a control signal that controls the on / off of the semiconductor chips 2a, 2b to the gate electrodes of the semiconductor chips 2a, 2b via the printed circuit board 4 and post electrodes 3a, 3b. Each auxiliary source terminal detects the current on the source side of the semiconductor chips 2a, 2b via the post electrodes 3a, 3b and the printed circuit board 4.

[0027] A conductive block (conductive member) 7 is provided so as to surround the outer periphery of the drain-side connection terminal 6a and the source-side connection terminal 6b. The conductive block 7 is provided above the printed circuit board 4 and spaced apart from the printed circuit board 4. The conductive block 7 has, for example, a rectangular parallelepiped shape extending along the longitudinal direction of the insulating circuit board 1. The conductive block 7 is made of a conductive material made of a metal such as copper (Cu), a Cu alloy containing Cu as the main component, aluminum (Al), or an Al alloy containing Al as the main component.

[0028] Fig. 2 shows a plan view of the conductive block 7, drain-side connection terminal 6a, source-side connection terminal 6b, and output terminal 6c shown in Fig. 1. Fig. 3 shows a cross-sectional view passing through the conductive block 7 as seen from the direction AA shown in Fig. 2. In Fig. 2, the outlines of the planar patterns of the insulating circuit board 1, semiconductor chips 2a and 2b, and printed circuit board 4 are schematically shown by dashed lines.

[0029] As shown in Fig. 2, the outline of the planar pattern of the printed circuit board 4 is L-shaped, but is not limited to this. Furthermore, the planar pattern of the conductive block 7 is rectangular, but is not limited to this. The drain-side connection terminal 6a and the source-side connection terminal 6b are arranged side by side in the longitudinal direction of the rectangular planar pattern of the insulating circuit board 1. The conductive block 7 is arranged so as to be spaced apart from the output terminal 6c.

[0030] 2 and 3, the conductive block 7 has a plurality of through holes 7x and 7y, through which the drain side connection terminal 6a and the source side connection terminal 6b pass, respectively. The thickness t1 of the conductive block 7 is, for example, but not limited to, 1 mm or more and 5 mm or less. The width w1 in the short-side direction of the rectangular planar pattern of the conductive block 7 is, for example, but not limited to, 1 mm or more and 5 mm or less. The distance (gap) d1 between the through holes 7x and 7y of the conductive block 7 and the drain side connection terminal 6a and the source side connection terminal 6b is, for example, but not limited to, 0.1 mm or more and 1 mm or less.

[0031] Insulating members (intervening components) 9a and 9b are provided between the through holes 7x and 7y of the conductive block 7 and the drain side connection terminal 6a and source side connection terminal 6b. Resin or other insulating materials can be used for the insulating members 9a and 9b. The insulating members 9a and 9b function to maintain a constant distance between the drain side connection terminal 6a and source side connection terminal 6b and the conductive block 7 so that the drain side connection terminal 6a and source side connection terminal 6b do not come into direct contact with the conductive block 7. The distance (gap) d1 between the drain side connection terminal 6a and source side connection terminal 6b and the conductive block 7 can be adjusted by adjusting the thickness of the insulating members 9a and 9b.

[0032] Although the insulating members 9a and 9b are provided between the through-holes 7x and 7y of the conductive block 7 and the drain-side connection terminal 6a and the source-side connection terminal 6b in the above example, the present invention is not limited to this. For example, instead of the insulating members 9a and 9b, parts of the sealing member 8 may be inserted between the through-holes 7x and 7y of the conductive block 7 and the drain-side connection terminal 6a and the source-side connection terminal 6b.

[0033] 1 constitutes the housing of the semiconductor device according to the first embodiment and has a substantially rectangular parallelepiped shape. The insulating circuit board 1 is exposed from the bottom surface of the sealing member 8. For the sealing member 8, for example, a resin material such as a highly heat-resistant and hard thermosetting resin can be used, and specifically, epoxy resin, maleimide resin, cyanate resin, etc. can be used.

[0034] An example of an equivalent circuit of the semiconductor device according to the first embodiment is shown in FIG. 4. As shown in FIG. 4, the semiconductor device according to the first embodiment constitutes a part of a three-phase bridge circuit. A second main electrode (drain electrode) of the transistor T1 on the upper arm side is connected to the drain side connection terminal P, and a first main electrode (source electrode) of the transistor T2 on the lower arm side is connected to the source side connection terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1, respectively. The auxiliary source terminal S2 is connected to the source electrode of the transistor T2. Gate control terminals G1 and G2 are connected to the gate electrodes of the transistors T1 and T2. Body diodes D1 and D2, which serve as freewheeling diodes (FWD), are built into the transistors T1 and T2 and are connected in anti-parallel.

[0035] The drain side connection terminal P, the source side connection terminal N, and the output terminal U shown in Fig. 4 correspond to the drain side connection terminal 6a, the source side connection terminal 6b, and the output terminal 6c shown in Fig. 1. The transistors T1 and T2 shown in Fig. 4 correspond to the semiconductor chips 2a and 2b, respectively, shown in Fig. 1. The gate control terminals G1 and G2 and the auxiliary source terminals S1 and S2 shown in Fig. 4 are not shown in Fig. 1.

[0036] Next, we will explain the operation of the semiconductor device according to the first embodiment. A control signal for controlling the on / off of the semiconductor chips 2a and 2b is applied to the gate electrodes of the semiconductor chips 2a and 2b via a gate control terminal (not shown) and the printed circuit board 4 and post electrodes 3a and 3b, causing the semiconductor chips 2a and 2b to alternately perform switching operations.

[0037] Arrows I1 to I6 in Fig. 1 schematically show current paths in the semiconductor device according to the first embodiment. Current (arrow I1) entering from drain-side connection terminal 6a passes through upper conductor layer 12a of insulating circuit board 1, flows from upper arm semiconductor chip 2a to post electrode 3a (arrow I2), passes through printed circuit board 4, and flows from output terminal 6c to an external circuit (arrow I3). Current (arrow I4) entering from the external circuit to output terminal 6c passes through upper conductor layer 12b of insulating circuit board 1, flows from lower arm semiconductor chip 2b to post electrode 3b (arrow I5), passes through printed circuit board 4, and flows from source-side connection terminal 6b to the external circuit (arrow I6).

[0038] Here, a semiconductor device according to a comparative example will be described. As shown in Fig. 5, the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that it does not have the conductive block 7. When the semiconductor device according to the comparative example is switched on by a power conversion device, an induced electromotive force ΔV expressed by the following equation (1) is generated in the semiconductor chips 2a and 2b. ΔV=Ls×di / dt …(1)

[0039] In equation (1), Ls is the parasitic inductance of the conversion circuit section in the power conversion device. Parasitic inductance exists inside the input capacitor, inside the semiconductor device of the comparative example, and in the connecting wiring between the input capacitor and the semiconductor device of the comparative example. In equation (1), di / dt is the rate of change of current during switching. In addition to the DC voltage of the circuit, the induced electromotive force ΔV in equation (1) is applied to the semiconductor chips 2a and 2b as an extra surge voltage. Therefore, when determining the rated voltage, it is necessary to set it so that the surge voltage is not exceeded.

[0040] On the other hand, in the current paths I1 to I6 of the semiconductor device according to the comparative example, the drain side connection terminal 6a, the source side connection terminal 6b, and the output terminal 6c are long, so the parasitic inductance of the drain side connection terminal 6a, the source side connection terminal 6b, and the output terminal 6c themselves accounts for a large proportion of the parasitic inductance of the entire current paths I1 to I6, which limits the suppression of induced voltage during switching operations.

[0041] 1 to 3 includes a conductive block 7. During switching operation of the semiconductor device according to the first embodiment, magnetic fields Ma and Mb are generated around the currents flowing through the drain-side connecting terminal 6a and the source-side connecting terminal 6b according to Ampere's law, as shown by the arrows in FIG. 。

[0042] As shown in Figure 2, when viewed from the top of the conductive block 7, a current flows through the drain-side connection terminal 6a from the front to the back of the page. A clockwise magnetic field Ma is generated around the drain-side connection terminal 6a. On the other hand, a current flows through the source-side connection terminal 6b from the back to the front of the page, in the opposite direction to that of the drain-side connection terminal 6a. A counterclockwise magnetic field Mb is generated around the source-side connection terminal 6b.

[0043] At this time, as shown by the arrows in Fig. 3, eddy currents Ia and Ib are generated in the conductive block 7 in directions that suppress the generated magnetic fields Ma and Mb. These eddy currents Ia and Ib cancel out and reduce the magnetic fields Ma and Mb around the drain side connection terminal 6a and the source side connection terminal 6b. As a result, the parasitic inductance of the drain side connection terminal 6a and the source side connection terminal 6b themselves can be reduced.

[0044] <Method of manufacturing a semiconductor device> Next, an example of a manufacturing method (assembly method) of the semiconductor device according to the first embodiment will be described. The insulating circuit board 1 shown in Fig. 1 is prepared, and semiconductor chips 2a and 2b are mounted on upper conductor layers 12a and 12b of the insulating circuit board 1 via a bonding material. Next, post electrodes 3a and 3b are mounted on the semiconductor chips 2a and 2b via the bonding material, and a printed circuit board 4 is mounted on the post electrodes 3a and 3b via the bonding material.

[0045] Next, the lower ends of the drain side connection terminal 6a and the output terminal 6c are mounted on the upper conductor layers 12a and 12b of the insulating circuit board 1 via a bonding material, and the lower end of the source side connection terminal 6b is mounted on the upper wiring layer 42 of the printed circuit board 4 via a bonding material. Next, a conductive block 7 having insulating members 9a and 9b provided in through holes 7x and 7y is prepared, and the drain side connection terminal 6a and the source side connection terminal 6b are press-fitted into the through holes 7x and 7y of the conductive block 7 via the insulating members 9a and 9b. Alternatively, after the drain side connection terminal 6a and the source side connection terminal 6b are press-fitted into the through holes 7x and 7y of the conductive block 7 via the insulating members 9a and 9b, the lower end of the drain side connection terminal 6a may be connected to the upper conductor layer 12a of the insulating circuit board 1, and the lower end of the source side connection terminal 6b may be connected to the upper wiring layer 42 of the printed circuit board 4.

[0046] Next, the insulating circuit board 1, semiconductor chips 2a, 2b, post electrodes 3a, 3b, and printed circuit board 4 are bonded together by heat treatment. Next, the semiconductor chips 2a, 2b, post electrodes 3a, 3b, printed circuit board 4, and conductive block 7 are sealed with sealing member 8. This completes the semiconductor device according to the first embodiment shown in FIG.

[0047] <Example> Next, we will explain the results of a simulation of the frequency dependence of the inductance between the PN terminals (between the drain-side connection terminal 6a and the source-side connection terminal 6b) for examples in which each parameter of the conductive block 7 of the semiconductor device according to the first embodiment is changed. Figure 6 shows the results of a simulation of the frequency dependence of the inductance between the PN terminals for examples in which the thickness t1 of the conductive block 7 of the semiconductor device according to the embodiment is 1 mm, 3 mm, and 5 mm, and for a comparative example in which the conductive block 7 is not present. As shown in Figure 6, it can be seen that the thicker the thickness t1 of the conductive block 7, the lower the inductance between the PN terminals.

[0048] 7 shows the results of a simulation of the frequency dependence of the inductance between the P and N terminals for examples in which the width w1 of the conductive block 7 of the semiconductor device according to the first embodiment is set to 3 mm, 4 mm, and 5 mm, and for a comparative example in which there is no conductive block 7. As shown in FIG. 7, it can be seen that the wider the width w1 of the conductive block 7, the more the inductance between the P and N terminals decreases.

[0049] 8 shows the results of a simulation of the frequency dependence of the inductance between the P and N terminals for examples in which the gap d1 between the conductive blocks 7 of the semiconductor device according to the first embodiment is set to 0.5 mm, 0.2 mm, and 0.1 mm, and for a comparative example in which there is no conductive block 7. As shown in FIG. 8, it can be seen that the smaller the gap d1 between the conductive blocks 7, the more the inductance between the P and N terminals decreases.

[0050] 9 shows the results of a simulation of the frequency dependence of the inductance between the P and N terminals for an example in which the material of the conductive block 7 of the semiconductor device according to the first embodiment is aluminum (Al) or copper (Cu), and for a comparative example in which there is no conductive block 7. As shown in FIG. 9, when the material of the conductive block 7 is Al or Cu, the inductance between the P and N terminals is reduced to approximately the same extent.

[0051] <Effects> As described above, the semiconductor device according to the first embodiment includes the conductive block 7, which allows the eddy currents Ia and Ib to suppress the magnetic fields Ma and Mb generated by the currents flowing through the drain-side connection terminal 6a and the source-side connection terminal 6b, without significantly changing the configuration of the semiconductor device according to the comparative example shown in FIG. 5. This reduces the parasitic inductance of the drain-side connection terminal 6a and the source-side connection terminal 6b themselves and the parasitic inductance of the entire conversion circuit path, making it possible to suppress induced voltages during switching operations. Furthermore, the conductive block 7 extends along the longitudinal direction of the insulating circuit board 1, thereby suppressing warping of the insulating circuit board 1.

[0052] (Second embodiment) As shown in FIG. 10, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 1 in that conductive blocks 7a and 7b are provided individually around the outer periphery of the drain side connection terminal 6a and the source side connection terminal 6b, respectively.

[0053] The conductive blocks 7a and 7b are spaced apart from each other. The conductive blocks 7a and 7b have the same thickness t1. The outer shape of the planar patterns of the conductive blocks 7a and 7b may be rectangular or circular, and is not particularly limited. The planar patterns of the conductive blocks 7a and 7b do not have to be closed rings, and a cutout may be provided in part of the ring. It is also possible to have only one of the conductive blocks 7a and 7b, and not the other.

[0054] The other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted. The semiconductor device according to the second embodiment can be realized by the same procedures as the manufacturing method of the semiconductor device according to the first embodiment, except that the conductive blocks 7a and 7b are provided separately.

[0055] The semiconductor device according to the second embodiment can reduce the parasitic inductance of the drain-side connection terminal 6 a and the source-side connection terminal 6 b, similar to the configuration of the semiconductor device according to the first embodiment. Furthermore, by providing the conductive blocks 7 a and 7 b separately, the space between the conductive blocks 7 a and 7 b can be effectively utilized.

[0056] (Third embodiment) As shown in FIG. 11, the semiconductor device according to the third embodiment has conductive blocks 7a and 7b provided individually around the drain side connection terminal 6a and the source side connection terminal 6b, respectively, and further differs from the configuration of the semiconductor device according to the first embodiment shown in FIG. 1 in that the thicknesses t1 and t2 of the conductive blocks 7a and 7b are different from each other.

[0057] 11, the thickness t1 of the conductive block 7a surrounding the outer periphery of the drain-side connection terminal 6a is thicker than the thickness t2 of the conductive block 7b surrounding the outer periphery of the source-side connection terminal 6b. However, the thickness t1 of the conductive block 7a may be thinner than the thickness t2 of the conductive block 7b. Other configurations of the semiconductor device according to the third embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted. The semiconductor device according to the third embodiment can be realized by the same procedures as those of the semiconductor device according to the first embodiment, except that the conductive blocks 7a and 7b having different thicknesses t1 and t2 are individually provided.

[0058] According to the semiconductor device of the third embodiment, the parasitic inductance of the drain side connection terminal 6 a and the source side connection terminal 6 b can be reduced, similar to the configuration of the semiconductor device of the first embodiment. Furthermore, by providing conductive blocks 7 a and 7 b individually around the outer peripheries of the drain side connection terminal 6 a and the source side connection terminal 6 b and making the thicknesses t1 and t2 of the conductive blocks 7 a and 7 b different from each other, it is possible to effectively utilize the space around the conductive blocks 7 a and 7 b and individually adjust the amount of reduction in parasitic inductance of each of the drain side connection terminal 6 a and the source side connection terminal 6 b.

[0059] (Fourth embodiment) As shown in FIG. 12, the semiconductor device according to the fourth embodiment differs from the configuration of the semiconductor device according to the first embodiment shown in FIG. 3 in that step portions 61, 62 are provided at positions below the conductive blocks 7 on the outer periphery of the drain side connection terminal 6a and the source side connection terminal 6b.

[0060] 12 illustrates an example in which the step portions 61, 62 contact the lower surface of the conductive block 7, but the step portions 61, 62 may be spaced apart from the conductive block 7. To prevent the step portions 61, 62 from contacting the conductive block 7, the step portions 61, 62 are set to be smaller than the distance (gap) d1 between the drain side connection terminal 6a and the source side connection terminal 6b and the conductive block 7.

[0061] Other configurations of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted. The semiconductor device according to the fourth embodiment can be realized by the same procedures as the manufacturing method of the semiconductor device according to the first embodiment, except that the drain-side connection terminal 6 a and the source-side connection terminal 6 b are provided with step portions 61, 62.

[0062] According to the semiconductor device in accordance with the fourth embodiment, the parasitic inductance of the drain-side connection terminal 6 a and the source-side connection terminal 6 b can be reduced, as in the configuration of the semiconductor device in accordance with the first embodiment. Furthermore, since the stepped portions 61, 62 are provided at positions below the conductive block 7 on the outer peripheries of the drain-side connection terminal 6 a and the source-side connection terminal 6 b, when the conductive block 7 is press-fitted into the drain-side connection terminal 6 a and the source-side connection terminal 6 b during assembly of the semiconductor device in accordance with the fourth embodiment, the stepped portions 61, 62 act as stoppers, preventing contact between the conductive block 7 and the printed circuit board 4.

[0063] (Fifth embodiment) 13, the semiconductor device according to the fifth embodiment differs from the configuration of the semiconductor device according to the first embodiment shown in FIG. 3 in that an insulating layer 71 is provided on the lower surface of the conductive block 7. The insulating layer 71 is provided so as to cover the entire lower surface of the conductive block 7. The insulating layer 71 is made of an insulating material such as resin.

[0064] Other configurations of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted. The semiconductor device according to the fifth embodiment can be realized by the same procedures as the manufacturing method of the semiconductor device according to the first embodiment, except for preparing a conductive block 7 having an insulating layer 71 provided on its underside.

[0065] According to the semiconductor device in accordance with the fifth embodiment, the parasitic inductance of the drain-side connection terminal 6 a and the source-side connection terminal 6 b can be reduced, as in the configuration of the semiconductor device in accordance with the first embodiment. Furthermore, since the insulating layer 71 is provided on the lower surface of the conductive block 7, contact between the conductive block 7 and the printed circuit board 4 can be prevented during assembly of the semiconductor device in accordance with the fifth embodiment.

[0066] (Sixth embodiment) As shown in FIG. 14, the semiconductor device according to the sixth embodiment differs from the configuration of the semiconductor device according to the first embodiment shown in FIG. 2 in that the conductive block 7 is arranged to surround not only the drain side connection terminal 6a and the source side connection terminal 6b but also the outer periphery of the output terminal 6c.

[0067] The conductive block 7 has three through holes 7x, 7y, and 7z. The through hole 7z of the conductive block 7 is provided so that the output terminal 6c passes through it. An insulating member 9c is provided between the through hole 7z of the conductive block 7 and the output terminal 6c. The other configurations of the semiconductor device according to the sixth embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted. The semiconductor device according to the sixth embodiment can be realized by the same procedures as those of the manufacturing method of the semiconductor device according to the first embodiment, except that the drain side connection terminal 6a, the source side connection terminal 6b, and the output terminal 6c are press-fitted into the through holes 7x, 7y, and 7z of the conductive block 7.

[0068] The semiconductor device according to the sixth embodiment can reduce the parasitic inductance of the drain-side connection terminal 6 a and the source-side connection terminal 6 b, similarly to the configuration of the semiconductor device according to the first embodiment. Furthermore, since the conductive block 7 surrounds the outer periphery of the output terminal 6 c in addition to the drain-side connection terminal 6 a and the source-side connection terminal 6 b, the parasitic inductance of the output terminal 6 c itself can also be reduced.

[0069] (Seventh embodiment) 15, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 3 in that the insulating members 9a and 9b extend downward below the lower surface of the conductive block 7. Other configurations of the semiconductor device according to the seventh embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted. The semiconductor device according to the seventh embodiment can be realized by the same procedures as the method for manufacturing the semiconductor device according to the first embodiment.

[0070] According to the semiconductor device of the seventh embodiment, the parasitic inductance of the drain side connection terminal 6 a and the source side connection terminal 6 b can be reduced, similar to the configuration of the semiconductor device of the first embodiment. Note that, although Fig. 15 illustrates the case where the insulating members 9 a, 9 b extend downward from the lower surface of the conductive block 7, the insulating members 9 a, 9 b may extend upward from the upper surface of the conductive block 7 to an extent that does not prevent the upper ends of the drain side connection terminal 6 a and the source side connection terminal 6 b from being connected to an external circuit.

[0071] (Other embodiments) As described above, the present invention has been described with reference to the first to seventh embodiments, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will become apparent to those skilled in the art from this disclosure.

[0072] For example, as the semiconductor device according to the first to seventh embodiments, a "2-in-1" configuration having the functions of two power semiconductor elements has been exemplified, but it is also applicable to a "1-in-1" configuration having the functions of one power semiconductor element.

[0073] Furthermore, the configurations disclosed in the first to seventh embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0074] 1...Insulated circuit board 2a, 2b...Semiconductor chip 3a, 3b...Post electrodes (bumps) 4...Printed circuit board 6a...Drain side connection terminal (external connection terminal) 6b...Source side connection terminal (external connection terminal) 6c...Output terminal (external connection terminal) 7, 7a, 7b...Conductive block (conductive member) 7x,7y,7z…Through hole 8...Sealing member 9a, 9b…Insulating members (intervening parts) 11...Insulating substrate 12a, 12b...Upper conductor layer (conductive plate) 13...Lower conductor layer (heat sink) 41...insulating layer 42...Upper wiring layer 43...Lower wiring layer 61,62...Stepped section 71...insulating layer D1, D2...Freewheeling diodes G1, G2...Gate control terminals I1~I6...Current path Ia,Ib…eddy current Ma,Mb…Magnetic field N: Source side connection terminal P: Drain side connection terminal S1, S2: Auxiliary source terminals T1, T2...Transistors U: Output terminal

Claims

1. an insulating circuit board having a conductive plate on its upper surface; a semiconductor chip mounted on the conductive plate; a printed circuit board provided above the semiconductor chip and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending above the conductive plate; a first conductive block that surrounds the outer periphery of the first external connection terminal and is insulated from the first external connection terminal; a sealing member that seals the semiconductor chip, the printed circuit board, and the first conductive block; Equipped with The semiconductor device is characterized in that the lower end of the first external connection terminal is joined to the printed circuit board.

2. 2. The semiconductor device according to claim 1, wherein the first conductive block includes copper or aluminum.

3. 3. The semiconductor device according to claim 1, further comprising an insulating member provided between the first external connection terminal and the first conductive block.

4. 3. The semiconductor device according to claim 1, wherein a part of the sealing member is provided between the first external connection terminal and the first conductive block.

5. a second external connection terminal electrically connected to the conductive plate and extending above the conductive plate; The first conductive block surrounds the outer periphery of the second external connection terminal and is insulated from the second external connection terminal.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

6. An insulating circuit board having a conductive plate on its upper surface; a semiconductor chip mounted on the conductive plate; a printed circuit board provided above the semiconductor chip and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending above the conductive plate; a first conductive block that surrounds the outer periphery of the first external connection terminal and is insulated from the first external connection terminal; a sealing member that seals the semiconductor chip, the printed circuit board, and the first conductive block; a second external connection terminal electrically connected to the conductive plate and extending above the conductive plate; a second conductive block spaced apart from the first conductive block, surrounding the outer periphery of the second external connection terminal, and insulated from the second external connection terminal; A semiconductor device comprising:

7. 7. The semiconductor device according to claim 6, wherein the first conductive block and the second conductive block have the same thickness.

8. 7. The semiconductor device according to claim 6, wherein the first conductive block and the second conductive block have different thicknesses.

9. 9. The semiconductor device according to claim 1, wherein a step portion is provided on the periphery of the first external connection terminal at a position lower than the lower surface of the first conductive block.

10. 4. The semiconductor device according to claim 1, further comprising an insulating layer provided on a lower surface of the first conductive block.

10. The semiconductor device according to any one of items 1 to 9.

11. 9. The semiconductor device according to claim 5, wherein currents flow through the first external connection terminal and the second external connection terminal in mutually opposite directions.

12. a third external connection terminal electrically connected to the conductive plate and extending above the conductive plate; The first conductive block surrounds the outer periphery of the third external connection terminal and is insulated from the third external connection terminal.

6. The semiconductor device according to claim 5, wherein the semiconductor device is a semiconductor device having a first insulating layer.

13. 6. The semiconductor device according to claim 1, wherein the first conductive block is provided so as to extend in the longitudinal direction of the insulating circuit board.

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