Semiconductor Devices

Abstract

To realize a semiconductor device capable of both securing heat dissipation in a plane direction of a metal layer on which semiconductor elements are mounted and suppressing increases in inductance and decreases in output density.SOLUTION: A semiconductor element 2 is bonded to a high thermal conductivity layer 32 of a metal insulating substrate 3, which consists of an insulating substrate 31, a high thermal conductivity layer 32, and an electrical conductivity layer 33. In the metal insulating substrate 3, the high thermal conductivity layer 32 is bonded to one side 31a of the insulating substrate 31, and the conductivity layer 33 is bonded to the other surface on an opposite side 31b. The high thermal conductivity layer 32 has thermal conductivity greater than 398 W / m-K in the plane direction orthogonal to a thickness direction. As a result, the high thermal conductivity layer 32 can ensure heat dissipation of the semiconductor element 2 in the plane direction even when a thickness of the portion to which the semiconductor element 2 is bonded is less than a specified value, and as a result, increase in inductance and decrease in power density are suppressed respectively.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device in which a semiconductor element is mounted on a metal insulating substrate having conductive layers formed on both sides of the insulating substrate. [Background technology]

[0002] Conventionally, there has been known a semiconductor device in which a power semiconductor element such as an IGBT or a power MOSFET is mounted on one of the conductive layers of a metal insulating substrate, which has conductive layers made of copper or the like formed on both sides of an insulating substrate made of ceramic or the like (see, for example, Patent Document 1). IGBT is an abbreviation for Insulated Gate Bipolar Transistor. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0003] The semiconductor device described in Patent Document 1 is a so-called DBC substrate, in which copper metal layers are bonded to both the front and back sides of a ceramic substrate. A recess is provided in one of the metal layers of the DBC substrate, and a power semiconductor element is mounted inside the recess. DBC is an abbreviation for Direct Bonded Copper. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,964,635 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor device described in Patent Document 1, the thickness of the portion of the metal layer on which the power semiconductor element is mounted is thin, which reduces the heat dissipation efficiency in the plane direction perpendicular to the thickness direction of the metal layer, and there is a risk that the heat dissipation efficiency will decrease when the device is driven at a high current density.

[0006] To improve the heat dissipation efficiency in the planar direction, it is conceivable to increase the thickness of the metal layer on which the power semiconductor elements are mounted, but in this case, the current path becomes longer by the amount of the increase in the thickness of the metal layer, which increases the inductance and also increases the height of the semiconductor device, i.e., the size in the thickness direction.

[0007] In view of the above, the present invention aims to provide a semiconductor device in which a semiconductor element is mounted on a metal insulating substrate, which ensures heat dissipation in the planar direction of the metal layer on which the semiconductor element is mounted, while simultaneously suppressing an increase in inductance and suppressing the thickness of the semiconductor device. [Means for solving the problem]

[0008] In order to achieve the above object, the semiconductor device according to claim 1 is a semiconductor device comprising: a semiconductor element (2); an insulating substrate (31) having one surface (31a) and another surface (31b) that are opposite surfaces; a highly thermally conductive layer (32) bonded to one surface, having electrical conductivity, and having a thermal conductivity of greater than 398 W / m·K in a planar direction perpendicular to the thickness direction; and a conductive layer (33) bonded to the other surface, wherein the semiconductor element is bonded to the highly thermally conductive layer. The insulating substrate is larger in planar size than the highly thermally conductive layer, and the highly thermally conductive layer is a boiling cooling device having a storage section (323) which is a closed space located between the insulating substrate and the semiconductor element, and a heat medium (324) sealed in the storage section. .

[0009] As a result, the conductive layer of the metal insulating substrate on which the semiconductor element is mounted becomes a highly thermally conductive layer with a thermal conductivity of greater than 398 W / m·K in the plane direction, resulting in a semiconductor device that can ensure heat dissipation even when the thickness is thin. Therefore, this semiconductor device can simultaneously ensure heat dissipation in the plane direction, suppress an increase in inductance, and reduce the thickness of the semiconductor device.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment; [Figure 2] FIG. 2 is a cross-sectional view showing the cross-sectional configuration taken along line II-II in FIG. [Figure 3] FIG. 10 is a cross-sectional view corresponding to FIG. 2, showing a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view corresponding to FIG. 2, showing a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) A semiconductor device 1 according to a first embodiment will be described with reference to the drawings.

[0014] [Semiconductor Device] The semiconductor device 1 of this embodiment includes a semiconductor element 2 and a metal insulating substrate 3, as shown in FIG. 1, and the semiconductor element 2 is mounted on a high thermal conductivity layer 32 (described later) of the metal insulating substrate 3, which has a thermal conductivity in its planar direction that is at least higher than that of copper.

[0015] The semiconductor element 2 is a power semiconductor element including, for example, an IGBT, a power MOSFET, or an FWD primarily composed of a semiconductor material such as Si (silicon) or SiC (silicon carbide), and is manufactured using a known semiconductor process. FWD is an abbreviation for free wheeling diode. The semiconductor element 2 is, for example, a rectangular plate having a surface 2a and a back surface 2b and smaller in planar size than a recess 321 (described later) of the high thermal conductivity layer 32. As shown in FIG. 2, the semiconductor element 2 is disposed inside the recess 321 of the high thermal conductivity layer 32 and mounted on the high thermal conductivity layer 32 via a bonding material (not shown) such as solder. The semiconductor element 2 is disposed such that the surface 2a opposite the high thermal conductivity layer 32 is substantially flush with the plane defined by the upper surface 32a of the high thermal conductivity layer 32 opposite the insulating substrate 31. Note that "substantially coplanar" not only refers to a state in which the surface 2a of the semiconductor element 2 and the upper surface 32a of the high thermal conductivity layer 32 are coplanar, but also includes a state in which the surface 2a is slightly tilted or slightly protrudes from the upper surface 32a to an unavoidable extent during the manufacturing process. The semiconductor element 2 is, for example, a vertical power semiconductor element in which current flows in the thickness direction when in the on state, and has a pair of electrodes (emitter / collector or source / drain) (not shown) on the surface 2a and the back surface 2b, and a gate electrode (not shown) on the surface 2a.

[0016] The metal insulating substrate 3 comprises, for example, an insulating substrate 31 having one surface 31a and another surface 31b which are opposite surfaces, a highly thermally conductive layer 32 bonded to the one surface 31a, which is electrically conductive and has a thermal conductivity in the surface direction equal to or greater than a predetermined value, and a conductive layer 33 bonded to the other surface 31b.

[0017] The insulating substrate 31 is a ceramic substrate made of an insulating material such as Al2O3 (aluminum oxide) or AlN (aluminum nitride). The insulating substrate 31 has a thickness ranging from several hundred micrometers to several millimeters, and is generally rectangular, for example, but is not limited to, a planar size of the insulating substrate 31 that is larger than the high thermal conductivity layer 32 and the conductive layer 33, and has ends that protrude from the high thermal conductivity layer 32 and the conductive layer 33. The width of the portions of the insulating substrate 31 that protrude from the high thermal conductivity layer 32 and the conductive layer 33 is, for example, within a range from several hundred micrometers to several millimeters, but is not limited to this and can be changed as appropriate.

[0018] The highly thermally conductive layer 32 is disposed inside the outer periphery of one surface 31a of the insulating substrate 31 and has an outer shape, for example, a substantially rectangular plate. In this embodiment, the highly thermally conductive layer 32 is a boiling cooling device including a conductive base 322 having a recess 321 and a housing 323, which is an inner space for housing the heat medium 324, and the heat medium 324 sealed in the housing 323, as shown in FIG. 2 . The highly thermally conductive layer 32 is a component that dissipates heat from the semiconductor element 2 by repeating the process of the liquid heat medium 324 absorbing heat from the semiconductor element 2 bonded to the recess 321 of the base 322 and vaporizing, and then condensing and liquefying at a position away from the semiconductor element 2. The highly thermally conductive layer 32 has a thermal conductivity in the planar direction that is at least greater than that of copper, 398 W / m·K, due to the heat medium 324 flowing within the housing 323. As a result, the high thermal conductivity layer 32 can ensure heat dissipation in the plane direction perpendicular to its thickness direction while being made low-profile, and is a member with high heat dissipation efficiency even when the semiconductor element 2 is driven at a high current density. Note that "high thermal conductivity" here refers to a thermal conductivity in the plane direction that is greater than 398 W / m K.

[0019] The base 322 has, for example, an upper plate 3221 having a recess 321, a middle plate 3222 having a housing portion 323, and a bottom plate 3223 bonded to the insulating substrate 31, and is made of a conductive material such as a metal such as copper or an alloy thereof. The base 322 is configured such that the bottom plate 3223, middle plate 3222, and upper plate 3221 are bonded in this order from the insulating substrate 31 side by a bonding material (not shown).

[0020] The recess 321 in the upper plate 3221 has a planar size larger than the planar size of the semiconductor element 2 to be mounted. The accommodation section 323 of the middle plate 3222 has, for example, a plurality of columnar sections (not shown) arranged along the surface direction of the middle plate 3222 and a hollow member (not shown) connecting the columnar sections, thereby enabling the heat medium 324 evaporated by heat to re-condense into a liquid. The middle plate 3222 has, for example, an injection port (not shown) for injecting the heat medium 324 into the accommodation section 323 from the outside. After the base 322 is bonded to the insulating substrate 31 with a brazing material (not shown), the heat medium 324 can be injected into the accommodation section 323. This injection port (not shown) is closed after the heat medium 324 is injected into the accommodation section 323.

[0021] From the viewpoint of suppressing a decrease in inductance, the thickness t of the base 322 at the portion where the recess 321 is formed, i.e., the portion where the semiconductor element 2 is bonded, is, for example, 2 mm or less. The heat medium 324 is, for example, a fluorine-based refrigerant with a boiling point of 100°C or less, but other materials may be used and may be changed as appropriate depending on the heat generation amount of the semiconductor element 2. In other words, the high thermal conductivity layer 32 is a member that forms part of the current path together with the semiconductor element 2 and also serves as a heat spreader that diffuses the heat of the semiconductor element 2 in the planar direction.

[0022] In this embodiment, the high thermal conductivity layer 32 may be bonded to the first surface 31a of the insulating substrate 31 by molecular bonding at a temperature below the boiling point of the heat medium 324 after bonding the conductive layer 33 to the second surface 31b of the insulating substrate 31 with a brazing material (not shown). Bonding the high thermal conductivity layer 32 to the insulating substrate 31 by molecular bonding can be performed, for example, by the following process. After subjecting the lower surface 32b of the high thermal conductivity layer 32, opposite the upper surface 32a on which the recess 321 is formed, to plasma treatment or the like, the layer is immersed in a solution containing a molecular bonding agent having a dithiol triazine group, thereby bonding the dithiol triazine group to the surface layer of the lower surface 32b. The first surface 31a of the insulating substrate 31, to which the conductive layer 33 is bonded, and the lower surface 32b of the high thermal conductivity layer 32 to which the dithiol triazine group is bonded are then brought into contact and pressure-bonded, thereby bonding the insulating substrate 31 and the high thermal conductivity layer 32. As the molecular bonding agent, for example, TES (triethoxysilylpropylamino-1,3,5-triazine-2,4-dithiol) can be used.

[0023] Note that the high thermal conductivity layer 32 may be in the shape of a substantially square plate, but from the viewpoint of reducing inductance, it is preferable that the shape be such that two intersecting sides of the outer periphery have different lengths (for example, a substantially rectangular plate). As a result, when terminals of the high thermal conductivity layer 32 are connected to the semiconductor element 2 along its short side, the short side becomes the main current path, suppressing an increase in inductance, while diffusing heat from the semiconductor element 2 over a wide area in the longitudinal direction, thereby further improving heat dissipation efficiency.

[0024] The conductive layer 33 is a member made of a conductive material, such as a metal such as copper or an alloy thereof. The conductive layer 33 is, for example, a copper foil, and is bonded to the insulating substrate 31 in a flat state without any recesses. The conductive layer 33 is thermally connected to the high thermal conductivity layer 32 via the insulating substrate 31, and functions as a heat sink.

[0025] The above is the basic configuration of the semiconductor device 1 of this embodiment. The semiconductor device 1 is suitable for use as a part of a power converter, which will be described next, for example, but can also be used as a part of other power devices.

[0026] According to this embodiment, the semiconductor element 2 is bonded to the high thermal conductivity layer 32 of the metal insulating substrate 3, which has a thermal conductivity of greater than 398 W / m·K in the planar direction, resulting in a semiconductor device 1 that can ensure heat dissipation even when the high thermal conductivity layer 32 is thin. Furthermore, since it is not necessary to increase the thickness of the high thermal conductivity layer 32 in order to ensure heat dissipation in the planar direction of the semiconductor element 2, an increase in inductance and an increase in the size of the semiconductor device 1 in the thickness direction can be suppressed. Therefore, this semiconductor device 1 can simultaneously ensure heat dissipation in the planar direction, suppress an increase in inductance, and suppress the thickness of the entire device.

[0027] (Second embodiment) The semiconductor device 1 of the second embodiment will be described with reference to FIG.

[0028] The semiconductor device 1 of this embodiment differs from the first embodiment in that the highly thermally conductive layer 32 is made of a graphite sheet instead of a boiling cooling device. This difference will be mainly described in this embodiment.

[0029] In this embodiment, as shown in Fig. 3, the highly thermally conductive layer 32 has a base 322 with a recess 321, but does not have an accommodation portion 323 or a heat medium 324 inside. The highly thermally conductive layer 32 is, for example, a graphite sheet with a thermal conductivity in the plane direction of greater than 398 W / m K, and is bonded to one surface 31a of the insulating substrate 31 with any bonding material. Even in this case, the thickness of the portion of the highly thermally conductive layer 32 to which the semiconductor element 2 is bonded is 2 mm or less, which reduces the height of the semiconductor device 1 and ensures heat dissipation while suppressing an increase in inductance and a decrease in power density.

[0030] The present embodiment also provides the semiconductor device 1 with the same effects as those of the first embodiment. Furthermore, by using a graphite sheet as the highly thermally conductive layer 32, it is possible to bond the highly thermally conductive layer 32 to the insulating substrate 31 before bonding the conductive layer 33, thereby eliminating the need for a process of sealing in the heat medium 324.

[0031] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one, are also within the scope and spirit of the present disclosure.

[0032] 4, the semiconductor device 1 may have a configuration in which the high thermal conductivity layer 32 does not have the recess 321. Even in this case, the thickness of the portion of the high thermal conductivity layer 32 to which the semiconductor element 2 is bonded can be set to a predetermined value or less, while still ensuring heat dissipation in the surface direction of the semiconductor element 2. [Explanation of symbols]

[0033] 2. Semiconductor elements 3 Metal insulating substrate 31 Insulating substrate 31a one side 31b Other side 32 High thermal conductivity layer 321 recess 33 Conductive layer

Claims

1. A semiconductor device, A semiconductor element (2), The metal insulating substrate (3) comprises an insulating substrate (31) having one surface (31a) and another surface (31b) that are opposite surfaces, a highly thermally conductive layer (32) bonded to the one surface, the highly thermally conductive layer having a thermal conductivity of greater than 398 W / m·K in a plane direction perpendicular to the thickness direction, and a conductive layer (33) bonded to the other surface, the semiconductor element is bonded to the high thermal conductivity layer; the insulating substrate has a planar size larger than that of the high thermal conductivity layer; The semiconductor device is a boiling cooling device having a storage section (323) that is a closed space located between the insulating substrate and the semiconductor element, and a heat medium (324) sealed in the storage section.

2. The high thermal conductivity layer has a recess (321) having a planar size larger than that of the semiconductor element, The semiconductor device according to claim 1 , wherein the semiconductor element is disposed inside the recess.

3. 3. The semiconductor device according to claim 1, wherein the high thermal conductivity layer has two intersecting sides of its outer periphery that have different lengths.

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