Method for manufacturing a wiring board

Abstract

A method for producing a wiring board according to the present disclosure comprises: (A1) a step for preparing a laminate which is provided with an insulating material layer and a copper layer that is provided on the surface of the insulating material layer, wherein the copper layer is an electroless copper plating layer; (A2) a step for forming a resist pattern on the surface of the copper layer, said resist pattern having a groove that reaches the surface of the copper layer; and (A3) a step for filling the groove with a conductive material, which contains copper, by means of electrolytic copper plating. A copper layer with a carrier according to the present disclosure is provided with: a copper layer that is formed by means of electroless copper plating; and a carrier that is provided to the copper layer in a removable manner. A laminate according to the present disclosure is provided with an insulating material layer and a copper layer that is provided on the surface of the insulating material layer; and the copper layer is an electroless copper plating layer. The thickness of the electroless copper plating layer is, for example, from 20 nm to 200 nm.

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a wiring board, a laminate including an electroless copper plating layer and a method for manufacturing the same, and a copper layer with a carrier. [Background technology]

[0002] To increase the density and performance of semiconductor packages, a packaging format has been proposed in which semiconductor elements (hereinafter sometimes referred to as "chips") with different performance are mixed in one package. From the viewpoint of cost, high-density interconnect technology between chips is becoming increasingly important (see Patent Document 1).

[0003] A connection method known as package-on-package is widely adopted for smartphones and tablet devices. Package-on-package is a method of connecting different packages on one package by flip-chip mounting (see Non-Patent Documents 1 and 2). To achieve even higher density, various packaging technologies have been proposed, including packaging technology using organic substrates with high-density wiring (organic interposers), fan-out packaging technology with through-mold vias (TMVs) (FO-WLP), packaging technology using silicon or glass interposers, packaging technology using through-silicon vias (TSVs), and packaging technology using chips embedded in a substrate for inter-chip transmission. In particular, when mounting chips in parallel with each other in organic interposers and FO-WLPs, a fine wiring layer is required to ensure high-density electrical continuity (see Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-318519 [Patent Document 2] US Patent Application Publication No. 2001 / 0221071 [Non-patent literature]

[0005] [Non-Patent Document 1] Application of Through Mold Via(TMV) as PoP Base Package, Electronic Components and Technology Conference(ECTC),2008 [Non-patent document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP(eWLB-PoP)Technology,ECTC,2012 Summary of the Invention [Problem to be solved by the invention]

[0006] However, according to the investigations of the present inventors, when a conductive portion (e.g., a fine wiring) of a wiring board is formed by electrolytic copper plating, the continuity between the seed layer and the electrolytic copper plating layer may be insufficient due to the crystalline state of the metal layer constituting the seed layer. For example, when a fine wiring is formed by electroless copper plating on the surface of a copper foil formed by rolling, a discontinuous interface is formed between the copper foil and the electroless copper plating layer. Therefore, when forming even finer wiring, there is room for improvement in terms of reliability.

[0007] Therefore, the present disclosure provides a method for manufacturing a wiring board with excellent reliability, a laminate applicable to the manufacturing method, a method for manufacturing the same, and a copper layer with a carrier. [Means for solving the problem]

[0008] One aspect of the present disclosure relates to a method for manufacturing a wiring substrate, the method including the following steps. (A1) A step of preparing a laminate comprising an insulating material layer and a copper layer provided on the surface of the insulating material layer, the copper layer being an electroless copper plating layer. (A2) A step of forming a resist pattern having grooves reaching the surface of the copper layer on the surface of the copper layer. (A3) A step of filling the grooves with a copper-containing conductive material by electrolytic copper plating.

[0009] According to the inventors' investigations, by applying electrolytic plating to the surface of an electroless copper-plated layer, excellent continuity at the interface between the electroless copper-plated layer and the electrolytic copper-plated layer can be achieved, ensuring excellent adhesion between the two layers. According to the above-described manufacturing method, fine wiring can be formed from a conductive material formed by electrolytic copper plating and a copper layer (electroless copper-plated layer) in contact with the conductive material. Therefore, a wiring board having highly reliable fine wiring can be manufactured.

[0010] The method for manufacturing a wiring board according to the present disclosure may be configured to manufacture a multilayer wiring board having conductive portions between layers. The manufacturing method according to this embodiment includes the following steps. (B1) A step of preparing a laminate having a support substrate, an insulating material layer, and a copper layer in this order, the copper layer being an electroless copper plating layer. (B2) forming a first opening through the copper layer and the insulating material layer to the surface of the support substrate; (B3) forming a seed layer on the surface of the sidewall of the first opening by electroless copper plating; (B4) A step of forming a resist pattern having second openings communicating with the first openings on the surface of the copper layer. (B5) A step of filling the first opening and the second opening with a conductive material containing copper by electrolytic copper plating.

[0011] According to this manufacturing method, an interlayer conductive portion can be formed by a conductive material formed by electrolytic copper plating and a copper layer (electroless copper plating layer) in contact with the conductive material. This allows the manufacture of a wiring board having a highly reliable conductive portion. This is presumably because, as mentioned above, the conductive material and the copper layer have high continuity at their interface.

[0012] The thickness of the copper layer (electroless copper plating layer) is, for example, 20 to 200 nm. Because the copper layer is much thinner than copper foil or a copper layer obtained by electrolytic copper plating, it is useful for further miniaturizing wiring. Because the copper layer is much thinner, unnecessary portions of the copper layer can be efficiently removed by etching in the wiring board manufacturing process. This reduces the labor and time required for this process. Furthermore, the etching process can prevent variations in the cross-sectional area of the fine wiring.

[0013] The laminate in step (B1) can be prepared, for example, through the following steps. (b1) A step of preparing a copper layer with a carrier, which comprises a copper layer that is an electroless copper plating layer and a carrier that is provided so as to be releasable from the copper layer. (b2) applying a copper layer to the surface of the insulating material layer; (b3) peeling the carrier from the copper layer. By selecting a carrier made of a material suitable for electroless copper plating and forming a copper layer on its surface by electroless copper plating, a copper layer with a sufficiently uniform thickness can be formed on the surface of the carrier.In contrast, when a copper layer is formed directly on the surface of the insulating material layer by electroless copper plating without using a carrier, it is difficult to form a copper layer with a sufficiently uniform thickness due to the condition of the surface (e.g., low wettability), or sufficient adhesion of the copper layer to the insulating material layer cannot be obtained.

[0014] One aspect of the present disclosure provides a laminate. The laminate includes an insulating material layer and a copper layer provided on a surface of the insulating material layer, the copper layer being an electroless copper plating layer. Another aspect of the present disclosure provides a copper layer with a carrier. The copper layer with a carrier includes a copper layer formed by electroless copper plating and a carrier releasably provided on the copper layer. [Effects of the Invention]

[0015] The present disclosure provides a method for manufacturing a wiring board with excellent reliability. The present disclosure also provides a laminate applicable to the manufacturing method, a method for manufacturing the same, and a copper layer with a carrier. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating one embodiment of a carrier-attached copper layer according to the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view schematically illustrating one embodiment of a laminate according to the present disclosure. [Figure 3] 3(a) to 3(c) are cross-sectional views that schematically show the manufacturing process of the wiring board. [Figure 4] 4(a) to 4(c) are cross-sectional views that schematically show the manufacturing process of the wiring board. [Figure 5] 5(a) to 5(c) are cross-sectional views that schematically show the manufacturing process of the wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. The dimensional ratios of the drawings are not limited to those shown in the drawings.

[0018] When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, they are intended for explanatory purposes and do not necessarily mean that the relative positions are permanent. Furthermore, the term "layer" encompasses not only a shaped structure formed over the entire surface when observed in a plan view, but also a shaped structure formed on a portion of the surface. "A or B" may include either A or B, or may include both.

[0019] In this specification, the term "process" includes not only an independent process but also a process that cannot be clearly distinguished from other processes as long as the intended effect of the process is achieved. Furthermore, a numerical range indicated using "to" indicates a range that includes the numerical values before and after "to" as the minimum and maximum values, respectively.

[0020] In this specification, the content of each component in a composition refers to the total amount of the components present in the composition unless otherwise specified, when the composition contains multiple substances corresponding to each component. Furthermore, unless otherwise specified, the exemplified materials may be used alone or in combination of two or more. Furthermore, in the numerical ranges described in stages in this specification, the upper or lower limit of a certain numerical range may be replaced with the upper or lower limit of another numerical range. Furthermore, in the numerical ranges described in this specification, the upper or lower limit of that numerical range may be replaced with the value shown in the examples.

[0021] [Copper layer with carrier] Fig. 1 is a cross-sectional view schematically showing a copper layer with a carrier according to this embodiment. The copper layer with a carrier 5 shown in this figure comprises a copper layer 1 formed by electroless copper plating and a carrier 2 provided so as to be releasable from the copper layer 1. In this embodiment, the copper layer with a carrier 5 is used to transfer the copper layer 1 to an insulating material layer 6, which will be described later (see Fig. 2).

[0022] (copper layer) The copper layer 1 is a copper layer (electroless copper plating layer) formed by electroless plating. In addition to copper, which is the main component, the electroless copper plating layer may contain nickel, phosphorus, boron, palladium, etc. The fact that the copper layer 1 is formed by electroless copper plating can be confirmed by elemental analysis of the copper layer 1.

[0023] The thickness of the copper layer 1 is preferably 20 nm to 200 nm, more preferably 40 nm to 200 nm, and even more preferably 60 nm to 200 nm. When the thickness of the copper layer 1 is 20 nm or more, it tends to be able to fully function as a seed layer for electrolytic copper plating in the wiring board manufacturing process. On the other hand, when the thickness is 200 nm or less, the amount of etching of the copper layer 1 in the wiring board manufacturing process is small, and fine wiring with small variations in cross-sectional dimensions tends to be able to be stably formed.

[0024] (Career) The carrier 2 is provided so as to be peelable from the copper layer 1. There are no particular limitations on the carrier 2, but a flexible film is preferred. Specific examples of the carrier 2 include a polyethylene terephthalate (PET) film and a silicone film. The thickness of the carrier 2 is preferably in the range of 0.2 mm to 2.0 mm. A thickness of 0.2 mm or more tends to improve handling, while a thickness of 2.0 mm or less tends to reduce material costs.

[0025] The shape of the carrier 2 may be, for example, a wafer (substantially circular) or a panel (rectangular or square). If it is a wafer, its diameter may be, for example, 200 to 450 mm, and may be 200 mm, 300 mm, or 450 mm. If it is a panel, the length of one side may be, for example, 300 to 700 mm.

[0026] [Method of manufacturing a carrier-attached copper layer] The carrier-attached copper layer 5 is produced through a process of forming the copper layer 1 by electroless copper plating on the surface of the carrier 2. The method for forming the copper layer 1 will be described below.

[0027] Prior to the process of adsorbing palladium (a catalyst for electroless copper plating) onto the surface of the carrier 2, the following process is carried out. First, the surface of the carrier 2 is washed with a pretreatment liquid. The pretreatment liquid may be a commercially available alkaline pretreatment liquid containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is, for example, 1% to 30%. The carrier 2 is immersed in the pretreatment liquid for, for example, 1 minute to 60 minutes. The immersion temperature is, for example, 25°C to 80°C. After the pretreatment, the carrier 2 may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess pretreatment liquid.

[0028] After the pretreatment solution is removed, the carrier 2 is immersed and washed in an acidic aqueous solution to remove alkaline ions from the surface of the carrier 2. For example, a sulfuric acid aqueous solution with a concentration of 1% to 20% is used as the acidic aqueous solution. The immersion time is, for example, 1 minute to 60 minutes. After immersion, the carrier 2 may be washed with city water, pure water, ultrapure water, or an organic solvent to remove the acidic aqueous solution.

[0029] Palladium is deposited on the surface of the carrier 2 after immersion washing. For example, a commercially available palladium-tin colloidal solution, an aqueous solution containing palladium ions, or a palladium ion suspension may be used. Of these, an aqueous solution containing palladium ions is preferred because it can effectively adsorb palladium onto the surface of the carrier 2. When the carrier 2 is immersed in this aqueous solution, the temperature of the aqueous solution is, for example, 25°C to 80°C, and the immersion time is, for example, 1 minute to 60 minutes. After the palladium ions have been adsorbed, the carrier 2 may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess palladium ions.

[0030] After the palladium ions are adsorbed, activation is performed to allow the palladium ions to act as a catalyst. The reagent for activating the palladium ions may be a commercially available activator (activation treatment solution). For example, the palladium ions can be activated by immersing the carrier 2 in the activator. The temperature of the activator is, for example, 25°C to 80°C, and the immersion time is, for example, 1 minute to 60 minutes. After the activation of the palladium ions, the carrier 2 may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess activator.

[0031] Subsequently, a copper layer 1 is formed on the surface of the carrier 2 by electroless copper plating. This results in a carrier-attached copper layer 5. Examples of electroless copper plating include electroless pure copper plating (purity of 99% by mass or more) and electroless copper-nickel-phosphorus plating (nickel content: 1% by mass to 10% by mass, phosphorus content: 1% by mass to 13% by mass). Non-magnetic electroless copper plating is preferred from the viewpoint of ensuring good signal integrity. The electroless copper plating solution may be a commercially available plating solution, for example, an electroless copper plating solution (manufactured by Uemura Kogyo Co., Ltd., product name "Thru-Cup") can be used. The electroless copper plating is carried out in an electroless copper plating solution at 25°C to 60°C. After electroless copper plating, the carrier-attached copper layer 5 may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess plating solution.

[0032] If it is difficult to form the copper layer 1 on the surface of the carrier 2, the carrier 2 may be subjected to a surface treatment in advance. Examples of the surface treatment method include modification using oxygen plasma, argon plasma, nitrogen plasma, ultraviolet light-ozone, or the like.

[0033] [Laminate] 2 is a cross-sectional view schematically illustrating a laminate according to this embodiment. The laminate 10 shown in this figure includes an insulating material layer 6 and a copper layer 1 provided on the surface of the insulating material layer 6. The process for producing the laminate 10 includes a step of attaching the copper layer 1 of the carrier-attached copper layer 5 to the surface of the insulating material layer 6, and a step of peeling the carrier 2 from the copper layer 1. In other words, the laminate 10 is obtained by transferring the copper layer 1 of the carrier-attached copper layer 5 to the surface of the insulating material layer 6.

[0034] Methods for attaching the copper layer 1 of the carrier-attached copper layer 5 to the insulating material layer 6 include atmospheric pressure pressing, vacuum pressing, vacuum lamination, roll lamination, and vacuum roll lamination. Among these, vacuum pressing is preferred because it allows for the bonding of a large area at once. The copper layer 1 attached to the insulating material layer 6 by these methods has higher adhesion to the insulating material layer 6 than to the carrier 2. Therefore, the carrier 2 can be easily peeled off from the copper layer 1, for example, by hand.

[0035] (insulating material layer) The insulating material layer 6 is made of, for example, a thermosetting insulating material. Examples of thermosetting insulating materials include liquid and film-like materials, with film-like thermosetting insulating materials being preferred from the viewpoints of film thickness uniformity and cost. Furthermore, in order to enable the formation of fine wiring, the thermosetting insulating material preferably contains a filler with an average particle size of 500 nm or less (more preferably 50 to 200 nm). The filler content of the thermosetting insulating material is preferably more than 0 parts by mass and not more than 70 parts by mass, more preferably more than 0 parts by mass and not more than 50 parts by mass, per 100 parts by mass of the thermosetting insulating material excluding the filler.

[0036] When using a film-type thermosetting insulating material, it is preferable to use a thermosetting insulating film that can be pressed at 40°C to 250°C. Thermosetting insulating films that can be vacuum pressed at temperatures of 40°C or higher tend to have a moderate level of tack at room temperature (approximately 25°C) and are easy to handle. On the other hand, thermosetting insulating films that can be vacuum pressed at temperatures of 250°C or lower tend to be able to suppress warping after lamination.

[0037] The thermal expansion coefficient of the insulating material layer 6 after curing is set to 80×10 -6 / K or less is preferable, and in terms of obtaining high reliability, -6 / K or less is more preferable. In addition, in terms of the stress relaxation of the insulating material layer 6 and the ability to obtain a highly precise pattern, it is preferable that the -6 / K or more is preferable.

[0038] The thickness of the insulating material layer 6 is preferably 50 μm or less, more preferably 40 μm or less, and even more preferably 30 μm or less. When the thickness of the insulating material layer 6 is within the above range, it is easy to form fine circular or elliptical openings H1. From the viewpoint of insulation reliability, the thickness of the insulating material layer 6 is preferably 1 μm or more.

[0039] [Method of manufacturing wiring board] A method for manufacturing a wiring board according to this embodiment will be described with reference to the drawings. The wiring board 20 shown in Fig. 5(c) is manufactured through the following steps. (1) A step of preparing a laminate 11 having a copper layer 1, an insulating material layer 6, and a support substrate 7 in this order (see FIG. 3(a)). The laminate 11 may be produced by first preparing a laminate 10 including a copper layer 1 and an insulating material layer 6, and then laminating a support substrate 7 on the laminate 10, or by first preparing a laminate including an insulating material layer 6 and a support substrate 7, and then transferring the copper layer 1 from the carrier-attached copper layer 5 to the laminate. The support substrate 7 may be, for example, a copper-clad laminate, which has a copper layer 7a on its surface. (2) A step of forming an opening H1 (first opening) that penetrates the copper layer 1 and the insulating material layer 6 and reaches the surface (copper layer 7a) of the support substrate 7 (see FIG. 3(b)). The openings H1 can be formed by, for example, laser irradiation. If residues are found in the openings H1, a desmearing process may be carried out after the step (2). (3) A step of forming a seed layer 8 on the surface of the side wall of the opening H1 by electroless copper plating (see FIG. 3(c)). The seed layer 8, together with the copper layer 1, constitutes a seed layer for carrying out electrolytic plating in the following step (5). (4) A step of forming a resist pattern 12 on the surface of the copper layer 1, the resist pattern 12 having an opening H2 (second opening) communicating with the opening H1 and a plurality of grooves G extending to the surface of the copper layer 1 (see FIG. 4(a)). (5) A step of filling the openings H2 and the grooves G with a conductive material containing copper by electrolytic copper plating (see FIG. 4(b)). A conductive material containing copper is filled into the groove G by electrolytic copper plating, thereby forming a conductive portion 9a that constitutes a part of the fine wiring. A conductive material containing copper is filled into the openings H1 and H2 by electrolytic copper plating, thereby forming a conductive portion 9b (a part of the conduction portion between layers).

[0040] (6) Step of removing the resist pattern 12 (see FIG. 4(c)). (7) A step of removing the copper layer 1 exposed by peeling off the resist pattern 12 (see FIG. 5(a)). By removing unnecessary portions of the copper layer 1 by, for example, etching, the conductive portions 9a and the remaining portions of the copper layer 1 form fine wiring. (8) A step of forming an insulating material layer 15 so as to cover the surface of the copper layer 7a and the fine wiring (see FIG. 5(b)). (9) A step of forming an opening H3 (third opening) in the insulating material layer 15, reaching the conductive portion 9b (see FIG. 5(c)). The openings H1, H2, and H3 form via holes. The via holes are filled with a conductive material, and the wiring board is completed after surface finishing and other processes.

[0041] Although the embodiments of the present disclosure have been described in detail above, the present invention is not limited to the above embodiments. For example, the above embodiments illustrate a method for manufacturing a wiring board having a single wiring layer composed of fine wiring and an insulating material layer 15 covering the wiring, but a wiring board having multiple wiring layers may also be manufactured. A multilayer wiring layer can be manufactured by using laminate 10 instead of laminate 11 in step (1) after step (9) above and performing a series of steps (2) to (9) one or more times. [Example]

[0042] The present disclosure will be described below based on examples, but the present invention is not limited to the following examples.

[0043] Example 1A <Preparation of copper layer with carrier> An electroless copper plating layer was formed on the surface of a polyethylene terephthalate film (G2-16, manufactured by Teijin Limited, trade name, thickness: 16 μm, hereinafter referred to as "carrier") used as a carrier as follows: First, the carrier was immersed in an acid cleaner (manufactured by Uemura Kogyo Co., Ltd., trade name: MCD) at 40°C for 5 minutes. Then, the carrier was immersed in pure water at 40°C for 1 minute. Next, the carrier was immersed in a 10% aqueous sulfuric acid solution at 25°C for 1 minute. Then, the carrier was washed with running pure water at 25°C for 1 minute. Next, the carrier was immersed in a pre-dip solution (manufactured by Uemura Kogyo Co., Ltd., trade name: MDP) at 25°C for 1 minute. Next, the carrier was immersed in an activator solution (manufactured by Uemura Kogyo Co., Ltd., trade name: MAT) at 40°C for 5 minutes. Then, the carrier was washed with running pure water at 25°C for 1 minute. Next, the carrier was immersed in a reducer solution (Uemura Kogyo Co., Ltd., product name: MAB) for 3 minutes at 35°C. Thereafter, the carrier was washed with running pure water at 25°C for 1 minute. Next, the carrier was immersed in an accelerator solution (Uemura Kogyo Co., Ltd., product name: MEL) for 1 minute at 25°C. Thereafter, the carrier was immersed in an electroless copper plating solution (Uemura Kogyo Co., Ltd., product name: PEAV2) for 5 minutes at 36°C. This resulted in the deposition of a copper layer on the surface of the carrier. The copper layer with the carrier obtained through these processes was immersed in pure water for 1 minute and then dried on a hot plate at 85°C for 5 minutes.

[0044] Example 2A A copper layer with a carrier was produced in the same manner as in Example 1A, except that the immersion time in the electroless copper plating solution was changed from 5 minutes to 10 minutes.

[0045] Example 3A A copper layer with a carrier was produced in the same manner as in Example 1A, except that the immersion time in the electroless copper plating solution was changed from 5 minutes to 20 minutes.

[0046] Example 4A A copper layer with a carrier was produced in the same manner as in Example 1A, except that the immersion time in the electroless copper plating solution was changed from 5 minutes to 40 minutes.

[0047] <Measuring the thickness of the copper layer> The thickness of the copper layer (electroless copper plating layer) in each of the carrier-attached copper layers in Examples 1A to 4A was measured by cross-sectional observation using a scanning electron microscope (Regulus 8930, manufactured by Hitachi High-Technologies Corporation). Table 1 shows the results.

[0048] [Table 1]

[0049] Example 1B <Preparation of thermosetting resin film> First, a thermosetting resin composition was prepared using the following components. Biphenyl aralkyl epoxy resin (manufactured by Nippon Kayaku Co., Ltd., product name: NC-3000H): 70 parts by mass Curing agent: 30 parts by weight of a curing agent having a sulfone group in the molecular main chain and having an acidic substituent and an unsaturated N-substituted maleimide group. This curing agent was synthesized as follows: The following compounds were placed in a reactor (volume 2 liters) equipped with a thermometer, a stirrer, and a reflux condenser, and reacted at 140°C for 5 hours. The reactor used was capable of heating and cooling and was equipped with a moisture content monitor. Bis(4-aminophenyl) sulfone: 26.40g 2,2'-bis[4-(4-maleimidophenoxy)phenyl]propane: 484.50g p-aminobenzoic acid: 29.10g Dimethylacetamide: 360.00g Inorganic filler component: Silica filler (average particle size: 50 nm, treated with vinyl silane for silane coupling) Silica filler was blended so that it accounted for 30% by mass of the total mass of the resin. The particle size distribution of the silica filler was measured using a dynamic light scattering nanotrac particle size distribution analyzer "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrac particle size distribution analyzer "MT-3100" (manufactured by Nikkiso Co., Ltd.), and it was confirmed that the maximum particle size was 1 μm or less.

[0050] A solution of the thermosetting resin composition having the above composition was applied to the surface of a polyethylene terephthalate film (G2-16, product name, manufactured by Teijin Limited, thickness: 16 μm, hereinafter referred to as "PET film"). The coating was dried at 100°C for about 10 minutes using a hot air convection dryer. A thermosetting resin film having a thickness of 10 μm was formed on the PET film.

[0051] <Fabrication of laminated plates> A glass cloth-filled wiring substrate (size: 200 mm square, thickness: 1.5 mm) was prepared as a support substrate. This support substrate had a 20 μm-thick copper layer formed on its surface. The support substrate, thermosetting resin film (insulating material layer), and carrier-attached copper layer according to Example 1A were placed in this order and pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). The pressing conditions were a press hot plate temperature of 70°C, a vacuum time of 20 seconds, a laminating press time of 40 seconds, an atmospheric pressure of 4 kPa or less, and a bonding pressure of 0.5 MPa. Next, additional pressing was performed using a press machine. The pressing conditions were a temperature increase to 220°C over a pressing time of 0 to 60 minutes, a temperature maintenance period of 220°C over a pressing time of 60 to 190 minutes, and a temperature decrease to 25°C over a pressing time of 190 to 220 minutes. The pressing pressure was 2.0 MPa, and the atmospheric pressure was 4 kPa. After pressing, the carrier was peeled off from the copper layer.

[0052] <Creating a wiring board> A laser processing machine (product name: LC-2K21, manufactured by Via Mechanics) was used to process vias, creating a first opening extending to the surface of the wiring substrate. The via processing conditions were an aperture diameter of 6.5 mm, an output of 6.3 W, a pulse pitch of 20 μm x 3 times, and burst mode. A copper layer (seed layer) was formed on the surface of the sidewall of this opening by electroless plating. The electroless plating was performed using the same method as when forming the electroless copper plating layer on the carrier surface.

[0053] Using a vacuum laminator (V-160 manufactured by Nikko Materials Co., Ltd.), a wiring resist (RY-5107UT manufactured by Showa Denko Materials Co., Ltd.) was vacuum laminated onto the surface of the copper layer (thickness: 60 nm) according to Example 1A. The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa.

[0054] After vacuum lamination, the resist for forming wiring was left for one day and then exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Surma Precision Co., Ltd.). The exposure dose was 140 mJ / cm. 2 The focus was -15 μm. After exposure, the resist was left for one day, the protective film on the wiring formation resist was peeled off, and the resist was developed using a spray developer (AD-3000, manufactured by Mikasa Co., Ltd.). A 1.0% aqueous solution of sodium carbonate was used as the developer. The development temperature was 30°C, and the spray pressure was 0.14 MPa. As a result, a resist pattern for forming the following L / S (line / space) wiring was formed on the copper layer of Example 1A. L / S=100μm / 100μm (number of wires: 10) L / S=80μm / 80μm (number of wires: 10) L / S=30μm / 30μm (number of wires: 10) L / S=10μm / 10μm (number of wires: 10) L / S=1μm / 1μm (number of wires: 10) The resist for forming wiring was also provided with a second opening communicating with the first opening.

[0055] The laminate was immersed in a 100 mL / L aqueous solution of cleaner (manufactured by Okuno Pharmaceutical Industries Co., Ltd., product name: ICP Clean S-135) at 50°C for 1 minute, followed by immersion in pure water at 50°C for 1 minute. The laminate was then immersed in pure water at 25°C for 1 minute, followed by immersion in a 10% aqueous sulfuric acid solution at 25°C for 1 minute. Next, electrolytic copper plating was performed on the laminate as follows. An aqueous solution was prepared by adding 0.25 mL of hydrochloric acid, 10 mL of Top Lucina GT-3 (manufactured by Okuno Pharmaceutical Industries Co., Ltd., product name: TOP LUCINA GT-2), and 1 mL of Top Lucina GT-2 (manufactured by Okuno Pharmaceutical Industries Co., Ltd.) to 7.3 L of an aqueous solution containing 120 g / L of copper sulfate pentahydrate and 220 g / L of 96% sulfuric acid. Using this aqueous solution, electrolytic plating was performed on the surface of the laminate under the following conditions. The copper layer of Example 1A was used as a seed layer. Thereafter, the laminate was immersed in pure water at 25°C for 5 minutes, and then dried on a hot plate at 80°C for 5 minutes. ·Temperature: 25℃ ·Current density: 1.5A / dm 2 Duration: 10 minutes

[0056] The resist for forming wiring was stripped using a spray developer (AD-3000, manufactured by Mikasa Co., Ltd.) A 2.38% TMAH aqueous solution was used as the stripping solution, and the stripping temperature was 40° C. and the spray pressure was 0.2 MPa.

[0057] The copper layer (seed layer) of Example 1A that was exposed by stripping the resist was removed. To remove this copper layer, an aqueous solution having the following composition was prepared. Etching solution (JCU Corporation, SAC-700W3C): 5% by volume 98% sulfuric acid: 4% by volume 35% hydrogen peroxide: 5% by volume Copper sulfate pentahydrate: 30g / L The wiring substrate was immersed in this aqueous solution for 1 minute at 35°C. The unnecessary portions of the copper layer were removed to obtain the wiring substrate of Example 1B (see FIG. 5(a)). The wiring substrate was then immersed in pure water at 25°C for 5 minutes, and then dried on a hot plate at 80°C for 5 minutes.

[0058] [Examples 2B to 4B] Wiring boards according to Examples 2B to 4B were fabricated in the same manner as Example 1B, except that the copper layers with carriers according to Examples 2A to 4A were used instead of the copper layer with carriers according to Example 1A.

[0059] [Comparative Examples 1 to 3] Three types of copper foil with a carrier (manufactured by Mitsui Mining & Smelting Co., Ltd.) were prepared. All of the copper foils were formed by rolled copper foil and had the following thicknesses. Thickness of copper foil in Comparative Example 1: 5 μm Thickness of copper foil in Comparative Example 2: 10 μm Thickness of copper foil in Comparative Example 3: 20 μm

[0060] Wiring boards according to Examples 1 to 3 were produced in the same manner as in Example 1B, except that the copper foils of the carrier-attached copper foils according to Comparative Examples 1 to 3 were used instead of the copper layer (electroless copper plating layer) of the carrier-attached copper layer according to Example 1A.

[0061] <Evaluation of wiring formability> The interconnect formability was evaluated based on microscopic images of the cross-sectional areas of the interconnects of the examples and comparative examples before and after removing the seed layer. That is, the average cross-sectional area of 10 interconnects with L / S = 100 μm / 100 μm was calculated before and after removing the seed layer. The average cross-sectional area of 10 interconnects with L / S = 80 μm / 80 μm, 30 μm / 30 μm, 10 μm / 10 μm, and 1 μm / 1 μm was calculated in the same manner. The interconnect formability was evaluated based on the following criteria. The results are shown in Table 2. A: The rate of change in the average cross-sectional area before and after seed layer removal is less than 5%. B: The rate of change in the average cross-sectional area before and after the removal of the seed layer is 5% or more and less than 10%. C: The rate of change in the average cross-sectional area before and after the removal of the seed layer is 10% or more.

[0062] [Table 2]

[0063] <Evaluation of the reliability of fine wiring> The substrate after the wiring formation was subjected to a temperature cycle test. That is, the substrate was placed in a test device (manufactured by Espec Corporation) and the test was carried out under the following conditions. ·Temperature: -65℃~150℃ ·Holding time: 15 minutes 1000 cycles After the above test, the interface between the seed layer and the electroplated layer of the wiring cross section was analyzed using a field emission scanning electron microscope (FE-SEM, Hitachi High-Tech Corporation, Regulus 8230) to confirm the presence or absence of peeling at the interface. The reliability of the fine wiring was evaluated based on the following criteria. The results are shown in Table 3. A: No peeling was observed in any of the 10 wires. B: Peeling was observed in 1 to 3 of the 10 wires. C: Peeling was observed in 4 or more of the 10 wires. [Table 3] [Industrial Applicability]

[0064] The present disclosure provides a method for manufacturing a wiring board with excellent reliability. The present disclosure also provides a laminate applicable to the manufacturing method, a method for manufacturing the same, and a copper layer with a carrier. [Explanation of symbols]

[0065] 1...copper layer, 2...carrier, 5...copper layer with carrier, 6, 15...insulating material layer, 7...support substrate, 8...seed layer, 9a, 9b...conductive portion, 10, 11...laminate, 12...resist pattern, G...groove portion, H1...opening (first opening), H2...opening (second opening), H3...opening.

Claims

1. preparing a laminate comprising, in this order, a support substrate, an insulating material layer, and a copper layer, the copper layer being an electroless copper plating layer formed directly on the surface of the insulating material layer; forming a first opening through the copper layer and the insulating material layer to a surface of the support substrate; forming a seed layer on a surface of a sidewall of the first opening by electroless copper plating; forming a resist pattern on a surface of the copper layer, the resist pattern having a second opening communicating with the first opening; filling the first opening and the second opening with a conductive material containing copper by electrolytic copper plating; A method for manufacturing a wiring board, comprising:

2. 2. The method for manufacturing a wiring board according to claim 1, wherein the copper layer has a thickness of 20 nm to 200 nm.

3. The laminate is preparing a copper layer with a carrier, the copper layer being formed by electroless copper plating and a carrier supporting the copper layer; applying the copper layer to the surface of the insulating material layer; peeling the carrier from the copper layer; The method for manufacturing a wiring board according to claim 1 or 2, wherein the wiring board is prepared through the steps of:

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