Semiconductor Devices

Abstract

To provide a semiconductor device that can reduce the switching loss at the time of turn-off while suppressing the loss at the time of conduction.SOLUTION: An emitter p- layer 11, a collector p layer 23, a drift layer 10, an emitter electrode 18, a collector electrode 28, an emitter side gate electrode 17, an emitter n layer 12, a collector p- layer 23a, a collector side gate electrode 27, and a collector n layer 22 constitute a semiconductor device 1, and the total length in the gate width direction in a first facing region of the emitter side gate electrode 17 facing an emitter layer p- 11 via a gate insulating film 15 is longer than the total length in the gate width direction in a second facing region of the collector side gate electrode 27 facing an impurity layer 23a through a collector side gate insulating film 25.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] One type of power semiconductor device is the insulated gate bipolar transistor (hereinafter referred to as "IGBT"). The IGBT is a semiconductor device with an input section having a MOSFET structure and an output section having a bipolar structure. The IGBT was developed to compensate for the drawback of MOS transistors, which have large conduction losses, but tends to have larger switching losses than power MOSFETs. Such IGBTs are publicly known, for example, from Patent Document 1 and Patent Document 2.

[0003] In the voltage-driven semiconductor device described in Patent Document 1, in addition to a first transistor, a second transistor having a polarity opposite to that of the drain of the first transistor is formed, and carriers are supplied from the second transistor to the drain of the first transistor. With this configuration, the voltage-driven semiconductor device described in Patent Document 1 can cause conductivity modulation in the drain of the first transistor, thereby reducing conduction loss and reducing on-state voltage drop.

[0004] The semiconductor device described in Patent Document 2 is a planar gate IGBT having a main gate electrode on the surface of a semiconductor layer. This semiconductor device also has a control gate electrode on the back surface of the semiconductor layer. The semiconductor device of Patent Document 2 can suppress the injection of holes into the drift region during turn-off operation, thereby reducing turn-off loss (switching loss). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 8-37295 [Patent Document 2] Japanese Patent Application Publication No. 2020-47789 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a configuration that uses the conductivity modulation effect to reduce conduction loss, as described in Patent Document 1, a tail current is generated in the latter half of the turn-off of the first and second transistors, resulting in increased switching loss. To address this issue, a control gate electrode is provided on one side of the semiconductor layer, as described in Patent Document 2. This limits the space available for forming the collector electrode, reducing the amount of carrier injection required for conductivity modulation, resulting in increased conduction loss. In other words, in IGBTs, there is a trade-off between reducing conduction loss and switching loss.

[0007] The present invention has been made in view of the above-mentioned points, and has as its object to provide a semiconductor device that can reduce switching loss at turn-off while suppressing conduction loss. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor device of the present invention includes an emitter layer of a first conductivity type, a collector layer of the first conductivity type, a drift layer of a second conductivity type provided between the emitter layer and the collector layer, an emitter electrode electrically connected to the emitter layer, a collector electrode electrically connected to the collector layer, one or more emitter-side gate electrodes arranged to face the emitter layer via an emitter-side gate insulating film, a first highly doped layer of the second conductivity type provided between the emitter electrode and the emitter layer and having a higher dopant concentration than the emitter layer, and a second highly doped layer provided between the drift layer and the collector electrode. a first conductivity type impurity layer formed on the emitter layer, one or more collector-side gate electrodes arranged opposite the impurity layer with a collector-side gate insulating film interposed therebetween; and a second high-concentration impurity layer of a second conductivity type provided between the collector electrode and the impurity layer and having a higher impurity concentration than the impurity layer, wherein the total length in the gate width direction of a first opposing region of the emitter-side gate electrode opposing the emitter layer via the emitter-side gate insulating film is longer than the total length in the gate width direction of a second opposing region of the collector-side gate electrode opposing the impurity layer via the collector-side gate insulating film. [Effects of the Invention]

[0009] According to the present invention, by making the length in the gate width direction of a first opposing region of the emitter-side gate electrode, which is arranged opposite the emitter layer with the emitter-side gate insulating film interposed therebetween, longer than the length in the gate width direction of a second opposing region of the collector-side gate electrode, which is arranged opposite the impurity layer with the collector-side gate insulating film interposed therebetween, it is possible to reduce switching loss at turn-off while suppressing conduction loss at the time of injection of electrons into the drift layer. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment; [Figure 2] 1. (a) is a cross-sectional view taken along line IIa-IIa in FIG. 1. (b) is a cross-sectional view taken along line IIb-IIb in FIG. [Figure 3] FIG. 2 is a schematic diagram for explaining an inversion layer formed in an emitter p-layer and an inversion layer formed in a collector p-layer. [Figure 4] 1A is a circuit diagram showing a conventional IGBT evaluation circuit as a comparative example, and FIG. 1B is a circuit diagram showing a semiconductor device evaluation circuit according to the first embodiment. [Figure 5] 1A is a graph showing the simulation results of the relationship between the gate density ratio and the switching loss, and FIG. 1B is a graph showing the simulation results of the relationship between the gate density ratio and the on-state voltage drop. [Figure 6] 10 is a graph showing a simulation result illustrating the relationship between the difference in gate-on timing between the emitter side and the collector side and switching loss. [Figure 7A] 3A to 3C are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7B] 7(d) and 7(e) are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment following FIG. 7A. [Figure 8] FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first modified example. [Figure 9] 9A is a cross-sectional view taken along line IXa-IXa of the semiconductor device shown in FIG. 8, viewed from above downward; and FIG. 9B is a cross-sectional view taken along line IXb-IXb of the semiconductor device, viewed from below upward. [Figure 10] FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second modification. [Figure 11] 11A is a cross-sectional view taken along line XIa-XIa of the semiconductor device shown in FIG. 10, viewed from above downward; and FIG. 11B is a cross-sectional view taken along line XIb-XIb of the semiconductor device, viewed from below upward. [Figure 12] 10A, 10B, 10C, and 10D are timing charts for explaining modified examples of the operation of the semiconductor device of the first embodiment. [Figure 13]10A, 10B, and 10C are timing charts for explaining a modified example of the operation of the semiconductor device of the first embodiment at the time of turning on. [Figure 14] 10A, 10B, 10C, and 10D are timing charts for explaining a modified example of the operation of the semiconductor device of the first embodiment at the time of turn-off. [Figure 15] 1A is a diagram showing the upper surface of an emitter electrode, and FIG. 1B is a diagram showing the upper surface of a collector electrode. [Figure 16] This is a cross-sectional view of the semiconductor device shown in Figures 15(a) and 15(b), taken along the dashed dotted line between arrows XV and XV, looking in the direction of arrow XV. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a first embodiment and a second embodiment of the present invention will be described. In the drawings of the first embodiment and the second embodiment, like components are denoted by like reference numerals, and overlapping descriptions will be omitted.

[0012] [First embodiment] A first embodiment of the present invention will be described below. (Configuration of semiconductor device) Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device 1 of a first embodiment. Fig. 2(a) is a cross-sectional view of the cross-section of the semiconductor device 1 taken along line IIa-IIa in Fig. 1, viewed from above. Fig. 2(b) is a cross-sectional view of the cross-section of the semiconductor device 1 taken along line IIb-IIb, viewed from below. Fig. 1 shows a cross-sectional side view of the semiconductor device 1 taken along line II in Fig. 2(a), in a configuration in which an emitter electrode 18, a collector electrode 28, and the like, which will be described later in Figs. 2(a) and 2(b), are provided.

[0013] 1, 2(a), and 2(b), the Z direction indicates the thickness direction of the semiconductor device 1, and the X direction indicates a direction parallel to a first surface fa and a second surface fb, which is the back surface of the semiconductor substrate (hereinafter simply referred to as "substrate") 5 of the semiconductor device 1, and a direction perpendicular to the Z direction. The Y direction indicates a direction parallel to the first surface fa and the second surface fb, and a direction perpendicular to the Z direction and the X direction. For ease of explanation, the direction indicated by the arrow in the Z direction, which is the thickness direction in FIG. 1, will be referred to as the downward direction, and the direction opposite to the arrow in the Z direction will be referred to as the upward direction.

[0014] The semiconductor device 1 is an IGBT type semiconductor device, and has a substrate 5 made of, for example, a Si crystal. The substrate 5 has an emitter p - layer 11, a collector p layer 23 as a collector layer, and an emitter p - The drift layer 10 is provided between the layer 11 and the collector p layer 23, the emitter n layer 12 which is a first high concentration impurity layer, the emitter p layer 13, the buffer layer 29, and the collector p - The drift layer 10 has a first high-concentration impurity layer 23a and a second high-concentration impurity layer, i.e., a collector n-layer 22. In the following description, the part on the emitter electrode 18 side across the drift layer 10 will be referred to as the "emitter side," and the part on the collector electrode 28 side will be referred to as the "collector side."

[0015] In the first embodiment, the emitter p layer 13, the emitter p - Layer 11 and collector p layer 23 are impurity layers of p-type conductivity (here, the first conductivity type), and emitter n layer 12, drift layer 10, buffer layer 29 and collector n layer 22 are impurity layers of n-type conductivity (here, the second conductivity type).

[0016] Emitter p - The layer 11 is formed on the upper surface of the drift layer 10. - An emitter n-layer 12 and an emitter p-layer 13 are formed above the layer 11. The emitter n-layer 12 and the emitter p-layer 13 are formed so as to be exposed on the first surface fa of the substrate 5, and are electrically connected to the emitter electrode 18. The emitter n-layer 12, which is a first highly doped impurity layer, is electrically connected to the emitter electrode 18 and the emitter p- However, a part of the emitter n layer 12 is provided between the interlayer insulating layer 16 and the emitter p - The emitter p layer 13 may be disposed between the emitter electrode 18 and the emitter p - The emitter n layer 12 and the emitter p layer 13 are disposed between the emitter n layer 12 and the emitter p layer 13. - It is a contact layer to layer 11, and both are emitter p - It has a higher impurity concentration than layer 11 .

[0017] The emitter n layer 12 is - Inject electrons into layer 11 + The emitter p layer 13 is a lower emitter p - p which drains holes from layer 11 + A trench hole 14 (described later) penetrating the emitter n layer 12 is formed on the first surface fa of the substrate 5.

[0018] The drift layer 10 has n - The impurity concentration is, for example, 2×10 13 cm -3 The impurity concentration of the emitter n-layer 12 and the emitter p-layer 13 is, for example, 10 18 ~10 21 cm -3 That's about it.

[0019] As a result, on the first surface fa of the substrate 5, emitter n layers 12 are disposed adjacent to each trench hole 14, and emitter p layers 13 are disposed between the emitter n layers 12 formed adjacent to each trench hole 14. As shown in FIG. 2(a), the emitter n layers 12 are formed in a strip shape when viewed from above, and are disposed on both sides of the trench hole 14 so as to extend in the Y direction on the first surface fa. The emitter p layers 13 are also formed in a strip shape when viewed from above, and are disposed between the emitter n layers 12 so as to extend in the Y direction on the first surface fa.

[0020] As shown in FIG. 2(a), a plurality of trench holes 14 extending in the Y direction are provided on the first surface fa of the substrate 5. The trench holes 14 according to the first embodiment have the same configuration, are arranged parallel to one another along the Y direction on the first surface fa, and are provided at predetermined intervals in the X direction. As shown in FIG. 1, the trench holes 14 extend from the first surface fa of the substrate 5 to the emitter n layer 12 and the emitter p - It penetrates through layer 11 and reaches drift layer 10 .

[0021] A gate insulating film 15, which is an emitter-side gate insulating film, is formed on the inner surface of each trench hole 14, and a trench-type emitter-side gate electrode 17 is formed in the area surrounded by the gate insulating film 15. The gate insulating film 15 is formed of, for example, an oxide film, and the emitter-side gate electrode 17 is connected to the substrate 5 (drift layer 10, emitter p - The emitter n-layer 12 is insulated from the n-layer 11.

[0022] The emitter-side gate electrodes 17 are formed of, for example, polycrystalline silicon (polysilicon) or the like, and their upper ends are covered with an interlayer insulating layer 16 made of an oxide film or the like. An emitter-side gate wiring (not shown) is connected to each emitter-side gate electrode 17, and a predetermined gate voltage Vgg1 is applied via the emitter-side gate wiring. The upper ends of the emitter-side gate electrodes 17 according to the first embodiment are located within the trench holes 14 without protruding from the first surface fa of the substrate 5, and the interlayer insulating layer 16 is also provided within the trench holes 14 and is connected to the gate insulating film 15.

[0023] 1, 2(a), and 2(b), the semiconductor device 1 has a predetermined number of emitter-side gate electrodes 17 extending parallel to one another in the Y direction and arranged at predetermined intervals in the X direction. Here, the configuration within the element region R0 is defined as one pattern, and the configuration within the element region R0 is formed as a repeated pattern at a predetermined period in the X direction. The configuration of the semiconductor device 1 will be described below, focusing on the element region R0 defined in the X direction.

[0024] The emitter-side gate electrode 17 is connected to the emitter p - The emitter-side gate electrodes 17 have first opposing regions (hereinafter referred to as emitter-side opposing regions) disposed opposite the layer 11. In Fig. 1, five emitter-side gate electrodes 17 are shown, and ten emitter-side opposing regions Ja0 to Ja8 are shown as the emitter-side opposing regions Ja.

[0025] 1, in the first embodiment, the emitter-side facing region Ja0 on the left side of the emitter-side gate electrode 17 at the leftmost end in the drawing is not included in the repeated element region R0, while the emitter-side facing region Ja1 on the right side in the drawing is included in the element region R0. Also, the emitter-side facing region Ja0 on the right side of the emitter-side gate electrode 17 at the rightmost end in the drawing is not included in the repeated element region R0, while the emitter-side facing region Ja8 on the left side in the drawing is included in the element region R0. Thus, a total of eight emitter-side facing regions Ja1 to Ja8 are formed as the emitter-side facing regions Ja of the emitter-side gate electrode 17 within one element region R0 according to the first embodiment. When the eight emitter-side facing regions Ja1 to Ja8 are not to be distinguished from one another, they will simply be referred to as emitter-side facing regions Ja.

[0026] As shown in FIG. 2(a), the emitter-side gate electrode 17 according to the first embodiment is formed in a strip shape in top view, and its length in the Y direction on the first surface fa of the substrate 5 (the length of the emitter-side gate electrode 17 in the extension direction in the XY plane) can be defined as W. The length W in the Y direction, which is the extension direction, is the length in the gate width direction of the emitter-side facing region Ja of the emitter-side gate electrode 17, and in the first embodiment, this length will also be referred to as the "first facing region length." In the first embodiment, the length in the gate width direction of each emitter-side facing region Ja is W. Therefore, in the first embodiment, the total first facing region length of the eight emitter-side facing regions Ja1 to Ja8 in one device region R0, which forms a repeated pattern, can be defined as 8·W.

[0027] 2(a) and 2(b), in the first embodiment, the emitter-side gate electrode 17 and the collector-side gate electrode 27 both extend in the Y direction shown in Fig. 1. The length L1 of the emitter-side facing region is the channel length of the emitter-side gate electrode 17 extending in the Z direction, which is different from the Y direction. The length L2 of the collector-side facing region is the channel length of the collector-side gate electrode 27 extending in the X direction, which is different from the Y direction.

[0028] In addition, an emitter electrode 18 made of, for example, aluminum (Al) or copper (Cu) is provided on the first surface fa of the substrate 5, covering the surface of the first surface fa and the interlayer insulating layer 16. The emitter-side gate electrode 17 in the trench hole 14 is insulated from the emitter electrode 18 by the interlayer insulating layer 16 provided on the substrate 5.

[0029] A contact hole 16a is formed between adjacent interlayer insulating layers 16, and an emitter electrode 18 provided on the first surface fa of the substrate 5 is also provided in the contact hole 16a. The emitter electrode 18 is in contact with the emitter p layer 13 in the contact hole 16a. - The interlayer insulating layer 16 is electrically connected to the layer 11. The interlayer insulating layer 16 is provided on the first surface fa of the substrate 5 so as to cover the entire upper surface of the emitter-side gate electrode 17 and also to cover a partial region of the upper surface of the emitter n layer 12 adjacent to the trench hole 14.

[0030] In this way, the interlayer insulating layer 16 covers not only the upper part of the emitter-side gate electrode 17 but also the emitter n-layer 12 around the emitter-side gate electrode 17, thereby preventing a short circuit between the emitter electrode 18 and the emitter-side gate electrode 17. L1 indicates a region on the first surface fa of the substrate 5 where the interlayer insulating layer 16 is formed.

[0031] Next, the second surface fb side (lower surface) of the substrate 5 will be described. In the substrate 5, a buffer layer 29 is formed on the other surface 10b of the drift layer 10. Below the buffer layer 29, a collector p layer 23 and a collector p- The collector n-layer 22 is connected to the collector electrode 28 and the collector p - The collector p - The n layer has a higher impurity concentration than the layer 23a. + The collector n layer 22 and the collector p - The layer 23 a is electrically connected to the collector electrode 28 .

[0032] The buffer layer 29 is located between the drift layer 10 and the collector p layer 23, and has a higher impurity concentration than the drift layer 10 to prevent the depletion layer from reaching the collector p layer 23. If the drift layer 10 is configured to be sufficiently thick so that the depletion layer does not reach the collector p layer 23, the buffer layer 29 does not need to be formed. - The layer 23a has a lower impurity concentration than the collector p-layer 23. - The impurity concentration of the collector p-layer 23 and the collector n-layer 22 is, for example, 10 18 cm -3 From 10 21 cm -3 The impurity concentration of the buffer layer 29 is, for example, 10 15 cm -3 From 10 18 cm -3 That's about it.

[0033] Collector P - The layer 23a is a p-type layer having a lower impurity concentration than the collector p-type layer 23 formed by, for example, ion implantation. - On the second surface fb, the collector n layer 22 is formed in the collector p layer 23. The collector n layer 22 is - The collector p-layer 23 is formed in a partial region on the second surface fb side of the substrate 5 so as to straddle the layer 23a and the collector p-layer 23.

[0034] As shown in FIG. 2(b), the collector p layer 23 on the second surface fb of the substrate 5 is formed in a strip shape in bottom view and is arranged to extend in the Y direction on the second surface fb. - The collector p layer 23a and the collector n layer 22 are arranged in this order. - The layer 23a and the collector n layer 22 are disposed to extend in the Y direction on the second surface fb.

[0035] 1, the second surface fb of the substrate 5 is provided with a planar collector-side gate electrode 27, a gate insulating film 25 serving as a collector-side gate insulating film formed on the upper surface of the collector-side gate electrode 27, and a collector electrode 28. The planar collector-side gate electrode 27, which is disposed on the surface of the second surface fb (the XY plane of the second surface fb) of the substrate 5 with the gate insulating film 25 interposed therebetween, is made of, for example, polycrystalline silicon (polysilicon) or the like, and the collector p layer 23 and the collector p - The collector-side gate electrode 27 is disposed below the layer 23a via a gate insulating film 25 made of an oxide film or the like. A collector-side gate wiring (not shown) is connected to the collector-side gate electrode 27, and a predetermined gate voltage Vgg2 is applied via the collector-side gate wiring.

[0036] The collector-side gate electrode 27 is connected to the collector p of the second surface fb via the gate insulating film 25. - 1, one collector-side gate electrode 27 is provided in the repeated pattern element region R0, and two collector-side facing regions Jb1 and Jb2 are provided in the element region R0. When there is no need to distinguish between the two collector-side facing regions Jb1 and Jb2, they will simply be referred to as collector-side facing regions Jb.

[0037] 2(b), the collector-side gate electrode 27 according to the first embodiment is formed in a strip shape in bottom view, and its length in the Y direction on the second surface fb of the substrate 5 (the length of the collector-side gate electrode 27 in the extending direction in the XY plane) can be defined as W. The length W in the extending Y direction is the length in the gate width direction of the collector-side opposing region Jb of the collector-side gate electrode 27, and in the first embodiment, this will also be referred to as the "second opposing region length." Therefore, in one element region R0 that forms a repeated pattern in the first embodiment, the sum of the second opposing region lengths of the two collector-side opposing regions Jb1 and Jb2 can be defined as 2·W.

[0038] A gate insulating film 25 provided on the second surface fb of the substrate 5 is disposed on the collector-side gate electrode 27, and an interlayer insulating layer 26 is formed below and on the sides of the collector-side gate electrode 27. The collector-side gate electrode 27 is entirely covered by the gate insulating film 25 and the interlayer insulating layer 26. A collector electrode 28 made of, for example, aluminum (Al) or copper (Cu) is provided on the second surface fb of the substrate 5, and covers the surface of the second surface fb and the interlayer insulating layer 26. The collector electrode 28 is adjacent to the collector n layer 22 and the collector p layer 23, and is electrically connected to the collector n layer 22 and the collector p layer 23. The collector-side gate electrode 27 is separated from the buffer layer 29 and the collector p layer 24 by the gate insulating film 25 provided on the second surface fb of the substrate 5. - It is insulated from layer 23a.

[0039] Here, in one element region R0, which is a repeating pattern in the first embodiment, the total length of the first opposing regions of the emitter-side opposing regions Ja1 to Ja8 is specified as 8·W, and is configured to be longer than the total length of the second opposing regions of the collector-side opposing regions Jb1 and Jb2, which is 2·W.

[0040] In the first embodiment, the length of one first opposing region of the emitter-side gate electrode 17 is equal to the length of one second opposing region of the collector-side gate electrode 27, and therefore, in order to make the total of the first opposing region lengths longer than the total of the second opposing region lengths in the element region R0, the emitter-side gate electrodes 17 on the first face fa are arranged at a higher density than the collector-side gate electrodes 27 on the second face fb. In the first embodiment, when the total of the second opposing region lengths in the element region R0 is set to 1, the ratio of the total of the first opposing region lengths to the total of the second opposing region lengths in the element region R0 is referred to as the gate density ratio.

[0041] In the semiconductor device 1 according to the first embodiment, the gate density ratio Ja:Jb is 4:1, i.e., the total length of the first opposing regions is four times the total length of the second opposing regions. Note that, although the present embodiment describes a case in which the total length of the first opposing regions is four times the total length of the second opposing regions, the present invention is not limited thereto, and it is sufficient that the total length of the first opposing regions is longer than the total length of the second opposing regions. The total length of the first opposing regions may be, for example, two or more times longer than the total length of the second opposing regions, or even four or more times longer.

[0042] The gate density ratio Ja:Jb is preferably greater than 1:1 and less than 8:1. The gate density ratio Ja:Jb is preferably in the range of 2:1 to 7:1, and more preferably in the range of 3:1 to 5:1. Simulation results have confirmed that by setting the gate density ratio Ja:Jb in this range, it is possible to reduce conduction losses during on / off operation of the semiconductor device 1 while also reducing switching losses during turn-off, the details of which will be described later.

[0043] As described above, in the first embodiment, the conduction loss and switching loss are adjusted by comparing the sum of the first opposing region lengths and the sum of the second opposing region lengths within the element region R0. This is done to adjust the driving force between the first surface fa (top surface) and the second surface fb (bottom surface) of the semiconductor device 1, focusing on the fact that the driving force of the semiconductor device is proportional to the gate width of the gate electrode. Although the driving force increases as the gate length decreases, the effect of differences in the lengths L1 and L2 on the driving force is negligible because it is sufficiently small compared to the gate width W. However, in the first embodiment, in addition to adjusting the total length of the first opposing region and the total length of the second opposing region, the lengths L1 and L2 shown in FIGS. 1, 2(a), and 2(b) may be designed to be longer or shorter to further adjust the driving force on the emitter side and the collector side.

[0044] (On / off operation of semiconductor device) Next, the on / off operation of the semiconductor device 1 described above will be explained. It is assumed that a positive voltage Vce is applied between the emitter electrode 18 and the collector electrode 28 of the semiconductor device 1. The semiconductor device 1 is controlled by the application states of a gate voltage Vgg1, which is a first gate voltage applied to the emitter-side gate electrode 17, and a gate voltage Vgg2, which is a second gate voltage applied to the collector-side gate electrode 27. When the semiconductor device 1 is in the on state, there is conduction between the emitter n-layer 12 and the drift layer 10, and there is no conduction between the collector n-layer 22 and the drift layer 10. At this time, the emitter p - Electrons are injected from the emitter electrode 18 into the drift layer 10 through an inversion layer formed in the layer 11, and holes are injected from the collector p-layer 23 into the drift layer 10. When the semiconductor device 1 is turned off, at least the collector n-layer 22 and the drift layer 10 are electrically connected. -Electrons are discharged from the drift layer 10 to the collector electrode 28 via the inversion layer formed in the layer 23a and the collector n layer 22. When the collector n layer 22 and the drift layer 10 are electrically connected, if the emitter n layer 12 and the drift layer 10 are electrically disconnected, the injection of electrons into the drift layer 10 stops, and electrons are discharged from the drift layer 10 to the emitter p - Holes are discharged to layer 11. The on and off operations will be described in detail below.

[0045] During an ON operation, a high (for example, threshold value or higher) gate voltage Vgg1 (ON voltage) is applied to the emitter-side gate electrode 17, and a low (for example, 0 V) gate voltage Vgg2 (OFF voltage) is applied to the collector-side gate electrode 27. As a result, in the semiconductor device 1, as shown in FIG. - In the layer 11, an inversion layer (n-channel) La is formed.

[0046] During on-operation, the semiconductor device 1 is in a conductive state between the emitter n-layer 12 and the drift layer 10 due to the inversion layer La, and electrons are injected from the emitter n-layer 12 into the drift layer 10 through the inversion layer La. The on-voltage applied to the emitter-side gate electrode 17 may be a positive voltage with respect to the emitter electrode 18.

[0047] In the semiconductor device 1, when a low (for example, 0 V) gate voltage Vgg2 (off voltage) different from the gate voltage Vgg1 is applied to the collector-side gate electrode 27, the collector p - The collector p along the collector-side facing region Jb of the collector-side gate electrode 27 facing the layer 23a -In this case, an inversion layer Lb (n-channel) is not formed in layer 23a. Therefore, in semiconductor device 1, collector n layer 22 and buffer layer 29 are insulated and non-conductive, and the p-n junction formed by collector p layer 23 and buffer layer 29 is forward biased. In semiconductor device 1, the forward bias of the p-n junction formed by collector p layer 23 and buffer layer 29 causes holes to be injected from collector p layer 23 through buffer layer 29 into drift layer 10. Note that here, collector n layer 22 and drift layer 10 are electrically connected via buffer layer 29, and therefore conduction and non-conduction between collector n layer 22 and buffer layer 29 are synonymous with conduction and non-conduction between collector n layer 22 and drift layer 10.

[0048] The gate voltage Vgg2, which is different from the gate voltage Vgg1 described above, is not limited to 0 V, and may be, for example, a negative voltage, or a positive voltage that does not form an inversion layer under the collector-side gate electrode 27. In other words, the gate voltages Vgg1 and Vgg2 that are applied simultaneously may be any voltages that form an inversion layer in one of the opposing regions on the emitter side and the collector side, but do not form an inversion layer in the other opposing region.

[0049] As a result, during on-state operation, the density of electrons and holes present in the drift layer 10 increases, causing conductivity modulation and reducing the resistance of the drift layer 10. The on-state voltage of the semiconductor device 1 corresponds to the voltage drop between the collector electrode 28 and the emitter electrode 18 when the semiconductor device 1 is on.

[0050] Next, an OFF operation for switching the semiconductor device 1 from the ON state to the OFF state will be described. In this case, a low gate voltage Vgg1 is applied to the emitter-side gate electrode 17 as an OFF voltage, and a high gate voltage Vgg2 is applied to the collector-side gate electrode 27 as an ON voltage. As a result, the semiconductor device 1 is turned on by applying a low gate voltage Vgg1 to the emitter-side gate electrode 17 as an ON voltage. -The inversion layer (n-channel) La formed in layer 11 is no longer formed, and a non-conductive state is established between emitter n-layer 12 and drift layer 10. As a result, in semiconductor device 1, the disappearance of the inversion layer during off operation stops the injection of electrons from emitter n-layer 12 to drift layer 10. Note that the on-voltage applied to collector-side gate electrode 27 may be a positive voltage with respect to collector electrode 28.

[0051] 3, in the semiconductor device 1, when a high gate voltage Vgg2 is applied to the collector-side gate electrode 27 during the off-operation, the collector p - An inversion layer Lb is formed in the layer 23a. The buffer layer 29 and the collector p-layer 23 have the same potential via this inversion layer Lb, and injection of holes from the collector p-layer 23 to the drift layer 10 is stopped around the collector-side gate electrode 27b.

[0052] The electrons stored in the drift layer 10 are discharged from the buffer layer 29 to the collector n layer 22 via the inversion layer Lb, and then from the collector n layer 22 to the collector electrode 28. In addition, the holes in the drift layer 10 are discharged to the emitter p - The electrons are discharged to the emitter electrode 18 via the emitter p layer 11 and the emitter p layer 13. - The pn junction between the layer 11 and the drift layer 10 becomes a depletion layer, and the semiconductor device 1 enters an off state.

[0053] In this way, when the semiconductor device 1 is turned on, the emitter p - The inversion layer La formed in the layer 11 is connected to the emitter p - The collector p - The inversion layer Lb formed in the layer 23a is connected to the collector p - It is formed in layer 23a.

[0054] In the first embodiment, in one element region R0 that forms a repeated pattern, the sum of the first opposing region lengths of the emitter-side opposing regions Ja1 to Ja8 is configured to be longer than the sum of the second opposing region lengths of the collector-side opposing regions Jb1 and Jb2. Therefore, in the semiconductor device 1, in the element region R0, the sum of the lengths in the gate width direction of the inversion layers La formed along the emitter-side opposing regions Ja during on-operation is set to be longer than the sum of the lengths of the collector p - It can be made longer than the total length in the gate width direction of the inversion layer Lb formed along the collector-side facing region Jb in the layer 23a.

[0055] In the semiconductor device 1, the total length of the first opposing regions of the emitter-side opposing regions Ja is set to be longer than the total length of the second opposing regions of the collector-side opposing regions Jb in the element region R0 (i.e., the value of Ja in the gate density ratio Ja:Jb is set to be larger than the value of Jb). - The total length of the inversion layer La in the layer 11 in the gate width direction is defined as the collector p - The length is made longer than the total length in the gate width direction of the inversion layers Lb in the layer 23a, and as a result, the conduction loss is suppressed while the switching loss at turn-off is reduced.

[0056] (Simulation results) Next, in the semiconductor device 1 described above, the relationship between conduction loss and switching loss when the gate density ratio Ja:Jb is changed was investigated by simulation. Here, FIGS. 4(a) and 4(b) show the evaluation circuit used in the simulation. The evaluation circuit shown in FIG. 4(a) is a comparative example, and shows the circuit configuration of a single-sided IGBT in which an emitter-side gate electrode 17 is provided but a collector-side gate electrode 27 is not provided. The evaluation circuit shown in FIG. 4(b) shows the circuit configuration of the semiconductor device 1 according to the first embodiment.

[0057] In the evaluation circuit of the comparative example shown in FIG. 4(a), a load inductance L and a diode FWD1 (Free Wheeling Diode) are connected in parallel, and the IGBT section T r1and diode FWD2 are connected in parallel. FWD1 and FWD2 are connected in parallel to the IGBT section T r1 This device returns the energy stored in the inductance L to the power supply Vdc side when the power supply is turned off. The power supply Vdc is connected to one end of the inductance L and the diode FWD1.

[0058] IGBT part T r1 has a gate terminal G corresponding to the emitter-side gate electrode 17, a collector terminal C corresponding to the collector electrode 28, and an emitter terminal E corresponding to the emitter electrode 18, and a pulse voltage for turning the gate on or off is a gate voltage Vgg1, and a resistor R g The voltage Vce is applied to the gate terminal G via the collector terminal C. The collector terminal C is connected to the other end of the inductance L and the diode FWD1, and also to one end of the diode FWD1. The emitter terminal E is connected to the other end of the diode FWD2 and to the ground. Note that Vce denotes the voltage between the emitter terminal E and the collector terminal C.

[0059] The evaluation circuit shown in Fig. 4(b) is the same as the evaluation circuit shown in Fig. 4(a) and the IGBT part T r2 The other components are the same as the evaluation circuit in Figure 4(a), so the explanation is omitted. r2 The emitter-side gate terminal G1 corresponds to the emitter-side gate electrode 17, and the collector-side gate terminal G2 corresponds to the collector-side gate electrode 27. The collector-side gate terminal G2 is connected to the collector terminal C via a resistor Rg or the like. In the simulation, the resistor R g1 Applying the gate voltage Vgg1 to the emitter side gate terminal G1 via the resistor R g2 The gate voltage Vgg2 was applied to the collector-side gate terminal G2 via the gate electrode .

[0060] In the evaluation circuit shown in Fig. 4(b), we conducted simulations to investigate the relationship between conduction loss and switching loss when the gate density ratio Ja:Jb was 1:1, 2:1, 4:1, and 8:1, and obtained the results shown in Fig. 5(a) and Fig. 5(b).

[0061] 5(a) and 5(b) are diagrams illustrating the influence of the gate density ratio between the emitter side and the collector side on the semiconductor device 1. FIG. 5(a) is a diagram illustrating the results of a simulation investigating the relationship between the gate density ratio Ja:Jb and switching loss. The horizontal axis of FIG. 5(a) represents the gate density ratio, and the vertical axis represents the minimum value (mJ) of switching loss in FIG. 6. Switching loss is the energy consumed in one switching operation, and decreases as the time during which voltage is applied to the semiconductor device 1 and current flows due to abrupt switching is shortened. Reducing switching loss allows for an increase in switching frequency.

[0062] Figure 5(b) shows the results of a simulation that investigated the relationship between the gate density ratio Ja:Jb and the on-state voltage drop. The horizontal axis of Figure 5(b) represents the gate density ratio, and the vertical axis represents the on-state voltage drop (V). The on-state voltage drop is a physical quantity related to the conduction loss of an IGBT, and a smaller on-state voltage drop indicates a smaller conduction loss.

[0063] 5(a) and 5(b) show the simulation results for the evaluation circuit of FIG. 4(a) which has gate electrodes on only one side of the substrate 5. Also, D shown in FIGS. 5(a) and 5(b) shows the simulation results for the evaluation circuit of FIG. 4(b) which has gate electrodes on both sides of the substrate 5.

[0064] 5(a), in the comparative example, the switching loss was approximately 185 mJ. On the other hand, as shown by the solid line D, in the evaluation circuit showing the semiconductor device 1 of the first embodiment, the switching loss was approximately 27 mJ when the gate density ratio was 1:1, and the switching loss was approximately 30 mJ when the gate density ratio was 2:1.

[0065] Then, further, when the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb was increased by changing the parameters of the evaluation circuit shown in FIG. 4(b), the switching loss increased. When the gate density ratio was 4:1, the switching loss was about 68 mJ, and when the gate density ratio was 8:1, the switching loss was about 122 mJ. From the results shown in FIG. 5(a), it was confirmed that in the evaluation circuit showing the semiconductor device 1 according to the first embodiment, the switching loss was smaller than that of the comparative example regardless of the gate density ratio.

[0066] However, it was confirmed that the switching loss gradually increased as the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb was increased. Therefore, in order to reduce the switching loss, it was confirmed that it was desirable to reduce the total length of the gate width direction of the emitter-side gate electrode 17 of the evaluation circuit, that is, to reduce the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb.

[0067] The above characteristics are considered to be due to the fact that reducing the value of Ja in the gate density ratio Ja:Jb, that is, shortening the total length of the gate width direction of the emitter-side opposing region Ja, or in other words, relatively increasing the total length of the gate width direction of the collector-side opposing region Jb enhances the effect of discharging electrons from the drift layer 10, and the loss decreases as the switching speed increases.

[0068] Also, as shown in FIG. 5(b), the on-voltage drop of the comparative example was about 1.66 V. On the other hand, in the evaluation circuit showing the semiconductor device 1 of the first embodiment, the on-voltage drop was about 2.06 V when the gate density ratio was 1:1, and the on-voltage drop when the gate density ratio was 2:1 was about 1.86 V.

[0069] Furthermore, when the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb of the evaluation circuit shown in FIG. 4(b) was increased by changing the parameters of the evaluation circuit, the on-voltage drop decreased. When the gate density ratio was 4:1, the on-voltage drop was approximately 1.77 V, and when the gate density ratio was 8:1, the on-voltage drop was approximately 1.72 V. From the results shown in FIG. 5(b), it was confirmed that the evaluation circuit showing the semiconductor device 1 according to the first embodiment had a larger on-voltage drop than the comparative example regardless of the gate density ratio.

[0070] It was also confirmed that the on-voltage drop gradually increased as the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb of the emitter side of the evaluation circuit was decreased. Therefore, it was confirmed that in order to reduce the on-voltage drop, it was desirable to increase the value of the emitter-side opposing region Ja in the gate density ratio Ja:Jb.

[0071] It is considered that the above characteristics are caused by reducing the value of the collector-side opposing region Jb with respect to the emitter-side opposing region Ja in the gate density ratio Ja:Jb, that is, relatively increasing the ratio of the region of the collector p-layer 23 that contributes to hole emission. When the value of Jb in the gate density ratio Ja:Jb, that is, the total length in the gate width direction of the collector-side opposing region Jb increases, the hole injection area on the collector side decreases, and the resistance of the drift layer 10 increases.

[0072] From the above simulation results, it was confirmed that there is a trade-off relationship between reducing conduction loss and reducing switching loss. And it was confirmed that there is a condition that by increasing the ratio of the emitter-side opposing region Ja to the collector-side opposing region Jb in the gate density ratio Ja:Jb, the switching loss at turn-off can be reduced while suppressing the conduction loss.

[0073] Specifically, from the above simulation results, it was confirmed that in order to reduce switching losses at turn-off while suppressing conduction losses during on-off operation of the semiconductor device 1, it is desirable to set the gate density ratio Ja:Jb to be greater than 1:1 to less than 8:1, preferably in the range of 2:1 to 7:1, and more preferably in the range of 3:1 to 5:1.

[0074] Next, we conducted a simulation to investigate the switching loss when the gate density ratio Ja:Jb was changed in the evaluation circuit of the semiconductor device 1 shown in Figure 4(b) and the timing of applying an off-voltage to the emitter-side gate terminal G1 and the timing of applying an on-voltage to the collector-side gate terminal G2 were shifted when switching the evaluation circuit of the semiconductor device 1 from the on state to the off state. As a result, the simulation results shown in Figure 6 were obtained.

[0075] The vertical axis in Figure 6 represents switching loss (mJ), and the horizontal axis represents collector-side gate-on timing (μs). The collector-side gate-on timing represents the timing at which an on-voltage is applied to the collector-side gate terminal G2 relative to the timing at which an off-voltage is applied to the emitter-side gate terminal G1. A negative value on the horizontal axis indicates that the timing at which an on-voltage is applied to the collector-side gate terminal G2 is earlier than the timing at which an off-voltage is applied to the emitter-side gate terminal G1. A positive value on the horizontal axis indicates that the timing at which an on-voltage is applied to the collector-side gate terminal G2 is later than the timing at which an off-voltage is applied to the emitter-side gate terminal G1.

[0076] 6, it was confirmed that when the gate density ratio Ja:Jb is 1:1 and 2:1, if the timing of applying the on-voltage to the collector-side gate terminal G2 is earlier than the timing of applying the off-voltage to the emitter-side gate terminal G1, the switching loss increases rapidly. This phenomenon is thought to occur because the application of the on-voltage to the collector-side gate terminal G2 causes a rapid decrease in carriers in the drift layer 10, causing the semiconductor device 1 to operate in a high-resistance state.

[0077] On the other hand, when the gate density ratio Ja:Jb is 4:1 or 8:1, it was confirmed that no sudden switching loss occurs even if the timing of applying the turn-on voltage to the collector-side gate terminal G2 is earlier than the timing of applying the turn-off voltage to the emitter-side gate terminal G1. The reason for this is thought to be that when the total length of the collector-side facing region Jb in the gate width direction is shorter than the total length of the emitter-side facing region Ja in the gate width direction, the hole injection suppression effect sufficient to stop the conductivity modulation cannot be obtained, and even if the gate voltage Vgg2 is turned on earlier than the gate voltage Vgg1, the hole injection into the drift layer 10 does not stop completely, making it possible to avoid an extreme increase in the resistance of the drift layer 10 and causing large switching loss.

[0078] From the above simulation results, it was confirmed that by setting the gate density ratio Ja:Jb to greater than 2:1, it is possible to suppress the occurrence of sudden switching loss even if the timing of applying the on-voltage to the collector-side gate electrode 27 (collector-side gate terminal G2) differs from the timing of applying the off-voltage to the emitter-side gate electrode 17 (emitter-side gate terminal G1).

[0079] (Manufacturing method) Next, a method for manufacturing the semiconductor device 1 of the first embodiment will be described. 7A(a) to 7A(c), 7B(d) and 7B(e) are diagrams for explaining an example of a manufacturing method for manufacturing the semiconductor device 1 of the first embodiment. In the first embodiment, impurities are implanted into a bare substrate made of single crystal silicon to form a substrate having a drift layer 10, and impurities are sequentially implanted into this to form the substrate 5 (FIG. 7B(d)). Of the impurity layers shown in FIG. 7A(a), the emitter p - The layer 11 is a relatively lightly doped p - The emitter n layer 12 is an emitter p - Relatively high concentration of n for layer 11 + The emitter p layer 13 is an emitter p - Relatively high concentration of p for layer 11 + The buffer layer 29 is a high-concentration n-layer relative to the drift layer 10. - The formation of layer 11, emitter n-layer 12, emitter p-layer 13, collector p-layer 23 and buffer layer 29 can be performed by, for example, ion implantation.

[0080] Next, in the first embodiment, as shown in FIG. 7A(b), the emitter n layer 12 on the first surface fa is - A trench hole 14 is formed through the layer 11 to reach the drift layer 10. The trench hole 14 can be formed by photolithography. Next, a gate insulating film 15 is formed on the inner surface of the trench hole 14. The gate insulating film 15 is formed by forming an insulating film over the entire surface of the wafer in the state shown in FIG. 7A(b). Next, in the first embodiment, as shown in FIG. 7A(c), polysilicon is filled into the trench hole 14 from above the gate insulating film 15, and an emitter-side gate electrode 17 is formed in the trench hole 14.

[0081] 7B(d), in the first embodiment, a layered gate insulating film 25 is formed on the back surface of the buffer layer 29, and then polysilicon is deposited and etched together with the gate insulating film 25 by photolithography to form a planar collector-side gate electrode 27 on the back surface of the buffer layer 29 via the gate insulating film 25. Then, using the collector-side gate electrode 27 as a mask, a p-type impurity layer is implanted into the back surface of the buffer layer 29, forming a collector p - The collector p-layer 23 having the layer 23a is formed by, for example, ion implantation. Furthermore, n-type impurities are implanted into the collector p-layer 23 at a high concentration, and the collector p-layer 23 around the collector-side gate electrode 27 is doped with n-type impurities. - A collector n-layer 22 is formed on the layer 23a. Through the above steps, the substrate 5 is completed.

[0082] 7B(e), an interlayer insulating layer 16 is formed on the emitter-side gate electrode 17, a contact hole is formed by photolithography, and a metal is deposited on the first surface fa of the substrate 5 to form the emitter electrode 18. Similarly, an interlayer insulating layer 26 is formed around the collector-side gate electrode 27, a contact hole is formed by photolithography, and a metal is deposited on the second surface fb of the substrate 5 to form the collector electrode 28.

[0083] In this way, the semiconductor device 1 of the first embodiment can be manufactured. However, the semiconductor device 1 is not manufactured only by the method described above. The method and conditions of the manufacturing process are appropriately selected depending on the design and required conditions of the semiconductor device 1.

[0084] [Variations] Next, a modification of the first embodiment described above will be described. (First Modification) Fig. 8 is a cross-sectional view showing the configuration of a semiconductor device 2 of a first modified example. Fig. 9(a) is a cross-sectional view of the cross-section of the semiconductor device 2 shown in Fig. 8 taken along line IXa-IXa, viewed from above downward. Fig. 9(b) is a cross-sectional view of the cross-section of the semiconductor device 2 taken along line IXb-IXb, viewed from below upward. Fig. 8 shows a cross-sectional side view of the semiconductor device 2 taken along line VIII-VIII in Fig. 9(a), in a configuration in which the emitter electrode 18, the collector electrode 28, etc. are provided as shown in Figs. 9(a) and 9(b).

[0085] In the semiconductor device 2, five trench holes 14 are formed in the element region R0, and dummy gate electrodes 17a are formed in the trench holes 14a at the rightmost and leftmost ends in FIG. 8 with gate insulating films 15 interposed therebetween, and emitter-side gate electrodes 17 are formed in the remaining three central trench holes 14 with gate insulating films 15 interposed therebetween, and it is preferable that the dummy gate electrodes 17a are short-circuited to the emitter layer 11.

[0086] In the first modification, the emitter n layer 12 and the emitter p layer 13 are formed on the first surface fa between the three central emitter-side gate electrodes 17, and the emitter p layer 13 is not formed on the first surface fa between the dummy gate electrode 17a and the emitter-side gate electrode 17. - The layer 11 is covered with an interlayer insulating layer 16. L3 indicates the length of each interlayer insulating layer 16 in the X direction.

[0087] As shown in FIGS. 8 and 9(a), in the element region R0 on the first surface fa side of the semiconductor device 2, an emitter-side gate electrode 17 is connected to an emitter p - In the emitter-side facing region Ja facing the layer 11, the emitter p - As the emitter-side facing regions Ja in which an inversion layer is formed in the layer 11, four emitter-side facing regions Ja11 to Ja14 are provided.

[0088] Note that, since the emitter n layer 12 is not formed on the first surface fa of the substrate 5, electrons are not injected into the inversion layer formed in the emitter-side facing region Ja10 of the emitter-side gate electrode 17 facing the dummy gate electrode 17a. Hereinafter, the emitter-side facing region Ja refers to the emitter-side facing regions Ja11 to Ja14 in which an inversion layer is formed and which is connected to the emitter electrode via the emitter n layer 12. In other words, the first facing region in the first embodiment does not include a region that does not have the emitter n layer 12 for electrical connection to the emitter electrode 18.

[0089] Here, if the length of the emitter-side facing region Ja in the Y direction is W, the total length of the first facing regions of the four emitter-side facing regions Ja11 to Ja14 in one element region R0 forming a repeated pattern is 4·W.

[0090] As another embodiment of the first modification, only three emitter-side gate electrodes 17 may be formed in the element region R0 without forming the dummy gate electrodes 17a, but this may cause variations in the etching rate and selectivity between the center and periphery of the element region R0 due to the microloading effect. In order to suppress such variations, the first modification also forms dummy gate electrodes 17a that do not contribute to the formation of an inversion layer, thereby making the density of the dummy gate electrodes 17a and the emitter-side gate electrodes 17 uniform in the element region R0.

[0091] The semiconductor device 2 according to the first modified example can be realized by changing the mask used when implanting the impurity layers that become the emitter n-layer 12 and the emitter p-layer 13 and the mask used when forming the contact holes.

[0092] The semiconductor device 2 according to the first modification is different from the first embodiment in that a trench-type collector-side gate electrode 27 is provided on the second surface fb of the substrate 5. In this case, the element region R0 includes a collector n layer 22 and a collector p layer 23 extending from the second surface fb. -A single trench hole 14b is formed in the semiconductor layer 23a, penetrating the layer 23a and the buffer layer 29 to reach the drift layer 10. A trench-type collector-side gate electrode 27 is provided in the trench hole 14b via a gate insulating film 25. However, the collector-side gate electrode 27 does not have to penetrate the buffer layer 29.

[0093] The semiconductor device 2 has a collector p layer between the collector p layer 23 and the buffer layer 29. - 9B, a gate insulating film 25 is formed along two longitudinal sides of the strip-shaped collector-side gate electrode 27, and the collector n-layer 22 is formed on the opposite side of the gate insulating film 25 that is not adjacent to the collector-side gate electrode 27.

[0094] An interlayer insulating layer 26 is provided below the collector-side gate electrode 27. A collector electrode 28 is provided on the collector n-layer 22, the collector p-layer 23, and the interlayer insulating layer 26, which are arranged on the second surface fb of the substrate 5.

[0095] The trench-type collector-side gate electrode 27 is advantageous in increasing the area of the collector p layer 23 into which holes are injected. - By lengthening the layer 23a in the Z direction perpendicular to the second surface fb, the size of the inversion layer formed in the collector p layer 23 can be determined, thereby increasing the degree of freedom in designing the collector-side facing region Jb, which can specify the size of the inversion layer related to the emission of electrons.

[0096] Here, if the length of the collector-side facing region Jb in the Y direction (second facing region length) is W, the total second facing region length of the two collector-side facing regions Jb10 and Ja11 in one element region R0 that forms a repeated pattern is defined as 2·W.

[0097] In the semiconductor device 2 of the first variant, when the total length of the second opposing region in the element region R0 is set to 1, the ratio (gate density ratio) Ja:Jb of the total length of the first opposing region to the total length of the second opposing region in the element region R0 is described as 2:1.

[0098] In the above configuration, in the semiconductor device 2 according to the first modification, as in the first embodiment described above, the total length of the first opposing regions is made longer than the total length of the second opposing regions in the element region R0, so that the emitter p - The total length of the inversion layers in the layer 11 in the gate width direction is - The length is longer than the total length of the inversion layers in the layer 23a in the gate width direction, and as a result, it is possible to reduce the switching loss at turn-off while suppressing the loss during conduction.

[0099] (Second Modification) Fig. 10 is a cross-sectional view illustrating the configuration of a semiconductor device 3 according to a second modification. Fig. 11(a) is a cross-sectional view of the cross-section of the semiconductor device 3 taken along line XIa-XIa in Fig. 10, viewed from above. Fig. 11(b) is a cross-sectional view of the cross-section of the semiconductor device 3 taken along line XIb-XIb, viewed from below. Fig. 10 shows a cross-sectional side view of the semiconductor device 3 taken along line XX in Fig. 11(a), in a configuration in which the emitter electrode 18, the collector electrode 28, etc. are provided as shown in Figs. 11(a) and 11(b).

[0100] The semiconductor device 3 has five emitter-side gate electrodes 17 on the first surface fa. The five emitter-side gate electrodes 17 form a total of ten emitter-side facing regions. However, the element region R0 of the semiconductor device 3 does not include the emitter-side facing regions Ja0, Ja0 of the emitter-side gate electrodes 17 located at the rightmost and leftmost ends in FIG. 10, so there are eight emitter-side facing regions Ja21 to Ja28 in the element region R0. If the length of the emitter-side facing region Ja in the Y direction is W, then the total first facing region length of the eight emitter-side facing regions Ja21 to Ja28 in one element region R0 forming a repeated pattern is 8·W.

[0101] 10 and 11(b), collector-side facing regions Jb21 and Jb22 are formed in the collector-side gate electrode 27 on the second face fb of the semiconductor device 3. Therefore, the total length of the second facing regions of the two collector-side facing regions Jb21 and Jb22 in one element region R0 is 2·W.

[0102] In the semiconductor device 3 of the second variant, when the sum of the second opposing region lengths of the collector-side opposing regions Jb in the element region R0 is set to 1, the ratio (gate density ratio) Ja:Jb between the sum of the first opposing region lengths of the emitter-side opposing regions Ja in the element region R0 and the sum of the second opposing region lengths of the collector-side opposing regions Jb is described as 4:1.

[0103] The semiconductor device 3 has a trench-type collector-side gate electrode 27 on the second face fb, similar to the semiconductor device 2. However, the semiconductor device 3 has a collector p - The semiconductor device 3 differs from the semiconductor device 2 in that a collector n layer 22 and a collector p layer 23a are formed on the second surface fb. - A single trench hole 14b is formed in the semiconductor layer 23a, penetrating the layer 23a and the buffer layer 29 to reach the drift layer 10. A trench-type collector-side gate electrode 27 is provided in the trench hole 14b via a gate insulating film 25. However, the collector-side gate electrode 27 does not have to penetrate the buffer layer 29.

[0104] 10, the semiconductor device 3 differs from the semiconductor devices 1 and 2 in that the emitter n-layers 12 and the emitter p-layers 13 are alternately formed in the direction of the gate width W (Y direction) of the emitter-side gate electrode 17. With this configuration, the patterns of the emitter n-layers 12 and the emitter p-layers 13 can be made wider, which makes it easier to manufacture the semiconductor device 3.

[0105] In the second modified example of the above configuration, similarly to the first embodiment, the total length of the emitter-side opposing region Ja in the gate width direction is made longer than the total length of the collector-side opposing region Jb in the gate width direction in the element region R0. - The total length of the inversion layers in the layer 11 in the gate width direction is - The length is longer than the total length of the inversion layers in the layer 23a in the gate width direction, and as a result, it is possible to reduce the switching loss at turn-off while suppressing the loss during conduction.

[0106] (others) The first embodiment is not limited to the configuration described above. In the first embodiment described above, the emitter-side gate electrode 17 is a trench-type gate electrode formed in a trench hole 14 formed in the first surface fa of the substrate 5. However, the present invention is not limited to this. The emitter-side gate electrode 17 may also be a planar-type gate electrode. A planar-type emitter-side gate electrode formed on the emitter side refers to a gate electrode disposed on the surface of the first surface fa via an insulating film that serves as a gate insulating film. Furthermore, in the first embodiment, the collector-side gate electrode 27 may be a planar-type gate electrode, or may be a trench-type collector-side gate electrode formed in a trench hole in the second surface fb. Furthermore, trench-type gate electrodes and planar-type gate electrodes may be formed together on the first surface fa and the second surface fb of the substrate 5.

[0107] Furthermore, while the configurations described above all include one collector-side gate electrode 27 in the element region R0, the first embodiment is not limited to a single collector-side gate electrode 27, and may include multiple collector-side gate electrodes 27 in the element region R0. The first embodiment is not limited to a configuration in which multiple emitter-side gate electrodes 17 are provided in the element region R0, and may include one emitter-side gate electrode 17 in the element region R0. The emitter-side gate electrode 17 and the collector-side gate electrode 27 are not limited to having the same length in the gate width direction (i.e., the Y direction), and may have different gate widths. The element region R0 does not necessarily have to be periodically and repeatedly formed throughout the entire element main region R1 (FIGS. 15(a) and 15(b)). The first embodiment may include other impurity layers or other elements as appropriate depending on the design and application of the semiconductor device.

[0108] Furthermore, the semiconductor device may have a configuration in which the configuration of the first embodiment, the configuration of the first modified example, the configuration of the second modified example, and the configuration of the third modified example are appropriately combined.

[0109] Furthermore, the semiconductor device 1 of the first embodiment, the semiconductor device 2 of the first modification, and the semiconductor device 3 of the second modification described above are not limited to those driven by the above-described operations. Below, modifications of the operations of the semiconductor devices 1 to 3 of the first embodiment (hereinafter referred to as "semiconductor device 1, etc.") will be described. 12(a) and 12(b) are diagrams showing the voltage Vce between the emitter electrode 18 and the collector electrode 28 and the collector current Ic flowing through the collector electrode 28 when the semiconductor device 1, etc. is turned on and when it is turned off, respectively. Fig. 12(a) shows the voltage Vce and the collector current Ic when the semiconductor device 1, etc. is turned on, and Fig. 12(b) shows the voltage Vce and the collector current Ic when the semiconductor device 1, etc. is turned off.

[0110] Fig. 12(c) is a diagram for explaining the voltages applied to the emitter-side gate electrode 17 and the collector-side gate electrode 27 at the time of turn-on shown in Fig. 12(a). Fig. 12(d) is a diagram for explaining the gate voltages applied to the emitter-side gate electrode 17 and the collector-side gate electrode 27 at the time of turn-off shown in Fig. 12(b). Figs. 12(c) and 12(d) are timing charts of what has been described as the operation of the semiconductor device 1 and the like described above.

[0111] In both Figures 12(a) and 12(b), the horizontal axis represents time, and the vertical axis represents voltage or current. In Figures 12(a) and 12(b), the solid lines represent voltage Vce, and the dashed lines represent collector current Ic. In both Figures 12(c) and 12(d), the horizontal axis represents time, and the vertical axis represents voltage. In Figures 12(c) and 12(d), the solid lines represent gate voltage Vgg1 applied to the emitter-side gate electrode 17, and the dashed lines represent gate voltage Vgg2 applied to the collector-side gate electrode 27.

[0112] As shown in FIG. 12(a), when turning on, the semiconductor device 1 or the like switches from the off state to the on state. At this time, as shown in FIG. 12(c), in the off state, a gate voltage Vgg2 is applied to the collector-side gate electrode 27, and a constant voltage Vce is applied between the emitter-side gate electrode 17 and the collector-side gate electrode 27. The gate voltage Vgg2 becomes 0 V at the timing Tsw of switching to the on state, and instead, a gate voltage Vgg1 is applied to the emitter-side gate electrode 17. At this time, the emitter-side gate electrode 17 turns on, causing the drift layer 10 to have a low resistance, and the voltage Vce begins to fall and reach a constant minimum value near 0 V. The collector current Ic reaches a constant maximum value when the semiconductor device 1 or the like is in the on state.

[0113] 12(b), when turning off, the semiconductor device 1 etc. switches from the on state to the off state. At this time, as shown in FIG. 12(d), in the on state, the gate voltage Vgg1 is applied to the emitter-side gate electrode 17, and the voltage Vce has a constant minimum value. The gate voltage Vgg1 becomes 0 V at the timing Tsw of switching to the off state, and instead, the gate voltage Vgg2 is applied to the collector-side gate electrode 27. At this time, the drift layer 10 becomes highly resistive as the collector-side gate electrode 27 turns on, and the voltage Vce starts to rise and reaches a constant maximum value.

[0114] Next, we will explain the operation of applying gate voltages to the emitter-side gate electrode 17 and the collector-side gate electrode 27, which are different from those shown in Figures 12(c) and 12(d). Figures 13(a), 13(b), and 13(c) are all diagrams for explaining the gate voltage Vgg1 applied to the emitter-side gate electrode 17 and the gate voltage Vgg2 applied to the collector-side gate electrode 27 during turn-on. In all of Figures 13(a) to 13(c), the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 at the same timing as the gate voltage Vgg1 shown in Figure 12(c). Figure 13(a) is a diagram showing an example of operation in which the gate voltage Vgg2 of the collector-side gate electrode 27 is 0 V (zero bias) when the semiconductor device 1 is off. In this case, the semiconductor device 1 operates similarly to a single-type IGBT without a collector-side gate electrode 27.

[0115] However, when a gate voltage is applied to the semiconductor device 1 provided with the collector-side gate electrode 27 together with the emitter-side gate electrode 17 as shown in FIG. 13(a), the collector p - This reduces the area of the layer 23. Therefore, when the gate voltages Vgg1 and Vgg2 shown in Fig. 13(a) are applied to the semiconductor device 1 or the like, there is a risk that the conduction loss will be larger than that of a single-type IGBT.

[0116] 13(b) is a diagram showing an example of an operation in which the collector-side gate electrode 27 is set to 0 bias when the semiconductor device 1 is turned off, and a negative gate voltage Vgg2 is applied to the collector-side gate electrode 27 when the semiconductor device 1 is turned on. - The layer 23a contributes to the injection of holes into the drift layer 10, and the conduction loss of the semiconductor device 1 and the like can be reduced.

[0117] 13(c) shows an example of an operation in which the collector-side gate electrode 27 is set to 0 bias when the semiconductor device 1 is turned off, and a negative gate voltage Vgg2 is applied to the collector-side gate electrode 27 earlier than in the example shown in FIG. 13(b) when the semiconductor device 1 is turned on. According to this operation, the collector p - By increasing the number of holes injected from the layer 23a into the drift layer 10, the conduction loss of the semiconductor device 1 etc. can be further reduced.

[0118] 14(a), 14(b), 14(c), and 14(d) are diagrams illustrating the gate voltage Vgg1 applied to the emitter-side gate electrode 17 and the gate voltage Vgg2 applied to the collector-side gate electrode 27 during turn-off. FIG. 14(a) illustrates an example of an operation in which a positive gate voltage Vgg2 is applied to the collector-side gate electrode 27 before the timing at which the gate voltage Vgg1 falls during turn-off of the semiconductor device 1, etc. In the example illustrated in FIG. 14(a), the gate voltage Vgg1 is applied to the emitter-side gate electrode 17 at the same timing as the gate voltage Vgg1 illustrated in FIG. 12(d). This operation suppresses injection of holes from the collector p-layer 23 into the drift layer 10 before the semiconductor device 1, etc. is turned off, shortening the time from when the gate voltage Vgg1 is turned off until the collector current Ic reaches its minimum value, i.e., reducing switching loss.

[0119] 14(b) is a diagram showing an example of an operation in which the gate voltage Vgg1 applied to the emitter-side gate electrode 17 switches from positive to negative when the semiconductor device 1 or the like is turned off. In the example shown in FIG. 14(b), the gate voltage Vgg2 applied to the collector-side gate electrode 27 is applied to the collector-side gate electrode 27 at the same timing as the gate voltage Vgg2 shown in FIG. 12(d). This operation causes the inversion layer La formed in the emitter-side facing region Ja of the collector-side gate electrode 27 to disappear early, and it is possible to quickly suppress the injection of electrons into the drift layer 10 when the semiconductor device 1 or the like is turned off. Therefore, the example of the operation shown in FIG. 14(b) can reduce the switching loss of the semiconductor device 1 or the like.

[0120] FIG. 14(c) shows an example of an operation in which, when the semiconductor device 1 or the like is turned off, the gate voltage Vgg1 applied to the emitter-side gate electrode 17 falls to 0 V or a negative voltage (a negative voltage in the example shown in FIG. 14(c)), and a positive gate voltage Vgg2 is applied to the collector-side gate electrode 27 while the positive gate voltage Vgg1 is being applied. That is, the positive gate voltage Vgg1 is applied to the emitter-side gate electrode 17 at the timing when the semiconductor device 1 is turned on. The positive gate voltage Vgg2 rises after the application of the gate voltage Vgg1 begins and falls to 0 V at the timing before the gate voltage Vgg1 falls (turns off). This operation can prevent holes from being injected into the drift layer 10 before the semiconductor device 1 or the like is turned off.

[0121] 14(c), if a negative gate voltage Vgg1 is applied to the emitter-side gate electrode 17 after the semiconductor device 1 is turned off, the holes accumulated in the drift layer 10 are extracted to the emitter electrode 18, and the amount of holes in the drift layer 10 can be reduced in a short time. This type of operation shown in FIG. 14(c) can achieve a significant reduction in switching loss. The operation example shown in FIG. 14(c) includes three states: a state in which the emitter n layer 12 and the drift layer are conductive and the collector n layer 22 and the drift layer are non-conductive; a state in which both the emitter n layer 12 and the drift layer and the collector n layer 22 and the drift layer are conductive; and a state in which both the emitter n layer 12 and the drift layer and the collector n layer 22 and the drift layer are non-conductive.

[0122] 14(d) is a diagram showing an example of an operation in which, when the semiconductor device 1, etc. is turned off, the gate voltage Vgg1 falls to 0 V or a negative voltage, and then a positive gate voltage Vgg2 is applied to the collector-side gate electrode 27. This operation allows a portion of the reflux current generated in the turn-on / turn-off loop of the semiconductor device 1, etc., to flow from the emitter electrode 18 to the collector electrode 28 during the off state, thereby supporting the reflux operation.

[0123] [Second embodiment] Next, a second embodiment of the present invention will be described. Figures 15(a) and 15(b) illustrate a semiconductor device 6 of the second embodiment. Figure 15(a) is a schematic diagram showing the top surface configuration of a semiconductor chip 60 on which the semiconductor device 6 is formed, as viewed from above, and Figure 15(b) is a schematic diagram showing the bottom surface configuration of the semiconductor chip 60 on which the semiconductor device 6 is formed, as viewed from below.

[0124] 15(a), in the semiconductor device 6 according to the second embodiment, a main region R1 in which an emitter electrode 18 is formed and a peripheral region Re surrounding the periphery of the main region R1 are formed in a semiconductor chip 60. In addition, a field limiting ring (FLR) structure for alleviating the electric field in the lateral direction is formed in the peripheral region Re on one side on which the emitter electrode 18 is formed. FIG. 16 is a cross-sectional view showing a side cross-sectional configuration of a region R at the boundary between the main region R1 and the peripheral region Re in the cross section of the semiconductor chip 60 taken along line XV-XV in FIG. 15(a).

[0125] The main region R1 is a region where the above-mentioned element region R0 is formed in a repeated pattern, and for example, the emitter-side gate electrode 17, the emitter electrode 18, the collector-side gate electrode 27, and the collector electrode 28 shown in the above-mentioned first embodiment are repeatedly arranged at predetermined intervals. Note that the main region R1 is provided with the element region R0 of any of the semiconductor device 1 according to the first embodiment (FIG. 1), the semiconductor device 2 according to the first modification (FIG. 8), the semiconductor device 3 according to the second modification (FIG. 10), or the semiconductor device 4 according to the third modification.

[0126] Note that Figure 16 shows an example in which the element region R0 of the semiconductor device 1 according to the first embodiment (Figure 1) is provided, although the formation position of the collector-side gate electrode 27 is different from that of the element region R0 of the semiconductor device 1 according to the first embodiment, and therefore the description thereof will be omitted below to avoid duplication.

[0127] 15(a), in the peripheral region Re of the semiconductor device 6, for example, an emitter-side gate wiring 18a is provided so as to surround the emitter electrode 18. The emitter-side gate wiring 18a is electrically connected to each internal emitter-side gate electrode 17 by an emitter-side gate pad 18b, and applies the gate voltage to the emitter-side gate electrode 17. The peripheral region Re is a region in the main region R1 where the emitter electrodes 18 provided on the first surface fa of the substrate 5, the emitter-side gate electrodes 17 formed in the substrate 5, etc. are not formed on the upper surface side.

[0128] 15(b), a collector electrode 28 is provided in a main region R1 on the underside of the semiconductor chip 60, and the collector electrode 28 in the main region R1 extends to the peripheral region Re. That is, the formation area of the collector electrode 28 provided on the underside of the semiconductor chip 60 is larger than the formation area of the emitter electrode 18 provided on the upper surface of the semiconductor chip 60. The main region R1 shown in FIG. 15(a) is indicated by a two-dot chain line in the collector electrode 28 shown in FIG. 15(b).

[0129] In the peripheral region Re of the underside of the semiconductor chip 60, for example, a collector-side gate wiring 28a is provided so as to surround the collector electrode 28. The collector-side gate wiring 28a is electrically connected to each internal collector-side gate electrode 27 by a collector-side gate pad 28b, and applies a gate voltage to the collector-side gate electrode 27. Note that an electrode having the same potential as the collector electrode 28 may be further provided outside the collector-side gate wiring 28a on the other surface side on which the collector electrode 28 is provided.

[0130] 15(a) and 15(b) indicate the positions of one and the other opposing sides of the collector electrode 28, which is provided on the underside of the semiconductor chip 60 and has a substantially square shape in a bottom view. On the other hand, the line e2 shown in Fig. 15(a) indicates the positions of one and the other opposing sides of the emitter electrode 18, which is provided on the top surface of the semiconductor chip 60 and has a substantially square shape in a top view, i.e., the positions of one and the other sides of the main region R1.

[0131] The straight lines e1 along one side and the other side of the collector electrode 28 are both located outside the straight lines e2 along one side and the other side of the emitter electrode 18, and the collector electrode 28 formed in the main region R1 is extended to the peripheral region Re, and the collector electrode 28 is formed larger than the emitter electrode 18.

[0132] In the second embodiment, for example, the collector electrode 28 is formed larger by a difference Y1 between a straight line e1 along one side of the collector electrode 28 and a straight line e2 along one side of the emitter electrode 18. Here, each of the four sides of the collector electrode 28 is spaced apart from each of the four sides of the emitter electrode 18 by the difference Y1, and the collector electrode 28 is formed larger than the emitter electrode 18 overall.

[0133] In the second embodiment, the collector electrode 28 is formed to be larger than the emitter electrode 18 overall, but the present invention is not limited to this. At least one of the four sides of the collector electrode 28 may be spaced apart from the side of the emitter electrode 18 by a difference Y1, making the collector electrode 28 larger than the emitter electrode 18.

[0134] Next, a cross-sectional configuration of the peripheral region Re of the semiconductor device 6 according to the second embodiment will be described. As shown in Fig. 16, the peripheral region Re includes a substrate 5 provided in the main region R1, and the drift layer 10 of the substrate 5 extends from the substrate 5. The first surface fa of the substrate 5 in the peripheral region Re includes the emitter p formed in the main region R1. - The layer 11 extends over the drift layer 10. - A layer 11 is provided.

[0135] Unlike the main region R1, the peripheral region Re does not have an emitter-side gate electrode 17 provided on the first surface fa of the substrate 5, and instead has a p-type impurity layer 131 having a polarity different from that of the drift layer 10. - An insulating film 132 is formed on the first surface fa of the substrate 5 on which the layer 11 and the p-type impurity layer 131 are formed. An emitter-side gate wiring 18a is arranged at a predetermined position of the insulating film 132 formed on the p-type impurity layer 131.

[0136] On the other hand, the second surface fb of the substrate 5 in the peripheral region Re has the same configuration as the second surface fb of the substrate 5 in the main region R1, and includes the buffer layer 29, the collector p layer 23, the collector p -The second embodiment includes a collector n layer 23a, a collector n layer 22, and a collector-side gate electrode 27. In the second embodiment, a plurality of collector-side gate electrodes 27 are provided in the peripheral region Re, but the collector-side gate electrodes 27 and their surroundings all have the same configuration.

[0137] In this case, the second surface fb of the substrate 5 in the peripheral region Re has the same configuration as the second surface fb of the substrate of the semiconductor device 1 according to the first embodiment described above. Specifically, the buffer layer 29 and the collector p layer 23 provided in the main region R1 are extended to the peripheral region Re, and the collector n layer 22 and the collector p layer 23 are provided in the collector p layer 23. - A layer 23a is formed.

[0138] A part of the buffer layer 29 is exposed on the second surface fb of the substrate, and collector p - The collector p - The collector n layer 22 is formed at the boundary between the layer 23a and the collector p layer 23, and the buffer layer 29 and the collector p layer 23 are exposed on the second surface fb of the substrate. - A collector-side gate electrode 27 is provided below the layer 23a via a gate insulating film 25. An interlayer insulating layer 26 is provided around the collector-side gate electrode 27.

[0139] On the second surface fb of the substrate, an interlayer insulating layer 26 and a collector electrode 28 are disposed below the collector n layer 22 exposed on the second surface fb. The collector electrode 28 in the peripheral region Re is provided on the second surface fb so as to cover the second surface fb of the substrate and the interlayer insulating layer 26, similar to the collector electrode 28 in the main region R1.

[0140] In the above configuration, the semiconductor device 6 according to the second embodiment includes a main region R1 having an element region R0 and a peripheral region Re adjacent to the main region R1. The peripheral region Re does not include the emitter-side gate electrode 17 formed in the main region R1, but includes the buffer layer 29, the collector p layer 23, and the collector p -A layer 23a, a collector n-layer 22, a collector-side gate electrode 27, and a collector electrode 28 are formed.

[0141] As a result, in the semiconductor device 6 according to the second embodiment, during on-operation, a forward bias is applied between the collector p layer 23 and the buffer layer 29 by a positive voltage not only in the main region R1 but also in the peripheral region Re, and holes can be injected into the drift layer 10. At this time, in the semiconductor device 6, holes can be injected into the drift layer 10 not only from the main region R1 but also from the peripheral region Re, so that even more holes can be injected into the drift layer 10 than in a configuration in which holes are injected into the drift layer 10 only from the main region R1.

[0142] It is preferable that the difference Y1 between the side of the collector electrode 28 and the side of the emitter electrode 18 is equal to or greater than the thickness of the substrate 5. The reason for this is that the conductivity modulation region formed by the collector electrode 27 extends from the end of the emitter electrode 18 in the direction of the substrate surface by approximately the thickness of the substrate 5, and therefore it is desirable to provide the collector electrode 27 on the second surface fb within the range where the conductivity modulation region extends in order to prevent an increase in conduction loss.

[0143] Furthermore, according to the second embodiment, when the semiconductor device 6 is turned off, the injection of holes from the peripheral region Re into the drift layer of the main region R1 can be efficiently stopped, thereby reducing switching loss.

[0144] In the above-described embodiment, the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is not limited to this, and the second conductivity type may be p-type and the first conductivity type may be n-type.

[0145] In the above-described embodiment, the impurity layer is a collector p layer having a lower impurity concentration than the collector p layer 23. - Although the case where the collector p layer 23a is provided separately has been described, the present invention is not limited to this. For example, the collector p layer 23 and the collector p - The impurity concentration of the collector p layer 23a is not changed, and a part of the collector p layer 23 is simply- It may be the layer 23a (impurity layer). [Explanation of symbols]

[0146] 1, 2, 3, 4, 6 Semiconductor device (semiconductor device) 5. Substrate 10 Drift layer (drift layer) 11 Emitter p - Layer (emitter layer) 12 Emitter n-layer (first highly doped layer) 13 Emitter p-layer 14, 14a, 14b Trench holes 15 Gate insulating film (emitter-side gate insulating film) 17 Emitter side gate electrode 18 Emitter electrode (emitter electrode) 22 Collector n-layer (second highly doped layer) 23 Collector p layer (collector layer) 23a Collector P - layer (impurity layer) 25 Gate insulating film (collector-side gate insulating film) 27 Collector side gate electrode 28 Collector electrode (collector electrode) 29 Buffer Layer Ja Emitter-side facing area (first facing area) Jb Collector side facing area (second facing area) R0 element area R1 main area

Claims

1. an emitter layer of a first conductivity type; a collector layer of a first conductivity type; a drift layer of a second conductivity type provided between the emitter layer and the collector layer; an emitter electrode electrically connected to the emitter layer; a collector electrode electrically connected to the collector layer; one or more emitter-side gate electrodes arranged opposite to the emitter layer via an emitter-side gate insulating film; a first heavily doped layer of a second conductivity type provided between the emitter electrode and the emitter layer and having a higher impurity concentration than the emitter layer; an impurity layer of a first conductivity type provided between the drift layer and the collector electrode; one or more collector-side gate electrodes arranged opposite the impurity layer via a collector-side gate insulating film; a second high-concentration impurity layer of a second conductivity type provided between the collector electrode and the impurity layer and having an impurity concentration higher than that of the impurity layer, a total length in the gate width direction of a first opposing region of the emitter-side gate electrode, which is opposed to the emitter layer via the emitter-side gate insulating film, is longer than a total length in the gate width direction of a second opposing region of the collector-side gate electrode, which is opposed to the impurity layer via the collector-side gate insulating film.

2. an on state in which the first high-concentration impurity layer and the drift layer are electrically connected and the second high-concentration impurity layer and the drift layer are electrically disconnected; a state in which at least the second high-concentration impurity layer and the drift layer are electrically connected to each other; The semiconductor device according to claim 1 .

3. a total length of the first opposing regions in the gate width direction is equal to or greater than two times and less than eight times a total length of the second opposing regions in the gate width direction; 3. The semiconductor device according to claim 1.

4. a total length of the first opposing regions in the gate width direction is equal to or greater than four times and less than eight times a total length of the second opposing regions in the gate width direction; 3. The semiconductor device according to claim 1.

5. the emitter-side gate electrode is either a planar-type emitter-side gate electrode disposed on a surface of the emitter layer via an insulating film, or a trench-type emitter-side gate electrode formed in a trench hole in the emitter layer, the collector-side gate electrode is either a planar-type collector-side gate electrode disposed on a surface of the impurity layer, or a trench-type collector-side gate electrode formed in a trench hole of the impurity layer; The semiconductor device according to claim 1 .

6. a configuration of an element region in which the emitter-side gate electrodes and the collector-side gate electrodes are arranged at a predetermined interval in a predetermined direction is defined as one pattern, and the configuration of the element region is formed as a repeated pattern at a predetermined period in the predetermined direction, In one of the element regions, the total length of the first opposing regions in the gate width direction is longer than the total length of the second opposing regions in the gate width direction. The semiconductor device according to claim 1 .

7. a main region having the element region and a peripheral region adjacent to the main region, the emitter-side gate electrode formed in the main region is not formed in the peripheral region, and the collector layer, the collector electrode, the impurity layer, and the collector-side gate electrode are formed in the peripheral region. The semiconductor device according to claim 6.

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