Pulsed plasma deposition of thin film layers

Abstract

Examples of the technology herein include a semiconductor processing method, which may include generating a plasma from a deposition precursor within a processing region of a semiconductor processing chamber. The plasma may be generated at a supplied power during a first time period during which plasma power is supplied from the power supply operating at a first duty cycle. The method may further include transitioning the power supply from the first duty cycle to a second duty cycle after the first time period. From the generated plasma, a layer may be deposited on a substrate within the processing region of the semiconductor processing chamber. The layer, when deposited, may be characterized by a thickness of 50 Å or less. Exemplary deposition precursors may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 16 / 986,897, filed Aug. 6, 2020, entitled "PULSED-PLASMA DEPOSITION OF THIN FILM LAYERS," the entirety of which is incorporated herein by reference.

[0002] TECHNICAL FIELD

[0002] The technology herein relates to methods and systems for semiconductor processing. More particularly, the technology herein relates to systems and methods for fabricating thin films of semiconductor materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing material. As device sizes continue to shrink, the properties of films can have an increasing impact on device performance. The materials used to form layers of material can affect the operating characteristics of the fabricated devices. As material thicknesses continue to decrease, the properties of as-deposited films can have a greater impact on device performance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. The technology herein addresses this and other needs. Summary of the Invention

[0005]

[0005] Embodiments of the technology herein include a semiconductor processing method, which may include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma may be generated at a supplied power during a first time period during which plasma power is supplied from a power supply operating at a first duty cycle. The method may further include, after the first time period, transitioning the power supply from the first duty cycle to a second duty cycle. A layer may be deposited on a substrate from the generated plasma in the processing region of the semiconductor processing chamber. The layer, when deposited, may be characterized by a thickness of 50 Å or less.

[0006] In an exemplary embodiment, the plasma power used to generate the plasma for depositing a layer on the substrate may have an effective power of about 4 Watts or less. The first period during which the plasma power is activated at the first duty cycle may be about 2 seconds or less. There may be a second period during which the plasma power is maintained at a second duty cycle, which may be longer than the first period during which the plasma power is activated at the first duty cycle. An exemplary embodiment includes the first duty cycle being 20% or more and the second duty cycle being 5% or less. An exemplary deposition precursor may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include one or more silicon-containing layers.

[0007] An additional embodiment of a semiconductor processing method can include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma can be generated at a supplied power during a first period of time during which plasma power is supplied from a power supply operating at a first peak power level. The method can further include transitioning the power supply from the first peak power level to a second peak power level after the first period of time. A layer can be deposited on a substrate from the generated plasma in the processing region of the semiconductor processing chamber. The layer, when deposited, can be characterized by a thickness of 50 Å or less.

[0008] In an exemplary embodiment, the first peak power level provided by the power source may be about 60 Watts or less. The plasma power may be provided at a pulsed plasma frequency of about 10 kHz or less and may have an effective power of about 4 Watts or less. An exemplary deposition precursor may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer.

[0009]

[0009] Yet additional embodiments of the semiconductor processing method may include flowing a deposition precursor into a processing region of a semiconductor processing chamber. A deposition plasma may be generated with the deposition precursor and may be struck using a first supplied power operating for a first period of time. The plasma may be maintained using a second supplied power operating for a second period of time. The method may further include depositing a layer on a substrate from the generated plasma in the processing region of the semiconductor processing chamber. The layer, once deposited, may be characterized by a thickness of 50 Å or less. The method may still further include treating the deposited layer with a treatment plasma. The treatment plasma may replace the deposition plasma in the processing region of the semiconductor processing chamber.

[0010] In exemplary embodiments, a first period of time during which the deposition plasma is generated can be shorter than a second period of time during which the plasma is maintained. The first supplied power can have a first duty cycle of about 20% or greater, and the second supplied power can have a second duty cycle of about 5% or less. The first supplied power can have a power level greater than a power level of the second supplied power. An exemplary deposition precursor can include a silicon-containing precursor, and an exemplary layer deposited on the substrate can include a silicon-containing layer. An exemplary processing plasma can be generated from a processing precursor that does not include a deposition precursor and can include, for example, helium.

[0011] Such techniques may offer numerous advantages over conventional systems and techniques. For example, embodiments of the techniques herein may produce thin layers characterized by thicknesses of 50 Å or less using a direct plasma generated and maintained within a processing region of a semiconductor processing chamber. Additionally, the techniques herein may use the plasma to generate stable and reproducible deposition plasmas for depositing such thin layers on substrates present within the processing region. These and other embodiments, along with their numerous advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology may be better understood by reference to the following portions of this specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the technology herein. [Figure 2] 1 shows a schematic cross-sectional view of an exemplary semiconductor processing chamber in accordance with some embodiments of the technology herein; [Figure 3] 1 illustrates steps in a semiconductor processing method according to some embodiments of the technology herein. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0016] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless specifically noted as such. Additionally, the figures are presented as schematic diagrams to aid understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0015]

[0017] In the accompanying figures, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished by a letter following the reference numeral, which distinguishes between the similar components. When only a first reference numeral is used herein, the description is applicable to any similar component having the same first reference numeral, regardless of the subsequent letter.

[0016]

[0018] The technology herein includes systems and process methods for depositing thin layers of material on semiconductor substrates using low-power, short-duration plasmas. These system and method embodiments address the challenge of generating and maintaining such plasmas in a stable and reproducible manner without relying on high plasma powers or duty cycles. Conventional plasma generation involves supplying a plasma precursor with a plasma power above a minimum threshold and a duty cycle above a minimum threshold. Higher plasma powers and duty cycles for generating and maintaining the deposition plasma result in higher rates of material deposition on the substrate. In conventional plasma-enhanced chemical vapor deposition (PECVD), the amount of material deposited (e.g., as measured by the thickness of the deposited layer) is sufficiently high without concern for excessive material deposition during short-duration deposition at standard plasma powers and duty cycles.

[0017]

[0019] As semiconductor device sizes continue to shrink, there has been an increasing need to reduce the amount of material deposited and thin layers on a substrate. Critical dimensions of many semiconductor devices (e.g., the width between adjacent features formed within or on the surface of a substrate) have decreased to 10 nm or less. Because the depth of many substrate features has not decreased that much, the ratio of depth to width (referred to as the aspect ratio (AR)) of the gaps between substrate features typically exceeds 10:1. Filling such gaps without forming voids, cracks, and other defects in the deposited material has proven extremely difficult with the high deposition rates and high deposition volumes inherent in conventional PECVD processing methods. While slowing deposition rates and reducing deposition volumes have reduced the number of defects during gap filling, this has also introduced new challenges for PECVD, namely, the difficulty of generating and maintaining a stable and reproducible plasma at low power and low duty cycles.

[0018]

[0020] One aspect of the technology herein addresses the challenge of generating and sustaining a low-power, low-duty-cycle plasma for depositing a thin layer of material (e.g., about 50 Å or less) on a substrate. Embodiments of the technology herein include systems and process methods for generating and sustaining a deposition plasma within a processing region of a semiconductor processing chamber over at least two time periods having different duty cycles for the power supplied to the plasma precursor. The time periods include a first time period during which plasma power is supplied to the precursor from a power supply operating at a first duty cycle, and a second time period during which plasma power is supplied at a second duty cycle less than the first duty cycle. The first duty cycle used during the first time period is sufficient to generate a stable and reproducible plasma from the deposition precursor within the processing region of the semiconductor processing chamber. The second duty cycle used during the second time period is sufficient to sustain the plasma generated during the first time period, but reduces the deposition rate and amount of deposited material so that the deposited layer does not exceed the target thickness. Generating and maintaining a stable low-power plasma for at least two periods with different duty cycles allows for the reproducible formation of thin layers of material on a substrate.

[0019]

[0021] While the following disclosure routinely identifies specific deposition processes utilizing the disclosed technology, it will be readily understood that the above systems and methods are equally applicable to other deposition and processing processes that may be performed in the chambers described or any other chambers. Accordingly, the technology should not be considered limited to use with only such specific deposition processes or chambers. This disclosure describes one possible system and chamber that may be used to implement processing methods according to some embodiments of the technology herein, followed by additional examples of variations and adaptations of this system according to some embodiments of the technology herein.

[0020]

[0022] FIG. 1 illustrates a top view of one embodiment of a semiconductor processing system 100 with deposition, etch, bake, and cure chambers, according to an embodiment. In this illustration, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robot arm 104 and placed in a low-pressure holding area 106, which is then placed in one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and vice versa. Each substrate processing chamber 108a-f can be equipped to perform several substrate processing steps, including plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PCVD), etching, pre-cleaning, degassing, orientation, and the formation of semiconductor material stacks as described herein, in addition to other substrate processes including annealing, ashing, and the like.

[0021]

[0023] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit an alternating stack of dielectric films on a substrate. Any one or more of the described processes may be performed in chambers separate from the fabrication system shown in various embodiments. It should be appreciated that additional configurations of chambers for depositing, etching, annealing, and curing dielectric films are also contemplated by system 100.

[0022]

[0024] FIG. 2 shows a schematic cross-sectional view of an exemplary semiconductor processing chamber 200 in accordance with some embodiments of the technology herein. This diagram may provide an overview of a system that may include one or more aspects of the technology herein and / or be specifically configured to perform one or more steps in accordance with embodiments of the technology herein. Additional details of the chamber 200 or the methods performed therein may be further described below. While the chamber 200 may be utilized to form thin film layers in accordance with some embodiments of the technology herein, it should be understood that the methods may similarly be performed in any chamber in which film formation may occur. The semiconductor processing chamber 200 may include a chamber body 202, a substrate support 204 disposed within the chamber body 202, and a lid assembly 206 coupled to the chamber body 202 and enclosing the substrate support 204 within a processing region 220. A substrate 203 may be provided to the processing region 220 through an opening 226, which may be conventionally sealed for processing using a slit valve or door. The substrate 203 may rest on a surface 205 of the substrate support during processing. The substrate support 204 may be rotatable, as indicated by arrow 245, along an axis 247 about which a shaft 244 of the substrate support 204 may be disposed. Alternatively, the substrate support 204 may be elevated to rotate as needed during the deposition process.

[0023]

[0025] A plasma profile modulator 211 may be disposed in the processing chamber 200 to control plasma distribution across a substrate 203 disposed on a substrate support 204. The plasma profile modulator 211 may include a first electrode 208. The first electrode 208 may be disposed adjacent to the chamber body 202 and may separate the chamber body 202 from other components of the lid assembly 206. The first electrode 208 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 208 may be an annular or ring-shaped member, or may be a ring electrode. The first electrode 208 may be a continuous loop surrounding the processing region 220 along the periphery of the processing chamber 200, or may be discontinuous at selected locations as needed. The first electrode 208 may also be a perforated electrode (such as a perforated ring or mesh electrode) or a plate electrode (e.g., a secondary gas distributor).

[0024]

[0026] One or more isolators 210 a, 210 b, which may be a dielectric material (e.g., ceramic or a metal oxide such as aluminum oxide and / or aluminum nitride), may contact the first electrode 208 and electrically and thermally isolate the first electrode 208 from the gas distributor 212 and the chamber body 202. The gas distributor 212 may define an aperture 218 for distributing process precursors into the processing region 220. The gas distributor 212 may be coupled to a first power source 242 (e.g., an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that may be coupled to a processing chamber). In some embodiments, the first power source 242 may be an RF power supply.

[0025]

[0027] Embodiments of the technology herein include at least one power source to provide pulsed RF power to the deposition precursor in the processing region 220 to generate a plasma from the precursor. In some embodiments of the processing chamber 200, this pulsed RF power may be provided by a first power source 242. The power source may provide plasma power at a first duty cycle during a first period of time during which the plasma is generated in the processing region 220. In some embodiments, the power source transitions from the first duty cycle to a second duty cycle in which the deposition plasma is maintained while the remainder of the layer on the substrate 203 is deposited.

[0026]

[0028] The plasma power supplied at the first duty cycle to generate the plasma can be greater than the plasma power supplied at the second duty cycle to maintain the plasma. An exemplary embodiment includes a first duty cycle of 20% or greater and a second duty cycle of 5% or less. An exemplary first period (during which plasma power is supplied to the deposition precursor and / or plasma at the first duty cycle) can be about 2 seconds or less. An exemplary level of effective plasma power supplied to the deposition precursor and / or plasma during the first period can be about 4 Watts or less.

[0027]

[0029] The gas distribution apparatus 212 may be a conductive gas distribution apparatus or a non-conductive gas distribution apparatus. The gas distribution apparatus 212 may further be formed of conductive and non-conductive components. For example, the body of the gas distribution apparatus 212 may be conductive, while the faceplate of the gas distribution apparatus 212 may be non-conductive. The gas distribution apparatus 212 may be powered, for example, by the first power source 242 shown in FIG. 2, or in some embodiments, the gas distribution apparatus 212 may be coupled to ground.

[0028]

[0030] The first electrode 208 may be coupled to a first tuned circuit 228 that may control a ground path of the processing chamber 200. The first tuned circuit 228 may include a first electronic sensor 230 and a first electronic controller 234. The first electronic controller 234 may be or may include a variable capacitor or other circuit element. The first tuned circuit 228 may be or may include one or more inductors 232. The first tuned circuit 228 may be any circuit capable of providing a variable or controllable impedance under plasma conditions in the processing region 220 during processing. In some illustrated embodiments, the first tuned circuit 228 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 230. The first circuit leg may include a first inductor 232A. The second circuit leg may include a second inductor 232B coupled in series with the first electronic controller 234. A second inductor 232B may be disposed between the first electronic controller 234 and a node connecting both the first and second circuit legs to the first electronic sensor 230. The first electronic sensor 230 may be a voltage sensor or a current sensor and may be coupled to the first electronic controller 234. The first electronic controller 234 may provide a degree of closed-loop control over the plasma conditions within the processing region 220.

[0029]

[0031] A second electrode 222 may be coupled to the substrate support 204. The second electrode 222 may be embedded within the substrate support 204 or coupled to a surface of the substrate support 204. The second electrode 222 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed conductive element. The second electrode 222 may be a tuning electrode and may be coupled to a second tuning circuit 236 by a conduit 246 (e.g., a cable having a selected resistance, such as 50 ohms) disposed within a shaft 244 of the substrate support 204. The second tuning circuit 236 may include a second electronic sensor 238 and a second electronic controller 240 (which may be a second variable capacitor). The second electronic sensor 238 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 240 to provide further control over plasma conditions in the processing region 220.

[0030]

[0032] A third electrode 224 (which may be a bias electrode and / or an electrostatic chuck electrode) may be coupled to the substrate support 204. The third electrode may be coupled to a second power source 250 through a filter 248, which may be an impedance matching circuit. The second power source 250 may be DC power, pulsed DC power, RF bias power, a pulsed RF source, or a pulsed RF bias power, or a combination of these or other power sources. In some embodiments, the second power source 250 may be RF bias power. The substrate support 204 may further include one or more heating elements configured to heat the substrate to a processing temperature, which may be between about 25° C. and about 800° C. or higher.

[0031]

[0033] In some embodiments, the second power source 250 can be a pulsed RF power source. Additional embodiments include where both the first power source 242 and the second power source 250 are pulsed RF power sources. In some of the above embodiments, the first power source 242 and the second power source 250 can cooperate to provide plasma power that generates and maintains a deposition plasma during deposition of a layer of material on the substrate 203. For example, one of the power sources can supply plasma power at a first duty cycle during a first period, and the other power source can supply plasma power at a second duty cycle following the first period (e.g., a second period). In yet another embodiment, the first power source 242 or the second power source 250 supplies plasma power to the deposition precursor and plasma at both the first duty cycle and the second duty cycle both during and after the first period.

[0032]

[0034] The first power source 242 and / or the second power source 250 can provide plasma power at adjustable RF generation and RF pulse frequencies. For example, the plasma power can be generated at a plasma generation frequency such as, in one non-limiting example, 13.56 MHz. The plasma power can further be pulsed at a pulsed frequency that can be about 10 kHz or less, and can be about 9 kHz or less, about 8 kHz or less, about 7 kHz or less, about 6 kHz or less, about 5 kHz or less, about 4 kHz or less, about 3 kHz or less, about 2 kHz or less, about 1 kHz or less, or less.

[0033]

[0035] The lid assembly 206 and substrate support 204 of FIG. 2 may be used in any processing chamber for plasma or thermal processing. During operation, the processing chamber 200 may provide real-time control of plasma conditions within the processing region 220. A substrate 203 may be placed on the substrate support 204, and deposition precursors and other process gases may be flowed through the lid assembly 206 using the inlet 214 according to any desired flow plan. The gases may exit the processing chamber 200 through the outlet 252. Power may be coupled to the gas distribution system 212 to establish a plasma within the processing region 220. In some embodiments, an electrical bias may be applied to the substrate using the third electrode 224.

[0034]

[0036] When a plasma is excited in the processing region 220, a potential difference may be established between the plasma and the first electrode 208. A potential difference may also be established between the plasma and the second electrode 222. Electronic controllers 234, 240 may then be used to adjust the flow characteristics of the paths to ground represented by the two tuned circuits 228 and 236. Set points may be sent to the first tuned circuit 228 and the second tuned circuit 236 to provide independent control of the deposition rate and center-to-edge plasma density uniformity. In embodiments where both electronic controllers may be variable capacitors, electronic sensors may independently adjust the variable capacitors to limit the deposition rate and minimize thickness non-uniformity.

[0035]

[0037] Each of the tuned circuits 228, 236 may have a variable impedance that may be adjusted using the respective electronic controllers 234, 240. If the electronic controllers 234, 240 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 232A and the second inductor 232B may be selected to provide an impedance range. This impedance range may depend on the frequency, duty cycle, and voltage characteristics of the plasma, which may have a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 234 is minimum or maximum, the impedance of the first tuned circuit 228 may be high, resulting in a plasma shape with minimal aerial or lateral coverage above the substrate support. As the capacitance of the first electronic controller 234 approaches a value that minimizes the impedance of the first tuned circuit 228, the plasma's air coverage may expand to a maximum, effectively covering the entire active area of the substrate support 204. As the capacitance of the first electronic controller 234 deviates from the minimum impedance setting, the plasma shape may contract from the chamber walls and the air coverage of the substrate support may decrease. The second electronic controller 240 may have a similar effect, in that the plasma's air coverage above the substrate support may increase or decrease as the capacitance of the second electronic controller 240 changes.

[0036]

[0038] Electronic sensors 230, 238 may be used to tune the respective circuits 228, 236 in a closed loop. Set points for current, voltage, duty cycle, and / or RF frequency may be installed in each sensor depending on the type of sensor used, and the sensors may be provided with control software that determines adjustments to the respective electronic controllers 234, 240 to minimize deviations from such set points. As a result, the plasma shape may be selected and dynamically controlled during processing. While the above description is based on the electronic controllers 234, 240 being variable capacitors, it should be understood that any electronic component with adjustable characteristics may be used to provide the tuning circuits 228, 236 with adjustable impedance.

[0037]

[0039] FIG. 3 illustrates exemplary steps in a processing method 300 in accordance with some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 200 described above. Method 300 may include one or more steps prior to the initiation of the above-described method steps, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the above-described steps. The method may also include several optional steps that may or may not be specifically associated with the method in accordance with the present technology, as illustrated. For example, many of these steps are described to broaden the scope of semiconductor processing, but are not critical to the present technology or may be performed by alternative methodologies, as described further below.

[0038]

[0040] Method 300 may include optional steps to develop the semiconductor structure for a particular manufacturing process. In some embodiments, method 300 may be performed on a base structure, although in some embodiments, the method may be performed after the formation or removal of other materials. For example, any number of deposition, masking, or removal steps may be performed to fabricate any transistor, memory, or other structural aspects on the substrate. In some embodiments, one or more structures formed on the substrate may be characterized by a thermal budget of about 500°C or less, about 450°C or less, about 400°C or less, or less. Thus, method 300 and any subsequent steps may be performed at a temperature at or below the structural thermal budget. The substrate may be placed on a substrate support that may be positioned within a processing region of a semiconductor processing chamber. Steps to fabricate the underlying structure may be performed in the same chamber in which aspects of method 300 are performed, and one or more steps may be performed in one or more chambers on the same platform as the chamber in which steps of method 300 are performed, or on another platform.

[0039]

[0041] In some embodiments, method 300 may include forming a thin layer (e.g., about 50 Å or less) of deposition material on a substrate and processing it. The method may include, in step 305, providing a deposition precursor to a substrate processing region of a substrate processing chamber housing the substrate. The deposition precursor may be a single compound or a combination of two or more compounds. For example, the deposition precursor may be a combination of at least one deposition compound (e.g., a silicon-containing deposition precursor) that generates plasma effluents that form a deposition layer material on the substrate and at least one inert compound (e.g., helium or argon) that helps transport the at least one deposition compound into the substrate processing region of the processing chamber. Specific examples of deposition precursors include silicon-containing precursors (e.g., silane and tetrasilane, but other silicon-containing precursors are also possible). Examples of deposition precursors also include hydrogen (H2) and nitrogen (N2). Exemplary process pressures for the deposition precursor in the substrate processing region of the processing chamber can be about 1 Torr or greater, about 2 Torr or greater, about 5 Torr or greater, about 10 Torr or greater, and about 20 Torr or greater, although other process pressure ranges are possible.

[0040]

[0042] In step 310, a plasma is generated from the deposition precursor in the substrate processing region for a first time period. The first time period can include initial generation of the plasma and stabilization of the generated plasma. Generating the plasma in step 310 includes providing power to the deposition precursor from a power source operating at a first duty cycle. The power source can be a pulsed RF power source operating at a first duty cycle of 20% or greater. Additional examples of the first duty cycle include 25% or greater, 30% or greater, 35% or greater, 40% or greater, 45% or greater, and 50% or greater, although other duty cycle ranges are also included. Exemplary ranges for the first time period include about 2 seconds or less, about 1.5 seconds or less, about 1 second or less, or about 0.5 seconds or less, although other time ranges are also included.

[0041]

[0043] The plasma power supplied during the first time period can be low and can have a peak power of about 100 Watts or less. Additional examples of peak power ranges include about 80 Watts or less, about 60 Watts or less, about 50 Watts or less, and about 40 Watts or less, among other power ranges. The plasma power drops to 0 Watts during the "off" portion of the duty cycle, resulting in an effective (i.e., average) plasma power that is significantly lower than the peak power. The effective plasma power supplied to the deposition precursor and / or plasma during the first time period can be about 40 Watts or less, about 30 Watts or less, about 20 Watts or less, about 10 Watts or less, and about 5 Watts or less, among other effective power ranges.

[0042]

[0044] Generating the plasma during the first period can include stabilizing the plasma to help provide reproducible deposition of a layer having a thickness of about 50 Å or less, where a stable plasma has a variation of 10% or less in one or more plasma characteristics, such as, but not limited to, plasma source power, plasma forward power, plasma reflected power, plasma setpoint power, and plasma ion density.

[0043]

[0045] After the first period of time has expired, the plasma may be maintained under varying conditions 315 for a second period of time. In some embodiments, such varying conditions may include maintaining the plasma using a power supply having a second duty cycle that is shorter than the first duty cycle. This may be achieved by transitioning a power supply that supplies power to the deposition precursor and plasma during the first period of time from the first duty cycle to a second duty cycle. In additional embodiments, the first power supply that supplies power at the first duty cycle during the first period of time may transition to a second power supply within the processing chamber, which supplies power at the second duty cycle for the second period of time. The second duty cycle may be shorter than the first duty cycle. Exemplary second duty cycles may include 5% or less, 4% or less, 3% or less, 2% or less, and 1% or less, although other duty cycle ranges may also be included. Having the second duty cycle shorter than the first duty cycle allows for more precise control of the deposition endpoint.

[0044]

[0046] In additional embodiments, the various conditions for maintaining the plasma during the second time period can include supplying plasma power at a second power level different from the first power level during the first time period. In some embodiments, the second power level can be lower than the first power level. Exemplary second power levels can include peak powers of about 80 Watts or less, about 60 Watts or less, about 50 Watts or less, about 40 Watts or less, about 30 Watts or less, about 20 Watts or less, and about 10 Watts or less, although other second power level ranges may be included. The plasma power is reduced to 0 Watts during the "off" portion of the second duty cycle, resulting in an effective (i.e., average) second plasma power that is significantly lower than the peak power. The effective second plasma power supplied to the deposition precursor and / or plasma during the first time period can be about 10 Watts or less, about 7.5 Watts or less, about 5 Watts or less, about 4 Watts or less, and about 2 Watts or less, although other effective power ranges are also possible.

[0045]

[0047] The deposition plasma can be maintained with a plasma power supplied during a second time period at a lower duty cycle and / or power level than the plasma power supplied during the first time period. In some embodiments, the second time period is longer than the first time period. Exemplary ranges for the second time period include greater than 2 seconds, about 2.5 seconds or more, about 3 seconds or more, about 4 seconds or more, and about 5 seconds or more, although other time ranges are possible.

[0046]

[0048] The generated and maintained deposition plasma deposited a layer of material on the substrate in step 320. To perform direct plasma deposition of a layer on a substrate, both the deposition plasma and the substrate can be disposed in a substrate processing region of a substrate processing chamber. In some embodiments, the layer is deposited at two or more different deposition rates during a first time period and a subsequent time period until a final thickness is reached. For example, a first portion of the layer can be deposited at a first deposition rate during a first time period, and a second portion of the layer can be deposited at a second deposition rate that is slower than the first deposition rate during a second time period. In some embodiments, the remainder of the layer is deposited on the substrate during the second time period, while in additional embodiments, an additional portion of the layer can be deposited during a second time period after the layer material is deposited. Exemplary first deposition rates of the layer material during the first time period can include ranges of about 5 Å / sec or greater, about 7 Å / sec or greater, or about 10 Å / sec or greater, although other first deposition rates may also be included. Exemplary second deposition rates of the layer material during the second time period include ranges of less than 10 Å, less than 5 Å / sec, about 3 Å / sec or less, about 2 Å / sec or less, and about 1 Å / sec or less, although other second deposition rates may be included. An exemplary final thickness of the deposited layer may be, for example, about 50 Å or less. Other exemplary thickness ranges include about 40 Å or less, about 30 Å or less, about 20 Å or less, or about 10 Å or less, although other thickness ranges may be included.

[0047]

[0049] In embodiments of the technology herein, example compositions of deposited layers include silicon-containing layers. Specific examples of silicon-containing layers include amorphous silicon, doped silicon, and crystalline silicon, but may include other silicon-containing layers.

[0048]

[0050] In some embodiments, the substrate having a layer of material formed thereon may be further processed in an optional treatment process in step 325. This optional post-deposition treatment may be performed in the same chamber as the deposition, or the substrate may be transferred from the first treatment chamber to a second treatment chamber. In some embodiments, the second chamber may be on the same tool, as described above, and the transfer may be performed while maintaining vacuum conditions for the substrate. The treatment process may be configured to anneal, densify, etch, polish, and / or pattern the deposited layer, but may also be configured to perform other treatment processes. The optional treatment process may include any number of processes configured to provide additional energy transfer. For example, the treatment process may be a thermal annealing process performed at a temperature that does not exceed the thermal budget of the substrate (e.g., about 550°C or less). Additional examples of treatment processes may include UV exposure, microwave exposure, or in situ plasma exposure. Such exposure treatments can be carried out for periods of about 10 seconds or more, about 30 seconds or more, about 1 minute or more, about 2 minutes or more, about 5 minutes or more, about 10 minutes or more, about 15 minutes or more, or more. Embodiments of treatment processes involving in situ plasma exposure can include exposing the deposited layer to a treatment plasma generated from a treatment precursor. The treatment precursor can include hydrogen and / or an inert gas (such as helium or argon), but can also be other treatment precursors. The treatment plasma can be formed at low power to limit sputtering of the resulting film; in some embodiments, the treatment plasma can be formed at or below about 2,500 W, about 2,000 W, about 1,500 W, about 1,000 W, or about 500 W.

[0049]

[0051] The formation and processing of layers of deposition material described in method 300 can be performed within the thermal budget of the substrate. Exemplary temperature ranges for the thermal budget can include temperatures below about 550°C, below about 500°C, below about 450°C, below about 400°C, below about 350°C, below about 300°C, or below, although other thermal budget temperature ranges may be included. Thus, in some embodiments, layers of material can be deposited and optionally processed at or below any of the above temperatures to accommodate the underlying material. In some embodiments, one or more steps (including all steps of method 300) can be performed at or below any of the above temperatures. The substrate being processed can be maintained at a temperature below or near any of the above temperatures throughout processing.

[0050]

[0052] Embodiments of the technology herein further include treatment processes having two or more cycles of forming and treating a thin layer of deposition material on a substrate, as described above in method 300. For example, after a first layer of material is deposited and treated in a first cycle, a second cycle can be performed to form a second layer of deposition material. Depositing an additional layer of material can limit the formation of pores and other inconsistencies in the surface of the previously deposited layer. In some embodiments, each cycle of deposition and optional treatment can form a layer that constitutes a portion of the total amount of material deposited on the substrate. For example, each layer of deposition material can constitute about 50% or less, about 30% or less, about 25% or less, about 20% or less, or less of the total amount of material deposited on the substrate, based on the total film thickness. If a cycle includes an optional treatment step after layer deposition, the treatment step can be performed in the deposition chamber, and other energy treatments can be performed in chambers in the same tool as the deposition chamber, to reduce delays between the deposition and treatment steps.

[0051]

[0053] The technology herein includes process method embodiments that enable reproducible deposition of material on a substrate that is significantly thinner than layers of material deposited by conventional PECVD processes. This deposition reproducibility is achieved in part by generating a deposition plasma by providing plasma power at a first duty cycle and / or for a first period of time, and then maintaining the deposition plasma at a second duty cycle and / or plasma power that is lower than the first duty cycle and / or plasma power. The thin layer of deposited material formed on the substrate has fewer deposition defects (e.g., voids, cracks, etc.) and is thin enough to allow more thorough penetration of heat, UV light, plasma ions, etc. through the layer during processing. As critical dimensions of substrate features continue to decrease, reducing the amount and thickness of material layers deposited on these substrates, the technology herein expands the feasibility of direct plasma deposition for forming these layers.

[0052]

[0054] In the above description, for purposes of explanation, numerous details are set forth in order to facilitate an understanding of various embodiments of the technology herein. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0053]

[0055] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the essence of the embodiments. Additionally, in order to avoid unnecessarily obscuring the technology herein, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology herein.

[0054]

[0056] Where a range of values is provided, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is understood to be specifically disclosed, down to the smallest unit of the lower limit. Narrower ranges between any stated or unstated intervening values in a stated range, as well as other stated or intervening values in that stated range, if any, are included. The upper and lower limits of any such narrower range may individually be included in or excluded from the range. Each range where either, neither, or both limits are included in the narrower range is also encompassed within the technology herein, provided that there is a specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0055]

[0057] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0056]

[0058] Furthermore, the words "comprise(s) / comprising", "contain(s) / containing", and "include(s) / including", when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber, the plasma being generated at a supplied power for a first time period, the plasma power being supplied from a power supply operating at a first duty cycle; transitioning the power supply from the first duty cycle to a second duty cycle after the first period of time, the first period of time being set based on an amount of time it takes for the plasma to stabilize after being generated; depositing a layer on a substrate in the processing region of the semiconductor processing chamber from the generated plasma, wherein the deposited layer is characterized by a thickness of 50 Å or less, and the plasma is maintained at the second duty cycle for a second period of time.

2. 10. The semiconductor processing method of claim 1, wherein said plasma power has an effective power of 4 watts or less.

3. 2. The semiconductor processing method of claim 1, wherein said first period of time is 2 seconds or less.

4. A semiconductor processing method as described in claim 1, wherein the second period is longer than the first period.

5. 2. The semiconductor processing method of claim 1, wherein said first duty cycle is greater than or equal to 20%.

6. 2. The semiconductor processing method of claim 1, wherein said second duty cycle is less than or equal to 5%.

7. The semiconductor processing method of claim 1 , wherein the deposition precursor comprises a silicon-containing precursor.

8. 10. The semiconductor processing method of claim 1, wherein the layer deposited on the substrate comprises a silicon-containing layer.

9. generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber, the plasma being initially generated at a supplied power for a first time period, the plasma power being supplied from a power supply operating at a first peak power level; transitioning the power source from the first peak power level to a second peak power level after the first period of time, the first period of time being set based on an amount of time it takes for the plasma to stabilize after being generated; depositing a layer on a substrate in the processing region of the semiconductor processing chamber from the generated plasma, wherein the deposited layer is characterized by a thickness of 50 Å or less.

10. 10. The semiconductor processing method of claim 9, wherein the first peak power level is greater than the second peak power level.

11. 10. The semiconductor processing method of claim 9, wherein said first peak power level is less than or equal to 60 watts.

12. 10. The semiconductor processing method of claim 9, wherein the plasma power is supplied at a pulsed plasma frequency of 10 kHz or less.

13. 10. The semiconductor processing method of claim 9, wherein the plasma power has an effective power of 4 watts or less.

14. 10. The semiconductor processing method of claim 9, wherein the layer deposited on the substrate comprises an amorphous silicon layer.

15. flowing a deposition precursor into a processing region of a semiconductor processing chamber; generating a deposition plasma of the deposition precursor, the deposition plasma being initially generated at a first supplied power operating for a first time period, the operation of the first supplied power continuing after generation until the deposition plasma stabilizes, and the plasma being maintained at a second supplied power operating for a second time period; depositing a layer on a substrate in the processing region of the semiconductor processing chamber from the generated plasma, the deposited layer being characterized by a thickness of 50 Å or less; and treating the deposited layer with a treatment plasma, the treatment plasma replacing the deposition plasma in the processing region of the semiconductor processing chamber.

16. 16. The semiconductor processing method of claim 15, wherein the first period of time is shorter than the second period of time.

17. 16. The semiconductor processing method of claim 15, wherein the first supplied power has a duty cycle of 20% or more and the second supplied power has a duty cycle of 5% or less.

18. The semiconductor processing method of claim 15, wherein the first supply power has a power level greater than a power level of the second supply power.

19. 16. The semiconductor processing method of claim 15, wherein the deposition precursor comprises a silicon-containing precursor.

20. 16. The semiconductor processing method of claim 15, wherein the processing plasma is generated from a process precursor containing helium.

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