Semiconductor device and data storage system including the same

Abstract

To provide a more reliable semiconductor device, and a data storage system having the semiconductor device.SOLUTION: The semiconductor device of the present invention includes: a first substrate; a circuit element on the first substrate; a second substrate in the upper part of the circuit element; a gate electrode deposited apart from each other on the second substrate along a first direction; a channel structure penetrating the gate electrode, extending along the first direction, and having a channel layer; a separation region penetrating the gate electrode and extending in a second direction; a penetration contact plug penetrating the second substrate, extending along the first direction, and electrically connecting the gate electrode and the circuit element; and a barrier structure separate from the penetration contact plug, the barrier structure surrounding the penetration contact plug and having a first region with a first width and a second region with a second width larger than the first width.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems that require data storage, semiconductor devices capable of storing large amounts of data are required. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-112363 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved reliability. Another object of the present invention is to provide a data storage system including a semiconductor device with improved reliability. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a second substrate disposed on the peripheral circuit structure and having a first region and a second region; gate electrodes stacked spaced apart from each other in a first direction on the first region and extending in a stepped manner in a second direction on the second region; an interlayer insulating layer alternately stacked with the gate electrodes; channel structures each including a channel layer penetrating the gate electrodes and extending in the first direction; and isolation regions extending in the second direction through the gate electrodes and spaced apart from each other in a third direction, the semiconductor device further comprising a through wiring region including a sacrificial insulating layer arranged parallel to the gate electrodes in the second region and alternately stacked with the interlayer insulating layer, and through contact plugs electrically connecting the gate electrodes and the circuit elements, the semiconductor device further comprising: a barrier structure disposed to surround the through wiring region and having an inner surface with a plurality of protrusions.

[0006] According to another aspect of the present invention, which has been made to achieve the above object, a semiconductor device includes a first substrate, a circuit element on the first substrate, a second substrate disposed on top of the circuit element, gate electrodes stacked spaced apart from each other along a first direction on the second substrate, channel structures each including a channel layer extending along the first direction and penetrating the gate electrode, an isolation region extending in a second direction through the gate electrode, a through contact plug extending in the first direction through the second substrate and electrically connecting the gate electrode and the circuit element, and a barrier structure disposed to surround the through contact plug and spaced from the through contact plug, the barrier structure having a first region having a first width and a second region having a second width greater than the first width.

[0007] a second substrate disposed on the second substrate; gate electrodes stacked spaced apart from each other along a first direction; channel structures each including a channel layer extending along the first direction and penetrating the gate electrode; an isolation region extending in a second direction and penetrating the gate electrode; a through contact plug extending in the first direction and penetrating the second substrate, electrically connecting the gate electrode and the circuit element; a barrier structure disposed to surround the through contact plug and spaced from the through contact plug, the barrier structure having a first region having a first width and a second region having a second width greater than the first width; a semiconductor storage device including input / output pads electrically connected to the circuit element; and a controller electrically connected to the semiconductor storage device through the input / output pads and controlling the semiconductor storage device. [Effects of the Invention]

[0008] According to the present invention, a semiconductor device and a data storage system including the same can be provided that have improved reliability by including a barrier structure including regions with different widths. [Brief explanation of the drawings]

[0009] [Figure 1a] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Figure 1b] This is an enlarged view of area "A" in Figure 1a. [Figure 1c] This is an enlarged view of area "B" in Figure 1a. [Figure 2a] FIG. 2 is a cross-sectional view taken along line II' in FIGS. 1a and 1b. [Figure 2b] FIG. 2 is a cross-sectional view taken along the line II-II′ in FIGS. 1a and 1c. [Figure 2c] FIG. 1b is a cross-sectional view taken along the line III-III' in FIG. 1a. [Figure 3]1 is an enlarged plan view showing a barrier structure of a semiconductor device according to an embodiment of the present invention; [Figure 4a] FIG. 10 is a plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 4b] FIG. 10 is a plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A is a plan view showing yet another example of a semiconductor device according to an embodiment of the present invention, and is an enlarged view of region "A" in FIG. 1A. [Figure 6a] FIG. 10 is a plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 6b] FIG. 10 is a plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 6c] FIG. 10 is a plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 8a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 8b] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 9b] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10b]1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 11b] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 12b] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 13b] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13c] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1 is a schematic diagram of a data storage system including a semiconductor device according to an embodiment of the present invention; [Figure 15] 1 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an embodiment of the present invention; [Figure 16] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, specific examples of embodiments of the present invention will be described with reference to the drawings.

[0011] 1a to 1c are schematic plan views of a semiconductor device according to one embodiment of the present invention, in which Fig. 1b is an enlarged view of region "A" in Fig. 1a, and Fig. 1c is an enlarged view of region "B" in Fig. 1a.

[0012] 2a to 2c are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention, where Fig. 2a shows a cross-section along section line I-I' in Fig. 1a and Fig. 1b, Fig. 2b shows a cross-section along section line II-II' in Fig. 1a and Fig. 1c, and Fig. 2c shows a cross-section along section line III-III' in Fig. 1a.

[0013] FIG. 3 is an enlarged plan view showing a barrier structure of a semiconductor device according to one embodiment of the present invention.

[0014] 1a to 2c, a semiconductor device 100 includes a peripheral circuit structure PERI including a first substrate 201 and a memory cell structure CELL including a second substrate 101, and a through wiring region TR including a through contact plug 170 electrically connecting the peripheral circuit structure PERI and the memory cell structure CELL. The memory cell structure CELL may be disposed above the peripheral circuit structure PERI, and the through wiring region TR may be disposed to connect the memory cell structure CELL and the peripheral circuit structure PERI by passing through the memory cell structure CELL. In one embodiment, the memory cell structure CELL is disposed below the peripheral circuit structure PERI, conversely. In another embodiment, the memory cell structure CELL and the peripheral circuit structure PERI are bonded together, for example, by copper (Cu)-to-copper bonding.

[0015] The peripheral circuit structure PERI includes a first substrate 201, source / drain regions 205 and an element isolation layer 210 in the first substrate 201, circuit elements 220 arranged on the first substrate 201, circuit contact plugs 270, circuit wiring lines 280, and a peripheral region insulating layer 290.

[0016] The first substrate 201 has an upper surface extending in the X and Y directions. An active region is defined in the first substrate 201 by an isolation layer 210. Impurity-containing source / drain regions 205 are disposed in a portion of the active region. The first substrate 201 includes a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The first substrate 201 is provided as a bulk wafer or an epitaxial layer.

[0017] The circuit elements 220 include planar transistors and / or three-dimensional transistors. Each circuit element 220 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 are disposed in the first substrate 201 on both sides of the circuit gate electrode 225. The circuit elements 220 include active elements and / or passive elements. The circuit elements 220 include active elements such as diodes and / or transistors. The circuit elements 220 may include at least one passive element of a resistor, a capacitor, an inductor, and a memristor.

[0018] A peripheral region insulating layer 290 is disposed on the circuit elements 220 on the first substrate 201. Circuit contact plugs 270 penetrate the peripheral region insulating layer 290 and are connected to the source / drain regions 205. Electrical signals are applied to the circuit elements 220 through the circuit contact plugs 270. In a region not shown, the circuit contact plugs 270 are also connected to the circuit gate electrodes 225. Circuit wiring lines 280 are connected to the circuit contact plugs 270 and are disposed in multiple layers.

[0019] The memory cell structure CELL includes a second substrate 101 having a first region R1 and a second region R2, a first horizontal conductive layer 102 on the first region R1 of the second substrate 101, a horizontal insulating layer 110 arranged alongside the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, a second horizontal conductive layer 104 on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a gate electrode 130 stacked on the second horizontal conductive layer 104, a first isolation region MS1 and a second isolation region MS2a, MS2b extending through a stacked structure GS of the gate electrode 130, a barrier structure 160 arranged to surround the through-wiring region TR in the second region R2, an upper isolation region SS that penetrates a portion of the stacked structure GS, and a channel structure CH arranged to penetrate the stacked structure GS. The memory cell structure CELL further includes an interlayer insulating layer 120, a wiring line 180, and a cell region insulating layer 190, which are alternately stacked with the gate electrode 130 on the second substrate 101.

[0020] The first region R1 of the second substrate 101 is a region where the gate electrodes 130 are vertically stacked and the channel structures CH are disposed, and corresponds to a region where the memory cells are disposed, and the second region R2 is a region where the gate electrodes 130 extend to different lengths and corresponds to a region for electrically connecting the memory cells to the peripheral circuit structures PER1. The second region R2 is disposed at least at one end of the first region R1 in at least one direction, for example, the X direction.

[0021] The second substrate 101 has an upper surface extending in the X and Y directions. The second substrate 101 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor includes silicon, germanium, or silicon-germanium. The second substrate 101 further includes an impurity. The second substrate 101 is provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0022] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 are sequentially stacked on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 does not extend to the second region R2 of the second substrate 101, and the second horizontal conductive layer 104 extends to the second region R2.

[0023] The first horizontal conductive layer 102 functions as a part of the common source line of the semiconductor device 100, for example, functions as a common source line together with the second substrate 101. As shown in the enlarged view of Figure 2b, the first horizontal conductive layer 102 is directly connected to the channel layer 140 around the channel layer 140.

[0024] The second horizontal conductive layer 104 contacts the second substrate 101 in a region where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 bends and extends onto the second substrate 101 while covering the end of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in the region.

[0025] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 include a semiconductor material, for example, the first horizontal conductive layer 102 and the second horizontal conductive layer 104 both include polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 is a doped layer, and the second horizontal conductive layer 104 is a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. However, in one embodiment, the second horizontal conductive layer 104 is replaced with an insulating layer.

[0026] The horizontal insulating layer 110 is disposed on the second substrate 101 alongside the first horizontal conductive layer 102 in at least a portion of the second region R2. As shown in the enlarged view of FIG. 2a, the horizontal insulating layer 110 includes first to third horizontal insulating layers (111, 112, 113) sequentially stacked on the second region R2 of the second substrate 101. The horizontal insulating layer 110 is a layer that remains after a portion of it is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100.

[0027] The horizontal insulating layer 110 includes silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111, the third horizontal insulating layer 113, and the second horizontal insulating layer 112 include different insulating materials. The first and third horizontal insulating layers (111, 113) include the same material. For example, the first and third horizontal insulating layers (111, 113) are made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of the same material as the sacrificial insulating layer 118.

[0028] The gate electrodes 130 are stacked vertically on the second substrate 101 and spaced apart to form a stack structure GS. The gate electrodes 130 include a lower gate electrode 130L forming a gate of a ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and an upper gate electrode 130U forming a gate of a string selection transistor. The number of memory gate electrodes 130M forming memory cells is determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the upper and lower gate electrodes 130U and 130L may each be one to four or more and may have the same or different structure as the memory gate electrode 130M. In one embodiment, the gate electrode 130 further includes a gate electrode 130 forming an erase transistor disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L and used for an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, some of the gate electrodes 130, for example, the memory gate electrode 130M adjacent to the upper or lower gate electrode (130U, 130L), are dummy gate electrodes.

[0029] The gate electrodes 130 are stacked vertically on the first region R1 and spaced apart from one another. The gate electrodes 130 extend from the first region R1 to the second region R2 by different lengths, forming a stepped structure. As shown in FIG. 2c, the gate electrodes 130 form a stepped structure between the gate electrodes 130 along the X direction. In one embodiment, at least some of the gate electrodes 130 form a gate group, with a fixed number of gate electrodes 130 (e.g., two to six gate electrodes 130) forming a stepped structure between the gate groups along the X direction. In this case, the gate electrodes 130 of one gate group are also arranged to have a stepped structure with respect to one another in the Y direction. Due to the stepped structure, the gate electrodes 130 form a stepped structure with the lower gate electrodes 130 extending longer than the upper gate electrodes 130, providing ends exposed upward from the interlayer insulating layer 120. In one embodiment, the gate electrodes 130 have an upwardly directed thickness at the ends.

[0030] 1a, the gate electrodes 130 are arranged to be separated from each other in the Y direction by a first isolation region MS1 extending in the X direction. The gate electrodes 130 between a pair of first isolation regions MS1 form one memory block, but the scope of the memory block is not limited thereto. Some of the gate electrodes 130, for example, memory gate electrode 130M, form one layer within one memory block.

[0031] The gate electrode 130 includes a metal material, such as tungsten (W). In some embodiments, the gate electrode 130 includes a polycrystalline silicon or metal silicide material. In one embodiment, the gate electrode 130 further includes a diffusion barrier, such as tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0032] The interlayer insulating layers 120 are disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 are also disposed to be spaced apart from each other in a direction perpendicular to the top surface of the second substrate 101 and extend in the X direction. The interlayer insulating layers 120 include an insulating material such as silicon oxide or silicon nitride.

[0033] The first isolation region MS1 and the second isolation region (MS2a, MS2b) are arranged to penetrate the gate electrode 130 and extend in the X direction. The first isolation region MS1 and the second isolation region (MS2a, MS2b) are arranged parallel to each other. The first isolation region MS1 and the second isolation region (MS2a, MS2b) are connected to the second substrate 101 by penetrating the entire gate electrode 130 stacked on the second substrate 101. The first isolation region MS1 extends in the X direction, and the second isolation regions (MS2a, MS2b) extend intermittently between the pair of first isolation regions MS1 or are arranged only in a partial region. For example, the second central isolation region MS2a extends in the first region R1 and extends intermittently in the X direction in the second region R2. The second auxiliary isolation region MS2b is arranged only in the second region R2 and extends intermittently in the X direction. However, in the embodiment, the arrangement order and number of the first isolation region MS1 and the second isolation region (MS2a, MS2b) are not limited to those shown in Fig. 1a. The first isolation region MS1 and the second isolation region (MS2a, MS2b) are not arranged to overlap with the through-wiring region TR, but are arranged apart from the through-wiring region TR.

[0034] 2a and 2b, an isolation insulating layer 105 is disposed in the first isolation region MS1 and the second isolation regions MS2a and MS2b. The isolation insulating layer 105 has a shape in which its width decreases toward the second substrate 101 due to a high aspect ratio, but is not limited thereto, and has side surfaces perpendicular to the top surface of the second substrate 101. In one embodiment, a conductive layer is further disposed within the isolation insulating layer 105 in the first isolation region MS1 and the second isolation regions MS2a and MS2b. In this case, the conductive layer functions as a common source line of the semiconductor device 100 or a contact plug connected to the common source line.

[0035] As shown in FIG. 1a, the upper isolation region SS extends in the X direction in the first region R1 between the first isolation region MS1 and the second central isolation region MS2a and between the second central isolation region MS2a. The upper isolation region SS is disposed to penetrate a portion of the gate electrodes 130, including the uppermost upper gate electrode 130U. As shown in FIG. 2b, the upper isolation region SS separates a total of four gate electrodes 130, including the upper gate electrode 130U, from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper isolation region SS may vary depending on the embodiment. The upper gate electrodes 130U separated by the upper isolation region SS form different string selection lines. An upper insulating layer 103 is disposed in the upper isolation region SS. The upper insulating layer 103 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0036] 1c, the channel structures CH each form one memory cell string and are arranged in rows and columns on the first region R1, spaced apart from one another. The channel structures CH may be arranged to form a lattice or in a zigzag pattern in one direction. The channel structures CH have a columnar shape and have sloping side surfaces that become thinner toward the second substrate 101 according to the aspect ratio.

[0037] As shown in the enlarged view of FIG. 2b, a channel layer 140 is disposed within the channel structure CH. The channel layer 140 within the channel structure CH is formed in an annular shape surrounding the channel-buried insulating layer 150 therein. However, in some embodiments, the channel layer 140 may have a columnar or rectangular pillar shape without the channel-buried insulating layer 150. The channel layer 140 is connected to the first horizontal conductive layer 102 at its bottom. The channel layer 140 includes a semiconductor material such as polycrystalline silicon or single-crystalline silicon.

[0038] In the channel structure CH, a channel pad 155 is disposed on the channel layer 140. The channel pad 155 is disposed to cover an upper surface of the channel-buried insulating layer 150 and to be electrically connected to the channel layer 140. The channel pad 155 includes, for example, doped polycrystalline silicon.

[0039] The gate dielectric layer 145 is disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the gate dielectric layer 145 includes a tunneling layer, a charge storage layer, and a blocking layer stacked in sequence from the channel layer 140. The tunneling layer tunnels charges to the charge storage layer and includes, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer is a charge trap layer or a floating gate conductive layer. The blocking layer includes silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In one embodiment, at least a portion of the gate dielectric layer 145 extends horizontally along the gate electrode 130.

[0040] The dummy channel structures DCH have the same or similar structure as the channel structures CH and are arranged spaced apart from each other in rows and columns in a part of the first region R1 and the second region R2. The dummy channel structures DCH are not electrically connected to an upper wiring structure, and unlike the channel structures CH, do not form memory cell strings within the semiconductor device 100. In the first region R1, the dummy channel structures DCH are arranged in a region adjacent to the second region R2.

[0041] 2a, in the second region R2, the dummy channel structures DCH are disposed to penetrate the horizontal insulating layer 110 along the Z direction. The lower portions of the dummy channel structures DCH are surrounded by the second horizontal conductive layer 104 and the horizontal insulating layer 110, and are spaced apart from the first horizontal conductive layer 102. Specifically, the dummy channel structures DCH penetrate the interlayer insulating layer 120 and the gate electrode 130, and penetrate the second horizontal conductive layer 104 and the horizontal insulating layer 110 at their lower ends. In one embodiment, the dummy channel structures DCH are further disposed in the through-via region TR, and are disposed to penetrate the interlayer insulating layer 120 and the sacrificial insulating layer 118, and penetrate the second horizontal conductive layer 104 and the horizontal insulating layer 110 at their lower ends.

[0042] The through wiring region TR is a region including wiring structures for electrically connecting the memory cell structures CELL and the peripheral circuit structures PERI to each other. In particular, the through wiring region TR is disposed to penetrate the second region R2. The through wiring region TR includes through contact plugs 170 extending in the Z direction through the second substrate 101 and an insulating region IR surrounding the through contact plugs 170. In this specification, a region within the barrier structure 160 in the second region R2 is designated as the through wiring region TR. For example, one through wiring region TR is disposed per memory block, and through wiring regions TR are also disposed in the first region R1. However, the number, size, arrangement, and shape of the through wiring regions TR may vary depending on the embodiment. For example, in some embodiments, one through wiring region TR is disposed per memory block.

[0043] 1a and 1b, the through wiring region TR is disposed apart from the first isolation region MS1 and the second isolation region (MS2a, MS2b). For example, the through wiring region TR is disposed at the center of the pair of first isolation regions MS1, apart from the first isolation regions MS1 adjacent to each other along the Y direction. With this arrangement, the sacrificial insulating layer 118 remains in the through wiring region TR.

[0044] The insulating region IR is disposed parallel to the second substrate 101 and the gate electrode 130, penetrating the memory cell structure CELL. The insulating region IR includes an insulating laminate structure made of an insulating material, where the gate electrode 130 may or may not be disposed. The insulating region IR includes a substrate insulating layer 109, which is a first insulating layer disposed parallel to the second substrate 101 and at the same height as the second substrate 101, an interlayer insulating layer 120, and a sacrificial insulating layer 118, which are second and third insulating layers alternately stacked on the top surface of the second substrate 101.

[0045] The first insulating layer, substrate insulating layer 109, is disposed in an area where portions of second substrate 101, horizontal insulating layer 110, and second horizontal conductive layer 104 have been removed, and is disposed so as to be surrounded by second substrate 101, horizontal insulating layer 110, and second horizontal conductive layer 104. The lower surface of substrate insulating layer 109 is coplanar with the lower surface of second substrate 101 or is located at a lower level than the lower surface of second substrate 101. In one embodiment, substrate insulating layer 109 includes multiple insulating layers. The second insulating layer is an extension of interlayer insulating layer 120, and is therefore located at substantially the same height level as interlayer insulating layer 120. The third insulating layer includes a sacrificial insulating layer 118 and is located at substantially the same height level as gate electrode 130.

[0046] The substrate insulating layer 109, the interlayer insulating layer 120, and the sacrificial insulating layer 118, which form the insulating region IR, are made of insulating materials. For example, the substrate insulating layer 109, the interlayer insulating layer 120, and the sacrificial insulating layer 118 each include silicon oxide, silicon nitride, or silicon oxynitride. The substrate insulating layer 109 and the sacrificial insulating layer 118 may have different widths or may have the same width depending on the embodiment.

[0047] The through contact plug 170 extends vertically through the entire insulating region IR to the top surface of the second substrate 101, electrically connecting the memory cell structure CELL to the circuit element 220 of the peripheral circuit structure PERI. For example, the through contact plug 170 electrically connects the gate electrode 130 and / or the channel structure CH of the memory cell structure CELL to the circuit element 220 of the peripheral circuit structure PERI. The through contact plug 170 is connected at its upper portion to an upper plug 178 and a wiring line 180, which are upper wiring structures. The through contact plug 170 is connected at its lower portion to a circuit wiring line 280, which is a lower wiring structure.

[0048] The via contact plugs 170 penetrate the interlayer insulating layer 120 and the sacrificial insulating layer 118 in the insulating region IR, and penetrate the substrate insulating layer 109 below. The number, shape, and configuration of the via contact plugs 170 in one via wiring region TR may vary depending on the embodiment. Depending on the embodiment, the via contact plugs 170 may have a shape in which a plurality of layers are connected. Also, depending on the embodiment, a wiring structure in the form of a wiring line may be further disposed in the insulating region IR in addition to the via contact plugs 170. The via contact plugs 170 include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0049] The barrier structure 160 is disposed in the second region R2 to surround the through-wiring region TR. The barrier structure 160 includes a horizontal region aligned with the first isolation region MS1 and the second isolation region MS2a and MS2b extending in the X direction in a plan view, and a vertical region extending in the Y direction. In this embodiment, the horizontal region and the vertical region form a single closed curve in a plan view. In a cross-sectional view, the horizontal region is referred to as a first horizontal region, and the vertical region is referred to as a second horizontal region.

[0050] 3, the barrier structure 160 has first and second barrier regions having different widths along the extension direction. The first and second barrier regions are alternately arranged in at least a portion of the region. The barrier structure 160 includes a ring-shaped or square-ring-shaped extension 162 extending in the X and Y directions with a substantially constant first width W1, and a protrusion 164 protruding from the extension 162 on an inner surface 160IS. For example, the second barrier region is the region where the protrusion 164 is arranged.

[0051] The protrusions 164 protrude in a direction perpendicular to the extension direction of the extensions 162. Specifically, the protrusions 164 protrude in the Y direction from the horizontal region and in the X direction from the vertical region. The protrusions 164 have a semicircular or similar shape. The inner surface 160IS of the barrier structure 160 is curved by the protrusions 164, and the outer surface 160OS of the barrier structure 160 is substantially flat. By making the outer surface 160OS flat, a space is secured outside the barrier structure 160 in which dummy channel structures DCH are to be disposed.

[0052] The protrusions 164 are spaced apart from one another at regular intervals on the extension 162. In one embodiment, the length L1 of the protrusions 164 along the extension direction of the extension 162 and the spacing L2 between the protrusions 164 may vary. For example, the ratio (L1 / L2) of the length L1 to the spacing L2 may be in the range of about 0.3 to about 2.0. If the ratio (L1 / L2) is smaller or larger than the above range, the effect of the protrusions 164, as described below, may be reduced. The extension 162 has a first width W1 in the direction perpendicular to the extension direction, and the protrusions 164 have a second width W2, which is their maximum width (height). As a result, the barrier structure 160 has a third width W3, which is their maximum width. The first width W1 is substantially the same as the width W4 of the first and second separation regions MS1 and MS2a and MS2b. For example, the third width W3 may be in the range of about 1.3 to about 2.5 times the first width W1. If the third width W3 is larger than the above range, i.e., if the second width W2 is relatively large, the process difficulty may increase, and if it is smaller than the above range, the effect of the protrusion 164 may be minimal. In particular, the third width W3 is in the range of about 1.3 to about 2 times the first width W1, and for example, the second width W2 may be smaller than the first width W1. For example, the third width W3 is in the range of about 180 nm to about 300 nm.

[0053] The barrier structure 160 has seams SP formed therein. The seams SP are located within the extensions 162 adjacent to the protrusions 164 and are spaced apart to correspond to the respective protrusions 164. The seams SP are formed at positions shifted from the center of the extensions 162 in a direction perpendicular to the extension direction thereof toward the protrusions 164. The seams SP have a shape in which their width decreases toward the protrusions 164, but are not limited to this. The maximum length L3 of the seams SP is smaller than the length L1 of the protrusions 164 and may vary depending on the embodiment.

[0054] 2a and 2c, the barrier structure 160 is located at the interface between the gate electrode 130 and the sacrificial insulating layer 118. The outer surface of the barrier structure 160 contacts the gate electrode 130, and the inner surface of the barrier structure 160 contacts the sacrificial insulating layer 118. The barrier structure 160 is located at substantially the same height level as the first isolation region MS1 and the second isolation regions MS2a and MS2b. This is because the barrier structure 160 is formed in a trench formed in the same process step as the first isolation region MS1 and the second isolation regions MS2a and MS2b. Furthermore, the barrier structure 160 is located in a region where the second horizontal conductive layer 104 directly contacts the second substrate 101, similar to the arrangement of the first isolation region MS1 and the second isolation regions MS2a and MS2b in the second region R2. As a result, the barrier structure 160 penetrates the second horizontal conductive layer 104 at its lower end and contacts the horizontal conductive layer 104 , while being spaced apart from the first horizontal conductive layer 102 and the horizontal insulating layer 110 .

[0055] As shown in the enlarged view of FIG. 2a, the barrier structure 160 includes first, second, and third barrier layers (160L, 160M, and 160H) sequentially stacked along the side and bottom surfaces. The first, second, and third barrier layers (160L, 160M, and 160H) include different materials. The seam SP is formed in the relatively thick third barrier layer 160H. For example, the first and second barrier layers 160L and 160M each include one of silicon oxide, silicon nitride, and silicon oxynitride, and the third barrier layer 160H includes polycrystalline silicon. However, the internal structure of the barrier structure 160 may vary depending on the embodiment.

[0056] The semiconductor device 100 includes the barrier structure 160, which prevents material forming the gate electrode 130 from flowing into the through-via region TR during the manufacturing process and controls the extension region of the gate electrode 130. However, because the materials of the stacked structures where the outer and inner surfaces of the barrier structure 160 are in contact are different, stresses on the outer and inner surfaces may be different, potentially resulting in a physically fragile structure. Therefore, if a seam occurs along the extension direction of the barrier structure 160, this may lead to defects such as cracks in the barrier structure 160. However, because the barrier structure 160 includes the protrusions 164, deposition continues in a region having a relatively large width W3, forming localized seams SP that are spaced apart and not connected to each other, thereby reducing physical fragility. In addition, the size and position of the seams SP can be controlled by adjusting the shape and size of the protrusions 164.

[0057] According to the simulation results, it was confirmed that in one embodiment of the barrier structure 160, by localizing the seam SP, the deformation amount is balanced in the laminated structures on both sides of the barrier structure 160, and cracks are improved.

[0058] As shown in FIG. 2c, the gate contact plug 175 is connected to the gate electrode 130, the upper surface of which is exposed in the second region R2 of the gate electrode 130.

[0059] The upper plugs 178 and the wiring lines 180 constitute an upper wiring structure electrically connected to the memory cells in the memory cell structure CELL. The wiring lines 180 are electrically connected to, for example, the through contact plugs 170, the gate electrodes 130, and the channel structures CH. The number of contact plugs and wiring lines constituting the wiring structure may vary depending on the embodiment. The upper plugs 178 and the wiring lines 180 include metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0060] The cell region insulating layer 190 is disposed to cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 is made of an insulating material and includes a plurality of insulating layers.

[0061] Figures 4a and 4b are plan views showing another example of a semiconductor device according to an embodiment of the present invention, each showing an enlarged view of a region corresponding to region "A" in Figure 1a.

[0062] 4a, in the semiconductor device 100a, the protrusion 164a of the barrier structure 160a has a rectangular or similar shape. Specifically, the protrusion 164a has a region with a constant width in a direction perpendicular to the extension direction of the extension 162. However, in one embodiment, the corners of the protrusion 164a are rounded due to process factors.

[0063] The seam SPa is formed at a distance within the extension 162 to correspond to the protrusion 164a, and has a shape corresponding to the protrusion 164a or a shape that is elongated in a direction perpendicular to the extension direction from that shown in FIG. 4a.

[0064] 4b, in a semiconductor device 100b, a protrusion 164b of a barrier structure 160b has a triangular or similar shape, although in one embodiment, the corners of the protrusion 164b are rounded due to process factors.

[0065] The seam SPb is formed in the extension 162 at a distance to correspond to the protrusion 164b, and has a shape corresponding to the protrusion 164b or a shape more curved than the protrusion 164b.

[0066] Thus, in one embodiment, the specific shape of the protrusions (164a, 164b) may be variously changed.

[0067] Figure 5 is a plan view showing yet another example of a semiconductor device according to an embodiment of the present invention, and is an enlarged view of a region corresponding to region "A" in Figure 1a.

[0068] 5, in the semiconductor device 100c, the protrusions 164c of the barrier structure 160c are disposed not only on the inner surface but also on the outer surface of the barrier structure 160c. The protrusions 164c are disposed in a zigzag pattern protruding in opposite directions on the inner and outer surfaces, but are not limited to this. For example, the protrusions 164c are disposed in a straight line on the inner and outer surfaces along a direction perpendicular to the extension direction of the extensions 162.

[0069] The seam SPc is formed at a distance in the extension 162 to correspond to the protrusion 164c, and has a shape that decreases in width toward the protrusion 164c, but is not limited to this.

[0070] Figures 6a to 6c are plan views showing other examples of a semiconductor device according to an embodiment of the present invention, and are enlarged views of a region corresponding to region "A" in Figure 1a.

[0071] 6a, in a semiconductor device 100d, a barrier structure 160d has a horizontal region 160F and a vertical region 160S spaced apart from each other. The horizontal region 160F is aligned with the adjacent second auxiliary isolation region MS2b in the X direction. The vertical region 160S is disposed between the horizontal regions 160F to extend in the Y direction. The distance between the horizontal region 160F and the vertical region 160S may vary depending on the embodiment.

[0072] 6b, in the semiconductor device 100e, the barrier structure 160e is disposed across a pair of adjacent first isolation regions MS1 in the Y direction. That is, the barrier structure 160e is disposed to have an expanded shape in the Y direction. However, in this case, the barrier structure 160e and the through wiring region TR are not disposed in the second region R2 adjacent in the Y direction. For example, the arrangement of the barrier structure 160e is changed in this manner when one through wiring region TR is disposed per memory block.

[0073] 6c, in a semiconductor device 100f, a barrier structure 160f is arranged to have a reduced length along the Y direction, unlike the embodiment of FIG. 1a. One of the horizontal regions of the barrier structure 160f is arranged alongside the second central isolation region MS2a, and the other is arranged alongside the second auxiliary isolation region MS2b. Thus, a second auxiliary isolation region MS2b is further arranged between the barrier structure 160f and the first isolation region MS1 on one side of the barrier structure 160f in the Y direction.

[0074] FIG. 7 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0075] 7, in the semiconductor device 100g, the stacked structure of the gate electrode 130 is composed of vertically stacked lower and upper stacked structures, and the channel structure CHg includes vertically stacked first and second channel structures CH1 and CH2. Dummy channel structures DCH (see FIG. 2a) are also arranged in the same shape as the channel structure CHg. This structure of the channel structure CHg is introduced to stably form the channel structure CHg when there are a relatively large number of stacked gate electrodes 130.

[0076] The channel structure CHg has a shape in which a lower first channel structure CH1 and an upper second channel structure CH2 are connected, and has a bent portion due to the difference in width in the connection region. The channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 150 are connected to each other between the first channel structure CH1 and the second channel structure CH2. A channel pad 155 is disposed only on the upper end of the upper second channel structure CH2. However, in one embodiment, the first channel structure CH1 and the second channel structure CH2 each include a channel pad 155, and in this case, the channel pad 155 of the first channel structure CH1 is connected to the channel layer 140 of the second channel structure CH2. A relatively thick upper interlayer insulating layer 125 is disposed on the top of the lower stack structure. However, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may vary depending on the embodiment.

[0077] In one embodiment, the number of stacked structures and the number of channel structures stacked along the Z direction may be variously changed.

[0078] 8a to 13c are schematic plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0079] Referring to Figures 8a to 8c, a peripheral circuit structure PERI including circuit elements 220 and lower wiring structures is formed on a first substrate 201, and a second substrate 101, a horizontal insulating layer 110, a second horizontal conductive layer 104, and a substrate insulating layer 109 are formed on top of the peripheral circuit structure PERI, on which a memory cell structure CELL is provided, and then sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked.

[0080] First, an isolation layer 210 is formed in a first substrate 201, and then a circuit gate dielectric layer 222 and a circuit gate electrode 225 are sequentially formed on the first substrate 201. The isolation layer 210 is formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 are formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 is formed of silicon oxide, and the circuit gate electrode 225 is formed of at least one of, but not limited to, polysilicon or a metal silicide layer. Next, a spacer layer 224 and source / drain regions 205 are formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on the embodiment, the spacer layer 224 may be composed of multiple layers. Next, an ion implantation process is performed to form the source / drain regions 205.

[0081] The circuit contact plug 270 of the lower wiring structure is formed by partially forming the peripheral region insulating layer 290, then etching away a portion of the insulating layer, and filling the remaining portion with a conductive material. The circuit wiring line 280 is formed by, for example, depositing a conductive material and then patterning the deposited conductive material.

[0082] The peripheral region insulating layer 290 is made up of a plurality of insulating layers, a portion of which is formed during each step of forming the lower wiring structure, and a portion of which is formed on the uppermost circuit wiring line 280, so that the peripheral region insulating layer 290 is ultimately formed to cover the circuit elements 220 and the upper and lower wiring structures.

[0083] Next, the second substrate 101 is formed on the peripheral region insulating layer 290. The second substrate 101 is made of, for example, polycrystalline silicon and is formed by a CVD process. The polycrystalline silicon forming the second substrate 101 contains impurities.

[0084] First to third horizontal insulating layers (111, 112, 113) constituting the horizontal insulating layer 110 are sequentially stacked on the second substrate 101. The horizontal insulating layer 110 is a layer that will be partially replaced by the first horizontal conductive layer 102 of FIG. 2b through a subsequent process. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 contain a different material from the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 are made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of the same material as the sacrificial insulating layer 118. Some regions of the horizontal insulating layer 110 are removed by a patterning process.

[0085] The second horizontal conductive layer 104 is formed on the horizontal insulating layer 110 and contacts the second substrate 101 in the area where the horizontal insulating layer 110 has been removed. As a result, the second horizontal conductive layer 104 bends along the edge of the horizontal insulating layer 110 and extends onto the second substrate 101, covering the edge.

[0086] The substrate insulating layer 109 is formed by removing a portion of the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the area corresponding to the through-wiring region TR (see FIG. 2a) and then filling the area with an insulating material. The substrate insulating layer 109 is formed over the entire area of the through-wiring region TR or is formed to be smaller than the area. After filling the area with the insulating material, a planarization process is further performed using a chemical mechanical polishing (CMP) process. As a result, the top surface of the substrate insulating layer 160 is substantially coplanar with the top surface of the second horizontal conductive layer 104.

[0087] Next, the sacrificial insulating layer 118 is a layer whose portion will be replaced by the gate electrode 130 (see FIG. 2a) in a subsequent process. The sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120 and is formed of a material that can be etched with etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 is made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the interlayer insulating layers 120 do not all need to have the same thickness. The thicknesses and the number of layers constituting the interlayer insulating layer 120 and the sacrificial insulating layer 118 may be variously changed from those shown in the drawings.

[0088] Next, a cell region insulating layer 190 is formed to cover the upper portion of the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120 .

[0089] Referring to Figures 9a to 9c, a channel structure CH (see Figure 2b) and a dummy channel structure DCH are formed through the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120, and openings (OP1, OP2) are formed through the stacked structure.

[0090] First, the upper isolation region SS is formed by removing a portion of the sacrificial insulating layer 118 and the interlayer insulating layer 120. The upper isolation region SS is formed by exposing the region where the upper isolation region SS will be formed using a separate mask layer, removing a predetermined number of the sacrificial insulating layer 118 and the interlayer insulating layer 120 from the top, and then depositing an insulating material. The upper isolation region SS extends downward in the Z direction from the region where the upper gate electrode 130U of FIG. 2b is formed.

[0091] Next, the channel structures CH and the dummy channel structures DCH are formed by anisotropically etching the sacrificial insulating layer 118, the interlayer insulating layer 120, and the horizontal insulating layer 110 to form hole-shaped channel holes, and then filling the holes. In one embodiment, the dummy channel structures DCH are formed to be larger than the channel structures CH. Depending on the height of the stacked structures, the sidewalls of the channel holes may not be perpendicular to the top surface of the second substrate 101. The channel holes are formed by recessing a portion of the second substrate 101.

[0092] Next, of the openings (OP1, OP2), a first opening OP1 is formed at the position of the first isolation region MS1 and the second isolation region (MS2a, MS2b) in FIG. 1a, and a second opening OP2 is formed at the position of the barrier structure 160 in FIG. 1a. Before forming the openings (OP1, OP2), a cell region insulating layer 190 is further formed on the channel structure CH and the dummy channel structure DCH. The openings (OP1, OP2) are formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure. The first opening OP1 is formed in the form of a trench extending in the X direction, and the second opening OP2 is formed in the form of a square ring or a similar shape. The second opening OP2 has a bend due to a protrusion on its inner surface in a plan view.

[0093] Referring to FIGS. 10a to 10c, first to third barrier layers (160L, 160M, 160H) are stacked in the openings (OP1, OP2) to form a preliminary barrier structure 160P.

[0094] The first to third barrier layers (160L, 160M, 160H) are sequentially stacked along the inner side and bottom surfaces of the openings (OP1, OP2). The first barrier layer 160L and the second barrier layer 160M are formed to be relatively thinner than the third barrier layer 160H. The first to third barrier layers (160L, 160M, 160H) contain different materials. For example, the first barrier layer 160L contains a different material from the sacrificial insulating layer 118 so as to have etching selectivity with the sacrificial insulating layer 118.

[0095] A seam SP is formed in a region including the center of the preliminary barrier structure 160P. The second opening OP2 includes a region with a relatively large width due to the protrusion, and the deposition material is continuously supplied to this region. As a result, a continuously extending seam is not formed in the relatively narrow extension portion 162P, and the seam SP is formed locally only in the extension portion 162P in the region corresponding to the protrusion 164P.

[0096] Referring to FIGS. 11a to 11c, the preliminary barrier structure 160P is removed from the first opening OP1.

[0097] A separate mask layer is used to cover the upper region of the second opening OP2, and the preliminary barrier structure 160P is removed only at the first opening OP1 to form the first opening OP1 again. The preliminary barrier structure 160P remains at the second opening OP2 to form the barrier structure 160.

[0098] 12a to 12c, after the first horizontal conductive layer 102 is formed, a portion of the sacrificial insulating layer 118 is removed through the first opening OP1 to form the tunnel portion TL.

[0099] First, a separate sacrificial spacer layer is formed in the first opening OP1, and an etch-back process is performed to expose the second horizontal insulating layer 112 in the first region R1 as shown in Figure 2b. The second horizontal insulating layer 112 is selectively removed from the exposed region, and then the upper and lower first and third horizontal insulating layers 111 and 113 are removed.

[0100] The first to third horizontal insulating layers (111, 112, 113) are removed by, for example, a wet etching process. During the process of removing the first horizontal insulating layer 111 and the third horizontal insulating layer 113, a portion of the gate dielectric layer 145 exposed in the area where the second horizontal insulating layer 112 has been removed is also removed. A conductive material is deposited in the area where the first to third horizontal insulating layers (111, 112, 113) have been removed to form the first horizontal conductive layer 102, and then the sacrificial spacer layer is removed within the opening. Through this process, the first horizontal conductive layer 102 is formed in the first region A.

[0101] Next, the sacrificial insulating layer 118 is removed outside the through-wiring region TR (see FIG. 2a). In the through-wiring region TR, the sacrificial insulating layer 118 remains and forms an insulating region IR of the through-wiring region TR together with the interlayer insulating layer 120 and the substrate insulating layer 109. The sacrificial insulating layer 118 is selectively removed with respect to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the substrate insulating layer 109, for example, by wet etching. This forms a plurality of tunnel portions TL between the interlayer insulating layers 120.

[0102] The region where the through wiring region TR is formed is separated from the first opening OP1 and cannot be reached by the etchant, so the sacrificial insulating layer 118 remains. Therefore, the through wiring region TR is formed between the adjacent first isolation region MS1 and second isolation region MS2a, MS2b at the center of the first isolation region MS1 and second isolation region MS2a, MS2b. In addition, since the barrier structure 160 blocks the inflow of the etchant, the region where the sacrificial insulating layer 118 is removed can be more accurately controlled. The region where the sacrificial insulating layer 118 remains may not coincide with the region where the substrate insulating layer 109 is disposed, but is not limited to this.

[0103] Referring to Figures 13a to 13c, a conductive material is filled in the tunnel portion TL to form a gate electrode 130, an isolation insulating layer 105 is formed in the first opening OP1, and a via hole VH is formed in the through wiring region TR to form a through contact plug 170 (see Figure 2a).

[0104] The conductive material forming the gate electrode 130 fills the tunnel portion TL. The conductive material may include metal, polycrystalline silicon, or metal silicide. The side of the gate electrode 130 contacts the side of the barrier structure 160. The barrier structure 160 prevents the conductive material from flowing into the through-via region TR during the formation of the gate electrode 130. After the gate electrode 130 is formed, the conductive material deposited in the first opening OP1 is removed through an additional process. The isolation insulating layer 105 is formed to fill the first opening OP1.

[0105] Before forming the via holes VH, a cell region insulating layer 190 is further formed to cover the isolation insulating layer 105. Next, via holes VH are formed penetrating the cell region insulating layer 190 and the insulating region IR. The circuit wiring lines 280 of the peripheral circuit structure PERI are exposed at the bottom ends of the via holes VH. In this step, holes PH for forming gate contact plugs 175 (see FIG. 2c) connected to the gate electrodes 130 are also formed.

[0106] Next, referring to Figures 1a to 2c, a through wiring region TR is formed by filling the via hole VH with a conductive material to form a through contact plug 170, and an upper plug 178 and a wiring line 180 connected to the upper end of the through contact plug 170 are formed to manufacture the semiconductor device 100.

[0107] FIG. 14 is a schematic diagram of a data storage system including a semiconductor device according to one embodiment of the present invention.

[0108] 14, a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD), a Universal Serial Bus (USB), a computer system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0109] The semiconductor device 1100 is a nonvolatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1 to 7. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is disposed beside the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0110] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to a common source line CSL, upper transistors (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiment.

[0111] In one embodiment, the upper transistors (UT1, UT2) comprise string select transistors, and the lower transistors (LT1, LT2) comprise ground select transistors. The gate lower lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0112] In one embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used in an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0113] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 are electrically connected to the decoder circuit 1110 through first connecting lines 1115 that extend from the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 through second connecting lines 1125 that extend from the first structure 1100F to the second structure 1100S.

[0114] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 through an input / output connecting wiring 1135 extending to the second structure 1100S within the first structure 1100F.

[0115] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0116] The processor 1210 controls the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transmitted through the NAND interface 1221. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0117] FIG. 15 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an embodiment of the present invention.

[0118] 15, a data storage system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001.

[0119] The main board 2001 includes a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In one embodiment, the data storage system 2000 communicates with the external host via one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, the data storage system 2000 operates using power supplied from the external host through the connector 2006. The data storage system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0120] The controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0121] DRAM 2004 is a buffer memory for reducing the speed difference between semiconductor package 2003, which is a data storage space, and an external host. DRAM 2004 included in data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 further includes a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0122] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0123] The package substrate 2100 is a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. The input / output pads 2210 correspond to the input / output pads 1101 in FIG. 14. Each semiconductor chip 2200 includes a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 includes the semiconductor device described above with reference to FIGS. 1 to 7.

[0124] In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 using a bonding wire method.

[0125] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. In another embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0126] Fig. 16 is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present invention, illustrating an exemplary embodiment of the semiconductor package 2003 of Fig. 15, and conceptually illustrating a region obtained by cutting the semiconductor package 2003 of Fig. 15 along cutting line IV-IV'.

[0127] 16, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 (see FIG. 15) disposed on the upper surface of the package substrate body 2120, lower pads 2125 disposed on or exposed through the lower surface of the package substrate body 2120, and internal wiring 2135 electrically connecting the package upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The package upper pads 2130 are electrically connected to a connecting structure 2400. The lower pads 2125 are connected to a wiring pattern 2005 of a main board 2001 of a data storage system 2000 through a conductive connecting part 2800, as shown in FIG. 15.

[0128] Each of the semiconductor chips 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an isolation region 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a gate contact plug 3235 electrically connected to a word line WL (see FIG. 14) of the gate stack structure 3210. As described above with reference to FIGS. 1A to 3, the barrier structure 160 surrounding the through wiring region TR in each of the semiconductor chips 2200 has an inner surface with a protrusion.

[0129] Each of the semiconductor chips 2200 includes a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 is disposed outside the gate stack structure 3210 and is further disposed to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 further includes an input / output pad 2210 (see FIG. 15 ) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0130] The present invention is not limited to the above-described embodiments and drawings, and various substitutions, modifications, and combinations of embodiments may be made by a person having ordinary skill in the art within the scope of the technical idea of the present invention. [Explanation of symbols]

[0131] CH, CHg channel structure CH1 First channel structure CH2 Second channel structure DCH Dummy Channel Structure GS laminated structure IR isolation area MS1 1st separation area MS2a 2nd central separation area MS2b 2nd auxiliary separation area SP, SPa, SPb, SPc seams SS upper separation area TR through wiring area VH Beer Hall 100, 100a-100g, 1100 Semiconductor devices 101 Second board 102 First horizontal conductive layer 103 Upper insulating layer 104 Second horizontal conductive layer 105 Separation insulating layer 109 Substrate insulating layer 110 Horizontal insulation layer 111 First horizontal insulating layer 112 Second horizontal insulating layer 113 Third horizontal insulating layer 118 Sacrificial insulating layer 120 Interlayer insulating layer 125 Upper interlayer insulating layer 130 gate electrode 130L Bottom gate electrode 130M memory gate electrode 130U Upper gate electrode 140 Channel Layer 145 Gate Dielectric Layer 150 channel buried insulation layer 155 Channel Pad 160, 160a-160f Barrier structures 160F horizontal area 160IS inner surface 160H 3rd barrier layer 160L First barrier layer 160M Second barrier layer 160OS outer surface 160P Preliminary Barrier Structure 160S vertical area 162, 162P extension 164, 164a, 164b, 164c, 164P protrusion 170 through contact plug 175 Gate contact plug 178 Upper plug 180 Wiring Line 190 Cell area insulating layer 201 First board 205 Source / Drain Region 210 Element isolation layer 220 Circuit Elements 222 Circuit gate dielectric layer 224 spacer layer 225 Circuit gate electrode 270 Circuit Contact Plug 280 Circuit Wiring Line 290 Peripheral area insulating layer 1000, 2000 data storage system 1100F, 3100 1st structure 1100S, 3200 2nd structure 1101, 2210 Input / Output Pads 1110 decoder circuit 1115 1st connection wiring 1120 page buffers 1125 2nd connection wiring 1130 Logic Circuit 1200, 2002 controller 1210 processor 1220 NAND controller 1221 NAND interface 1230 host interface 2001 Main board 2003 Semiconductor Package 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 package substrate 2120 Package substrate main body 2125 Lower Pad 2130 Package top pad 2135 Internal wiring 2200 semiconductor chips 2300 Adhesive layer 2400 Connected structures 2500 molding layer 2800 Conductive connection part 3010 Semiconductor substrate 3110 Peripheral wiring 3205 Common Source Line 3210 Gate stack structure 3220 Channel Structures 3230 Separation area 3235 Gate Contact Plug 3240 bit lines 3245 Through Wiring

Claims

1. a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a second substrate disposed on the peripheral circuit structure and having a first region and a second region; gate electrodes stacked on the first region and spaced apart from each other along a first direction and extending in a stepped manner along a second direction on the second region; interlayer insulating layers stacked alternately with the gate electrodes; channel structures each including a channel layer penetrating the gate electrodes and extending along the first direction; and memory cell structures each including isolation regions penetrating the gate electrodes and extending in the second direction and spaced apart from each other in a third direction, a through wiring region including a sacrificial insulating layer arranged next to the gate electrode in the second region and alternately stacked with the interlayer insulating layer, and a through contact plug electrically connecting the gate electrode and the circuit element; a barrier structure disposed to surround the through-wiring region and having an inner surface with a plurality of protrusions; the barrier structure has a first horizontal region extending in the second direction and a second horizontal region extending in the third direction, the first horizontal region and the second horizontal region forming a single closed curve; In the first horizontal region, the protrusions protrude in the third direction, and in the second horizontal region, the protrusions protrude in the second direction, The semiconductor device is characterized in that the barrier structure has a flat outer surface in a plan view.

2. 2. The semiconductor device according to claim 1, wherein an outer surface of the barrier structure contacts the gate electrode, and the inner surface contacts the sacrificial insulating layer.

3. 2. The semiconductor device of claim 1, wherein the barrier structure extends a first width and has a second width at the protruding portion, the second width being a maximum width greater than the first width.

4. 4. The semiconductor device according to claim 3, wherein the second width is in the range of 1.3 to 2.5 times the first width.

5. 2. The semiconductor device of claim 1, wherein the barrier structure has seams formed in regions adjacent to each of the protrusions and spaced apart from each other.

6. 2. The semiconductor device according to claim 1, wherein the first horizontal region is aligned with the adjacent isolation region.

7. the barrier structure includes a first barrier layer, a second barrier layer, and a third barrier layer that are sequentially stacked along a side surface and a bottom surface and that contain different materials; The semiconductor device according to claim 1 , wherein the first barrier layer contains a material different from that of the sacrificial insulating layer.

8. a first substrate; a circuit element on the first substrate; a second substrate disposed above the circuit element; Gate electrodes stacked on the second substrate and spaced apart from each other along a first direction; channel structures each including a channel layer extending along the first direction and penetrating the gate electrode; an isolation region extending in a second direction through the gate electrode; a through contact plug extending in the first direction through the second substrate and electrically connecting the gate electrode and the circuit element; a barrier structure disposed to surround the through contact plug and spaced apart from the through contact plug, the barrier structure having a first region with a first width and a second region with a second width greater than the first width; Each of the second regions of the barrier structure has a protrusion protruding from an inner surface of the barrier structure, The semiconductor device is characterized in that the barrier structure has a flat outer surface in a plan view.

9. 10. The semiconductor device of claim 8, wherein the barrier structure includes an extension having the first width in a direction perpendicular to an extension direction, and a protrusion protruding from the extension to have a third width smaller than the first width.

10. a second substrate disposed on the circuit element; gate electrodes stacked on the second substrate and spaced apart from each other along a first direction; channel structures each including a channel layer extending along the first direction and penetrating the gate electrode; an isolation region extending in a second direction and penetrating the gate electrode; a via contact plug extending in the first direction and penetrating the second substrate, electrically connecting the gate electrode and the circuit element; a barrier structure disposed to surround the via contact plug and spaced from the via contact plug, the barrier structure having a first region with a first width and a second region with a second width greater than the first width; and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor storage device through the input / output pads and controlling the semiconductor storage device; In the semiconductor storage device, each of the second regions of the barrier structure has a protrusion protruding from an inner surface of the barrier structure, The barrier structure has an outer surface that is flat in plan view.

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