Active matrix substrate and liquid crystal display device

Abstract

This active matrix substrate comprises, in order, a pixel TFT including an oxide semiconductor layer, a first interlayer insulation layer for covering the oxide semiconductor layer and a gate electrode, a first organic insulation layer, and a pixel electrode. A first pixel contact hole is formed in the first interlayer insulation layer, and a second pixel contact hole is formed in the first organic insulation layer. The pixel electrode is formed from a transparent electroconductive material. A first electrode layer includes a first portion contacting a drain contact region of the oxide semiconductor layer within the first pixel contact hole, and a second portion positioned within the second pixel contact hole. A second electrode layer includes a third portion contacting the second portion, and a fourth portion positioned on the first organic insulation layer. A third electrode layer includes a fifth portion contacting the fourth portion, and a sixth portion positioned on a second organic insulation layer. The length of the second electrode layer along a row direction is equal to or less than the length of the third electrode layer along the row direction. The active matrix substrate also comprises a second organic insulation layer filling the second pixel contact hole.

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate and a liquid crystal display device. [Background technology]

[0002] Currently, liquid crystal display devices equipped with active matrix substrates are widely used for various applications. Active matrix substrates have switching elements for each pixel area. Active matrix substrates that have thin film transistors (TFTs) as switching elements are called TFT substrates.

[0003] The TFT substrate has TFTs and pixel electrodes provided for each pixel region, gate wiring that supplies gate signals to the TFTs, and source wiring that supplies source signals to the TFTs. The gate electrode, source electrode, and drain electrode of the TFT are electrically connected to the gate wiring, source wiring, and pixel electrode, respectively. The TFTs are covered with an interlayer insulating layer (passivation layer).

[0004] An organic insulating layer may be formed on the interlayer insulating layer as a planarizing layer to flatten the surface. The formation of the organic insulating layer can also reduce load capacitance (parasitic capacitance) and power consumption. Photosensitive resin materials are often used as the material for the organic insulating layer. When an organic insulating layer is formed, the pixel electrode is provided on the organic insulating layer, and is connected to the drain electrode of the TFT within a contact hole formed in the organic insulating layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-152744 A Summary of the Invention [Problem to be solved by the invention]

[0006] To achieve sufficient planarization and load capacitance reduction effects, the photosensitive resin material is applied thickly (for example, several micrometers) when forming the organic insulating layer. Therefore, to form contact holes that reliably expose the underlying layer of the organic insulating layer, it is necessary to provide the photosensitive resin material with sufficient exposure energy during exposure so that it is fully exposed in the depth direction. Specifically, exposure is performed by extending the exposure time or increasing the size of the mask pattern so that the area to be removed by photolithography is more reliably exposed. Therefore, to form contact holes reliably (so that the underlying layer is more reliably exposed), the finished diameter of the contact hole must be increased.

[0007] Contact holes cause light leakage due to the disturbance in the alignment of liquid crystal molecules near the contact holes, resulting in a decrease in contrast ratio and display quality. Providing a light-shielding layer that blocks light from the vicinity of the contact holes can prevent the decrease in contrast ratio and display quality, but the area contributing to display in the pixel region is reduced by the amount of the light-shielding layer, resulting in a decrease in transmittance (light utilization efficiency). While liquid crystal display devices have become increasingly high-resolution in recent years, in high-resolution liquid crystal display devices (e.g., 1000 ppi or higher) such as those used in head-mounted displays, the proportion of the pixel region occupied by contact holes increases, resulting in a significant decrease in transmittance as described above.

[0008] Patent Document 1 discloses a pixel structure suitable for increasing the resolution of display devices. In the pixel structure disclosed in Patent Document 1, the drain electrode of the TFT (called a "pedestal" in Patent Document 1) is formed in a layer separate from the source wiring, which makes it possible to arrange the source wiring at a narrow pitch.

[0009] However, even when the pixel structure disclosed in Patent Document 1 is adopted, the vicinity of the contact holes formed in the organic insulating layer must be shielded from light because they cause light leakage, and therefore the decrease in transmittance caused by the contact holes formed in the organic insulating layer remains unresolved.

[0010] The present invention has been made in view of the above-mentioned problems, and its object is to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in an organic insulating layer is suppressed. [Means for solving the problem]

[0011] This specification discloses an active matrix substrate, a liquid crystal display device, and a method for manufacturing an active matrix substrate, as described in the following items.

[0012] [Item 1] a plurality of pixel regions arranged in a matrix including a plurality of rows and a plurality of columns; A substrate; a pixel TFT supported by the substrate and provided corresponding to each of the plurality of pixel regions, the pixel TFT having an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region, a gate insulating layer provided on the channel region of the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween, and a source electrode electrically connected to the source contact region; a gate line extending in the row direction and supplying a gate signal to the pixel TFT; a source line extending in the column direction and supplying a source signal to the pixel TFT; a light-shielding layer located between the substrate and the oxide semiconductor layer and facing at least the channel region of the oxide semiconductor layer; a first interlayer insulating layer provided to cover the oxide semiconductor layer and the gate electrode; a first organic insulating layer located on the first interlayer insulating layer and provided so as to cover the pixel TFT; a pixel electrode including a portion located on the first organic insulating layer and electrically connected to the pixel TFT; An active matrix substrate comprising: a first pixel contact hole is formed in at least the first interlayer insulating layer so as to expose at least a portion of the drain contact region; a second pixel contact hole is formed in the first organic insulating layer so as to at least partially overlap with at least one of the gate line and the light-shielding layer when viewed from a normal direction of the substrate; the pixel electrode includes a first electrode layer, a second electrode layer, and a third electrode layer, each of which is made of a transparent conductive material; the first electrode layer, the second electrode layer, and the third electrode layer are arranged in this order from the substrate side and are electrically connected to each other; the first electrode layer includes a first portion in contact with the drain contact region of the oxide semiconductor layer in the first pixel contact hole and a second portion located in the second pixel contact hole; the second electrode layer includes a third portion that is in contact with the second portion of the first electrode layer in the second pixel contact hole and a fourth portion that is located on the first organic insulating layer; The active matrix substrate comprises: a second organic insulating layer formed to fill the second pixel contact hole and cover the third portion of the second electrode layer; the third electrode layer includes a fifth portion in contact with the fourth portion of the second electrode layer and a sixth portion located on the second organic insulating layer; an active matrix substrate, wherein the length of the second electrode layer along the row direction is equal to or less than the length of the third electrode layer along the row direction;

[0013] [Item 2] the length of the second electrode layer along the row direction is smaller than the length of the third electrode layer along the row direction; Item 1. The active matrix substrate according to item 1, wherein, when viewed from the normal direction of the substrate, both ends of the second electrode layer in the row direction are located inside both ends of the third electrode layer in the row direction.

[0014] [Item 3] a length of the second electrode layer along the row direction is substantially the same as a length of the third electrode layer along the row direction; Item 1. The active matrix substrate according to item 1, wherein, when viewed from the normal direction of the substrate, the positions of both ends of the second electrode layer in the row direction are substantially the same as the positions of both ends of the third electrode layer in the row direction.

[0015] [Item 4] Item 4. The active matrix substrate according to item 3, wherein the second electrode layer and the third electrode layer are formed from the same transparent conductive material.

[0016] [Item 5] 5. The active matrix substrate according to any one of items 1 to 4, wherein the first organic insulating layer is a color filter layer.

[0017] [Item 6] Any two pixel regions adjacent to each other along the column direction among the plurality of pixel regions are referred to as a first pixel region and a second pixel region, When the pixel TFT corresponding to the first pixel region is called a first pixel TFT and the pixel TFT corresponding to the second pixel region is called a second pixel TFT, the second electrode layer of the pixel electrode electrically connected to the first pixel TFT extends in a column direction from within the second pixel contact hole corresponding to the first pixel TFT toward the second pixel region when viewed from a normal direction of the substrate, 6. The active matrix substrate according to any one of items 1 to 5, wherein an end of the second electrode layer on the second pixel region side is covered by the second organic insulating layer in the second pixel contact hole corresponding to the second pixel TFT.

[0018] [Item 7] Any two pixel regions adjacent to each other along the column direction among the plurality of pixel regions are referred to as a first pixel region and a second pixel region, When the pixel TFT corresponding to the first pixel region is called a first pixel TFT and the pixel TFT corresponding to the second pixel region is called a second pixel TFT, one end in a column direction of the third electrode layer of the pixel electrode electrically connected to the first pixel TFT at least partially overlaps with at least one of the gate line corresponding to the first pixel TFT and the light-shielding layer when viewed from a normal direction of the substrate; 7. The active matrix substrate according to any one of items 1 to 6, wherein the other end in the column direction of the third electrode layer of the pixel electrode electrically connected to the first pixel TFT at least partially overlaps with at least one of the gate line corresponding to the second pixel TFT and the light-shielding layer when viewed from the normal direction of the substrate.

[0019] [Item 8] a source contact hole is formed in the first interlayer insulating layer so that at least a portion of the source contact region of the oxide semiconductor layer is exposed; the source electrode is formed on the first interlayer insulating layer and in the source contact hole; 8. The active matrix substrate according to any one of items 1 to 7, further comprising a second interlayer insulating layer located between the first interlayer insulating layer and the first organic insulating layer and covering the source electrode.

[0020] [Item 9] 9. The active matrix substrate according to any one of items 1 to 8, wherein the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

[0021] [Item 10] An active matrix substrate according to any one of items 1 to 9, an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising:

[0022] [Item 11] A method for manufacturing an active matrix substrate according to item 3 or 4, a step (A) of forming the pixel TFT on the substrate; After the step (A), a step (B) of depositing a first transparent conductive film and then patterning the first transparent conductive film to form the first electrode layer; a step (C) of forming the first organic insulating layer covering the pixel TFT and the first electrode layer and having the second pixel contact hole; a step (D) of depositing a second transparent conductive film on the first organic insulating layer and in the second pixel contact hole, and then patterning the second transparent conductive film; After the step (D), a step (E) of forming the second organic insulating layer so as to fill the second pixel contact hole; a step (F) of depositing a third transparent conductive film on the second transparent conductive film, the first organic insulating layer, and the second organic insulating layer, and then simultaneously patterning the third transparent conductive film and further patterning the second transparent conductive film, thereby forming the third electrode layer and the second electrode layer; A method for manufacturing an active matrix substrate, comprising: [Effects of the Invention]

[0023] According to the embodiment of the present invention, it is possible to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in an organic insulating layer is suppressed. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a schematic diagram showing an example of a planar structure of an active matrix substrate 100 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a plan view schematically showing an active matrix substrate 100. [Figure 3] 3A is a cross-sectional view schematically showing the active matrix substrate 100, taken along line 3A-3A' in FIG. [Figure 4]4 is a cross-sectional view schematically showing the active matrix substrate 100, taken along line 4A-4A' in FIG. [Figure 5A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 5D] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 6C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 7A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 7B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 7C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 8A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 8B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 9A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 9B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 10A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 10B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 11] FIG. 10 is a plan view schematically showing another active matrix substrate 200 according to an embodiment of the present invention. [Figure 12A] 1A to 1C are plan views showing the manufacturing process of the active matrix substrate 200. [Figure 12B] 1A to 1C are plan views showing the manufacturing process of the active matrix substrate 200. [Figure 12C] 1A to 1C are plan views showing the manufacturing process of the active matrix substrate 200. [Figure 12D] 1A to 1C are plan views showing the manufacturing process of the active matrix substrate 200. [Figure 12E] 1A to 1C are plan views showing the manufacturing process of the active matrix substrate 200. [Figure 13A] FIG. 10 is a cross-sectional view schematically showing still another active matrix substrate 300 according to an embodiment of the present invention. [Figure 13B] FIG. 2 is a cross-sectional view schematically showing an active matrix substrate 300. [Figure 14] FIG. 1 is a cross-sectional view that schematically shows a liquid crystal display device 1000 that includes an active matrix substrate 100 (200, 300) according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, an active matrix substrate for a FFS (Fringe Field Switching) mode liquid crystal display device will be exemplified as an embodiment of the present invention, but the present invention is not limited to the following embodiment.

[0026] (Embodiment 1) An active matrix substrate 100 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing an example of the planar structure of the active matrix substrate 100.

[0027] As shown in FIG. 1, the active matrix substrate 100 has a display region DR and a non-display region (also called a "frame region") FR. The display region DR is defined by a plurality of pixel regions P. The pixel regions P are arranged in a matrix having a plurality of rows and a plurality of columns. The pixel regions P correspond to the pixels of the liquid crystal display device, and may also be simply called "pixels." The non-display region FR is located on the periphery of the display region DR and does not contribute to display.

[0028] In the display region DR, a plurality of gate lines GL extending in the row direction and a plurality of source lines SL extending in the column direction are formed. Each pixel region P is, for example, a region surrounded by a pair of adjacent gate lines GL and a pair of adjacent source lines SL.

[0029] Peripheral circuits are arranged in the non-display area FR. Here, the non-display area FR is monolithically formed with a gate driver GD for driving the gate lines GL, and a source driver SD for driving the source lines SL. The non-display area FR also includes a source shared driving circuit (SCD) for driving the source bus lines SL in a time-division manner. An SSD circuit or the like may be further disposed, and the SSD circuit or the like may be formed integrally with the gate driver GD.

[0030] Also arranged in the display region DR are thin film transistors (TFTs) 10 provided corresponding to each pixel region P, and pixel electrodes 17 electrically connected to the TFTs 10. The TFTs 10 are hereinafter referred to as "pixel TFTs." The pixel TFTs 10 are supplied with gate signals (scanning signals) from the corresponding gate lines GL, and with source signals (display signals) from the corresponding source lines SL.

[0031] Next, a more specific configuration of the active matrix substrate 100 will be described with reference to Figures 2, 3, and 4. Figure 2 is a plan view schematically showing the active matrix substrate 100. Figures 3 and 4 are cross-sectional views schematically showing the active matrix substrate 100, showing cross sections taken along lines 3A-3A' and 4A-4A' in Figure 2, respectively.

[0032] As shown in Figures 2, 3 and 4, the active matrix substrate 100 comprises a substrate 1, a pixel TFT 10 supported by the substrate 1, a first organic insulating layer (planarizing layer) 11 provided to cover the pixel TFT 10, and a pixel electrode 17 including a portion located on the first organic insulating layer 11.

[0033] The substrate 1 is transparent and insulating, and is, for example, a glass substrate or a plastic substrate.

[0034] A light-shielding layer 2 is provided on a substrate 1. A lower insulating layer 3 is provided to cover the light-shielding layer 2.

[0035] The pixel TFT 10 is provided corresponding to each pixel region P. The pixel TFT 10 has an oxide semiconductor layer 4, a gate insulating layer 5, a gate electrode 6, and a source electrode 7. The pixel TFT 10 has a top gate structure.

[0036] The oxide semiconductor layer 4 is provided on the lower insulating layer 3. The oxide semiconductor layer 4 includes a channel region 4c and a source contact region 4s and a drain contact region 4d located on either side of the channel region 4c. The oxide semiconductor layer 4 is made of a transparent oxide semiconductor material. The light-shielding layer 2 is located between the oxide semiconductor layer 4 and the substrate 1 and faces at least the channel region 4c of the oxide semiconductor layer 4.

[0037] In the illustrated example, the oxide semiconductor layer 4 is formed so that one end overlaps the source wiring SL and the other end is located approximately in the center between the two source wirings SL. The portion of the oxide semiconductor layer 4 connecting one end and the other end extends diagonally across the gate wiring GL (in a direction inclined with respect to the column direction). The source contact region 4s and the drain contact region 4d of the oxide semiconductor layer 4 have lower resistance than the channel region 4c (the region overlapping the gate wiring GL).

[0038] The gate insulating layer 5 is provided on the channel region 4c of the oxide semiconductor layer 4. The gate electrode 6 is provided on the gate insulating layer 5 and faces the channel region 4c of the oxide semiconductor layer 4 via the gate insulating layer 5. The gate electrode 6 is electrically connected to a corresponding gate wiring GL. In the illustrated example, a part of the gate wiring GL (specifically, the part facing the oxide semiconductor layer 4) functions as the gate electrode 6.

[0039] A first interlayer insulating layer 8 is provided to cover the gate electrode 6 and the oxide semiconductor layer 4. A source electrode 7 is provided on the first interlayer insulating layer 8. A contact hole (hereinafter referred to as a "source contact hole") CHs is formed in the first interlayer insulating layer 8 so as to expose at least a portion of the source contact region 4s of the oxide semiconductor layer 4. The source electrode 7 is formed on the first interlayer insulating layer 8 and in the source contact hole CHs, and is in contact with the source contact region 4s in the source contact hole CHs and is electrically connected to the source contact region 4s. The source electrode 7 is electrically connected to a corresponding source wiring SL. In the illustrated example, a portion of the source wiring SL functions as the source electrode 7.

[0040] A second interlayer insulating layer 9 is provided to cover the pixel TFT 10. The second interlayer insulating layer 9 is located between the first interlayer insulating layer 8 and the first organic insulating layer 11, and covers the source electrode 7. A first pixel contact hole CHp1 is formed in the second interlayer insulating layer 9 and the first interlayer insulating layer 8 so that at least a portion of the drain contact region 4d of the oxide semiconductor layer 4 is exposed.

[0041] A first organic insulating layer 11 is formed on the second interlayer insulating layer 9 (naturally, so as to be located on the first interlayer insulating layer 8). The first organic insulating layer 11 is made of, for example, a photosensitive resin material. A second pixel contact hole CHp2 is formed in the first organic insulating layer 11. The second pixel contact hole CHp2 is formed so as to at least partially overlap at least one of the gate line GL and the light-shielding layer 2 (here, both) when viewed from the normal direction of the substrate 1.

[0042] The pixel electrode 17 includes a portion located on the first organic insulating layer 11. In this embodiment, the pixel electrode 17 includes a first electrode layer (lower electrode layer) PL1, a second electrode layer (intermediate electrode layer) PL2, and a third electrode layer (upper electrode layer) PL3, each of which is formed from a transparent conductive material. The first electrode layer PL1, the second electrode layer PL2, and the third electrode layer PL3 are arranged in this order from the substrate 1 side. The first electrode layer PL1, the second electrode layer PL2, and the third electrode layer PL3 are electrically connected to each other.

[0043] The first electrode layer PL1 is formed on the second interlayer insulating layer 9 and in the first pixel contact hole CHp1. The first electrode layer PL1 includes a portion p1 (hereinafter referred to as the "first portion") that is in contact with the drain contact region 4d of the oxide semiconductor layer 4 in the first pixel contact hole CHp1, and a portion p2 (hereinafter referred to as the "second portion") that is located in the second pixel contact hole CHp2. The first electrode layer PL1 functions as a connection electrode that electrically connects the drain contact region 4d of the oxide semiconductor layer 4 and the second electrode layer PL2.

[0044] The second electrode layer PL2 is formed on the first organic insulating layer 11 and in the second pixel contact hole CHp2. The second electrode layer PL2 includes a portion p3 (hereinafter referred to as the "third portion") that contacts the second portion p2 of the first electrode layer PL1 in the second pixel contact hole CHp2, and a portion p4 (hereinafter referred to as the "fourth portion") that is located on the first organic insulating layer 11. The second electrode layer PL2 functions as a connection electrode that electrically connects the first electrode layer PL1 and the third electrode layer PL3.

[0045] The active matrix substrate 100 of this embodiment further includes a second organic insulating layer 12 formed to fill the second pixel contact hole CHp2. The second organic insulating layer 12 covers the third portion p3 of the second electrode layer PL2. The second organic insulating layer 12 is made of, for example, a photosensitive resin material.

[0046] The third electrode layer PL3 is formed on the first organic insulating layer 11, the second electrode layer PL2, and the second organic insulating layer 12. The third electrode layer PL3 includes a portion p5 (hereinafter referred to as the "fifth portion") that contacts the fourth portion p4 of the second electrode layer PL2, and a portion p6 (hereinafter referred to as the "sixth portion") that is located on the second organic insulating layer 12.

[0047] The length L2 (see FIG. 2) of the second electrode layer PL2 in the row direction is equal to or less than the length L3 (see FIG. 2) of the third electrode layer PL3 in the row direction. More specifically, as shown in FIG. 2, the length L2 of the second electrode layer PL2 in the row direction is shorter than the length L3 of the third electrode layer PL3 in the row direction. Furthermore, when viewed from the normal direction of the substrate 1, both ends of the second electrode layer PL2 in the row direction are located more inward than both ends of the third electrode layer PL3 in the row direction.

[0048] A dielectric layer 18 is provided to cover the pixel electrodes 17. A common electrode 19 is provided on the dielectric layer 18 so as to face the pixel electrodes 17. Although not shown here, at least one slit is formed in the common electrode 19 for each pixel region P.

[0049] As described above, the active matrix substrate 100 of this embodiment includes the second organic insulating layer 12 formed to fill the second pixel contact hole CHp2. This flattens the step caused by the second pixel contact hole CHp2, thereby suppressing the occurrence of alignment disturbance of liquid crystal molecules due to the second pixel contact hole CHp2. Therefore, there is no need to shield the second pixel contact hole CHp2 and its vicinity from light, and the area above and its vicinity can be used as an opening (a region contributing to display), thereby improving transmittance. The first electrode layer PL1, second electrode layer PL2, and third electrode layer PL3 included in the pixel electrode 17 are all formed of transparent conductive materials, so that the inclusion of these electrode layers in the pixel electrode 17 does not substantially reduce transmittance. Furthermore, since the first electrode layer PL1, including the portion (first portion) p1 that contacts the drain contact region 4d of the oxide semiconductor layer 4, is formed from a transparent conductive material, the area above the first pixel contact hole CHp1 (i.e., the area around the drain contact region 4d) can also be used as an opening, thereby further improving the transmittance.

[0050] Furthermore, in the active matrix substrate 100 of this embodiment, the length L2 of the second electrode layer PL2 along the row direction is smaller than the length L3 of the third electrode layer PL3 along the row direction, and both ends of the second electrode layer PL2 along the row direction are located inside both ends of the third electrode layer PL3 along the row direction. This suppresses the generation of unnecessary parasitic capacitance. For example, if the length L2 of the second electrode layer PL2 along the row direction is the same as the length L3 of the third electrode layer PL3 along the row direction, and the second electrode layer PL2 protrudes from the third electrode layer PL3 due to misalignment between the second electrode layer PL2 and the third electrode layer PL3, the width (length along the row direction) of the pixel electrode 17 may become larger than the width (length L3 along the row direction) of the third electrode layer PL3. In this case, the parasitic capacitance between the pixel electrode 17 and the source line SL increases, which may worsen crosstalk. In contrast, in the active matrix substrate 100 of this embodiment, both ends of the second electrode layer PL2 in the row direction are located inside both ends of the third electrode layer PL3 in the row direction, so that even if misalignment occurs between the second electrode layer PL2 and the third electrode layer PL3, it is possible to prevent both ends of the second electrode layer PL2 from protruding beyond both ends of the third electrode layer PL3. As a result, the generation of unnecessary parasitic capacitance is suppressed. 3 The difference between the length L2 of the second electrode layer PL2 along the row direction and the length L3 of the third electrode layer PL3 along the row direction is set according to the expected amount of misalignment. For example, the length L2 of the second electrode layer PL2 along the row direction is set to be 1 μm or more shorter than the length L3 of the third electrode layer PL3 along the row direction.

[0051] Furthermore, in this embodiment, the third electrode layer PL3 includes a portion (sixth portion) p6 located on the second organic insulating layer 12, which widens the area where the distance between the pixel electrode 17 and the common electrode 19 is kept constant and widens the area where a fringe electric field of sufficient strength is generated, thereby also improving the transmittance.

[0052] Here, among the multiple pixel regions P, any two pixel regions P adjacent to each other in the column direction will be referred to as the "first pixel region" and the "second pixel region." For example, in FIG. 2, the pixel region P shown in its entirety will be referred to as the first pixel region, and the pixel region P located above the first pixel region in the drawing will be referred to as the second pixel region. The pixel TFT 10A corresponding to the first pixel region will be referred to as the "first pixel TFT," and the pixel TFT 10B corresponding to the second pixel region will be referred to as the "second pixel TFT."

[0053] The second electrode layer PL2 of the pixel electrode 17 connected to the first pixel TFT 10A extends in the column direction from within the second pixel contact hole CHp2 corresponding to the first pixel TFT 10A toward the second pixel region side when viewed from the normal direction of the substrate 1. In the example shown in Fig. 4, the end of this second electrode layer PL2 on the second pixel region side is covered by the second organic insulating layer 12 within the second pixel contact hole CHp2 corresponding to the second pixel TFT 10B. By adopting this configuration, the occurrence of a step due to the end of the second electrode layer PL2 on the second pixel region side (i.e., the end opposite the third portion p3) is suppressed, and light leakage due to such a step can be suppressed.

[0054] 2 and other examples, one end in the column direction of the third electrode layer PL3 of the pixel electrode 17 electrically connected to the first pixel TFT 10A at least partially overlaps with at least one (here, both) of the gate line GL and the light-shielding layer 2 corresponding to the first pixel TFT 10A when viewed from the normal direction of the substrate 1. The other end in the column direction of the third electrode layer PL3 of the pixel electrode 17 electrically connected to the first pixel TFT 10A at least partially overlaps with at least one (here, both) of the gate line GL and the light-shielding layer 2 corresponding to the second pixel TFT 10B when viewed from the normal direction of the substrate 1. By adopting such a configuration, the third electrode layer PL3 widely covers the opening in the column direction, thereby further improving the transmittance.

[0055] The light-shielding layer 2 is made of a material having light-shielding properties. The light-shielding layer 2 may be made of a conductive material having light-shielding properties. The conductive light-shielding layer 2 may be in an electrically floating state (floating), or may be given a predetermined potential. By giving the light-shielding layer 2 a predetermined potential (fixed potential), the TFT characteristics of the pixel TFT 10 can be improved. Furthermore, the light-shielding layer 2 may be given substantially the same potential as the gate electrode 6, so that it functions as a lower gate electrode. In other words, the pixel TFT 10 may have a double-gate structure.

[0056] As described above, the active matrix substrate 100 of this embodiment can improve the transmittance, and is therefore suitable for use in high-definition (e.g., 1000 ppi or more) liquid crystal display devices such as liquid crystal display devices for head-mounted displays.

[0057] 5A to 10B, an example of a method for manufacturing the active matrix substrate 100 of this embodiment will be described. 5A to 10B are cross-sectional views showing the manufacturing process of the active matrix substrate 100.

[0058] 5A, a light-shielding layer 2 is formed on a substrate 1. For example, the light-shielding layer 2 can be formed by depositing a conductive film for the light-shielding layer by a sputtering method, and then patterning the conductive film for the light-shielding layer by a photolithography process.

[0059] The substrate 1 may be, for example, a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate). The conductive film for the light-shielding layer may be a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or an alloy thereof, or a metal nitride thereof. A laminated film obtained by laminating a plurality of these films may also be used. Here, a film obtained by laminating a tantalum nitride (TaN) film and a W film in this order is used as the conductive film for the light-shielding layer. The thickness of the conductive film for the light-shielding layer is, for example, 100 nm or more and 500 nm or less.

[0060] Next, as shown in FIG. 5B, a lower insulating layer 3 is formed to cover the light-shielding layer 2. For example, the lower insulating layer 3 can be formed by a CVD method. The lower insulating layer 3 can be formed from a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, a silicon nitride oxide (SiNxOy;x>y) layer, or the like, as appropriate. The lower insulating layer 3 may have a laminated structure. For example, a SiNx layer may be formed as a lower layer on the substrate 1 side to prevent the diffusion of impurities from the substrate 1, and a SiO2 layer may be formed as an upper layer thereon to ensure insulation. The thickness of the lower insulating layer 3 is, for example, 150 nm or more and 400 nm or less.

[0061] Next, as shown in FIG. 5C , an oxide semiconductor layer 4 is formed on the lower insulating layer 3. For example, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned by a photolithography process to form island-shaped oxide semiconductor layers 4. The oxide semiconductor layer 4 is formed so as to face the light-shielding layer 2 with the lower insulating layer 3 interposed therebetween. Here, an In-Ga-Zn-O-based semiconductor layer having a composition ratio of In:Ga:Zn=1:1:1 is formed as the oxide semiconductor layer 4. The thickness of the oxide semiconductor layer 4 is, for example, 10 nm or more and 200 nm or less.

[0062] Next, as shown in FIG. 5D, a gate insulating layer 5 is deposited to cover the oxide semiconductor layer 4. The gate insulating layer 5 is deposited by, for example, a CVD method. Then, the oxide semiconductor layer 4 is oxidized (e.g., baked or peroxidized). The gate insulating layer 5 may be, for example, an insulating layer similar to the lower insulating layer 3 (exemplified as the lower insulating layer 3). Here, a silicon oxide (SiO2) layer is formed as the gate insulating layer 5. When an oxide layer such as a silicon oxide layer is used as the gate insulating layer 5, the oxide layer can reduce oxygen vacancies occurring in the channel region 4c of the oxide semiconductor layer 4, thereby preventing the resistance of the channel region from decreasing. The thickness of the gate insulating layer 5 is, for example, 50 nm to 150 nm.

[0063] Next, as shown in FIG. 6A, a gate wiring GL including a gate electrode 6 is formed on the gate insulating layer 5. For example, the gate wiring GL can be formed by depositing a conductive film (gate metal film) by sputtering and then patterning the gate metal film by a photolithography process. The gate insulating layer 5 is then patterned. The gate insulating layer 5 can also be patterned together with the gate metal film. The gate metal film can be, for example, a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or an alloy thereof, or a metal nitride thereof. Here, a film formed by stacking a Ti film, an Al film, and a Ti film in this order is used as the gate metal film. The thickness of the gate metal film is, for example, 100 nm to 400 nm.

[0064] Thereafter, the oxide semiconductor layer 4 may be subjected to a resistance-reducing treatment using the gate insulating layer 5 and the gate electrode 6 as a mask. For example, plasma treatment can be used as the resistance-reducing treatment. As a result of the resistance-reducing treatment, the regions of the oxide semiconductor layer 4 that do not overlap with the gate insulating layer 5 and the gate electrode 6 (regions that will become the source contact region 4s and the drain contact region 4d) become low-resistance regions with lower resistivity than the regions of the oxide semiconductor layer 4 that overlap with the gate insulating layer 5 and the gate electrode 6 (regions that will become the channel region 4c). The low-resistance regions may be conductive regions (e.g., sheet resistance: 200 Ω / □ or less). The plasma treatment may be performed using the gate electrode 6 as a mask without patterning the gate insulating layer 5. In this case, the photolithography process for the gate insulating layer 5 can be omitted, thereby shortening the manufacturing process. The resistance-reducing treatment method is not limited to plasma treatment. For example, the exposed regions of the oxide semiconductor layer 4 can be reduced by contacting them with a reducing insulating film that can reduce the oxide semiconductor. Alternatively, the resistance can be reduced by an ion implantation process such as ion doping into the oxide semiconductor layer 4. In this case, the ion implantation process can be performed through the gate insulating layer 5, so that the process can be shortened.

[0065] Next, as shown in FIG. 6B, a first interlayer insulating layer 8 is formed to cover the oxide semiconductor layer 4 and the gate electrode 6. For example, the first interlayer insulating layer 8 can be formed by a CVD method. The first interlayer insulating layer 8 can be a single layer or a stack of inorganic insulating layers such as a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, or a silicon nitride oxide (SiNxOy;x>y) layer. The thickness of the first interlayer insulating layer 8 is, for example, 200 nm or more and 700 nm or less. Here, a silicon oxide layer is used as the first interlayer insulating layer 8.

[0066] Subsequently, as shown in FIG. 6C, a source contact hole CH is formed in the first interlayer insulating layer 8 so as to expose a part of the source contact region 4s of the oxide semiconductor layer 4. s Form a source contact hole CH s can be formed by patterning the first interlayer insulating layer 8 by a photolithography process, for example.

[0067] Next, as shown in FIG. 7A, a source wiring SL including a source electrode 7 is formed on the first interlayer insulating layer 8. For example, the source wiring SL can be formed by depositing a conductive film by sputtering and then patterning the conductive film by a photolithography process. The conductive film (source metal film) for forming the source wiring SL can be appropriately made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), or titanium (Ti), or an alloy thereof, or a metal nitride thereof. A laminated film obtained by laminating a plurality of these films may also be used. Here, a film obtained by laminating a Ti film, an Al film, and a Ti film in this order is used as the source metal film. The thickness of the source metal film is, for example, 200 nm to 700 nm.

[0068] Next, as shown in FIG. 7B, a second interlayer insulating layer 9 is formed to cover the pixel TFT 10. For example, the second interlayer insulating layer 9 can be formed by a CVD method. The second interlayer insulating layer 9 can be a single layer or a stack of inorganic insulating layers such as a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, or a silicon nitride oxide (SiNxOy;x>y) layer. The thickness of the second interlayer insulating layer 9 is, for example, 100 nm or more and 600 nm or less. Here, a silicon nitride layer is used as the second interlayer insulating layer 9.

[0069] 7C, a first pixel contact hole CHp1 is formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 so as to expose a portion of the drain contact region 4d of the oxide semiconductor layer 4. The first pixel contact hole CHp1 can be formed, for example, by patterning the first interlayer insulating layer 8 and the second interlayer insulating layer 9 using a photolithography process. The first pixel contact hole CHp1 is formed, for example, to have a size of 1.5 μm to 2.5 μm square.

[0070] Next, as shown in FIG. 8A, a first electrode layer PL1 is formed on the second interlayer insulating layer 9 and in the first pixel contact hole CHp1. For example, the first electrode layer PL1 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the first electrode layer PL1 include indium tin oxide (ITO) and indium zinc oxide (IZO). In this example, indium zinc oxide is used. The thickness of the first electrode layer PL1 is, for example, 30 nm or more and 100 nm or less.

[0071] Next, as shown in FIG. 8B, a first organic insulating layer 11 is formed to cover the second interlayer insulating layer 9 and the first electrode layer PL1. For example, by applying a photosensitive resin material and then performing exposure and development, the first organic insulating layer 11 is obtained in which the second pixel contact hole CHp2 is formed so that a part of the first electrode layer PL1 is exposed. For example, a photosensitive acrylic resin can be used as the photosensitive resin material. The second pixel contact hole CHp2 is formed to have, for example, a size of 2.5 μm to 3.5 μm square.

[0072] Next, as shown in FIG. 9A, a second electrode layer PL2 is formed on the first organic insulating layer 11 and in the second pixel contact hole CHp2. For example, the second electrode layer PL2 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the second electrode layer PL2 include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the second electrode layer PL2 is, for example, 30 nm or more and 100 nm or less.

[0073] Next, as shown in FIG. 9B, a second organic insulating layer 12 is formed to fill the second pixel contact hole CHp2. For example, the second organic insulating layer 12 can be obtained by applying a photosensitive resin material, exposing it to light, and developing it. For example, a photosensitive acrylic resin can be used as the photosensitive resin material. By using a multi-tone mask as a mask during exposure, the second pixel contact hole CHp2 can be accurately filled with the second organic insulating layer 12. Specifically, a gray-tone mask or a half-tone mask can be used as the multi-tone mask. A gray-tone mask has slits formed in it that are smaller than the resolution of the exposure machine, and these slits block part of the light, thereby achieving intermediate exposure. On the other hand, a half-tone mask uses a semi-transparent film to achieve intermediate exposure.

[0074] Next, as shown in FIG. 10A, a third electrode layer PL3 is formed on the first organic insulating layer 11, the second electrode layer PL2, and the second organic insulating layer 12. For example, the third electrode layer PL3 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the third electrode layer PL3 include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the third electrode layer PL3 is, for example, 30 nm or more and 100 nm or less.

[0075] Next, as shown in FIG. 10B, a dielectric layer 18 is formed to cover the third electrode layer PL3. For example, the dielectric layer 18 can be formed by a CVD method. For example, an inorganic insulating layer similar to the first interlayer insulating layer 8 and the second interlayer insulating layer 9 can be used as the dielectric layer 18. Here, a silicon nitride layer is used as the dielectric layer 18. The thickness of the dielectric layer 18 is, for example, not less than 50 nm and not more than 300 nm.

[0076] Thereafter, a common electrode 19 is formed on the dielectric layer 18, thereby obtaining the active matrix substrate 100 shown in FIG. 3 and other figures. For example, the common electrode 19 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the common electrode 19 include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the common electrode is, for example, 30 nm or more and 100 nm or less. In this manner, the active matrix substrate 100 is obtained.

[0077] (Embodiment 2) An active matrix substrate 200 according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a plan view schematically showing the active matrix substrate 200. The following description will focus on differences between the active matrix substrate 200 and the active matrix substrate 100 according to the first embodiment.

[0078] 11, in the active matrix substrate 200, the length L2 of the second electrode layer PL2 of the pixel electrode 17 along the row direction is substantially the same as the length L3 of the third electrode layer PL3 along the row direction. When viewed from the normal direction of the substrate 1, the positions of both ends of the second electrode layer PL2 in the row direction are substantially the same as the positions of both ends of the third electrode layer PL3 in the row direction. The second electrode layer PL2 and the third electrode layer PL3 are formed, for example, from the same transparent conductive material.

[0079] As described above, in the active matrix substrate 200 of this embodiment, the positions of both ends of the second electrode layer PL2 in the row direction are substantially the same as the positions of both ends of the third electrode layer PL3 in the row direction, which prevents the occurrence of an unnecessary step in the opening of the pixel region P and suppresses light leakage.

[0080] The active matrix substrate 200 can be manufactured, for example, as follows.

[0081] First, the pixel TFT 10 and the second interlayer insulating layer 9 are formed in this order on the substrate 1 in the same manner as described with reference to FIGS. 5A to 7C.

[0082] Next, the first electrode layer PL1 is formed in the same manner as described with reference to Fig. 8A. Specifically, after depositing a transparent conductive film (hereinafter referred to as "first transparent conductive film"), the first transparent conductive film is patterned to form the first electrode layer PL1.

[0083] Subsequently, in the same manner as described with reference to FIG. 8B, the first organic insulating layer 11 is formed to cover the pixel TFT 10 and the first electrode layer PL1 and to have the second pixel contact hole CHp2.

[0084] Next, as shown in FIG. 12A, a transparent conductive film (hereinafter referred to as the "second transparent conductive film") tc2 is deposited on the first organic insulating layer 11 and in the second pixel contact hole CHp2, and then the second transparent conductive film tc2 is patterned. The material of the second transparent conductive film tc2 is selected to be soluble in the etchant used to pattern the transparent conductive film for forming the third electrode layer PL3 (i.e., a material with a sufficiently high etching rate). After patterning, the second transparent conductive film tc2 is separated between adjacent pixel regions P in the column direction, but is continuous between adjacent pixel regions P in the row direction. Note that some components are omitted in FIG. 12A (and FIGS. 12B to 12E, described later) for ease of understanding.

[0085] 12B, the second organic insulating layer 12 is formed so as to fill the second pixel contact hole CHp2. As already explained, this step can be suitably carried out using a multi-tone mask.

[0086] Next, a transparent conductive film (hereinafter referred to as the "third transparent conductive film") is deposited on the second transparent conductive film tc2, the first organic insulating layer 11, and the second organic insulating layer 12, and then the third transparent conductive film is patterned and the second transparent conductive film tc2 is further patterned (for a second time) simultaneously to form the third electrode layer PL3 and the second electrode layer PL2.

[0087] Specifically, as shown in FIG. 12C, first, a third transparent conductive film tc3 is deposited on the second transparent conductive film tc2, the first organic insulating layer 11, and the second organic insulating layer 12. Next, as shown in FIG. 12D, a resist mask RM having a predetermined mask pattern is formed on the third transparent conductive film tc3. Thereafter, etching is performed to remove portions of the third transparent conductive film tc3 and the second transparent conductive film tc2 that are not covered by the resist mask RM, thereby forming a third electrode layer PL3 and a second electrode layer PL2, as shown in FIG. 12E. At this time, portions of the second transparent conductive film tc2 that are continuous in the row direction between pixel regions P are removed, thereby obtaining second electrode layers PL2 that are separated in the row direction.

[0088] Thereafter, a dielectric layer 18 is formed to cover the third electrode layer PL3, and then a common electrode 19 is formed on the dielectric layer 18, thereby obtaining the active matrix substrate 200. The above-described manufacturing method suppresses an increase in parasitic capacitance caused by forming the second electrode layer PL2 to protrude from the third electrode layer PL3.

[0089] (Embodiment 3) An active matrix substrate 300 according to this embodiment will be described with reference to Figures 13A and 13B. Figures 13A and 13B are cross-sectional views schematically showing the active matrix substrate 300, and correspond to the cross sections of the active matrix substrate 100 according to Embodiment 1 shown in Figures 3 and 4. The following description will focus on the differences between the active matrix substrate 300 and the active matrix substrate 100 according to Embodiment 1.

[0090] The first organic insulating layer 11A included in the active matrix substrate 300 of this embodiment is a color filter layer. The color filter layer includes, for example, a red color filter, a green color filter, and a blue color filter. The first organic insulating layer 11A, which is a color filter layer, is formed, for example, from a photosensitive resin material (color resist) in which a pigment is dispersed. If necessary, a further organic insulating layer (third organic insulating layer) may be provided on the first organic insulating layer 11A as a planarizing layer.

[0091] By using an active matrix substrate 300 having a color filter layer (first organic insulating layer 11A) as the active matrix substrate of a liquid crystal display device, a color filter on array (COA) structure can be realized. A structure in which a color filter layer is provided on the opposing substrate (called an "opposing CF structure") is a common structure for achieving color display. However, in the opposing CF structure, there is a risk of color mixing due to misalignment between the two substrates, and this color mixing becomes more pronounced in high-resolution liquid crystal display devices. In contrast, the COA structure can prevent color mixing due to misalignment.

[0092] [About oxide semiconductors] The oxide semiconductor contained in the oxide semiconductor layer 4 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axes are oriented approximately perpendicular to the layer surface.

[0093] The oxide semiconductor layer 4 may have a stacked structure of two or more layers. The oxide semiconductor layer 4 having a stacked structure may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer, or may include multiple crystalline oxide semiconductor layers with different crystal structures. Furthermore, the oxide semiconductor layer 4 having a stacked structure may include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer 4 has a stacked structure, the energy gaps of the layers may be different from each other.

[0094] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described, for example, in JP 2014-007399 A. The entire disclosure of JP 2014-007399 A is incorporated herein by reference.

[0095] The oxide semiconductor layer 4 may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In the above-described embodiment, the oxide semiconductor layer 4 contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer 4 may be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0096] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor with its c-axis oriented generally perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0097] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-007399, 2012-134475, and 2014-209727. The disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference in their entirety. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0098] The oxide semiconductor layer 4 may contain other oxide semiconductors instead of the In-Ga-Zn-O based semiconductor. For example, it may contain an In-Sn-Zn-O based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 4 may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, or the like.

[0099] (Liquid crystal display device) The active matrix substrates 100, 200 and 300 according to the embodiments of the present invention can be suitably used in a liquid crystal display device. An example of a liquid crystal display device is shown in FIG.

[0100] The liquid crystal display device 1000 shown in Figure 14 includes an active matrix substrate 100 (or active matrix substrates 200, 300), a counter substrate 500 arranged opposite to the active matrix substrate 100, and a liquid crystal layer 30 arranged between the active matrix substrate 100 and the counter substrate 500.

[0101] The active matrix substrate 100 includes a pixel TFT 10 (not shown) arranged in each pixel region P, a pixel electrode 17 electrically connected to the pixel TFT 10, a dielectric layer 18 provided to cover the pixel electrode 17, and a common electrode 19 provided on the dielectric layer 18 and facing the pixel electrode 17. At least one slit 19a is formed in the common electrode 19 for each pixel region P.

[0102] Alignment films 31 and 32 are provided on the outermost surfaces of the active matrix substrate 100 and the counter substrate 500 facing the liquid crystal layer 30, respectively. The counter substrate 500 has a color filter layer (not shown). When the active matrix substrate 300 is used instead of the active matrix substrate 100, the counter substrate 500 does not have a color filter layer. The thickness (cell gap) of the liquid crystal layer 30 is determined by columnar spacers (not shown) provided on the counter substrate 500 facing the liquid crystal layer 30.

[0103] The liquid crystal display device 1000 is suitable for use in high-definition (e.g., 1000 ppi or more) liquid crystal display devices, such as liquid crystal display devices for head-mounted displays. Liquid crystal display devices for head-mounted displays require not only high definition but also high-speed response. To achieve high-speed response, positive-type liquid crystal materials, which have lower viscosity than negative-type liquid crystal materials, are advantageous. When using positive-type liquid crystal materials, the initial alignment axes of the liquid crystal molecules are set approximately parallel to the extension direction of the slits 19a. For example, when the slits 19a extend in the column direction, the initial alignment axes of the liquid crystal molecules are set approximately parallel to the column direction.

[0104] Although light leakage due to steps in the direction along the initial alignment axis is slight and not a problem, light leakage due to steps in the direction perpendicular to the initial alignment axis may be problematic. In the liquid crystal display device 1000 including the active matrix substrate 100 (or the active matrix substrates 200, 300), the latter steps are flattened by the second organic insulating layer 12, thereby suppressing light leakage.

[0105] Although the liquid crystal display device 1000 of the FFS mode, which is a type of horizontal electric field mode, has been illustrated here, the active matrix substrate according to the embodiment of the present invention may be used in a liquid crystal display device of other display modes. In a liquid crystal display device of a vertical electric field mode such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, the common electrode is disposed between the opposing It is provided on the substrate side. [Industrial Applicability]

[0106] According to an embodiment of the present invention, it is possible to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in an organic insulating layer is suppressed. The active matrix substrate according to an embodiment of the present invention is suitable for use in high-resolution (e.g., 1000 ppi or higher) liquid crystal display devices such as liquid crystal display devices for head-mounted displays. [Explanation of symbols]

[0107] 1 board 2 Light blocking layer 3 Lower insulating layer 4. Oxide semiconductor layer 4c Channel region 4s Source Contact Area 4d Drain contact area 5 Gate insulating layer 6 gate electrode 7. Source electrode 8 First interlayer insulating layer 9 Second interlayer insulating layer 10 pixel TFT 11 First organic insulating layer 12 Second organic insulating layer 17 Pixel electrode 18 Dielectric Layer 19 Common electrode 30 Liquid crystal layer 31, 32 Alignment film 100, 200, 300 Active matrix substrate 500 Opposite substrate 1000 lcd display device DR display area FR hidden area P pixel area GL gate wiring SL Source wiring GD Gate driver SD Source Driver CHp1 1st pixel contact hole CHp2 2nd pixel contact hole CH sSource Contact Hole PL1 1st electrode layer PL2 2nd electrode layer PL3 3rd electrode layer

Claims

1. a plurality of pixel regions arranged in a matrix including a plurality of rows and a plurality of columns; A substrate; a pixel TFT supported by the substrate and provided corresponding to each of the plurality of pixel regions, the pixel TFT having an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region, a gate insulating layer provided on the channel region of the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween, and a source electrode electrically connected to the source contact region; a gate line extending in the row direction and supplying a gate signal to the pixel TFT; a source line extending in the column direction and supplying a source signal to the pixel TFT; a light-shielding layer located between the substrate and the oxide semiconductor layer and facing at least the channel region of the oxide semiconductor layer; a first interlayer insulating layer provided to cover the oxide semiconductor layer and the gate electrode; a first organic insulating layer located on the first interlayer insulating layer and provided so as to cover the pixel TFT; a pixel electrode including a portion located on the first organic insulating layer and electrically connected to the pixel TFT; An active matrix substrate comprising: a first pixel contact hole is formed in at least the first interlayer insulating layer so as to expose at least a portion of the drain contact region; a second pixel contact hole is formed in the first organic insulating layer so as to at least partially overlap with at least one of the gate line and the light-shielding layer when viewed from a normal direction of the substrate; the pixel electrode includes a first electrode layer, a second electrode layer, and a third electrode layer, each of which is made of a transparent conductive material; the first electrode layer, the second electrode layer, and the third electrode layer are arranged in this order from the substrate side and are electrically connected to each other; the first electrode layer includes a first portion in contact with the drain contact region of the oxide semiconductor layer in the first pixel contact hole and a second portion located in the second pixel contact hole; the second electrode layer includes a third portion in contact with the second portion of the first electrode layer in the second pixel contact hole and a fourth portion located on the first organic insulating layer; The active matrix substrate comprises: a second organic insulating layer formed to fill the second pixel contact hole and cover the third portion of the second electrode layer; the third electrode layer includes a fifth portion in contact with the fourth portion of the second electrode layer and a sixth portion located on the second organic insulating layer, a length of the second electrode layer along the row direction is smaller than a length of the third electrode layer along the row direction; an active matrix substrate, wherein, when viewed from a normal direction of the substrate, both ends of the second electrode layer in the row direction are located inside both ends of the third electrode layer in the row direction.

2. a plurality of pixel regions arranged in a matrix including a plurality of rows and a plurality of columns; A substrate; a pixel TFT supported by the substrate and provided corresponding to each of the plurality of pixel regions, the pixel TFT having an oxide semiconductor layer including a channel region and a source contact region and a drain contact region located on both sides of the channel region, a gate insulating layer provided on the channel region of the oxide semiconductor layer, a gate electrode provided on the gate insulating layer and facing the channel region with the gate insulating layer interposed therebetween, and a source electrode electrically connected to the source contact region; a gate line extending in the row direction and supplying a gate signal to the pixel TFT; a source line extending in the column direction and supplying a source signal to the pixel TFT; a light-shielding layer located between the substrate and the oxide semiconductor layer and facing at least the channel region of the oxide semiconductor layer; a first interlayer insulating layer provided to cover the oxide semiconductor layer and the gate electrode; a first organic insulating layer located on the first interlayer insulating layer and provided so as to cover the pixel TFT; a pixel electrode including a portion located on the first organic insulating layer and electrically connected to the pixel TFT; An active matrix substrate comprising: a first pixel contact hole is formed in at least the first interlayer insulating layer so as to expose at least a portion of the drain contact region; a second pixel contact hole is formed in the first organic insulating layer so as to at least partially overlap with at least one of the gate line and the light-shielding layer when viewed from a normal direction of the substrate; the pixel electrode includes a first electrode layer, a second electrode layer, and a third electrode layer, each of which is made of a transparent conductive material; the first electrode layer, the second electrode layer, and the third electrode layer are arranged in this order from the substrate side and are electrically connected to each other; the first electrode layer includes a first portion in contact with the drain contact region of the oxide semiconductor layer in the first pixel contact hole and a second portion located in the second pixel contact hole; the second electrode layer includes a third portion in contact with the second portion of the first electrode layer in the second pixel contact hole and a fourth portion located on the first organic insulating layer; The active matrix substrate comprises: a second organic insulating layer formed to fill the second pixel contact hole and cover the third portion of the second electrode layer; the third electrode layer includes a fifth portion in contact with the fourth portion of the second electrode layer and a sixth portion located on the second organic insulating layer, a length of the second electrode layer along the row direction is the same as a length of the third electrode layer along the row direction; an active matrix substrate, wherein, when viewed from a normal direction of the substrate, the positions of both ends of the second electrode layer in the row direction are the same as the positions of both ends of the third electrode layer in the row direction.

3. The active matrix substrate according to claim 2 , wherein the second electrode layer and the third electrode layer are formed from the same transparent conductive material.

4. 4. The active matrix substrate according to claim 1, wherein the first organic insulating layer is a color filter layer.

5. Among the plurality of pixel regions, any two pixel regions adjacent to each other along the column direction are referred to as a first pixel region and a second pixel region, When the pixel TFT corresponding to the first pixel region is called a first pixel TFT and the pixel TFT corresponding to the second pixel region is called a second pixel TFT, the second electrode layer of the pixel electrode electrically connected to the first pixel TFT extends in a column direction from within the second pixel contact hole corresponding to the first pixel TFT toward the second pixel region when viewed from a normal direction of the substrate, 4. The active matrix substrate according to claim 1, wherein an end of the second electrode layer on the second pixel region side is covered by the second organic insulating layer in the second pixel contact hole corresponding to the second pixel TFT.

6. Among the plurality of pixel regions, any two pixel regions adjacent to each other along the column direction are referred to as a first pixel region and a second pixel region, When the pixel TFT corresponding to the first pixel region is called a first pixel TFT and the pixel TFT corresponding to the second pixel region is called a second pixel TFT, one end in a column direction of the third electrode layer of the pixel electrode electrically connected to the first pixel TFT at least partially overlaps with at least one of the gate line corresponding to the first pixel TFT and the light-shielding layer when viewed from a normal direction of the substrate; 4. The active matrix substrate according to claim 1, wherein the other end in the column direction of the third electrode layer of the pixel electrode electrically connected to the first pixel TFT at least partially overlaps with at least one of the gate line corresponding to the second pixel TFT and the light-shielding layer when viewed from the normal direction of the substrate.

7. a source contact hole is formed in the first interlayer insulating layer so as to expose at least a portion of the source contact region of the oxide semiconductor layer; the source electrode is formed on the first interlayer insulating layer and in the source contact hole; 4. The active matrix substrate according to claim 1, further comprising a second interlayer insulating layer located between the first interlayer insulating layer and the first organic insulating layer and covering the source electrode.

8. 4. The active matrix substrate according to claim 1, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

9. An active matrix substrate according to any one of claims 1 to 3; an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising:

10. 4. A method for manufacturing an active matrix substrate according to claim 2, further comprising the steps of: a step (A) of forming the pixel TFT on the substrate; After the step (A), a step (B) of depositing a first transparent conductive film and then patterning the first transparent conductive film to form the first electrode layer; a step (C) of forming the first organic insulating layer covering the pixel TFT and the first electrode layer and having the second pixel contact hole; a step (D) of depositing a second transparent conductive film on the first organic insulating layer and in the second pixel contact hole, and then patterning the second transparent conductive film; a step (E) of forming the second organic insulating layer so as to fill the second pixel contact hole after the step (D); a step (F) of depositing a third transparent conductive film on the second transparent conductive film, the first organic insulating layer, and the second organic insulating layer, and then simultaneously patterning the third transparent conductive film and further patterning the second transparent conductive film, thereby forming the third electrode layer and the second electrode layer; A method for manufacturing an active matrix substrate, comprising:

Images