amorphous metal thin film transistor

Abstract

To provide a microelectronic device in which at least one layer of an amorphous metal film is built in a thin film transistor and a method for forming the device.SOLUTION: An amorphous metal thin film transistor (AMTFT) structure 100 formed on a supporting substrate (102) includes: an amorphous metal gate electrode 104 formed on a non-conductive supporting substrate; a first tunnel insulating body 106 formed on the first amorphous metal gate 104; source-drain electrodes 108, 110 made of amorphous metal; and a channel conductor 112 formed on the non-conductive supporting substrate.SELECTED DRAWING: Figure 1A-B

Description

[Technical Field]

[0001] The present disclosure relates to microelectronic devices that incorporate one or more layers of amorphous metal films in thin film transistors. [Background technology]

[0002] 2. Description of Related Art Amorphous metals are rigid solid materials with atomic structures that lack the long-range periodicity that characterizes crystalline materials. In amorphous metals, the formation of crystal planes is suppressed, for example, by incorporating two or more components. An example of an amorphous metal containing four components—zirconium, copper, aluminum, and nickel—is Zr, as described in U.S. Pat. No. 8,436,337. 55 Cu 30 Al 10 Examples of amorphous metals include Ni5. Amorphous metals can be identified by their resistivity measurements, which show that amorphous metal materials, while conductive, have resistivities approximately 10 times greater than their crystalline counterparts. Amorphous metals also have smoother surfaces than crystalline metals, as indicated by root-mean-square (RMS) surface roughness measurements.

[0003] Amorphous multicomponent metal films (AMMFs) in the range of approximately 10-200 nm can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. These AMMFs can be formed using standard deposition processes. Zr, an exemplary amorphous metal mentioned above, 55 Cu 30 Al 10 Ni5 is an AMMF that can be formed on a substrate by conventional sputter deposition using four different metal targets, resulting in a more uniform electric field at the interface between the AMMF and the oxide film.

[0004] Such uniformity has resulted in excellent current-voltage (IV) characteristic curves for metal-insulator-metal (MIM) diodes and transistors exhibiting Fowler-Nordheim tunneling. Tunneling MIM diodes employ AMMF for the bottom electrode and a crystalline metal film for the top electrode. These two electrodes are separated by a single dielectric barrier, which provides a tunneling path for charge carriers to move between the electrodes. This single dielectric barrier produces a current response that depends on the polarity of the applied voltage. At a given voltage, charge carriers within the device tunnel in only one direction (directional tunneling). That is, tunneling occurs either from the bottom electrode to the top electrode or from the top electrode to the bottom electrode, depending on the polarity of the applied voltage. Various diode and transistor applications of AMMF are discussed in U.S. Patents 8,436,337 and 8,822,978.

[0005] Amorphous metal thin-film nonlinear resistors (AMNRs), which have superior performance to existing thin-film nonlinear resistors, are discussed in U.S. Patent No. 9,099,230 and PCT Patent Application No. WO2014 / 074360. The current response of these AMNRs is independent of the polarity of the applied voltage, which is not the case for other thin-film resistors. This polarity independence is due to the presence of two dielectric barriers, where charge carriers across each barrier are forced to tunnel in substantially opposite directions. AMNRs exhibit bidirectional tunneling because, in response to an applied voltage, charge carriers within the device tunnel in both directions across the barrier. That is, tunneling occurs from the top electrode to the bottom electrode and from the bottom electrode to the top electrode, regardless of the polarity of the applied voltage. Such polarity-symmetric AMNRs may provide improved signal control in liquid crystal displays (LCDs), organic light-emitting diode (OLED) display technologies, and electromagnetic sensor arrays. Summary of the Invention

[0006] The present disclosure is directed to devices and systems that include amorphous metal thin film transistors (AMTFTs), including methods for forming same.

[0007] These AMTFTs are thin, high-performance devices that can replace transistors in display technologies, such as the control transistors for pixels in flat-panel displays. These devices can be highly efficient in that they require a smaller footprint compared to typical transistor technologies, thereby freeing up 50% or more of the pixel window area for light to pass through.

[0008] In various embodiments, the devices of the present disclosure include amorphous metal thin film transistors (AMTFTs) on a supporting substrate. The supporting substrate can be a non-conductive substrate that is more cost-effective than silicon or semiconductor substrates. For example, the supporting substrate can be aluminum borosilicate glass, fused silica, or other suitable non-conductive material.

[0009] If the substrate is conductive, an insulator may be formed between the surface of the substrate and the first electronic component on the substrate. For example, if a silicon or semiconductor substrate is used, a native oxide or other insulator may be formed on the surface of the substrate to separate the silicon from the first electronic component in order to ensure non-conductivity.

[0010] The support substrate can be any of a variety of materials, such as a glass substrate, a silicon or other semiconductor substrate, or a flexible substrate including a polymer (e.g., rubber or plastic). In various embodiments, the substrate is flexible. In some such embodiments, the transistor is made entirely of amorphous materials (i.e., the amorphous metal gate, source and drain electrodes, the amorphous metal oxide insulator, and the amorphous metal oxide semiconductor).

[0011] In embodiments, the transistors of the present disclosure include at least one amorphous metal layer. Any suitable amorphous metal can be used. In embodiments, the amorphous metal used includes Zr, Cu, Ni, Al, or a combination thereof. For example, the amorphous metal layer can be an alloy of titanium and aluminum. In some embodiments, the alloy is TiAl3, TiAl7, TiAl, or a combination thereof. In particular embodiments, the alloy is TiAl3. In particular embodiments, the alloy is TiAl3, i.e., aluminum with 25% of its atoms substituted with titanium. In other embodiments, the amorphous metal layer is an alloy of Cu, Zr, or both (e.g., CuZrB).

[0012] In various embodiments, the amorphous metal layer is formed on a supporting substrate. In some such embodiments, the surface of the supporting substrate on which the amorphous metal layer is formed is a flat surface. This flat surface, combined with the uniformly smooth surface of the amorphous metal layer, allows the amorphous metal gate electrode to have a uniformly smooth surface, resulting in reduced surface defects, compared to crystalline metals. Surface imperfections in crystalline metals cause non-uniformities in the electric field, which can lead to failure of electronic devices.

[0013] In some embodiments, the amorphous metal layer is or is formed into an amorphous metal gate structure. Thus, in embodiments, the AMTFTs of the present disclosure include an amorphous metal gate and a channel. Conduction part In various embodiments, the channel Conduction part is a semiconductor material. In some embodiments, the channel Conduction part is an oxide. In certain embodiments, the channel Conduction part is InGaZnO.

[0014] In embodiments, the AMTFT further includes source and drain electrodes. Such electrodes can be crystalline, amorphous, multi-material stacks, etc., as will be understood by those skilled in the art. The source and drain electrodes can be crystalline metals or other suitable conductors. In some embodiments, the material can be a metal (e.g., Al, Mo, etc.) or a semiconductor material (e.g., polysilicon). In some embodiments, the material can be a highly conductive aluminum-based material. These electrodes can be atomically thin, such as a graphene layer. In embodiments, the source and drain electrodes have the same thickness and material properties. In other embodiments, the source electrode is made of a different conductive material than the drain electrode. In this embodiment, the source and drain electrodes can be formed in separate steps. The source and drain electrodes can have different thicknesses, material properties, and dimensions depending on the product in which the transistor is incorporated.

[0015] In some embodiments, the amorphous metal layer is or is formed to be the source and drain electrodes. Thus, in embodiments, the AMTFTs of the present disclosure include amorphous metal source and drain electrodes and a channel Conduction part Thus, in embodiments, the AMTFTs of the present disclosure include amorphous metal gate, source, and drain electrodes.

[0016] In an embodiment, the transistor further includes a first tunnel insulator, which is generally a very thin layer, for example, about 20 nanometers (nm) or less. [Brief explanation of the drawings]

[0017] The detailed description is set forth with reference to the accompanying drawings. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements have been enlarged to improve the readability of the drawings. As will be appreciated by those skilled in the art, the shapes of certain elements can be modified (e.g., rounded, narrowed, elongated) to suit a particular application.

[0018] [Figure 1A-B] Figure 1A is a cross-sectional view of an amorphous metal thin film transistor (AMTFT) according to one embodiment of the present disclosure, and Figure 1B is a top view of a feature of the AMTFT in Figure 1A. [Figure 2A-B] 2A and 2B are cross-sectional and top views of features of an AMTFT according to another embodiment of the present disclosure. [Figure 3A-B] 3A and 3B are cross-sectional and top views of features of an AMTFT according to another embodiment of the present disclosure. [Figure 4A-B] 4A and 4B are cross-sectional and top views of features of an AMTFT according to another embodiment of the present disclosure. [Figure 5A-B] 5A and 5B are cross-sectional and top views of features of an AMTFT according to another embodiment of the present disclosure. [Figure 6A-B] Figure 6A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure, and Figure 6B is a top view of a feature of the AMTFT in Figure 6A. [Figure 7] FIG. 7 shows a display formed in accordance with the present disclosure. [Figure 8A] FIG. 8A illustrates an in-plane switching pixel according to an embodiment of the present disclosure. [Figure 8B-C] 8B and 8C are views of an in-plane switching pixel according to an embodiment of the present disclosure. [Figure 9]FIG. 9 includes a device having a screen with pixels formed in accordance with the present disclosure and a detailed view of the pixels. [Figure 10] FIG. 10 is a top view of a shared select line layout according to one embodiment of the present disclosure. [Figure 11] FIG. 11 shows a transistor structure in an array for a display. [Figure 12A-B] Figure 12A is a cross-sectional view of an AMTFT formed adjacent to an amorphous metal nonlinear resistor (AMNR) according to one embodiment of the present disclosure, and Figure 12B is a top view illustrating features of the AMTFT and AMNR of Figure 12A. [Figure 13A-B] Figure 13A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to one embodiment of the present disclosure, and Figure 13B is a top view illustrating features of the AMTFT and AMNR of Figure 13A. [Figure 14A-B] Figure 14A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to one embodiment of the present disclosure, and Figure 14B is a top view illustrating features of the AMTFT and AMNR of Figure 14A. [Figure 15A-B] Figure 15A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to one embodiment of the present disclosure, and Figure 15B is a top view illustrating features of the AMTFT and AMNR of Figure 15A. [Figure 16A-B] Figure 16A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to one embodiment of the present disclosure, and Figure 16B is a top view illustrating features of the AMTFT and AMNR of Figure 16A. [Figure 17A-B] Figure 17A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to one embodiment of the present disclosure, and Figure 17B is a top view illustrating features of the AMTFT and AMNR of Figure 17A. [Figure 18A-B] Figure 18A is a cross-sectional view of an AMTFT formed adjacent to an AMHET according to one embodiment of the present disclosure, and Figure 18B is a top view illustrating features of the AMTFT and AMNR of Figure 18A. [Figure 18C]FIG. 18C shows the AMTFT and AMNR performance data of FIGS. 18A and 18B. [Figure 18D] FIG. 18D shows the performance data for AMTFT and AMNR of FIGS. 18A and 18B. [Figure 19A] FIG. 19A shows an example of a circuit diagram of a Reset / Set flip-flop. [Figure 19B] FIG. 19B shows the measurements of each node of the Reset / Set flip-flop including the AMTFT. [Figure 19C] FIG. 19C shows the truth table. [Figure 20A] FIG. 20A shows a circuit diagram of an exemplary AMLCD or EPD circuit. [Figure 20B-C] Figure 20B is a top view of an exemplary matrix of AMLCD EPD circuits, and Figure 20C shows the circuitry of a single pixel in the array indicated by the rectangle in Figure 20B. [Figure 21A] FIG. 21A shows a circuit diagram of an exemplary AMOLED circuit. [Figure 21B-C] Figure 21B shows a top view of an exemplary matrix of AMOLED structures, and Figure 21C shows the circuitry of a single pixel in the array indicated by the rectangle in Figure 21B. [Figure 22] FIG. 22 shows a second exemplary AMOLED circuit that includes six transistors and one capacitor. [Figure 23] FIG. 23 shows a third exemplary AMOLED circuit that includes five transistors and two capacitors. [Figure 24A] FIG. 24A shows a block diagram of an exemplary gate driver circuit. [Figure 24B] Figure 24B shows an example gate driver shift register circuit, and Figure 24C shows an example gate driver buffer circuit in which AMTFTs may be used. [Figure 24C] Figure 24C shows an example of a gate driver buffer circuit in which AMTFTs may be used. [Figure 25]FIG. 25 shows an exemplary circuit diagram of a cascode amplifier circuit. [Figure 26A-B] 26A and 26B show schematic diagrams of angles that can be measured on a deformed flexible substrate. DETAILED DESCRIPTION OF THE INVENTION

[0019] Although particular embodiments of the present disclosure have been described for purposes of illustration, it will be understood that various modifications can be made without departing from the spirit and scope of the disclosure.

[0020] In this specification, specific details are described to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter can be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing that make up embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring other aspects of the disclosure.

[0021] References throughout this specification to "one embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the disclosure.

[0022] The present disclosure is directed to various implementations of transistors incorporating amorphous metal thin films. Used in combination with a tunnel insulating layer, the amorphous metal thin film performs the function of a transistor without the complexity of standard silicon-based transistors. Such amorphous metal transistors can be formed on numerous supporting substrates, providing designers with flexibility regarding the types of materials and products into which the transistor, or active circuitry, can be incorporated. These amorphous metal transistors can be formed on flexible substrates, allowing them to bend and change shape without damaging the circuitry. These flexible substrates can be polymer, glass, or other materials.

[0023] Many aspects of our lives benefit from the use of increasingly miniaturized electronic devices. These include mobile electronics such as televisions, cell phones, smartphones, and tablet computers, as well as wearable electronics such as smartwatches and pedometers. Transistors fabricated on semiconductor substrates are limited by the materials (semiconductor wafers, such as silicon) used to form circuits. The use of flexible transistors can further expand and improve the potential applications of electronic devices, including lightweight and fast displays, wearable displays, mobile or easily transportable displays, and displays integrated into Internet of Things applications and medical devices.

[0024] These transistor structures can be used to form high performance analog or digital devices depending on the end application. Furthermore, because these transistor structures do not utilize semiconductor materials, they open up a myriad of applications for non-semiconductor-based transistors. While semiconductor materials can be utilized as described in this disclosure, the transistor structures themselves are not based on doping silicon wafers, but instead incorporate the formation of amorphous metal thin films on a number of supporting substrates.

[0025] FIG. 1A is a first embodiment of an AMTFT with a cross-sectional view of the AMTFT structure 100 formed on a support substrate 102. FIG. 1B is a top view of the AMTFT structure 100 of FIG. 1A. The structure 100 includes an amorphous metal gate electrode 104 formed on the support substrate 102 and a first tunnel insulator 106 formed on the amorphous metal gate electrode 104. Source / drain electrodes 108, 110 (e.g., crystalline metal, amorphous metal, multi-material stack, etc.) are formed between the first tunnel insulator 106 and the amorphous metal gate electrode 104. L The source / drain electrodes 108, 110 overlap the amorphous metal gate electrode 104 by at least a first distance 105. Conduction part The second insulator 112 (which may be a semiconductor) overlaps the source / drain electrodes 108, 110 by at least a second distance 107. The second insulator 114 optionally forms a channel Conduction part It is placed on 112.

[0026] The substrate 102 can be a variety of materials, such as conductive, semiconductive, or nonconductive materials. As a result of the transistor structures comprising non-traditional materials, the substrate can have non-traditional properties. For example, the substrate can be deformable or bendable so that it can return to its resting shape. The transistor structures can also operate in a curved or bent configuration.

[0027] In some embodiments, the substrate is glass, a polymer, a plastic, or other material. In other embodiments, the substrate is rubber. As used herein, "rubber" includes polymers of isoprene, as well as forms of polyisoprene. In some such embodiments, the substrate is plastic. Any suitable plastic can be used. In some embodiments, the plastic is arylamide, acrylamide, polybenzimidazole (PBI), polyetherimide, polyetherketoneketone (PEKK), polyetheretheretherketone (PEEK), polyamide, polyimide, polyamideimide, polystyrene (PS), polyphenylene oxide (PPO), polyphthalamide (PPA), polyvinyl alcohol (PVA), acrylonitrile butadiene styrene (ABS), polycarbonate (PC), thermoset, PBI-PEEK, urea, epoxy, polyurethane, or any combination thereof. In some embodiments, the plastic is polyethylene. In certain embodiments, the plastic is high-density polyethylene.

[0028] In further embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 5 degrees. In some embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 10 degrees. Unless otherwise specified, the central angle is measured for a curve relative to the apex of the curve. In embodiments in which the substrate is deformed at one or more positions, a corresponding number of curves can be measured, as shown in FIG. 26B, including a first curve 2604 and a second curve 2602 corresponding to angle A and angle B, respectively. In some embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 10 degrees in each of the first curve and second curve. In other words, the substrate can be bent, contoured, or otherwise moved into a shape suitable for the end use. The transistor structures formed on this flexible substrate can be used in curved or contoured shapes. It is also envisioned that such transistors can be formed on rigid substrates if the end use is suitable for a non-flexible substrate.

[0029] In embodiments, the AMTFTs are formed while the flexible substrate is in a planar configuration, and in some such embodiments, the flexible substrate can then be deformed (e.g., bent, rolled, bowed) without damaging the AMTFT structures.

[0030] The material of the support substrate can be selected by the manufacturer based on the end use of the transistor structure and the final device to be produced. For example, if the transistor structures are incorporated in an array, the array can be implemented in a liquid crystal display. Other end uses include wearable electronics. The support substrate can be transparent or non-transparent, such as those that may be used in some reflective displays.

[0031] Manufacturing on a non-conductive, flexible support substrate can significantly reduce manufacturing costs. Such substrates can enable roll-to-roll transistor manufacturing. This change in manufacturing methods could redefine the electronics supply chain.

[0032] An amorphous metal layer is formed on the substrate. Excess portions of the amorphous metal layer are removed to form an amorphous metal gate electrode 104. Formation of the amorphous metal layer may involve any deposition technique, such as sputtering, solution deposition, or electron beam evaporation. For example, multi-source RF (or DC) magnetron sputtering may be employed using elemental or mixed-composition metal targets of Zr, Cu, Ni, and Al. Sputter deposition offers distinct manufacturing advantages over similar smooth semiconductors deposited using advanced epitaxial techniques such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).

[0033] As described above, portions of the amorphous metal layer can be etched or otherwise removed using masks, photolithography, and other techniques. In other embodiments, the amorphous metal layer can be deposited in a shape suitable for the application. The amorphous metal layer can be deposited at room temperature by sputtering and can maintain its amorphous and smooth properties during subsequent heating processes. The adaptability and flexibility of amorphous metal layers in how they are formed and used limitless the range of possible applications.

[0034] In embodiments having an amorphous metal gate on a flexible substrate, it is contemplated that the flexible substrate will be deformed (e.g., bent) to an angle of at least about ±5 degrees from a flat or resting plane 2601 formed by the substrate 102. Unless otherwise specified, all angles described in terms of measurements in degrees are measured from the plane 2601 (shown by the dashed lines in FIG. 26A).

[0035] The first tunnel insulator 106 is on the amorphous metal gate electrode 104. In some embodiments, the portion of the first tunnel insulator 106 layer between the source / drain electrodes 108, 110 and the amorphous metal gate electrode 104 may be thinner than other portions.

[0036] The first tunnel insulator 106 is formed as a conformal layer, which may be done by blanket deposition, which is the simplest and most cost-effective manufacturing option, although the first tunnel insulator 106 may also be patterned as appropriate for the end use of the transistor structure.

[0037] The tunnel insulator can be any suitable insulator, including oxide, nitride, silicon nitride, metal oxide (e.g., aluminum oxide), etc. In embodiments, the first tunnel insulator is a metal oxide (e.g., Al2O3) or metal nitride, which can be formed in a very thin layer. The first tunnel insulator is sufficiently thin to enable tunneling and hot electron generation. In some embodiments, the portion of the first tunnel insulator layer between the source / drain electrodes and the amorphous metal gate electrode may be thinner than other portions. In a particular embodiment, the first tunnel insulator is a 10 nm or less aluminum oxide layer deposited by atomic layer deposition.

[0038] In various embodiments, the AMTFTs of the present disclosure include a second insulator, which can be any suitable insulator, including an oxide, a nitride, silicon nitride, a metal oxide, or the like.

[0039] Source / drain electrodes 108, 110 are then formed on the first tunnel insulator 106. Each of the source / drain electrodes overlaps the amorphous metal gate electrode 104 by at least a distance 105. Figures 1A and 1B show one configuration of the source / drain electrodes relative to the amorphous metal gate electrode. Other configurations and orientations are possible. To achieve electron transport, the electrodes overlap the amorphous metal gate electrode by some amount.

[0040] In one embodiment, the source electrode is formed simultaneously with the drain electrode. This can be done by blanket deposition followed by an etching step. Thus, the source / drain electrodes have the same thickness and material properties. In an alternative embodiment, the source electrode is made of a different conductive material than the drain electrode and is formed in a separate step. The source / drain electrodes can have different thicknesses, material properties, and dimensions depending on the product in which the transistor is incorporated.

[0041] Channel on source / drain electrodes 108, 110 Conduction part 112. Channel Conduction part 1A and 1B show the channel structure for the source / drain electrodes 108, 110 and the first tunnel insulator 106. Conduction part 1 shows one embodiment of the configuration of 112. Other configurations and orientations are possible.

[0042] Some embodiments of the disclosed method include forming a second insulator 114 over the source / drain electrodes 108, 110. The second insulator 114 covers all exposed surfaces and is ideally conformal. This layer may be a protective layer for the transistor structure. In some embodiments, these are single device layer structures, although other structures may be formed over the transistor. In other variations, openings may be formed in the second insulator 114 to expose surfaces of the source / drain electrodes 108, 110 to which electrical connections may be made. In single device layer implementations, electrical connections to the gate, source, and drain are made side-by-side from edges 109, 111, and 113.

[0043] The ultra-smooth amorphous metal gate electrode used in this embodiment provides better electric field control across the AMTFT gate insulator compared to conventional thin film transistors that use a rough crystalline metal electrode for the gate.

[0044] Another embodiment of an AMTFT is shown in Figure 2A, which is a cross-sectional view of an AMTFT structure 200 formed on a support substrate 202. Figure 2B is a top view of the AMTFT structure 200 of Figure 2A. The structure 200 includes an amorphous metal gate electrode 204 formed on the support substrate 202 and a first tunnel insulator 206 formed on the amorphous metal gate electrode 204. The channel Conduction part 212 is on the first tunnel insulator 206. The source / drain electrodes 208, 210 are partially in contact with the channel Conduction part 212 and partially on the surface of the first tunnel insulator 206. Source / drain electrodes 208, 210 overlap the amorphous metal gate electrode 204. Optionally, a second insulator 214 is deposited on the source / drain electrodes 208, 210.

[0045] 2A and 2B, a gate electrode 204 is formed on the channel by a tunnel insulator 206. Conduction part 212. The source / drain electrodes 208 / 210 are separated from the channel by a tunnel insulator 206. Conduction part Gate 204, channel Conduction part 212 and the source / drain electrode 208. The source / drain electrodes 208 / 210 form an overlap region 219. Conduction part 212. This overlap region 219 is where electrons flow during operation through the tunnel oxide.

[0046] A further embodiment of an AMTFT is shown in FIG. 3A, which is a cross-sectional view of an AMTFT structure 300, and FIG. 3B, which is a top view of the AMTFT structure 300 of FIG. 3A formed on a supporting substrate 302. This is a gate-first device, since the gate is closest to the substrate, as compared to other stacks described below. The structure 300 includes a first amorphous metal gate electrode 304 formed on the supporting substrate 302, and a first tunnel insulator 306 formed on the first amorphous metal gate electrode 304. On the first tunnel insulator 306 is a channel Conduction part The source / drain electrodes 308, 310 are formed on the channel Conduction part 312 and the first amorphous metal gate electrode 304. The overlap region 301 between the gate, channel, and source / drain electrodes provides a path for electron movement.

[0047] All channels described herein Conduction part It should be noted that the can be formed of semiconductor materials using standard semiconductor processing techniques that are beneficial to the end application. Other conductive materials may be used as the channel. The source / drain electrodes of the present disclosure may also be made of a variety of materials. In some embodiments, the source / drain electrodes may be crystalline materials. In other embodiments, the source / drain electrodes may be amorphous materials, such as amorphous metals. In still other embodiments, the source / drain electrodes may be multi-layer stacks of materials, such as stacks of metal layers.

[0048] In some embodiments, the portion of the first tunnel insulating layer 306 between the source / drain electrodes 308, 310 and the first amorphous metal gate electrode 304 may be thinner than other portions. For example, the first tunnel insulating layer 306 may be thinner in region 301 to reduce the distance between the source / drain electrodes 308, 310 and the first amorphous metal gate electrode 304. In this configuration, the insulating layer has a recess, which reduces the distance between the source / drain electrodes 308, 310 and the first amorphous metal gate electrode 304. Conduction part 312 is formed within these recesses. These recesses in the tunnel insulator can be applied to any of the embodiments described herein.

[0049] A second insulator 314 is deposited on the source / drain electrodes 308, 310. A second gate electrode 316 is deposited on the second insulator 314. The second gate electrode 316 may be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack. The second gate electrode 316 is formed by insulating the amorphous metal gate electrode 304 and the channel Conduction part 312. The second gate electrode 316 extends across at least the region 301. The second gate electrode 316 may be incorporated into other embodiments. In this embodiment, the second gate electrode 316 extends beyond the edges 303, 305. In some embodiments, the second gate 316 is in contact with the edge 303 of the first gate and the channel. Conduction part The second gate electrode has ends 311, 313 disposed between end 307 of 312. In embodiments, the second gate electrode improves device performance.

[0050] Yet another embodiment of an AMTFT is shown in Figure 4A, which is a cross-sectional view of an AMTFT structure 400 in a gate-last formation method. Figure 4B is a top view of the AMTFT structure 400 of Figure 4A. The structure 400 includes a first insulator 414 on a support substrate 402. This can be formed by a blanket deposition to cover the entire substrate, or it can be formed by a blanket deposition to cover the surface of the substrate that will be processed to form the transistor. Conduction part412 is formed on a first insulator 414. Note that the sidewalls of the various layers are shown in an angled configuration. These sidewalls may be oriented closer to or more perpendicular to the surface 411 of the first insulator. The sidewalls are transverse to the surface of the insulator. The sidewalls of each layer in each embodiment may be at a different angle than shown.

[0051] The source / drain electrodes 408, 410 are Conduction part 412. In a preferred embodiment, the source / drain electrodes are amorphous metals. A second insulator 406, which is a tunnel insulator, is formed on the source / drain electrodes 408, 410. The second insulator is in direct contact with the amorphous metal of the source / drain electrodes. A gate electrode 416 is formed on the second tunnel insulator 406. The gate electrode 416 may be a crystalline metal, an amorphous metal, or a metal such as a multi-material stack. In an embodiment, the gate electrode 416 is in contact with the channel Conduction part 412. In an embodiment, a gate electrode 416 is aligned between the source / drain electrodes 408, 410. An overlap region 413, which is an active region, is at least between an edge 417 of the gate electrode 416 and an edge 419 of the source / drain electrode 408.

[0052] The gate 416 is furthest from the substrate in the embodiment of Figure 4A. The tunnel insulator 406 is between the gate and the source / drain electrodes 408 / 410. The channel is separated from the gate by the source / drain electrodes 408 / 410.

[0053] Another embodiment of an AMTFT is shown in FIG. 5A, which is a cross-sectional view of an AMTFT structure 500, and FIG. 5B, which is a top view of the AMTFT structure 500 of FIG. 5A formed on a supporting substrate 502. This is a gate-last configuration. The structure 500 includes a first insulator 514 formed on the supporting substrate 502. Source / drain electrodes 508, 510 formed of an amorphous metal are formed on the first insulator 514. The channel Conduction part512 overlaps with the source / drain electrodes 508, 510 in region 513. Conduction part is in direct contact with the source / drain electrodes, which may be a conformal layer that overlies and covers all exposed locations during deposition.

[0054] The second tunnel insulator 506 is Conduction part 512 and the source / drain electrodes 508, 510. A gate electrode 516 is deposited on the second tunnel insulator 506. The gate electrode 516 may be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack. The tunnel insulator works well when in direct contact with the amorphous metal, which in this embodiment is the source / drain electrode. In an embodiment, the gate electrode 516 has an overlap region 517, which overlaps the channel Conduction part 512. In an embodiment, a gate electrode 516 is aligned between the source / drain electrodes 508, 510 and has some overlap with the source / drain electrodes.

[0055] For each of the illustrated embodiments, the top view shows the ends of the various components that are coupled to other components in the final product. These couplings can be through vias, other overlapping layers, or other connection techniques that allow electrical signals to be transmitted to these transistor structures. A further embodiment of an AMTFT is shown in FIG. 6A, which is a cross-sectional view of an AMTFT structure 600, and FIG. 6B, which is a top view of the AMTFT structure 600 of FIG. 6A formed on a support substrate 602. The structure 600 includes an amorphous metal gate electrode 604 formed on the support substrate 602, and a first tunnel insulator 606 formed on the amorphous metal gate electrode 604. Above the first tunnel insulator 606, a channel Conduction part 612 is formed. Conduction part A second tunnel insulating film 618 is deposited on the channel 612. Conduction part 612 and gate electrode 604 have an overlap in region 611 .

[0056] In an embodiment, the second tunnel insulator 618 is substantially aligned with and completely overlaps the intermediate region of the amorphous metal gate electrode 604. The second gate electrode 616 is on the second tunnel insulator 618. In an embodiment, the second gate electrode 616 is substantially aligned with the amorphous metal gate electrode 604 such that their intermediate regions are aligned. Region 613 corresponds to the overlap region of the first and second gates. The second gate electrode 616 may be a metal, such as a crystalline metal, an amorphous metal, or may be a multi-material stack.

[0057] The second dielectric layer 618 is patterned and removed or otherwise formed to correspond to the dimensions of the second gate electrode 616. A third insulator 614 is on the second gate electrode 616. In an embodiment, the third insulator layer 614 is a layer that is formed over the channel Conduction part 612 is discontinuous so that it is exposed at locations 615 and 617. These locations or openings allow for the formation of channels by the source / drain electrodes 608 and 610. Conduction part 612. The source / drain electrodes 608, 610 are formed on the third insulator layer 614, forming a channel Conduction part 612. In some embodiments, the second gate electrode and source / drain electrodes 608, 610 may be formed simultaneously, followed by the formation of the third insulator layer.

[0058] 7 illustrates a display 700 that may include the AMTFTs of the present disclosure. The display 700 includes a display area 702 that includes a plurality of pixels 704. The display may be on a flexible or rigid substrate 706. In some embodiments, the substrate is glass. The display may be a flat panel display that forms images such as video, television, or other digital media.

[0059] Each pixel in a flat panel display is controlled by a thin film transistor, such as an AMTFT or an amorphous metal nonlinear resistor (AMNR), or a combination of both. These pixels receive two signals, one of which is a switch, i.e., an AM TFT The select drivers 708 are coupled to the pixels and activate the switches. These select drivers are sometimes called gate drivers. The select drivers are shown to the left of the display area.

[0060] The data driver 710 controls the brightness of the pixels. In known systems, the data driver and select driver are bulky, individually packaged chips. These chips occupy a significant amount of real estate on the edge of the substrate 706. They also drive up costs, as display manufacturers often purchase these chips from other silicon chip manufacturers. The select drivers of the present disclosure made with the AMTFTs of the present disclosure are formed during the same process steps as pixels also formed from AMTFTs or AMNRs. This significantly reduces the display bezel. The distance 712 from the edge of the display area 702 to the edge of the glass can be significantly reduced compared to current display technologies. This area must currently accommodate multiple integrated circuits soldered or otherwise coupled to the substrate and pixels. Note that in some embodiments, if desired, the pixels can be formed exclusively with AMNRs. It is also contemplated that the pixels can be formed using only AMTFTs.

[0061] AMTFTs allow select drivers to be formed directly on the display glass. This allows for a thinner glass bezel around the display area and eliminates separate integrated circuits. In various embodiments, sub-pixels in the display area are controlled by amorphous metal thin film nonlinear resistor (AMNR) devices. In various embodiments, sub-pixels in the display area are controlled by amorphous hot electron transistors (AMHETs). In various embodiments, sub-pixels in the display area are controlled by AMTFT devices.

[0062] In some embodiments, both the select driver and the data driver are formed directly on the glass during pixel fabrication using AMNR, AMTFT, and AMHET. As discussed above, amorphous metals provide very smooth surfaces. These smooth surfaces affect the electric field control across gate insulators, such as tunnel insulators. Furthermore, the transistors of the present disclosure can be formed from amorphous materials, i.e., the gate and source / drain electrodes can be amorphous metals, the insulators can be amorphous metal oxides, and the channel can be amorphous metal oxide semiconductors. All of these amorphous transistors and other circuits offer mechanical flexibility.

[0063] 8A, 8B, and 8C are top and cross-sectional views of a pixel 800 including an AMNR device. These devices can be used for in-plane switching (IPS). As used in this disclosure, pixel can refer to a pixel or a subpixel. Select drivers or other transistors used to control and drive pixels and subpixels can be formed as AMTFTs of the present disclosure. As described below, AMTFTs can be coupled to AMNR devices to control and drive various pixels.

[0064] FIG. 8A is a top view of a pixel 800 including a plurality of AMNR devices 802, and FIG. 8B is a cross-sectional view of the pixel 800 taken along line AA. FIG. 8C is a cross-sectional view of the pixel 800 taken along line BB. The pixel 800 is formed on a substrate 802 that is transparent or otherwise capable of transmitting light from a light source, which may be any one of the substrates discussed in this disclosure. A first plurality of interconnects 804a-804f are formed on the substrate 802, and in this embodiment, the first plurality of interconnects 804a-804f are all formed of amorphous metal thin films.

[0065] A first tunnel insulator 810 is formed over the first plurality of interconnects. A second plurality of interconnects 814a-814h are formed over the first tunnel insulator 810. Select lines 816, 818 can be formed simultaneously with the second plurality of interconnects 814a-814h.

[0066] A second insulator 822 is formed over the second plurality of interconnects 814a-814h. The second insulator may be a different material than the first tunnel insulator. A plurality of in-plane electrodes 826a, 826b are formed over the second insulator. A top glass layer 828 is disposed over the liquid crystal layer 830, and electrode 826a is a data line. In this in-plane switching configuration, the data line is formed on the substrate as opposed to on the top glass layer 828. The electrodes 826a, 826b are formed in a comb-like pattern. The number of combs may be fewer or greater as dictated by the application of the pixel.

[0067] 9 includes a device 900 comprising a screen 901 having an array 902 of pixels 904 formed in accordance with the present disclosure. The device may be any electronic device that includes a display, such as a television, computer, cell phone, tablet, or other device that includes pixels like the display of FIG.

[0068] Each pixel 904 includes a red subpixel 906, a green subpixel 908, and a blue subpixel 910. In some embodiments, it also includes a white subpixel 912. While the subpixels are illustrated as having a vertically aligned configuration, any configuration is contemplated, such as a subpixel formed using multiple AMNR devices having at least one active region. The illustrated configuration includes two AMNR devices of each color, with each AMNR device containing six active regions. Select lines 914 and 916 are shared across adjacent pixels and subpixels. Top or second electrodes 918, 920, 922, and 924 are coupled to other adjacent pixels in a column.

[0069] A vertically aligned (VA) pixel 906, 908, 910, 912 according to one embodiment of the present disclosure includes a first AMNR device 926 having six active regions and a second AMNR device 928 having six active regions. In other embodiments, the first AMNR device may have a different number of active regions compared to the second AMNR device. A pixel may be formed with only two active regions per AMNR device. For example, if only two of the first interconnects are formed, the pixel may include interconnects in which electrode extensions overlap the interconnects.

[0070] First interconnects are formed on the first glass layer. These first interconnects are amorphous metal thin films, which are extremely flat and smooth, simplifying the manufacturing process. A tunnel insulator is then formed on the first interconnects.

[0071] A second interconnect is formed on the tunnel insulator. Additional signal lines may be formed simultaneously with the second interconnect. The first electrode may also be formed simultaneously with the second interconnect. A liquid crystal or other display material layer is formed over the first electrode and the second interconnect.

[0072] A second electrode is formed on the second glass layer. In this embodiment, the first and second electrodes are staggered, but the electrodes may be aligned with one another so that the second electrode obscures at least the center of the first electrode when viewed from above. In this embodiment, the first and second electrodes are generally square in shape; however, other shapes are contemplated. The electrodes may also be comb-shaped.

[0073] Stated another way, a pixel can include a first glass layer (substrate), first and second amorphous metal thin film interconnects (interconnects) on the first glass layer, a first electrode (electrode) on the first glass layer, where the first electrode is coupled between the first and second amorphous metal thin film interconnects, a second electrode (electrode 918), a second glass layer, and a second electrode on the second glass layer. By combining different numbers of interconnects, designs can be modified to accommodate various combinations of interconnects and numbers of active areas as pixel requirements change.

[0074] The process for constructing pixels with vertical alignment and two active regions per AMNR element is simple and does not require semiconductors. When the pixels are used in a display, the process is called constructing a backplane. This backplane involves depositing and patterning amorphous metal thin-film interconnects on a first glass layer. A tunnel insulator is then deposited. A first electrode is then deposited and patterned. A second electrode is deposited and patterned on the second glass layer. The second glass layer can be color filter glass. This second electrode can be indium tin oxide.

[0075] The select lines for the pixels may be formed simultaneously with the first electrodes. In an alternative embodiment, the select lines are formed first, and then the first electrodes are formed and coupled to the select lines. The select lines in FIG. 9 are lines 916 and 914 and may include a second interconnect. The select lines may also be coupled to the first electrodes through vias, which are described in more detail below.

[0076] If the second electrode is a non-transparent conductor, four mask steps are used to form a pixel with two AMNR devices, each with two active regions. The pixel window material must be formed from a transparent conductive oxide. This process involves depositing and patterning an amorphous metal film to form spaced-apart first and second interconnects. This is the first mask step. This process involves forming a tunnel insulator, then depositing and patterning an upper select line to overlap the first and second interconnects. This is the second mask step. An insulator is formed over the select lines. A via is formed through the insulator to provide access to one of the select lines. Next, a first electrode is formed by depositing and patterning a conductive material and is connected to one of the select lines through the via. This is the third mask step. A second electrode is formed on the second glass layer using conductive oxide. This is the fourth mask step. A liquid crystal layer is placed between the first and second electrodes. Alternatively, to reduce the number of mask steps, a two-tone mask may be used when forming the select lines and the first electrodes.

[0077] The AMNR element can be completely formed with only two masking steps. When forming AMTFTs within pixels or as control circuits, there may be more than two masking steps as other layers are incorporated for other amorphous circuitry.

[0078] These amorphous metal thin film materials are excellent materials to start the manufacturing process with because they are very smooth and provide a solid surface on which to base subsequent steps. These amorphous metal thin films are often the first layers formed, however, other configurations are contemplated as described further in this disclosure.

[0079] The total height of the AMNR devices, from the top surface of the substrate to the top surface of the second level interconnect, is approximately 200 nanometers. These are very thin, high performance devices. TFT The total height may be in the range of 250 nanometers to 400 nanometers.

[0080] An AMNR device with only two active regions can achieve a threshold voltage of around 5 volts, and a device with 12 active regions can achieve a threshold voltage of around 30 volts, with each device having a similar or identical tunnel insulator thickness.

[0081] The threshold voltage relationship between two AMNR devices with different numbers of active regions is as follows:

number

[0082] The capacitance relationship between two AMNR devices with different numbers of active regions is as follows:

number

[0083] 10 is a top view of multiple subpixels with a shared select line layout according to one embodiment of the present disclosure. A first subpixel 1000 is disposed between a second subpixel 1002 and a third subpixel 1004. Each subpixel has two select lines. The first subpixel 1000 has a first select line 1006 shared with the second subpixel 1002 and a second select line 1008 shared with the third subpixel 1004. AMTFT circuitry can be incorporated into these pixels on displays or other electronic devices developed to achieve high performance on non-silicon-based substrates.

[0084] FIG. 11 is an exemplary array of transistor structures that may be used in a display, such as the display region shown in FIG. 7. The array may be incorporated into the display or integrated with a sensor, such as an X-ray detector. Array 1100 includes multiple rows 1104 and multiple columns 1102. Each row can conduct a base signal to an AMHET 1101 in array 1100. Each column can conduct an emitter signal to an AMHET 1101. AMHET 1101 includes an amorphous metal layer 1106. An emitter electrode 1110 overlaps amorphous metal layer 1106 and couples to row 1102. A base electrode 1108 overlaps amorphous metal layer 1108 and couples to column 1104. A collector electrode and contact 1114 overlaps amorphous metal layer 1106 and base electrode 1108. The collector electrode 1114 is coupled to other pixel or cell control elements. The collector electrode 1114 may or may not be coupled to a capacitor or other transistor. In various embodiments, the capacitor includes one or more amorphous metal layers. In some such embodiments, the amorphous metal in the capacitor is the same amorphous metal used in AMTFTs.

[0085] This AMHET transistor 1101 can operate as a matrix switch in common-base, common-emitter, or common-collector modes. In this particular illustrated example, it is in a common-emitter configuration. Such a matrix switch allows for the control of a single element.

[0086] Multiple AMHET transistors 1101 can be incorporated into various active matrix display technologies, such as liquid crystal displays, organic light emitting diode displays, electrophoretic displays, and electroluminescent displays. Each specific active matrix application has additional circuit elements to form the display. Some of these elements, such as resistors, capacitors, diodes, other transistors, or other electronic components, can be formed in the same processing step as the AMHET or in subsequent processing.

[0087] In embodiments, the AMHET structure includes an amorphous metal interconnect on a supporting substrate and a first tunnel insulator on the amorphous metal interconnect. A first electrode and a second electrode are on the first tunnel insulator. The first electrode and the second electrode overlap the amorphous metal interconnect. A third electrode overlaps the second electrode and is separated from the second electrode by a second insulator. Exemplary AMHET structures are described and disclosed, for example, in WO 2018 / 009901, the disclosure of which is incorporated herein by reference for its teachings regarding the above subject matter.

[0088] The structure includes a first terminal coupled to the first electrode. A second terminal is coupled to the second electrode. A third terminal may be included for coupling the third electrode to another electronic device. The first and second terminals may be formed simultaneously with the third electrode. Alternatively, the first and second terminals are formed in a subsequent processing step as forming the third electrode.

[0089] The AMHET structure operates like a transistor by adjusting the electric field applied to the first, second, and third electrodes. The first electrode can be an emitter electrode, the second electrode can be a base electrode, and the third electrode can be a collector electrode. The transistor structure can operate in common-emitter mode, common-base mode, or common-collector mode.

[0090] In response to a voltage applied through the first terminal, electrons tunnel from the first electrode, the emitter electrode, through the first tunnel insulator, and into the amorphous metal interconnect. The electrons travel through the amorphous metal interconnect and the first tunnel insulator to the second electrode, the base electrode. These electrons are considered "hot" when tunneling terminates because their energy exceeds the Fermi energy of the second electrode, the base electrode. These principles apply to all embodiments described in this disclosure.

[0091] Unlike typical transistor structures, the amorphous metal transistor structure can operate in a reverse mode, where electrons are transferred from the third electrode through the second electrode and amorphous metal interconnect to the first electrode. In this reverse mode, the transistor structure functions like a tunnel diode with adjustable threshold voltage and asymmetry. The adjustable threshold voltage and asymmetry are achieved by modulating the electric field applied to the second electrode in combination with the electric fields applied from the first electrode 108 and the third electrode.

[0092] In a further embodiment, the AMHET structure includes an amorphous metal layer formed on a non-conductive supporting substrate, or an insulator on the substrate to isolate the substrate from the amorphous metal layer. A tunnel oxide layer is formed on the amorphous metal layer. First and second electrodes are formed on the tunnel oxide, and are coplanarly arranged such that portions of the first and second electrodes overlap the amorphous metal layer.

[0093] A dielectric layer is formed on the first electrode and the second electrode. A third electrode and a fourth electrode are formed on the dielectric layer. Portions of the third electrode and the fourth electrode overlap the amorphous metal layer and the first electrode and the second electrode, respectively. The third electrode and the fourth electrode are formed simultaneously from the same material. A contact can also be formed simultaneously with the third electrode and the fourth electrode. The contact couples to the second electrode through the dielectric layer, and the contact couples to the first electrode through the dielectric layer.

[0094] The first overlapping region of the amorphous metal layer, the first electrode, and the third electrode formation portion is a region where electrons can travel between the first electrode and the amorphous metal layer. A second active region exists corresponding to the overlapping of the amorphous metal layer, the second electrode, and the fourth electrode. This second active region is a region where electrons can travel between the second electrode and the amorphous metal layer.

[0095] The first and second electrodes correspond to the emitter and base, respectively. The third and fourth electrodes correspond to the collector electrodes. These two collector electrodes form two transistor structures with a shared base and emitter. These two transistor structures can be formed in the same way as the transistor structure; the difference is simply that more conductive layers are left behind when forming the third electrode.

[0096] In another embodiment, the AMHET transistor structure includes an amorphous metal film formed on a substrate, and a tunnel insulator on the amorphous metal film.

[0097] In some regions, the tunnel dielectric is thinned or patterned to have a different thickness than other regions of the tunnel dielectric. By adjusting the thickness of the tunnel dielectric, the operating characteristics of the transistor structure can be adjusted. If the tunnel dielectric is selectively thinned in one active region, there may not be symmetrical conduction through the emitter-base structure due to the different thicknesses. This may be acceptable for some end use cases.

[0098] A first electrode is formed overlying the amorphous metal film and separated from the amorphous metal film by a tunnel insulator having a first thickness. A second electrode, which may be the same material as the first electrode and formed in the same processing step or a different material formed at a different time, is formed overlying the amorphous metal film. The second electrode is spaced from the first electrode and oriented generally parallel to the first electrode.

[0099] The second electrode is separated from the amorphous metal film by a tunnel insulator having a second thickness less than the first thickness. The behavior of electrons passing between the first electrode and the amorphous metal film differs from the behavior of electrons passing between the second electrode and the amorphous metal film as a result of the difference in the first thickness. For example, the patterned tunnel insulator can minimize parasitic capacitance that may form at the overlap between the first electrode and the second electrode and the amorphous metal film. In this manner, the tunnel insulator can be patterned in the overlap region of either electrode as required by manufacturing and the final product.

[0100] An insulator is formed on the first electrode and the second electrode. A third electrode is formed on the first electrode and the second electrode. Contacts for coupling to the second electrode and the first electrode, respectively, are formed simultaneously with the third electrode.

[0101] In a further embodiment, an AMHET transistor structure has base and emitter electrodes of different dimensions. The transistor structure includes an amorphous metal interconnect formed on a planar substrate. The amorphous metal interconnect is rectangular in top view and has a longest dimension extending in a first direction.

[0102] A tunnel insulator is located on the interconnect. An emitter electrode is located on the tunnel insulator. A base electrode is also located on the tunnel insulator and spaced from the emitter electrode. Both the emitter electrode and the base electrode at least partially overlie and overlap the interconnect.

[0103] The base electrode includes at least a portion that overlaps and aligns with the interconnect, the interconnect having a first dimension that is smaller than a second dimension of the emitter electrode. The different dimensions change the operating characteristics of the transistor and provide manufacturers with opportunities to tailor the transistor structure. For example, a thinner base electrode can increase the gain of the transistor structure. The base and emitter electrodes can be the same material or different materials.

[0104] The base electrode may be formed to a first thickness and then thinned as shown, such that a first portion of the base electrode has a first thickness and a second portion of the base electrode has a second thickness that is less than the first thickness. Alternatively, the base electrode may be formed in a different processing step from the emitter electrode or may be formed to be thinner than the emitter electrode. Instead of removing a portion of the base electrode once it has been formed, the base electrode may be formed as a layer thinner than the emitter electrode.

[0105] A first dielectric layer is formed over the base and emitter electrodes. A collector electrode is formed on the first dielectric layer. A contact to the base electrode can be formed simultaneously from the same material as the collector electrode. An opening through the first dielectric layer is formed to allow contact to the base electrode. Another contact to the emitter electrode can be formed in a similar manner.

[0106] A second dielectric layer can be formed over the collector electrode and the contact, and in some embodiments, the contact is formed through the second dielectric layer to couple the collector terminal to another device.

[0107] In a further embodiment, the AMHET transistor structure includes an amorphous metal layer formed on a substrate. A tunnel oxide layer is formed on the amorphous metal layer. A barrier layer is formed on the tunnel oxide layer. The barrier layer may be an inorganic material such as a metal oxide, an organic material such as a polymer, or any suitable material. The barrier layer can minimize parasitic capacitance that may occur due to overlap between the amorphous metal and the electrode.

[0108] A first opening is formed in the barrier layer. A first electrode is formed in the first opening. The first electrode overlaps the amorphous metal layer. A second opening is formed in the barrier layer so as to overlap a portion of the amorphous metal layer. A second electrode is formed so as to overlap a portion of the amorphous metal layer, with a portion of the second electrode in the second opening.

[0109] A dielectric layer is formed over the first electrode and the second electrode. A third electrode is formed over the dielectric layer. In embodiments, none of the layers are planarized. In other embodiments, each layer or portion of a layer is planarized.

[0110] The fourth electrode and the fifth electrode are paired with the first electrode and the second electrode, respectively, and can be formed from the same material as the third electrode at the same time.

[0111] The first and second electrodes of this embodiment or any embodiment of this disclosure may also be formed of ultrathin, two-dimensional conductors such as graphene, MoS2, W2, Ti3C2, GaN, BN, Ca2N, or other suitable materials. In some embodiments, the first electrode is an atomically thin layer of conductive material and the second electrode is a much thicker layer of conductive material. The conductive materials in these layers may be different types of conductors.

[0112] In another embodiment, an AMHET transistor structure includes an amorphous metal layer formed in a recess in a substrate, the first surface of the amorphous metal layer being coplanar with the first surface of the substrate.

[0113] A tunnel oxide layer is formed on the amorphous metal layer and the first surface of the substrate. A first electrode and a second electrode are formed on the tunnel oxide layer. The first electrode overlaps a first portion of the amorphous metal layer, and the second electrode overlaps a second portion of the amorphous metal layer.

[0114] A first dielectric layer is formed on the first electrode and the second electrode, a third electrode is formed on the flat surface of the first dielectric layer, and a second dielectric layer is formed on the third electrode.

[0115] In yet another embodiment, an AMHET transistor structure includes an amorphous metal layer formed on a flat surface of a substrate. A tunnel oxide layer is on the amorphous metal layer. The sides of the amorphous metal layer and the sides of the tunnel oxide layer are coplanar. This can be achieved by forming the amorphous layer, forming the tunnel oxide layer, and then simultaneously etching both layers.

[0116] A first electrode and a second electrode are formed on the tunnel oxide layer, a dielectric layer is formed on the first electrode and the second electrode, and a third electrode is formed on the dielectric layer.

[0117] Advantageously, the processing steps used to form the AMTFTs of the present disclosure can also be used to form AMNRs and / or AMHETs adjacent to the AMTFTs. For example, as shown in Figures 12A and 12B, an AMTFT 1200 (shown in Figure 1 and described above) is formed adjacent to an AMNR 1220 on a supporting substrate 1202. As will be appreciated by those of ordinary skill in the art, the AMNRs shown in Figures 12A-17 can be replaced with AMHETs, or any other suitable structures, and similar processing advantages can be achieved.

[0118] In an embodiment, the amorphous metal gate electrode 1204 and the amorphous metal interconnect 1224 are deposited and formed in the same processing steps, which may include forming a first amorphous metal layer on the substrate 1202, patterning the first amorphous metal layer, and removing portions of the first amorphous metal layer.

[0119] The AMTFT 1200 may be a transistor in a section circuit such that the AMNR 1220 is a pixel within the display area and the distance between the AMTFT and the AMNR is relatively large. In such an embodiment, the AMTFT and the AMNR may not be directly coupled. In other embodiments, the AMTFT and the AMNR may be part of a single pixel and directly coupled to each other.

[0120] A first tunnel insulator 1206 is deposited on the amorphous metal gate electrode 1204 and the amorphous metal interconnect 1224. This first tunnel insulator may be a conformal layer formed without a mask. Next, source / drain electrodes 1208, 1210 and first and second electrodes 1228, 1230 are deposited on the first tunnel insulator 1206, as described according to other embodiments of the present disclosure. The source / drain electrodes 1208, 1210 and first and second electrodes 1228, 1230 can be deposited as single layers, such as amorphous metal layers, patterned, and then etched to form the appropriate shapes. For example, the source / drain electrodes 1208, 1210 have ends 1211, 1213 that extend away from the gate 1204 to be coupled to other devices or to ends 1215, 1217 of the first and second electrodes 1228, 1230.

[0121] channel Conduction part 1212 is deposited to overlap the source / drain electrodes 1208, 1210. Additionally, a second insulator 1214 is optionally deposited over the channel Conduction part1212, deposited on the source / drain electrodes 1208, 1210, and the first and second electrodes 1228, 1230. Conduction part The AMNRs may be formed as a layer, such as an amorphous semiconductor layer, patterned, and then etched. This process may involve a three-mask process. This AMTFT structure allows the AMNRs to be formed well before the semiconductor layers required for the AMTFT channel are deposited. This reduces damage to the tunnel insulator of the AMNRs during channel deposition and formation.

[0122] Similarly, processing steps used to form other AMTFTs of the present disclosure can also be used to form such AMNRs adjacent to AMTFTs. For example, as shown in Figure 13A, cross-sectional view, and 13B, an AMTFT 1300 (shown in Figure 2 and described above) is formed adjacent to an AMNR 1320 on a supporting substrate 1302. In such an embodiment, an amorphous metal gate electrode 1304 and an amorphous metal interconnect 1324 are deposited and formed in the same processing step(s). A first tunnel insulator 1306 is then deposited and formed on the amorphous metal gate electrode 1304 and the amorphous metal interconnect 1324. Next, a channel Conduction part 1312 is deposited on the first tunnel insulator 1306. The channel is formed before the AMNR is completed and is patterned and etched to overlap the metal gate electrode 1304.

[0123] Next, source / drain electrodes 1308, 1310 are connected to the channel Conduction part1312 and the first tunnel insulator 1306, and first and second electrodes 1328, 1330 are deposited and formed on the first tunnel insulator 1306 as described herein. The source / drain electrodes 1308, 1310 and the first and second electrodes 1328, 1330 can be formed simultaneously from the same material. In some embodiments, they can be different materials formed in different processing steps, if this is beneficial to the final product. Additionally, the second insulator 1314 can optionally be formed between the source / drain electrodes 1308, 1310, the channel Conduction part 1312, and deposited on the first and second electrodes 1328, 1330. Although not shown, the AMNR and AMTFT can be coupled to each other and to other circuits, and this point can also be applied to the other embodiments described.

[0124] In an additional example, as shown in Figure 14A, cross-sectional view, and Figure 14B, top view, an AMTFT 1400 (as shown in Figure 3 and described above) is formed adjacent to an AMNR 1420 on a supporting substrate 1402. In such an embodiment, an amorphous metal gate electrode 1404 and an amorphous metal interconnect 1424 are deposited and formed in the same processing step(s). A first tunnel insulator 1406 is then deposited and formed on the amorphous metal gate electrode 1404 and the amorphous metal interconnect 1424. Thereafter, a channel Conduction part 1412 is deposited on the first tunnel insulator 1406. Then, source / drain electrodes 1408, 1410 are formed on the channel Conduction part 1412 and the first tunnel insulator 1406, and first and second electrodes 1428, 1430 are deposited and formed on the first tunnel insulator 1406 as described herein. Additionally, a second insulator 1414 is deposited and formed, optionally, on the source / drain electrodes 1408, 1410, the channel Conduction part 1412, and first and second electrodes 1428, 1430. A second gate electrode 1416 is then deposited on the second insulator 1414.

[0125] In a further embodiment, an AMTFT 1500 (shown in FIGS. 4A and 4B and described above) and an AMNR 1520 are formed adjacent to each other, as shown in FIG. 15A, a cross-sectional view, and FIG. 15B, a top view. A first insulator 1514 is deposited and formed on a supporting substrate 1502. Next, a channel Conduction part 1512 is deposited on the first insulator 1514. Source / drain electrodes 1508, 1510 are deposited with amorphous metal, forming a channel. Conduction part 1512. In the same step(s), an amorphous metal interconnect 1524 is deposited and formed on the first insulator 1514. Next, a second tunnel insulator 1506 is deposited and formed on the source / drain electrodes 1508, 1510 and on the amorphous metal interconnect 1524. The gate electrode 1516 and the first and second electrodes 1528, 1530 are then formed on the second tunnel insulator 1506, and may be formed in the same process step or steps. According to such an AMTFT structure, the AMTFT channel Conduction part The AMNRs can be fully formed after the underlying semiconducting layer is deposited and formed, which reduces the possibility of damaging the tunnel insulator of the AMNRs during channel deposition and formation.

[0126] In another embodiment, an AMTFT 1600 (shown in FIGS. 5A and 5B and described above) and an AMNR 1620 are formed adjacent to each other, as shown in FIG. 16A, a cross-sectional view, and FIG. 16B, a top view. A first insulator 1614 is formed by deposition on a supporting substrate 1602. Source / drain electrodes 1608, 1610 are formed by depositing amorphous metal on the first insulator 1614. In the same step(s), amorphous metal interconnects 1624 are formed by deposition on the first insulator 1614. Next, a channel Conduction part 1612 is deposited and formed to overlap the source / drain electrodes 1608, 1610. Next, a second tunnel insulator 1606 is formed between the source / drain electrodes 1608, 1610, the channel Conduction part1612, and amorphous metal interconnect 1624. Gate electrode 1616 and first and second electrodes 1628, 1630 are then formed on second tunnel insulator 1606 in the same processing step(s).

[0127] In another embodiment, as shown in Figure 17A, a cross-sectional view, and Figure 17B, an AMTFT 1700 (shown in Figures 6A and 6B and described above) and an AMNR 1720 are formed adjacent to each other. A first amorphous metal gate electrode 1704 and an amorphous metal interconnect 1724 are deposited and formed on a supporting substrate 1702. A first tunnel insulator 1706 is then formed on the amorphous metal gate electrode 1704 and the amorphous metal interconnect 1724. A channel insulator 1712 is then formed on the first tunnel insulator 1712. Conduction part A channel is formed. Conduction part A second tunnel insulator 1718 is deposited on the first gate electrode 1712. A second gate electrode 1716 is deposited on the second tunnel insulator 1718. A third insulator 1714 is deposited on the second gate electrode 1716 and the first tunnel insulator 1706. In an embodiment, the third insulator layer 1714 is deposited as a continuous layer, after which the channel Conduction part In another embodiment, the third insulator layer 1714 is partially removed to expose the first tunnel insulator 1706 at one or more locations. Conduction part The source / drain electrodes 1708, 1710 and the first and second electrodes 1728, 1730 are deposited as discontinuous layers such that the first tunnel insulator 1706 is exposed at one or more locations. Conduction part 1712 and formed on the third insulator layer 1714 in locations where the first tunnel insulator 1706 is exposed.

[0128] The embodiment of Figures 17A and 17B is a top-gate, self-aligned AMTFT with two gates: the first gate 1704 is the bottom gate, and the second gate 1716 is the last component formed.

[0129] A particular embodiment of an AMTFT and adjacent AMNR is shown in FIG. 18A , which is a cross-sectional view of an AMTFT structure 1800 and an AMNR structure 1820, and FIG. 18B , which is a similar top view. The AMTFT structure 1800 and the AMNR structure 1820 are formed on a supporting substrate 1802. The AMTFT 1800 includes an amorphous metal gate electrode 1804 on the supporting substrate 1802, and the AMNR structure 1820 includes an amorphous metal interconnect 1824. In embodiments, the amorphous metal gate electrode 1804 and the amorphous metal interconnect 1824 are deposited and formed in the same processing step(s). In some such embodiments, the amorphous metal gate electrode 1804 and the amorphous metal interconnect 1824 are formed of TiAl 3 . In some such embodiments, the amorphous metal gate electrode 1804 and the amorphous metal interconnect 1824 are about 60 nanometers (nm) thick.

[0130] A first tunnel insulator 1806 is then deposited and formed on the amorphous metal gate electrode 1804 and the amorphous metal interconnect 1824. In particular embodiments, the first tunnel insulator 1806 comprises Al2O3. In some such embodiments, the thickness of the first tunnel insulator 1806 is about 15 nm.

[0131] Then, the channel Conduction part 1812 is deposited and formed on the first tunnel insulator 1806. In some such embodiments, the channel Conduction part In some such embodiments, the channel 1812 is formed of InGaZnO. Conduction part The thickness of 1812 is about 20 nm.

[0132] The source / drain electrodes 1808, 1810 then form a channel Conduction part1812 and first tunnel insulator 1806, and first and second electrodes 1828, 1830 are deposited and formed on first tunnel insulator 1806 as described herein. In particular embodiments, source electrode 1808, drain electrode 1810, first electrode 1828, and second electrode 1830 are comprised of aluminum and molybdenum. In some such embodiments, each electrode includes a layer of aluminum that is about 300 nm thick and a layer of molybdenum that is about 80 nm thick.

[0133] The source / drain electrodes 1808, 1810 partially cover the channel Conduction part 1812 and partially on the surface of the first tunnel insulator 1806. Source / drain electrodes 1808, 1810 overlap the amorphous metal gate electrode 1804. In a specific embodiment, the source electrode 1808, drain electrode 1810 overlap the amorphous metal gate electrode 1804 by about 1 μm.

[0134] In some embodiments, the source and drain electrodes 1808, 1810 have a width of about 400 micrometers (μm). In particular embodiments, the source and drain electrodes 1808, 1810 are separated by a width of about 100 μm.

[0135] First and second electrodes 1828, 1830 are disposed on the amorphous metal interconnect 1824. In particular embodiments, the width of the first and second electrodes 1828, 1830 is about 5 μm. In some such embodiments, the amorphous metal interconnect 1824 is also about 5 μm wide.

[0136] The AMTFTs and AMNRs of Figures 18A and 18B were fabricated and tested. The resulting electron mobility transfer curves and plots are shown in Figure 18C. The current-voltage curve of the AMNR is shown in Figure 18D. The AMTFT is a bottom-gate, top-contact structure.

[0137] In various embodiments, the AMTFT structures described herein are used in circuit configurations. Accordingly, embodiments of the present disclosure include circuits that include AMTFTs. For example, AMTFTs can be used in reset / set flip-flops. An example circuit diagram of a reset / set flip-flop is shown in FIG. 19A. A timing diagram for a reset / set flip-flop that includes an AMTFT is shown in FIG. 19B, and a truth table is shown in FIG. 19C. The inputs and outputs are shown in the numbered lines in FIG. 19B that correspond to the "Phase" column in FIG. 19C.

[0138] In another embodiment, one or more AMTFTs are used in a display. In some such embodiments, the AMTFTs are used as switching TFTs in an active matrix liquid crystal display (AMLCD) or electrophoretic display (EPD) circuit. Figure 20A shows a circuit diagram of an exemplary AMLCD or EPD circuit. Figure 20B shows a top view of an exemplary matrix of AMLCDs in an EPD circuit. Figure 20C shows a single pixel circuit of the array, as indicated by the rectangle in Figure 20B. In this embodiment, the AMTFT structure 2000 includes a metal gate electrode 2004 and a first tunnel insulator (not shown) formed on the metal gate electrode 2004. The channel Conduction part 2012 is formed on the first tunnel insulator 2006. Source / drain electrodes 2008, 2010 are formed in part on the channel Conduction part The source / drain electrodes 2008, 2010 are disposed on the metal gate electrode 1904 and partially on the surface of the first tunnel insulator 2012.

[0139] In another embodiment, an AMTFT structure is used in an active matrix organic light emitting diode (AMOLED) circuit. As will be appreciated, an AMOLED circuit can have a variety of structures including different numbers of transistors and capacitors (e.g., two transistors and one capacitor, five transistors and two capacitors, six transistors and one capacitor, etc.). In various embodiments, any one or more transistors of an AMOLED circuit can be an AMTFT. In various embodiments, one of the transistors is an AMTFT. In embodiments, two of the transistors are AMTFT. In embodiments, three of the transistors are AMTFT. In embodiments, four of the transistors are AMTFT. In embodiments, five of the transistors are AMTFT. In embodiments, six of the transistors are AMTFT. In further embodiments, all of the transistors are AMTFT.

[0140] FIG. 21A shows a circuit diagram of an exemplary AMOLED circuit. Referring to FIG. 21A, the circuit includes two transistors and one capacitor. In various embodiments, the switching TFT, the driving TFT, or both are AMOLED TFTs. FIG. 21B shows a top view of an exemplary matrix of an AMOLED structure. FIG. 21C shows the circuitry of a single pixel of the array, as indicated by the rectangle in FIG. 21B.

[0141] A second exemplary AMOLED circuit containing six transistors and one capacitor is shown in FIG.

[0142] A third exemplary AMOLED circuit including five transistors and two capacitors is shown in FIG.

[0143] In further embodiments, the AMTFTs described herein are used in gate driver circuits. An exemplary gate driver circuit block diagram is shown in FIG. 24A and includes a shift register (G_SR), a clock line (CLK), and a buffer (BUF X5). An exemplary gate driver shift register circuit is shown in FIG. 24B. In various embodiments, any one or more of the transistors shown are AMTFTs. In other words, any of Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, or a combination thereof is an AMTFT. FIG. 24C shows an example of a gate driver buffer circuit in which AMTFTs can be used.

[0144] In a further embodiment, the source driver circuit includes one or more AMTFTs.

[0145] In a further embodiment, the cascode amplifier circuit includes one or more AMTFTs. An exemplary circuit diagram of a cascode amplifier circuit is shown in FIG.

[0146] In embodiments in which the substrate deforms at one or more locations, a corresponding number of angles can be measured. In some embodiments, the flexible substrate deforms at an angle of at least ±10 degrees. In some embodiments, the flexible substrate deforms at an angle of at least ±15 degrees. In some embodiments, the flexible substrate deforms at an angle of at least ±20 degrees. In some embodiments, the flexible substrate deforms at an angle of at least ±25 degrees. In some embodiments, the flexible substrate is deformed temporarily or permanently, as in use, to angles in the range of 45 to 90 degrees. In some embodiments, the flexible substrate is deformed at angles greater than 90 degrees.

[0147] As used herein, "about" means that the actual value may be slightly more or slightly less than the stated value or range, within ±20% of the stated value. In embodiments, "about" means that the actual value is within ±15% of the stated value. In embodiments, "about" means that the actual value is within ±10% of the stated value. In embodiments, about means that the actual value is within ±5% of the stated value. In embodiments, about means that the actual value is within ±1% of the stated value. In some embodiments, the first tunnel insulator is less than or equal to about 15 nanometers (nm). In some embodiments, the first tunnel insulator is not more than about 10 nanometers (nm). In some embodiments, the first tunnel insulator is not more than about 20 nanometers (nm). In some embodiments, the first tunnel insulator is about 15 nanometers (nm). In some embodiments, the first tunnel insulator is about 10 nanometers (nm).

[0148] The present disclosure provides a semiconductor device comprising a non-conductive substrate, an amorphous metal gate electrode on the substrate, and a channel Conduction part The present invention is directed to embodiments including: a first tunnel insulator on the amorphous metal gate electrode; a source electrode and a drain electrode, in some embodiments, on the first tunnel insulator; the source electrode and the drain electrode overlap the amorphous metal gate electrode; and a channel electrode, in some embodiments, on the first tunnel insulator. Conduction part It is between.

[0149] The source and drain electrodes are, in some embodiments, connected to the first tunnel insulator and the channel Conduction part The second tunnel insulator is located above and overlaps the amorphous metal gate electrode. Conduction part The second insulator is on the first tunnel insulator. In some embodiments, the second gate electrode is on the second tunnel insulator. The second tunnel insulator may be on the source electrode and the drain electrode.

[0150] In some embodiments, the second gate electrode is on the third insulator. The second tunnel insulator is between the second gate electrode and the channel Conduction part The source and drain electrodes may be on the second tunnel insulator. In some embodiments, the source and drain electrodes are on the channel Conduction part abutting the exposed portion of one or more portions of the first tunnel insulator and the non-conductive substrate. In another embodiment, the method includes an amorphous metal interconnect adjacent to the amorphous metal gate electrode on the non-conductive substrate, where the amorphous metal interconnect is between the first tunnel insulator and the non-conductive substrate.

[0151] In some embodiments, the non-conductive substrate comprises an amorphous metal source electrode, an amorphous metal drain electrode, and a channel Conduction part The first tunnel insulator is on the amorphous metal source electrode and the amorphous metal drain electrode. The gate electrode is on the first tunnel insulator. The second tunnel insulator is on the non-conductive substrate and the channel. Conduction part It may be between.

[0152] The various embodiments described above can be combined to provide further embodiments. The U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications, and / or their associated application data sheets, all of which are referenced herein, are incorporated by reference in their entirety. Aspects of the embodiments can be modified, as necessary, to incorporate concepts from the various patents, applications, and publications to provide further embodiments.

[0153] These and other changes can be made to the embodiments in light of the above detailed description. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments, along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

[0154] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 62 / 651,014, filed March 30, 2018, and U.S. Provisional Application No. 62 / 777,009, filed December 7, 2018, both of which are incorporated herein by reference in their entireties.

Claims

1. a non-conductive substrate; an amorphous metal alloy gate electrode; an insulator on the amorphous metal alloy gate electrode, wherein the insulator has a first surface and a second surface opposite the first surface, the second surface facing the amorphous metal alloy gate electrode; an amorphous metal source electrode having a third surface and formed of an amorphous metal; an amorphous metal drain electrode having a fourth surface and formed of an amorphous metal, wherein the third surface of the amorphous metal source electrode and the fourth surface of the amorphous metal drain electrode face each other with a gap therebetween that defines a distance from the amorphous metal source electrode to the amorphous metal drain electrode; Conduction channel and It is equipped with the channel conductive portion is in direct contact with the first surface of the insulator, the third surface of the amorphous metal source electrode, and the fourth surface of the amorphous metal drain electrode, with a portion of the channel conductive portion located in the gap between the third surface and the fourth surface. device.

2. the insulator contacts the amorphous metal source electrode and the amorphous metal drain electrode; The device of claim 1 .

3. the amorphous metal source electrode and the amorphous metal drain electrode are between the non-conductive substrate and the channel conducting portion; 3. A device according to claim 1 or 2.

4. The non-conductive substrate is a flexible substrate.

3. A device according to claim 1 or 2.

5. the device includes an amorphous metal thin film nonlinear resistor (AMNR) comprising an amorphous metal interconnect, a tunnel insulator on the amorphous metal interconnect, and first and second electrodes on the tunnel insulator; The amorphous metal interconnect is formed from the same metal layer as the amorphous metal alloy gate electrode. the tunnel insulator is formed of the same insulator layer as the insulator; the first electrode and the second electrode are formed from the same metal layer as the amorphous metal source electrode and the amorphous metal drain electrode; 3. A device according to claim 1 or 2.

6. forming an amorphous metal alloy gate electrode on a non-conductive substrate; forming an insulator on the amorphous metal alloy gate electrode, wherein the insulator has a first surface and a second surface opposite the first surface, the second surface facing the amorphous metal alloy gate electrode; forming an amorphous metal source electrode on a non-conductive substrate, the amorphous metal source electrode having a third surface; forming an amorphous metal drain electrode on the non-conductive substrate, the amorphous metal drain electrode having a fourth surface made of amorphous metal, wherein the third surface of the amorphous metal source electrode and the fourth surface of the amorphous metal drain electrode face each other with a gap therebetween that defines a distance from the amorphous metal source electrode to the amorphous metal drain electrode; forming a channel conductive portion, the channel conductive portion directly contacting the first surface of the insulator, the third surface of the amorphous metal source electrode, and the fourth surface of the amorphous metal drain electrode, with a portion of the channel conductive portion located in the gap between the third and fourth surfaces; A method comprising:

7. forming an amorphous metal interconnect, which is performed in the same process as forming the amorphous metal alloy gate electrode; forming first and second electrodes, the first and second electrodes being performed in the same process as both the amorphous metal source electrode and the amorphous metal drain electrode; Including, The insulator is deposited on the amorphous metal interconnect as a tunnel insulator, and the first and second electrodes are formed on the tunnel insulator to create an amorphous metal thin film nonlinear resistor (AMNR). The method of claim 6.

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