Semiconductor Devices

Abstract

To provide a semiconductor device having a novel configuration.SOLUTION: A first storage circuit unit includes a first storage circuit that holds a plurality of pieces of first weight data. A second storage circuit unit includes a second storage circuit that holds a plurality of pieces of second weight data. A first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit includes a function of providing any one of the plurality of pieces of first weight data to first wiring. The second switching circuit includes a function of providing any one of the plurality of pieces of second weight data to second wiring. The third switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit includes a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are becoming widespread. To process large amounts of data at high speed, such electronic devices are subject to active technological development aimed at improving the performance of semiconductor devices. One example of a technology that achieves high performance is the so-called SoC (System on Chip) technology, which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with a CPU. With semiconductor devices that achieve high performance through SoC technology, increased heat generation and power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the number of parameters becomes enormous, resulting in an increase in the amount of calculations. Since an increase in the amount of calculations leads to an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Typical architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective in reducing circuit scale and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] AI technology requires faster arithmetic processing. Circuit integration is an effective way to speed up arithmetic processing. By integrating an arithmetic circuit that performs arithmetic processing of weight data (also called weight parameters, filters, etc.) and input data with a memory circuit that stores the weight data, it is possible to realize AI technology calculations on an integrated circuit. In this case, necessary data such as weight data is read from the memory circuit to the arithmetic circuit via wiring such as bit lines. Data such as weight data is read more frequently along the path electrically connecting the memory circuit and arithmetic circuit. This increases the charge / discharge energy of the bit lines, which may increase power consumption.

[0007] In particular, neural networks that perform convolutional operations can be configured to perform arithmetic processing using the same weight data in multiple arithmetic circuits. In this case, the number of paths electrically connecting the storage circuits and the arithmetic circuits increases, which may make it difficult to charge and discharge the wiring quickly when reading data such as weight data at high speed. Therefore, it may be difficult to improve the arithmetic processing speed.

[0008] Shortening the bit lines is an effective way to reduce the charge / discharge energy of the bit lines, but this involves arranging the arithmetic circuits and memory circuits alternately, which can significantly increase the area of the peripheral circuits.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed.An object of one embodiment of the present invention is to provide a miniaturized semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0011] One aspect of the present invention includes a first calculation block having a first memory circuit unit and a first calculation circuit unit, a second calculation block having a second memory circuit unit and a second calculation circuit unit, and first wiring and second wiring, wherein the first memory circuit unit has a first memory circuit that holds a plurality of first weight data, the second memory circuit unit has a second memory circuit that holds a plurality of second weight data, the first calculation circuit unit has a first calculation circuit, a first switching circuit, and a third switching circuit, and the second calculation circuit unit has a second calculation circuit, a second switching circuit, and a fourth switching circuit. The semiconductor device has a first switching circuit that has a function of providing any one of a plurality of first weight data to a first wiring, a second switching circuit that has a function of providing any one of a plurality of second weight data to a second wiring, a third switching circuit that has a function of providing any one of the first weight data provided to the first wiring or the second weight data provided to the second wiring to a first arithmetic circuit, and a fourth switching circuit that has a function of providing any one of the first weight data provided to the first wiring or the second weight data provided to the second wiring to a second arithmetic circuit.

[0012] One embodiment of the present invention includes a first calculation block having a first memory circuit unit and a first calculation circuit unit, a second calculation block having a second memory circuit unit and a second calculation circuit unit, a first wiring, and a second wiring, wherein the first memory circuit unit has a first memory circuit that holds a plurality of first weight data, the second memory circuit unit has a second memory circuit that holds a plurality of second weight data, the first calculation circuit unit has a first calculation circuit, a first switching circuit, and a third switching circuit, and the second calculation circuit unit has a second calculation circuit, a second switching circuit, and a fourth switching circuit, wherein the first switching circuit has a function of providing any one of the plurality of first weight data to the first wiring, and the second switching circuit has a function of providing any one of the plurality of second weight data to the second wiring. the operation of providing any one of the plurality of first weight data to the first wiring is performed in a period different from the operation of providing any one of the plurality of second weight data to the second wiring; the third switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit; the fourth switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit; and the operation of providing the first weight data provided to the first wiring to the first arithmetic circuit is performed in a period different from the operation of providing the second weight data provided to the second wiring to the second arithmetic circuit.

[0013] In one embodiment of the present invention, the semiconductor device preferably has the first memory circuit unit provided in a layer stacked on a layer having the first arithmetic circuit unit, and the second memory circuit unit provided in a layer stacked on a layer having the second arithmetic circuit unit.

[0014] In one aspect of the present invention, the semiconductor device is preferably such that the first arithmetic circuit and the second arithmetic circuit each independently perform a product-sum operation.

[0015] In one embodiment of the present invention, the semiconductor device preferably includes a first transistor in each of the first memory circuit unit and the second memory circuit unit, and the first transistor includes a semiconductor layer having a metal oxide in a channel formation region.

[0016] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0017] In one embodiment of the present invention, the semiconductor device preferably includes a semiconductor layer having silicon in a channel formation region, and each of the first arithmetic circuit unit and the second arithmetic circuit unit includes a second transistor.

[0018] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with improved processing speed can be provided. Alternatively, according to one embodiment of the present invention, a miniaturized semiconductor device can be provided. Alternatively, a semiconductor device with a novel structure can be provided.

[0020] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0021] [Figure 1] 1A, 1B, and 1C are diagrams illustrating configuration examples of a semiconductor device. [Figure 2] 2A, 2B, 2C, and 2D are diagrams illustrating configuration examples of a semiconductor device. [Figure 3] 3A, 3B, and 3C are diagrams illustrating configuration examples of semiconductor devices. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 5]5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] 16A and 16B are diagrams illustrating a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of a processing system. [Figure 18] FIG. 18 is a diagram illustrating an example of the configuration of a CPU. [Figure 19] 19A and 19B are diagrams illustrating an example of the configuration of a CPU. [Figure 20] FIG. 20 is a timing chart showing an example of the operation of the CPU. [Figure 21] FIG. 21 is a diagram illustrating an example of the configuration of a transistor. [Figure 22] 22A and 22B are diagrams showing examples of the configuration of a transistor. [Figure 23] 23A and 23B are diagrams illustrating an example of the configuration of an integrated circuit. [Figure 24] 24A and 24B are diagrams illustrating an application example of an integrated circuit. [Figure 25] 25A and 25B are diagrams illustrating an application example of an integrated circuit. [Figure 26] 26A, 26B, and 26C are diagrams illustrating an application example of an integrated circuit. [Figure 27] FIG. 27 is a diagram illustrating an application example of an integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0022] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0024] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated explanations thereof may be omitted.

[0025] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0026] Furthermore, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, the symbol may be accompanied by an identifying symbol such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0027] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0028] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0029] Fig. 1A is a diagram illustrating a semiconductor device 10 according to one embodiment of the present invention, and Figs. 1B and 1C are diagrams illustrating configuration examples of a processing block included in the semiconductor device 10.

[0030] The semiconductor device 10 functions as an accelerator that executes a program (also called a kernel or kernel program) called from a host program. The semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0031] As shown in Fig. 1A, the semiconductor device 10 has a plurality of operation blocks 21. Each operation block 21 has a memory circuit unit 30 (also referred to as a memory cell array) and an operation circuit unit 40. As shown in Fig. 1A, the memory circuit unit 30 and the operation circuit unit 40 are provided in different layers in a direction approximately perpendicular to the xy plane in the figure (z direction in Fig. 1A). In other words, the memory circuit unit 30 and the operation circuit unit 40 are provided in a stacked manner.

[0032] Note that "substantially perpendicular" refers to a state in which the substrate is arranged at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X direction, Y direction, and Z direction shown in Figure 1A and other figures are perpendicular to or intersect with each other. The X direction and Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0033] The multiple processing blocks shown in FIG. 1A are roughly divided into two or more blocks with different operations and connection relationships. In this specification, the multiple processing blocks are described as odd-numbered processing block units 20_O and even-numbered processing block units 20_E, but they may be configured to be divided into three or more blocks. A processing block in processing block unit 20_O may be referred to as processing block 21_O. A processing block in processing block unit 20_E may be referred to as processing block 21_E.

[0034] 1B and 1C, the operation block 21_O and the operation block 21_E each have a memory circuit unit 30 and an operation circuit unit 40. Note that in the configurations shown in the operation block 21_O and the operation block 21_E, the explanations for the common parts can be used as appropriate.

[0035] The memory circuit unit 30 has a plurality of memory circuits 31. The memory circuit unit 30 may be called a memory cell array, and the memory circuits 31 may be called memory cells. Writing and reading of data to the memory circuits 31 is controlled by the driver circuits 12 and 13. The driver circuits 12 and 13 may also be called data control circuits.

[0036] The memory circuit 31 included in the memory circuit portion 30 includes a transistor having an oxide semiconductor in a channel formation region (OS transistor). Data stored (held) in the memory circuit 31 is data (weight data) corresponding to weight parameters used in product-sum calculation processing of a neural network. By storing the weight data as digital data, a semiconductor device that is resistant to noise and capable of high-speed calculation can be realized. Alternatively, the weight data may be analog data.

[0037] The weight data may be configured to perform arithmetic processing using 1-bit data (i.e., data of '1' or '0'), or may be configured to perform arithmetic processing using multi-bit data. In the case of multi-bit (e.g., n-bit) data, the weight data may be supplied using a number of wires corresponding to the number of bits.

[0038] The memory circuit 31 included in the memory circuit unit 30 can have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which the memory cells are two-transistor (2T) or three-transistor (3T) gain cells and the access transistors are OS transistors.

[0039] OS transistors have an extremely low leakage current, the current that flows between the source and drain when they are off. NOSRAM can be used as nonvolatile memory by utilizing its extremely low leakage current characteristics to retain a charge corresponding to the data within the memory circuit. NOSRAM is particularly suitable for parallel processing of product-sum operations in neural networks, which require repeated data read operations, because it can read the stored data without destroying it (non-destructive readout).

[0040] The memory circuit 31 is preferably a memory having an OS transistor, such as NOSRAM or DOSRAM (hereinafter also referred to as OS memory). The band gap of a metal oxide that functions as an oxide semiconductor is 2.5 eV or more, and therefore the OS transistor has a very small off-state current. For example, when the voltage between the source and drain is 3.5 V and the temperature is room temperature (25° C.), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 Therefore, the amount of charge leaked from the retention node of the OS memory via the OS transistor is extremely small. Therefore, the OS memory can function as a nonvolatile storage circuit, which enables power gating of the semiconductor device 10.

[0041] Semiconductor devices with highly integrated transistors may generate heat due to circuit operation. This heat increases the temperature of the transistor, which can change the transistor's characteristics, resulting in changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, making them less susceptible to temperature changes in field-effect mobility and a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, OS transistors enable stable operation in high-temperature environments.

[0042] Metal oxides suitable for OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical properties, such as field-effect mobility, by adjusting the ratio of elements. Furthermore, the oxide containing indium and zinc may contain one or more elements selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0043] To improve the reliability and electrical characteristics of OS transistors, the metal oxide used in the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0044] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0045] CAC-OS has the function of both allowing electrons (or holes) to flow and preventing electrons from flowing. By separating the electron flow function from the electron blocking function, both functions can be maximized. In other words, using CAC-OS in the channel formation region of an OS transistor can achieve both a high on-state current and an extremely low off-state current.

[0046] Metal oxides have a wide band gap, which makes it difficult for electrons to be excited, and they have a large effective mass for holes. This means that OS transistors are less susceptible to avalanche breakdown and other problems than typical Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0047] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), a short-channel effect, compared to inversion-type transistors (typically, Si transistors) with pn junctions. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0048] Because OS transistors have high resistance to short-channel effects, their channel length can be reduced without degrading their reliability, allowing for increased circuit integration. As the channel length decreases, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0049] Furthermore, because OS transistors have high resistance to short-channel effects, their gate insulating films can be thicker than those of Si transistors. For example, even for miniaturized transistors with channel lengths and widths of 50 nm or less, it may be possible to provide a gate insulating film as thick as about 10 nm. By increasing the gate insulating film thickness, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by increasing the gate insulating film thickness, leakage current through the gate insulating film can be reduced, leading to a reduction in static current consumption.

[0050] As described above, the semiconductor device 10 can retain data even when the supply of power supply voltage is stopped by having the storage circuit 31, which is an OS memory. This enables power gating of the semiconductor device 10, thereby enabling a significant reduction in power consumption.

[0051] The memory circuit unit 30 of the operation block 21_O may be referred to as the first memory circuit unit. The memory circuit unit 30 of the operation block 21_E may be referred to as the second memory circuit unit. The memory circuit 31 of the memory circuit unit 30 of the operation block 21_O may be referred to as the first memory circuit. The memory circuit 31 of the memory circuit unit 30 of the operation block 21_E may be referred to as the second memory circuit. The weight data stored in the memory circuit 31 of the memory circuit unit 30 of the operation block 21_O may be referred to as the first weight data. The weight data stored in the memory circuit 31 of the memory circuit unit 30 of the operation block 21_E may be referred to as the second weight data. The first weight data is weight data different from the second weight data.

[0052] The layer having the arithmetic circuit unit 40 has a latch circuit 41, a switching circuit 42, a buffer circuit 43_O (43_E), a switching circuit 44, and an arithmetic circuit 45. Control and processing of data input / output in the arithmetic circuit unit 40 are controlled by a control circuit 14 and a processing circuit 15. The control circuit 14 and the processing circuit 15 are also referred to as an arithmetic control circuit, an arithmetic processing circuit, or an arithmetic circuit.

[0053] Each of the latch circuit 41, the switching circuit 42, the buffer circuit 43_O (43_E), the switching circuit 44, and the arithmetic circuit 45 is preferably configured with a transistor having silicon in the channel forming region (Si transistor). This configuration enables high-speed switching of connection states and high-speed arithmetic processing.

[0054] Furthermore, by using Si transistors for each of the latch circuit 41, the switching circuit 42, the buffer circuit 43_O (43_E), the switching circuit 44, and the arithmetic circuit 45, they can be stacked with OS transistors. That is, the memory circuit unit 30, which is configured with OS transistors, can be stacked with the arithmetic circuit unit 40, which can be configured with Si transistors. This increases the area in which the memory circuit unit 30 can be arranged without increasing the circuit area. By locating the memory circuit unit 30 on the substrate on which the arithmetic circuit unit 40 is arranged, the memory capacity required for arithmetic processing in the semiconductor device 10 functioning as an accelerator can be increased compared to when the memory circuit unit 30 and the arithmetic circuit unit 40 are arranged on the same layer. The increased memory capacity reduces the number of data transfers required for arithmetic processing from an external storage device to the semiconductor device, thereby reducing power consumption.

[0055] The latch circuit 41 has a function of holding a plurality of weight data read out via wiring (also called a local bit line or a read bit line) connected to the memory circuit 31 of the memory circuit unit 30. Note that the latch circuit 41 can be omitted as necessary.

[0056] It is preferable that the wiring connected to the memory circuit 31 of the memory circuit unit 30 be short in order to read out the weight data from the memory circuit unit 30 to the latch circuit 41 at high speed. It is also preferable that the wiring connected to the memory circuit 31 of the memory circuit unit 30 be short in order to reduce energy consumption associated with charging and discharging. By shortening the physical distance between the arithmetic circuit unit 40 having the latch circuit 41 and the memory circuit unit 30 that stores the weight data, for example by stacking the layers, the parasitic capacitance generated in the signal lines can be reduced, thereby enabling lower power consumption.

[0057] The switching circuit 42 selects one of the multiple weight data held in the latch circuit 41 and outputs it to the buffer circuit 43_O (43_E). The switching circuit 42 has a multiplexer function. The switching circuit 42 has a function of selecting one of multiple input signals. The control signal lsel that controls the switching circuit 42 is the control signal lsel_O in the arithmetic circuit unit 40 of the operation block 21_O and the control signal lsel_E in the arithmetic circuit unit 40 of the operation block 21_E, allowing separate controls to be performed. The switching circuit 42 of the arithmetic circuit unit 40 of the operation block 21_O may be referred to as the first switching circuit. The switching circuit 42 of the arithmetic circuit unit 40 of the operation block 21_E may be referred to as the third switching circuit.

[0058] The buffer circuit 43_O transmits the weight data selected by the switching circuit 42 in the arithmetic circuit unit 40 of the arithmetic block 21_O to the wiring WOL. The buffer circuit 43_E transmits the weight data selected by the switching circuit 42 in the arithmetic circuit unit 40 of the arithmetic block 21_E to the wiring WEL. The buffer circuits 43_O and 43_E have the function of a tristate buffer circuit. The buffer circuits 43_O and 43_E are controlled by control signals gsel_O and gsel_E, respectively.

[0059] The wiring WOL is connected to the weight data (W O) stored in the memory circuit unit 30 in the operation block 21_E of the operation block unit 20_E. E ) The weight data transmitted via the wiring WOL and the wiring WEL is transmitted to the operation circuit 45 of each of the operation blocks 21_O and 21_E via the switching circuit 44. The wiring WOL may be referred to as the first wiring, and the wiring WEL may be referred to as the second wiring. The wirings WOL and WEL are wirings that are arranged according to the number of blocks in the multiple operation block section, and there may be three or more wirings.

[0060] The switching circuit 44 selects either the weight data transmitted to the wiring WOL or the weight data transmitted to the wiring WEL and outputs it to the arithmetic circuit 45. The switching circuit 44 has a multiplexer function. The control signal wsel that controls the switching circuit 44 can perform the same control for the arithmetic circuit unit 40 of the arithmetic block 21_O and the arithmetic circuit unit 40 of the arithmetic block 21_E. The switching circuit 44 of the arithmetic circuit unit 40 of the arithmetic block 21_O may be referred to as the second switching circuit. The switching circuit 44 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as the fourth switching circuit.

[0061] The arithmetic circuit 45 has the function of executing arithmetic processing such as a sum-of-products operation. The arithmetic circuit 45 performs a sum-of-products operation between input data input from the control circuit 14 and weight data provided from the switching circuit 44. The input data and weight data are preferably digital data. Digital data is less susceptible to noise. Therefore, the arithmetic circuit 45 is suitable for performing arithmetic processing that requires highly accurate calculation results. The arithmetic circuit 45 of the arithmetic circuit unit 40 of the arithmetic block 21_O may be referred to as a first arithmetic circuit. The arithmetic circuit 45 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as a second arithmetic circuit. In addition to arithmetic processing such as a sum-of-products operation, the arithmetic circuit 45 may also be configured to perform activation function calculations, quantization calculations, pooling calculations, etc.

[0062] Next, an example of the operation of the semiconductor device 10 shown in Figures 1A to 1C will be described. Figure 2A shows the weight data (weight data W) read out from the storage circuit 31 in the configuration of the operation block 21 applicable to the operation blocks 21_O and 21_E. O or W E , W in the figure O / W E 1 is a diagram showing, by dashed arrows, how the weight data W is supplied to the arithmetic circuit 45 via the buffer circuit 43 applicable to the buffer circuit 43_O or 43_E, the wiring WOL, WEL, and the switching circuit 44. The arithmetic circuit 45 receives the input data A and the weight data W O / W E The output data MAC is output by the multiplication and accumulation process of W. O (O stands for odd number), W O1 The weight data represented by W corresponds to the first weight data described above. E (E is even), W E1 The weight data represented as above corresponds to the second weight data described above.

[0063] The calculation circuit unit 40 in the calculation block 21_O of the calculation block unit 20_O can be represented in a simplified form as shown in Fig. 2B, when it is represented in a schematic manner following the state of the weight data shown in Fig. 2A. In Fig. 2B, the weight data W O 2B shows how the weight data W is given to the wiring WOL via the buffer circuit 43_O. O and the weight data W given to the wiring WEL E and either of the weight data (W in the figure) O / W E ) is selected by the switching circuit 44 and is provided to the arithmetic circuit 45 (not shown).

[0064] 2B, the arithmetic circuit unit 40 in the arithmetic block 21_E of the arithmetic block unit 20_E can be abbreviated as shown in FIG. 2C. In FIG. 2C, the weight data W E2C shows how the weight data W is given to the wiring WEL via the buffer circuit 43_E. O and the weight data W given to the wiring WEL E and either of the weight data (W in the figure) O / W E ) is selected by the switching circuit 44 and is provided to the arithmetic circuit 45 (not shown).

[0065] 2B and 2C, the calculation circuit unit 40 of the calculation block unit 20_O and the calculation circuit unit 40 of the calculation block unit 20_E are combined. In FIG. 2D, the weight data W read out from the memory circuit unit 30 (not shown) in the calculation circuit unit 40 of each calculation block unit 20_O is O1 or W ON (N is a natural number) is illustrated. In addition, in the calculation circuit unit 40 of each calculation block unit 20_E, weight data W E1 or W EN In the memory circuit unit 30 (not shown) corresponding to the arithmetic circuit unit 40 of the arithmetic block unit 20_O and the arithmetic block unit 20_E, different weight data are held, and the selected weight data (W in the figure) is stored. O / W E ) to the arithmetic circuit 45 (not shown).

[0066] 2B and 2C, the weight data W O / W E 3A and 3B, the weight data W is output to the switching circuit 44 without going through the buffer circuit 43_E (buffer circuit 43_O). FC 3A and 3B, the switching circuit 44 outputs the selected weight data (W in the figure). O / W E / W FC) can be output to an arithmetic circuit 45 (not shown).

[0067] Weight data W FC is the weight data used in the fully connected operation in a neural network that performs convolution operations. In fully connected operations, different weight data is used for each operation circuit. Different weight data W FC The weight data W FC_1 Weight data W FC_N (N is a natural number of 2 or more), as shown in FIG. 3C, different weight data W FC_1 Weight data W FC_N can be selected by a switching circuit 44 and output to an arithmetic circuit 45 (not shown).

[0068] 3A to 3C, the weight data W O / W E are shared by a plurality of arithmetic circuits, or different weight data W are used for each arithmetic circuit unit 40. FC Therefore, it is possible to configure a neural network that performs convolutional operations and fully connected operations so that the weight data required for these operations can be read out near the necessary operation circuits.

[0069] Next, the operations of the operation blocks 21_O and 21_E illustrated in FIG. 2D will be described with reference to FIGS. 4A, 4B, 5A, and 5B.

[0070] 4A will be described. In FIG. 4A, weight data W is stored in a storage circuit section corresponding to an arithmetic circuit section 40_O1 belonging to an odd-numbered arithmetic block section 20_O. O1 Select and read the wiring WOL as weight data W O14A is a diagram showing, with dashed arrows, a state in which the line WOL is charged and discharged to a potential corresponding to the line WOL. Note that FIG. 4A corresponds to the initial operation before the start of the calculation, and at this point the connection between the line WOL and the calculation circuit 45 is cut off by the switching circuit 44. Therefore, the charging and discharging operation of the line WOL does not determine the operation rate of the calculation in the calculation circuit 45. Note that it is preferable that the output of the switching circuit 44 does not become unstable by connecting the line WEL to the calculation circuit 45 or by supplying another fixed potential (H potential or L potential).

[0071] The operation of Fig. 4B will be described. Fig. 4B shows that the weight data W is transmitted to the arithmetic circuit 45 by turning on the connection between the wiring WOL and the arithmetic circuit 45 in the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E. O1 The buffer circuit 43_O included in the arithmetic circuit unit 40_O1 has already completed charging the wiring WOL in the immediately preceding operation, so even if the charge supply capability of the buffer circuit 43_O is small, it does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0072] In the operation of FIG. 4B, the weight data W is stored in the storage circuit section corresponding to the arithmetic circuit section 40_E1 belonging to the even-numbered arithmetic block section 20_E. E1 Select and read the wiring WEL and set the weight data W E1 At this point, the connection between the wiring WEL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WOL and the arithmetic circuit 45 are connected by the switching circuit 44. By driving in this manner, the charging and discharging operation of the wiring WEL does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0073] 5A will be described. In FIG. 5A, the weight data W is transmitted to the arithmetic circuit 45 by turning on the connection between the wiring WEL and the arithmetic circuit 45 in the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E. E1The buffer circuit 43_E included in the arithmetic circuit unit 40_E1 has already completed charging the wiring WEL in the immediately preceding operation, so even if the charge supply capability of the buffer circuit 43_E is small, it does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0074] In the operation of FIG. 5A, the weight data W is stored in the storage circuit section corresponding to the arithmetic circuit section 40_O2 belonging to the odd-numbered arithmetic block section 20_O. O2 Select and read the wiring WOL as weight data W O2 At this point, the connection between the wiring WOL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WEL and the arithmetic circuit 45 are connected by the switching circuit 44. By driving in this manner, the charging and discharging operation of the wiring WOL does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0075] The operation of Fig. 5B will be described. Fig. 5B shows how the weight data W is transmitted to the arithmetic circuit 45 by turning on the connection between the wiring WOL and the arithmetic circuit 45 in the switching circuit 44 in the arithmetic circuit unit 40 of the odd-numbered arithmetic block unit 20_O and the even-numbered arithmetic block unit 20_E. O2 The buffer circuit 43_O included in the arithmetic circuit unit 40_O2 has already completed charging the wiring WOL in the immediately preceding operation, so that even if the charge supply capability of the buffer circuit 43_O is small, it does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0076] In the operation of FIG. 5B, the weight data W is stored in the storage circuit section corresponding to the arithmetic circuit section 40_E2 belonging to the even-numbered arithmetic block section 20_E. E2 Select and read the wiring WEL and set the weight data W E2 At this point, the connection between the wiring WEL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WOL and the arithmetic circuit 45 are connected by the switching circuit 44. By driving in this manner, the charging and discharging operation of the wiring WEL does not become a rate-limiting factor for the operation of the arithmetic circuit 45.

[0077] 4A, 4B, 5A, and 5B, the odd-numbered operation block units 20_O and the even-numbered operation block units 20_E alternately charge and discharge the wiring WOL or WEL and supply the weight data charged and discharged to and from the wiring WOL or WEL to the operation circuit 45. As described above, in the configuration of one embodiment of the present invention, the charge and discharge operations of the wiring WOL and WEL do not limit the operation rate of the operation of the operation circuit 45, and the operation speed of the operation can be improved.

[0078] The above-described configuration of the semiconductor device 10 according to one embodiment of the present invention can be configured to charge the wiring at high speed even when the charge supply capability of the buffer circuit is limited, for example, when the buffer circuit is designed with a limited area. In contrast, as shown in FIG. 6 , when weight data W is supplied to the arithmetic circuit 45 via the wiring WL without switching the operation from the buffer circuit 43 of the arithmetic circuit unit 40, it takes time for the potential of the wiring WL to change according to the weight data, and the arithmetic processing speed may be insufficient. According to one embodiment of the present invention, in which the charging speed of the wiring WOL or WEL is increased, the arithmetic processing speed can be improved.

[0079] FIG. 7A is a schematic diagram showing a case where the memory circuit unit 30 and the arithmetic circuit unit 40 are stacked in the arithmetic block 21_O shown in FIG. 1B. The memory circuit unit 30 and the arithmetic circuit unit 40 are connected via wiring LBL. The configuration of FIG. 7A allows the area of the memory circuit unit to be increased without increasing the circuit area. As a result, a huge amount of weight data can be stored in the memory circuit unit, reducing the number of times weight data is transferred from an external memory, thereby achieving low power consumption. Furthermore, the semiconductor device can be made smaller.

[0080] Fig. 7B is a diagram for explaining transistors suitable for the memory circuit unit 30 and the arithmetic circuit unit 40 in the arithmetic block 21_O shown in Fig. 7A. It is also applicable to the arithmetic block 21_E.

[0081] The memory circuit portion 30 includes a memory circuit 31. The memory circuit 31 includes a transistor 51. When a semiconductor layer 52 included in the transistor 51 is an oxide semiconductor (metal oxide), the memory circuit 31 can be formed using the above-described OS transistor.

[0082] The arithmetic circuit unit 40 includes a latch circuit 41, a switching circuit 42, a buffer circuit 43_O, a switching circuit 44, and an arithmetic circuit 45. Each circuit included in the arithmetic circuit unit 40 includes a transistor 53. By using silicon for the semiconductor layer 54 included in the transistor 53, each circuit included in the arithmetic circuit unit 40 can be configured as the above-described Si transistor.

[0083] By locating the memory circuit unit 30 in an area on the substrate where the arithmetic circuit unit 40 is located, it is possible to increase the memory capacity required for arithmetic processing in the semiconductor device 10 functioning as an accelerator, i.e., the number of memory circuits, compared to when the memory circuit unit 30 and the arithmetic circuit unit 40 are located on the same layer. Increasing the memory capacity reduces the number of times data required for arithmetic processing is transferred from an external storage device to the semiconductor device, thereby achieving lower power consumption.

[0084] When the memory circuit unit 30 and the arithmetic circuit unit 40 are on separate chips, the bus width is limited by the number of pins on the chip. On the other hand, in a configuration in which the memory circuit unit 30 and the arithmetic circuit unit 40 are stacked as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased depending on the opening where the wiring LBL is provided, thereby enabling efficient arithmetic processing.

[0085] When there are multiple operation blocks, the operation blocks 21_O and 21_E are provided along the wirings WOL and WEL as shown in Fig. 8. This configuration shortens the distance between the wirings WOL and WEL and the operation blocks 21_O and 21_E, thereby enabling miniaturization and low power consumption of the semiconductor device.

[0086] Next, referring to FIG. 9, a block diagram showing the entire arithmetic processing system 100 including the semiconductor device 10 that functions as an AI accelerator will be described.

[0087] 9 illustrates an accelerator unit 130 having a plurality of semiconductor devices 10 described in FIG. 1A, as well as a CPU 110 and a bus 120. The CPU 110 has a CPU core 200 and a backup circuit 222. The accelerator unit 130 has a plurality of semiconductor devices 10, as well as a control unit 131 for controlling input and output of data between the semiconductor devices 10.

[0088] The CPU 110 has the function of performing general-purpose processing, such as running an operating system, controlling data, and executing various calculations and programs. The CPU 110 has a CPU core 200. The CPU core 200 corresponds to one or more CPU cores. The CPU 110 also has a backup circuit 222 that can retain data in the CPU core 200 even if the supply of power voltage is stopped. The supply of power voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power voltage is sometimes called a drive voltage. An OS memory having an OS transistor, for example, is suitable as the backup circuit 222.

[0089] The backup circuit 222, which is configured with OS transistors, can be stacked on the CPU core 200, which can be configured with Si transistors. Because the area of the backup circuit 222 is smaller than the area of the CPU core 200, the backup circuit 222 can be placed on the CPU core 200 without increasing the circuit area. The backup circuit 222 has a function of retaining data in the registers of the CPU core 200. The backup circuit 222 is also referred to as a data retention circuit. Details of the configuration of the CPU core 200 equipped with the backup circuit 222 having OS transistors will also be described in the third embodiment.

[0090] The control unit 131 has an internal memory circuit such as an SRAM. The control unit 131 stores output data MAC obtained from the multiple semiconductor devices 10 in the memory circuit. The control unit 131 is configured to output the output data MAC stored in the memory circuit to the multiple semiconductor devices. This configuration enables parallel calculation using the multiple semiconductor devices with an increased parallelism.

[0091] The bus 120 electrically connects the CPU 110 and the accelerator unit 130. That is, the CPU 110 and the semiconductor device 10 can transmit data via the bus 120.

[0092] 10A is a diagram illustrating an example of a circuit configuration applicable to the memory circuit unit 30 in the semiconductor device 10 of the present invention. Fig. 10A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wirings LBL_1 to LBL_N, which are arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or more). Also illustrated is a memory circuit 31 connected to each word line and bit line.

[0093] 10B illustrates an example of a circuit configuration that can be applied to the memory circuit 31. The memory circuit 31 includes a transistor 61, a transistor 62, a transistor 63, and a capacitor 64 (also referred to as a capacitor).

[0094] One of the source or drain of the transistor 61 is connected to a write bit line WBL. The gate of the transistor 61 is connected to a write word line WWL. The other of the source or drain of the transistor 61 is connected to one electrode of a capacitance element 64 and the gate of the transistor 62. One of the source or drain of the transistor 62 and the other electrode of the capacitance element 64 are connected to a wiring that applies a fixed potential, such as a ground potential. The other of the source or drain of the transistor 62 is connected to one of the source or drain of a transistor 63. The gate of the transistor 63 is connected to a read word line RWL. The other of the source or drain of the transistor 63 is connected to a wiring LBL. The wiring LBL is connected to a latch circuit 41 (not shown) in the arithmetic circuit unit 40 via a wiring that extends in a direction substantially perpendicular to the surface of the substrate on which the Si transistors of the arithmetic circuit unit 40 are provided.

[0095] The circuit configuration of the memory circuit 31 shown in FIG. 10B corresponds to a three-transistor (3T) gain cell NOSRAM. Transistors 61 to 63 are OS transistors. In an OS transistor, the current flowing between the source and drain in the off state, i.e., the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by utilizing its extremely small leakage current characteristic to retain charge corresponding to data within the memory circuit.

[0096] The circuit configuration applicable to the memory circuit 31 in FIG. 10A is not limited to the 3T NOSRAM in FIG. 10B. For example, a circuit equivalent to the 2T NOSRAM illustrated in FIG. 11A may also be used. FIG. 11A illustrates a memory circuit 31A including a transistor 61B, a transistor 62B, and a capacitor 64B. The transistors 61B and 62B are OS transistors. The transistors 61B and 62B may be OS transistors whose semiconductor layers are arranged in different layers or may be OS transistors whose semiconductor layers are arranged in the same layer. The memory circuit 31A is illustrated as being connected to a write bit line WBL, a wiring LBL functioning as a read bit line, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0097] A circuit configuration applicable to the memory circuit 31 of FIG. 10A may be a circuit combining 3T-type NOSRAMs as shown in FIG. 11B. FIG. 11B illustrates a memory circuit 31B including a memory circuit 31_P and a memory circuit 31_N, each capable of holding data of different logic levels. FIG. 11B illustrates a memory circuit 31_P including a transistor 61_P, a transistor 62_P, a transistor 63_P, and a capacitor 64_P, and a memory circuit 31_N including a transistor 61_N, a transistor 62_N, a transistor 63_N, and a capacitor 64_N. Each transistor included in the memory circuit 31_P and the memory circuit 31_N is an OS transistor. Each transistor included in the memory circuit 31_P and the memory circuit 31_N may be an OS transistor having semiconductor layers arranged in different layers or may be an OS transistor having semiconductor layers arranged in the same layer. The memory circuit 31B is shown connected to a write bit line WBL_P, a wiring LBL_P, a write bit line WBL_N, a wiring LBL_N, a write word line WWL, and a read word line RWL. The memory circuit 31B can store data of different logics and read the data of different logics to the wiring LBL_P and the wiring LBL_N.

[0098] FIG. 12 is a diagram for explaining the operations of the switching circuit 42, the buffer circuits 43 (43_O, 43_E), and the switching circuit 44. In FIG. 12, for ease of understanding, the semiconductor device will be described as having four arithmetic blocks. In FIG. 12, memory circuit units 30_1 to 30_4 and arithmetic circuit units 40_1 to 40_4 are illustrated as examples of the configuration of the four arithmetic blocks. A combination of the memory circuit unit 30_1 and the arithmetic circuit unit 40_1, and a combination of the memory circuit unit 30_3 and the arithmetic circuit unit 40_3 correspond to the configuration of odd-numbered arithmetic block units. A combination of the memory circuit unit 30_2 and the arithmetic circuit unit 40_2, and a combination of the memory circuit unit 30_4 and the arithmetic circuit unit 40_4 correspond to the configuration of even-numbered arithmetic block units.

[0099] The memory circuit portion 30_1 includes a memory circuit 31 connected to the wirings LBL_11 to LBL_1N. 11 or W 1N The memory circuit portion 30_2 includes a memory circuit 31 connected to the wirings LBL_21 to LBL_2N. 21 or W 2N The memory circuit portion 30_3 includes a memory circuit 31 connected to the wirings LBL_31 to LBL_3N. 31 or W 3N The memory circuit portion 30_4 includes a memory circuit 31 connected to the wirings LBL_41 to LBL_4N. 41 or W 4N Hold.

[0100] In FIG. 12, the wirings LBL_11 to LBL_1N, the wirings LBL_21 to LBL_2N, the wirings LBL_31 to LBL_3N, and the wirings LBL_41 to LBL_4N are shown. P corresponds to the wiring extending in the vertical direction connecting the memory circuit section on the upper layer and the arithmetic circuit section on the lower layer. Pare shorter than the wires extending in the horizontal direction. Therefore, the parasitic capacitance of the wires LBL_11 to LBL_1N, the wires LBL_21 to LBL_2N, the wires LBL_31 to LBL_3N, and the wires LBL_41 to LBL_4N can be reduced, the charge required for charging and discharging the wires can be reduced, and power consumption can be reduced and calculation efficiency can be improved. In addition, the weight data can be read from the memory circuit 31 to the latch circuit at high speed.

[0101] The arithmetic circuit portion 40_1 includes a latch circuit 41_1, a switching circuit 42_1, a buffer circuit 43_1, a switching circuit 44_1, and an arithmetic circuit 45_1. The latch circuit 41_1 receives weight data W read from the memory circuit 31 included in the memory circuit portion 30_1 via wirings LBL_11 to LBL_1N. 11 or W 1N The switching circuit 42_1 is controlled by a control signal lsel_O. The buffer circuit 43_1 is controlled by a control signal gsel_O1. The switching circuit 44_1 is controlled by a control signal wsel. The arithmetic circuit 45_1 performs arithmetic processing by multiplying and adding the input data A1 and the weight data selected by the switching circuit 44_1, and outputs output data MAC1.

[0102] The arithmetic circuit portion 40_2 includes a latch circuit 41_2, a switching circuit 42_2, a buffer circuit 43_2, a switching circuit 44_2, and an arithmetic circuit 45_2. The latch circuit 41_2 receives weight data W read from the memory circuit 31 included in the memory circuit portion 30_2 via wirings LBL_21 to LBL_2N. 21 or W 2N The switching circuit 42_2 is controlled by a control signal lsel_E. The buffer circuit 43_2 is controlled by a control signal gsel_E1. The switching circuit 44_2 is controlled by a control signal wsel. The arithmetic circuit 45_2 performs arithmetic processing by multiplying and adding the input data A2 and the weight data selected by the switching circuit 44_2, and outputs output data MAC2.

[0103] The arithmetic circuit portion 40_3 includes a latch circuit 41_3, a switching circuit 42_3, a buffer circuit 43_3, a switching circuit 44_3, and an arithmetic circuit 45_3. The latch circuit 41_3 receives weight data W read from the memory circuit 31 included in the memory circuit portion 30_3 via wirings LBL_31 to LBL_3N. 31 or W 3N The switching circuit 42_3 is controlled by a control signal lsel_O. The buffer circuit 43_3 is controlled by a control signal gsel_O2. The switching circuit 44_3 is controlled by a control signal wsel. The arithmetic circuit 45_3 performs arithmetic processing by multiplying and accumulating the input data A3 and the weight data selected by the switching circuit 44_3, and outputs output data MAC3.

[0104] The arithmetic circuit portion 40_4 includes a latch circuit 41_4, a switching circuit 42_4, a buffer circuit 43_4, a switching circuit 44_4, and an arithmetic circuit 45_4. The latch circuit 41_4 receives weight data W read from the memory circuit 31 included in the memory circuit portion 30_4 via wirings LBL_41 to LBL_4N. 41 or W 4N The switching circuit 42_4 is controlled by a control signal lsel_E. The buffer circuit 43_4 is controlled by a control signal gsel_E2. The switching circuit 44_4 is controlled by a control signal wsel. The arithmetic circuit 45_4 performs arithmetic processing by multiplying and accumulating the input data A4 and the weight data selected by the switching circuit 44_4, and outputs output data MAC4.

[0105] Fig. 13 shows a timing chart for explaining the operation of each component explained in Fig. 12. The arithmetic circuit 45 is given weight data in accordance with the toggle operation of the clock signal CLK (for example, times T0 to T6), and performs arithmetic processing with the input data A1 to A4. By configuring the clock signal CLK to have a higher frequency, the arithmetic processing speed can be increased.

[0106] Input data A IN When the weight data is switched at high speed in response to the clock signal CLK, the data of the wirings WOL and WEL that provide the weight data must be switched at high speed.

[0107] The weight data W is transmitted via the wirings LBL_11 to LBL_1N, the wirings LBL_21 to LBL_2N, the wirings LBL_31 to LBL_3N, and the wirings LBL_41 to LBL_4N. 11 or W 1N , weight data W 21 or W 2N , weight data W 31 or W 3N , weight data W 41 or W 4N are held in the latch circuits 41_1 to 41_4. 11 or W 1N , weight data W 21 or W 2N , weight data W 31 or W 3N , weight data W 41 or W 4N The readout may be performed simultaneously or sequentially in each memory circuit unit.

[0108] At time T1, the weight data W is output from the latch circuits 41_1 and 41_3 in response to the control signal lsel_0. 11 , weight data W 31 The control signal gsel_O1 is set to H level, and the weight data W selected by the switching circuit 42_1 is selected. 11 The wiring WOL is charged with a potential according to the voltage Vcc of the wiring WOL. At this time, the wiring WOL can be charged at high speed as described above.

[0109] At time T2, the weight data W is output from the latch circuits 41_2 and 41_4 in response to the control signal lsel_E. 21 , weight data W 41 The control signal gsel_E1 is set to H level, and the weight data W selected by the switching circuit 42_2 is selected. 21 The wiring WEL is charged with a potential according to the weight data W of the wiring WEL charged at the previous time T1. 11The control signal wsel is supplied to the switching circuits 44_1 to 44_4 to switch between potentials according to the weight data W, and the potentials are supplied to the arithmetic circuits 45_1 to 45_4. 11 and performs a product-sum operation according to the above to calculate output data MAC1 to MAC4.

[0110] At time T3, the control signal gsel_O2 is set to H level, and the weight data W selected by the switching circuit 42_3 is 31 The wiring WOL is charged with a potential corresponding to the weight data W of the wiring WEL charged at the previous time T2. 21 The control signal wsel is supplied to the switching circuits 44_1 to 44_4 to switch between potentials according to the weight data W, and the potentials are supplied to the arithmetic circuits 45_1 to 45_4. 21 and performs a product-sum operation according to the above to calculate output data MAC1 to MAC4.

[0111] At time T4, the control signal gsel_E2 is set to H level, and the weight data W selected by the switching circuit 42_4 is 41 The wiring WEL is charged with a potential corresponding to the weight data W of the wiring WEL charged at the previous time T3. 31 The control signal wsel is supplied to the switching circuits 44_1 to 44_4 to switch between potentials according to the weight data W, and the potentials are supplied to the arithmetic circuits 45_1 to 45_4. 31 and performs a product-sum operation according to the above to calculate output data MAC1 to MAC4.

[0112] At time T5, the weight data W is output from the latch circuits 41_1 and 41_3 in response to the control signal lsel_0. 12 , weight data W 32 The control signal gsel_O1 is set to H level, and the weight data W selected by the switching circuit 42_1 is selected. 12The wiring WOL is charged with a potential corresponding to the weight data W of the wiring WEL charged at the previous time T4. 41 The control signal wsel is supplied to the switching circuits 44_1 to 44_4 to switch between potentials according to the weight data W, and the potentials are supplied to the arithmetic circuits 45_1 to 45_4. 41 and performs a product-sum operation according to the above to calculate output data MAC1 to MAC4.

[0113] At time T6, the weight data W is output from the latch circuits 41_2 and 41_4 in response to the control signal lsel_E. 22 , weight data W 42 The control signal gsel_E1 is set to H level, and the weight data W selected by the switching circuit 42_2 is selected. 22 The wiring WEL is charged with a potential according to the weight data W of the wiring WEL charged at the previous time T5. 12 The control signal wsel is supplied to the switching circuits 44_1 to 44_4 to switch between potentials according to the weight data W, and the potentials are supplied to the arithmetic circuits 45_1 to 45_4. 12 and performs a product-sum operation according to the above to calculate output data MAC1 to MAC4.

[0114] At subsequent times, by switching each control signal, the calculation circuits 45_1 to 45_4 can perform product-sum calculations while switching weight data at high speed, thereby calculating output data MAC1 to MAC4.

[0115] 14 shows a specific example of the configuration of the arithmetic circuit 45. In FIG. 14, weight data W (the above-mentioned W O , W E14 illustrates an example configuration of an arithmetic circuit 45 capable of performing a multiply-and-accumulate operation on a weight data W and input data A. FIG. 14 illustrates a multiplier circuit 71, an adder circuit 72, and a register 73. The data multiplied by the multiplier circuit 71 is input to the adder circuit 72. The output of the adder circuit 72 is held in the register 73, and the data multiplied by the multiplier circuit 71 is added in the adder circuit 72, thereby performing a multiply-and-accumulate operation. The register 73 is controlled by a clock signal CLK and a reset signal reset_B. With this configuration, it is possible to obtain output data MAC equivalent to a multiply-and-accumulate operation on the weight data W and input data A.

[0116] 15 illustrates an example of the configuration of the memory circuit unit 30, which is stacked on the arithmetic circuit unit 40, and its peripheral circuits, as described in FIG. 1A. Specifically, FIG. 15 illustrates the drive circuit 12, the drive circuit 13, the control circuit 14, the processing circuit 15, the memory circuit 31, the switching circuit 42, the switching circuit 44, and the arithmetic circuit 45.

[0117] Although not shown in FIG. 15, each circuit in FIG. 15 is configured to receive and output control signals for controlling each circuit, input data, and output data from and to external circuits.

[0118] Fig. 16A is a diagram illustrating blocks that control the memory circuit unit 30 in each configuration illustrated in Fig. 15. In Fig. 16A, the memory circuit 31 in the memory circuit unit 30, as well as the drive circuit 12 and the drive circuit 13, are illustrated.

[0119] The driving circuits 12 and 13 process external input signals to generate signals for writing weight data to the memory circuit 31 and signals for reading weight data from the memory circuit 31. The generated signals are provided to the memory circuit via wiring.

[0120] Fig. 16B is a diagram extracting the blocks that control the arithmetic circuit unit 40 from the configurations shown in Fig. 15. Fig. 16B illustrates the control circuit 14, processing circuit 15, and wiring WOL and WEL in addition to the switching circuit 42, switching circuit 44, and arithmetic circuit 45 that the arithmetic circuit unit 40 has. Note that Fig. 16B omits the latch circuit 41, buffer circuit 43, etc.

[0121] The control circuit 14 generates input data A and outputs it to the arithmetic circuit 45. The switching circuit 42 selects the weight data read from the memory circuit 31 and provides it to the wiring WOL or WEL via a buffer circuit (not shown). The switching circuit 44 selects the wiring WOL or WEL and provides the weight data W (the above-mentioned W O , W E The calculation circuit 45 performs a product-sum operation on the weight data W and the input data A, and outputs the output data MAC to the processing circuit 15. The processing circuit 15 performs post-processing on the output data MAC and outputs it to the control circuit 14. The control circuit 14 re-inputs the input data A to the calculation circuit unit 40.

[0122] In the semiconductor device 10, the control circuit 14 can output processed data as input data to the arithmetic circuit unit 40 again. This allows for arithmetic processing without reading data during arithmetic processing into a main memory or other external memory. Furthermore, in the semiconductor device 10, electrical connections between the memory circuit unit and the arithmetic circuit unit can be made via wiring in openings in an insulating film or the like, allowing for an increased number of parallel connections. Therefore, the semiconductor device 10 enables parallel calculations with a bit count greater than the CPU data bus width. Furthermore, because the arithmetic circuit unit is stacked with the memory circuit unit, the area available for arranging the memory circuit can be increased. As a result, a huge number of weight data can be stored in the memory circuit unit, reducing the number of times weight data needs to be transferred from external memory, thereby achieving low power consumption.

[0123] As described above, one embodiment of the present invention can provide a miniaturized semiconductor device that functions as an accelerator. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator and has low power consumption. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator with a novel structure.

[0124] (Embodiment 2) In this embodiment, an example of operation will be described in which part of the calculations of a program executed by the CPU 110 described in the above embodiment is executed by an accelerator described as the semiconductor device 10.

[0125] FIG. 17 is a diagram illustrating an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0126] The host program is executed by the CPU (host program execution; step S1).

[0127] When the CPU confirms an instruction to reserve a data area required for calculations using the accelerator in the memory circuit unit (memory reservation instruction; step S2), it reserves the data area in the memory circuit unit (memory reservation; step S3).

[0128] Next, the CPU transmits weight data, which is input data, from the main memory or an external storage device to the memory circuit unit (data transmission; step S4). The memory circuit unit receives the weight data and stores it in the area reserved in step S2 (data reception; step S5).

[0129] When the CPU confirms an instruction to start the kernel program (start kernel program; step S6), the accelerator starts executing the kernel program (start operation; step S7).

[0130] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (PG state transition; step S8). In this case, immediately before the accelerator finishes executing the kernel program, the CPU is switched from the PG state to a state performing calculations (PG state stop; step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the entire calculation processing system.

[0131] When the accelerator finishes executing the kernel program, the output data is stored in a storage unit that holds the calculation results in the accelerator (computation end; step S10).

[0132] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit the output data stored in the memory unit to the main memory or an external storage device (data transmission request; step S11), the output data is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission; step S12).

[0133] By repeating the above operations from step S1 to step S14, the power consumption and heat generation of the CPU and the accelerator can be suppressed, and part of the computations to be performed by the CPU can be performed by the accelerator. The semiconductor device of one embodiment of the present invention has a non-von Neumann architecture, and can perform computations with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0134] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0135] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0136] 18 shows an example configuration of the CPU 110. The CPU 110 has a CPU core 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0137] The CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203 are interconnected by a bus interface unit 205.

[0138] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from the outside and signals such as the SLEEP1 signal issued by the CPU 110. The clock signal GCLK1 and the PG control signals are input to the CPU 110. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0139] Power switches 210 and 211 control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line), respectively. A power switch 212 controls the supply of a voltage VDDH to a level shifter (LS) 214. A voltage VSSS is input to the CPU 110 and PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0140] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0141] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. Each power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0142] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0143] 19 shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222.

[0144] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0145] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0146] The signal SCE is a scan enable signal and is generated by the PMU 193. The PMU 193 generates signals BK and RC. The level shifter 214 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0147] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 19. Flip-flops available in a standard circuit library can be applied.

[0148] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0149] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0150] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0151] The transistors M11 to M13 are OS transistors, similar to the transistors 61 to 63 included in the memory circuit 31. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0152] At least the transistors M11 and M12 are preferably OS transistors. The OS transistors have an extremely small off-state current, which prevents a voltage drop at the node SN11. Furthermore, the backup circuit 222 consumes almost no power to retain data, making it nonvolatile. Because data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and with low energy consumption.

[0153] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Fig. 19B, the backup circuit 222 can be stacked on a scan flip-flop 221 made up of a silicon CMOS circuit.

[0154] Since the backup circuit 222 has an extremely small number of elements compared to the scan flip-flop 221, stacking the backup circuit 222 does not require changing the circuit configuration and layout of the scan flip-flop 221. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be provided in the region where the scan flip-flop 221 is formed, even if the backup circuit 222 is incorporated, the area overhead of the flip-flop 220 can be reduced to zero. Therefore, providing the backup circuit 222 in the flip-flop 220 enables power gating of the CPU core 200. Because little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0155] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0156] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operating state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0157] For example, when transitioning from a normal operating state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0158] When the CPU core 200 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data of the scan flip-flop 221 to the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 222 to the scan flip-flop 221.

[0159] 20 shows an example of a power gating sequence of the CPU core 200. In FIG. 20, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0160] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, the level shifter 214 does not need to operate, so the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 20, at time t1, the node SN11 of the backup circuit 222 is "L".

[0161] At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 214 becomes active and outputs the signal BKH at "H" to the backup circuit 222.

[0162] The transistor M11 of the backup circuit 222 turns on, and the data at the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0163] The PMU 193 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to the power gating state. Note that the signal PSE0 may also fall at the same timing as the signal BK falls.

[0164] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at node Q1 is lost. Node SN11 continues to hold the data at node Q1 at time t3.

[0165] The operation during recovery will be explained below. At time t4, the PMU 193 sets the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage on the V_VDD line reaches VDDD (time t5), the PMU 193 sets the signals PSE2, RC, and SCE to "H".

[0166] Transistor M12 turns on, and the charge of capacitive element C11 is distributed between node SN11 and node SD. If node SN11 is "H," the voltage of node SD rises. Since node SE is "H," the data of node SD is written to the input latch circuit of scan flip-flop 221. When clock signal GCLK1 is input to node CK at time t6, the data of the input latch circuit is written to node Q1. In other words, the data of node SN11 has been written to node Q1.

[0167] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0168] The backup circuit 222 using OS transistors consumes low dynamic and static power, making it highly suitable for normally-off computing. A CPU 110 including a CPU core 200 with a backup circuit 222 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has nonvolatile memory and can stop power supply when operation is not required. Even if the flip-flop 220 is installed, it is possible to minimize the degradation of CPU core 200 performance and the increase in dynamic power.

[0169] The CPU core 200 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212.

[0170] The application of the flip-flop 220 is not limited to the CPU 110. In the CPU 110, the flip-flop 220 can be applied to a register provided in a power domain that is capable of power gating.

[0171] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0172] (Fourth embodiment) In this embodiment, an example of a configuration of a transistor applicable to the CPU 110 described in the above embodiment and the accelerator described as the semiconductor device 10 will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. This configuration can increase the degree of freedom in designing a semiconductor device. Furthermore, stacking transistors having different electrical characteristics can increase the degree of integration of a semiconductor device.

[0173] FIG. 21 shows a part of a cross-sectional structure of a semiconductor device. The semiconductor device shown in FIG. 21 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 22A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22B is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to an OS transistor included in the memory circuit 31 described in the above embodiment, that is, a transistor having an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the arithmetic circuit portion 40 described in the above embodiment, that is, a transistor having silicon in a channel formation region. The capacitor 600 corresponds to a capacitor included in the memory circuit 31.

[0174] The transistor 500 is an OS transistor. An OS transistor has an extremely low off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of refresh operations of the storage node can be reduced or no refresh operations are required, thereby reducing the power consumption of the semiconductor device.

[0175] In FIG. 21, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0176] The transistor 550 is provided on a substrate 311. The substrate 311 is, for example, a p-type silicon substrate. The substrate 311 may also be an n-type silicon substrate. The oxide layer 314 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxidation (buried oxide) in the substrate 311, such as silicon oxide. The transistor 550 is provided on a single-crystal silicon substrate provided on the substrate 311 with the oxide layer 314 interposed therebetween, a so-called SOI (Silicon On Insulator) substrate.

[0177] A substrate 311 in the SOI substrate is provided with an insulator 313 that functions as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a region that is given n-type or p-type conductivity depending on the conductivity type of the transistor 550. The single crystal silicon in the SOI substrate is provided with a semiconductor region 315, and low-resistance regions 316a and 316b that function as source and drain regions. A low-resistance region 316c is also provided on the well region 312.

[0178] The transistor 550 can be provided overlapping a well region 312 to which an impurity element imparting conductivity is added. The well region 312 can function as a bottom gate electrode of the transistor 550 by independently changing the potential via the low-resistance region 316c. This allows the threshold voltage of the transistor 550 to be controlled. In particular, when the transistor 550 is an n-channel transistor, applying a negative potential to the well region 312 can increase the threshold voltage of the transistor 550 and reduce its off-state current. Therefore, applying a negative potential to the well region 312 can reduce the drain current when the potential applied to the gate electrode of the Si transistor is 0 V. As a result, power consumption due to a through current or the like in the arithmetic circuit unit 40 including the transistor 550 can be reduced, thereby improving arithmetic efficiency.

[0179] The transistor 550 is preferably a so-called fin type transistor in which the top surface of the semiconductor layer and the side surfaces in the channel width direction are covered with a conductor 318 via an insulator 317. By using the fin type transistor 550, the effective channel width can be increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0180] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0181] The conductor 318 may function as a first gate (also called a top gate) electrode, and the well region 312 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 312 can be controlled via the low-resistance region 316c.

[0182] The region where the channel of the semiconductor region 315 is formed, the region nearby, the low-resistance region 316a and low-resistance region 316b that serve as the source or drain region, and the low-resistance region 316c connected to an electrode that controls the potential of the well region 312 preferably contain a semiconductor such as a silicon-based semiconductor, and preferably single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0183] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 316c contain, in addition to the semiconductor material applied to semiconductor region 315, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0184] The conductor 318 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, including an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron. The conductor 318 may also be made of a silicide, such as nickel silicide.

[0185] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0186] The low-resistance regions 316a, 316b, and 316c may be formed by stacking another conductor, for example, a silicide such as nickel silicide. This configuration can increase the conductivity of the regions that function as electrodes. In this case, an insulator that functions as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on the side surface of the conductor 318 that functions as the gate electrode and on the side surface of the insulator that functions as the gate insulating film. This configuration can prevent electrical conduction between the conductor 318 and the low-resistance regions 316a and 316b.

[0187] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0188] The insulators 320, 322, 324, and 326 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0189] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0190] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0191] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0192] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0193] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0194] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0195] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0196] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0197] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 21 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0198] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0199] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0200] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 21, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as the conductors 328 and 330.

[0201] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0202] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 21 , an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or wiring. The conductor 376 can be provided using the same material as the conductors 328 and 330.

[0203] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0204] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 21, an insulator 380, an insulator 382, and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0205] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0206] Although the above describes a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386, the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0207] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0208] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0209] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550.

[0210] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0211] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0212] For example, the insulator 512 and the insulator 516 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulators 512 and 516 can be made of a silicon oxide film or a silicon oxynitride film.

[0213] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0214] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0215] Above the insulator 516 is the transistor 500 .

[0216] As shown in Figures 22A and 22B, transistor 500 has conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, insulator 522 arranged on insulator 516 and conductor 503, insulator 524 arranged on insulator 522, oxide 530a arranged on insulator 524, oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, insulator 580 arranged on conductors 542a and 542b and having an opening formed therebetween overlapping conductors 542a and 542b, insulator 545 arranged on the bottom and side surfaces of the opening, and conductor 560 arranged on the surface on which insulator 545 is formed.

[0217] 22A and 22B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 have conductor 560a disposed inside insulator 545 and conductor 560b disposed so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 545, as shown in FIGS.

[0218] In this specification and other documents, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0219] Note that although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in and around the channel formation region, the present invention is not limited to this. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0220] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 21, 22A, and 22B is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0221] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0222] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0223] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0224] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0225] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like differs from the fin type configuration and the planar type configuration. By adopting the S-channel configuration, the transistor can be made more resistant to the short channel effect, in other words, less susceptible to the short channel effect.

[0226] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0227] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0228] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0229] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single-layer structure.

[0230] The insulator 522 and the insulator 524 function as a second gate insulating film.

[0231] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V OH.) functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0232] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0233] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO, which may be removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542.

[0234] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0235] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0236] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0237] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0238] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the conductor 503. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0239] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0240] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0241] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0242] 22A and 22B illustrate the insulators 522 and 524 as the second gate insulating film having a two-layer stack structure, the second gate insulating film may have a single layer, a three-layer, or a four- or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0243] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, the oxide 530 may be a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like).

[0244] The metal oxide that functions as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method.

[0245] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0246] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0247] Note that oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0248] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0249] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0250] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0251] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0252] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0253] 22A shows the conductor 542a and the conductor 542b as a single layer, but they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0254] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0255] 22A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0256] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0257] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0258] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0259] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of an oxidation-resistant material or a material whose conductivity does not decrease even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0260] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 544 can also prevent the conductor 542 from being oxidized by excess oxygen contained in the insulator 580.

[0261] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0262] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0263] By providing the insulator 545 as an insulator containing excess oxygen, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0264] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0265] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a layered structure that is thermally stable and has a high dielectric constant can be achieved.

[0266] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 22A and 22B, it may have a single-layer structure or a laminated structure of three or more layers.

[0267] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The oxygen-suppressing function of the conductor 560a can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 545, which can reduce the conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, an oxide semiconductor that can be used for the oxide 530 can be used for the conductor 560a. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0268] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0269] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0270] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0271] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0272] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0273] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0274] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0275] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0276] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0277] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0278] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0279] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0280] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0281] Furthermore, conductors 546, 548, etc. are embedded in insulators 522, 524, 544, 580, 574, 581, 582, and 586.

[0282] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0283] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0284] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0285] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0286] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0287] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0288] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0289] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0290] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0291] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0292] (Embodiment 5) In this embodiment, the configuration of an integrated circuit including each component of the arithmetic processing system 100 described in the above embodiment will be described with reference to FIGS. 23A and 23B.

[0293] 23A is an example of a schematic diagram for explaining an integrated circuit including each component of the arithmetic processing system 100. The integrated circuit 390 shown in FIG. 23A can be formed as a single integrated circuit by integrating each circuit of the CPU 110 and the accelerator described as the semiconductor device 10, by configuring some of the circuits of the accelerator using OS transistors.

[0294] As shown in FIG. 23A, the CPU 110 may be configured to include a backup circuit 222 in a layer having OS transistors above the CPU core 200. Also, as shown in FIG. 23A, in the accelerator described as the semiconductor device 10, a memory circuit unit 30 may be provided in a layer having OS transistors above a layer having Si transistors that constitute the arithmetic circuit unit 40. Alternatively, an OS memory 300N or the like may be provided in the layer having OS transistors. As the OS memory 300N, in addition to the NOSRAM described in the above embodiment, a DOSRAM may be used. Furthermore, in the OS memory 300N, stacking a layer having OS transistors on a driver circuit provided in a layer having Si transistors can improve memory density.

[0295] As shown in FIG. 23A, in the case of an SoC in which circuits such as the CPU 110, the accelerator described as the semiconductor device 10, and the OS memory 300N are tightly coupled, there is a problem of heat generation. However, OS transistors are preferable because the amount of change in electrical characteristics due to heat is smaller than that of Si transistors. Furthermore, by integrating circuits in a three-dimensional direction as shown in FIG. 23A, parasitic capacitance can be reduced compared to stacked structures using silicon through electrodes (Through Silicon Via: TSV). The power consumption required for charging and discharging each wiring can be reduced. As a result, the efficiency of computational processing can be improved.

[0296] FIG. 23B shows an example of a semiconductor chip incorporating an integrated circuit 390. The semiconductor chip 391 shown in FIG. 23B has leads 392 and an integrated circuit 390. As described with reference to FIG. 23A, the integrated circuit 390 has the various circuits described in the above embodiments provided on a single die. The integrated circuit 390 has a layered structure and is broadly divided into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). The OS transistor layer 395 can be provided by being layered on the Si transistor layer 393, which facilitates miniaturization of the semiconductor chip 391.

[0297] 23B, a QFP (Quad Flat Package) is used for the package of semiconductor chip 391, but the package form is not limited to this. Other examples of configurations that can be used as appropriate include an insertion mounting type DIP (Dual In-line Package) and PGA (Pin Grid Array), a surface mounting type SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), and a contact mounting type DTP (Dual Tape carrier Package) and QTP (Quad Tape-carrier Package).

[0298] The arithmetic circuit and switching circuit having Si transistors and the memory circuit having OS transistors can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the semiconductor device can be formed using the same manufacturing process. Therefore, even if the number of constituent elements increases, the IC shown in FIG. 23B does not require an increase in the manufacturing process, and the semiconductor device can be incorporated at low cost.

[0299] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0300] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0301] (Embodiment 6) In this embodiment mode, electronic devices, mobile objects, and arithmetic systems to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS.

[0302] Fig. 24A shows an external view of an automobile as an example of a moving body. Fig. 24B is a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also has various sensors (not shown) such as infrared radar, millimeter-wave radar, and laser radar.

[0303] In an automobile 590, the above-mentioned integrated circuit 390 (or a semiconductor chip 391 incorporating the above-mentioned integrated circuit 390) can be used in a camera 591 or the like. The automobile 590 processes a plurality of images acquired by the camera 591 in a plurality of imaging directions 592 using the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images collectively using a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. The automobile 590 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0304] In the integrated circuit 390, the obtained image data is subjected to arithmetic processing such as neural networks, making it possible to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0305] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0306] Fig. 25A is an external view showing an example of a portable electronic device. Fig. 25B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has printed wiring board 596, speaker 597, camera 598, microphone 599, etc.

[0307] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc. using integrated circuit 390 described in the above embodiment. In addition, the portable electronic device 595 can be used in systems that perform voice guidance, image search, etc.

[0308] In the integrated circuit 390, the obtained image data is subjected to arithmetic processing such as neural networks, making it possible to perform processes such as increasing the image resolution, reducing image noise, facial recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0309] 26A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, a video image displayed on the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated into a chip provided on a substrate of the housing 1102 or the housing 1103.

[0310] 26B shows a stick-type electronic device 1120 that is USB-connected. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 of the board 1124.

[0311] 26C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the integrated circuit 390 shown in the previous embodiment.

[0312] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 27 shows an example of the configuration of a system 3000.

[0313] The system 3000 is configured by an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an internet line 3003.

[0314] Server 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided in the racks, and integrated circuits 390 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. The results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This reduces the calculation load on electronic device 3001.

[0315] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0316] (Notes regarding the present specification) The above-described embodiment and each configuration in the embodiment will be described below with additional notes.

[0317] The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0318] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0319] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0320] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0321] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0322] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0323] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0324] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of a transistor can be appropriately changed to source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0325] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0326] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0327] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0328] In this specification, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" means a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0329] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0330] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0331] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0332] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." [Explanation of symbols]

[0333] WEL: wiring, WOL: wiring, 10: semiconductor device, 12: drive circuit, 13: drive circuit, 14: control circuit, 15: processing circuit, 20_E: operation block section, 20_O: operation block section, 21_E: operation block, 21_O: operation block, 21: operation block, 30: memory circuit section, 31: memory circuit, 40: operation circuit section, 41: latch circuit, 42: switching circuit, 43_E: buffer circuit, 43_O: buffer circuit, 44: switching circuit, 45: operation circuit

Claims

[Claim 1] a first processing block having a first memory circuit unit and a first processing circuit unit; a second calculation block having a second memory circuit unit and a second calculation circuit unit; A first wiring and a second wiring are included, the first storage circuit unit has a first storage circuit that holds a plurality of first weight data; the second storage circuit unit has a second storage circuit that holds a plurality of second weight data; the first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit; the second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit; the first switching circuit has a function of providing any one of the plurality of first weight data to the first wiring, the second switching circuit has a function of providing any one of the plurality of second weight data to the second wiring, the third switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit; the fourth switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.

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