Electronic Components

Abstract

The electronic component has a functional section and a cover. The functional section has a first surface facing a first side in a first direction. The cover overlaps the first surface. The cover also has two or more insulator layers, one or more dummy electrodes, and a base electrode. The two or more insulator layers and the one or more dummy electrodes are alternately overlapped in the first direction. The base electrode overlaps the outermost insulator layer from the first side. A range of the cover that overlaps with the base electrode or the dummy electrode in a planar perspective view from the first direction is referred to as a first range. The number of voids per unit area in a cross section along the first direction is referred to as a void density. In the first range, the void density of the innermost insulator layer is smaller than the void density of the outermost insulator layer. And / or, when the total area of voids per unit area in the cross section is referred to as a void ratio, the void ratio of the innermost insulator layer is smaller than the void ratio of the outermost insulator layer in the first range.

Description

[Technical Field]

[0001] The present disclosure relates to electronic components such as multilayer ceramic capacitors. [Background technology]

[0002] Multilayer ceramic capacitors in which ceramic layers and internal electrodes are alternately stacked are known (for example, see Patent Document 1 below). In Patent Document 1, a laminate in which ceramic layers and auxiliary electrodes are alternately stacked is placed on each of the upper and lower surfaces of a laminate made of ceramic layers and internal electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-212298 Summary of the Invention

[0004] An electronic component according to one embodiment of the present disclosure has a functional section and a cover section. The functional section has a first surface facing a first side in a first direction. The cover section overlaps the first surface. The cover section also has two or more insulator layers, one or more dummy electrodes, and a base electrode. The two or more insulator layers and the one or more dummy electrodes overlap alternately in the first direction. The base electrode overlaps the outermost insulator layer from the first side. A range of the cover section that overlaps with the base electrode or the dummy electrode in a planar perspective view from the first direction is referred to as a first range.

[0005] In one example, when the number of voids per unit area of an insulating layer in a cross section along the first direction is referred to as the void density, in the first range, the void density of the innermost insulating layer is smaller than the void density of the outermost insulating layer.

[0006] In one example, when the total area of voids per unit area of the insulating layer in a cross section along the first direction is referred to as the void occupied area ratio, in the first range, the void occupied area ratio of the innermost insulating layer is smaller than the void occupied area ratio of the outermost insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view showing a capacitor according to a first embodiment. [Figure 2] FIG. 2 is a schematic exploded perspective view of the capacitor of FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] An enlarged view of region IV in Figure 3 . [Figure 5] FIG. 10 is a perspective view showing a capacitor according to a second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a capacitor according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the drawings used in the following description are schematic. Therefore, for example, the dimensional ratios in the drawings do not necessarily correspond to the actual ones. Furthermore, the dimensional ratios may not match between drawings. Certain shapes and / or dimensions may be exaggerated, and details may be omitted. However, the above does not deny that the actual shapes and / or dimensions may be as shown in the drawings, or that features of shapes and / or dimensions may be extracted from the drawings.

[0009] Regarding the embodiments described relatively later, basically, only the differences from the embodiments described relatively earlier will be described. Matters not specifically mentioned may be considered to be the same as the embodiments described earlier or may be inferred from the embodiments described earlier. For convenience, the same reference numerals may be used for corresponding components between different embodiments, even if there are differences.

[0010] In the description of the embodiments, the term shape may or may not include dimensions. Either interpretation may be used unless a contradiction arises. When referring to a rectangle (or rectangular shape) or a rectangular parallelepiped (or rectangular shape), the corners may be chamfered. Furthermore, relatively small concave or convex portions (which are intentional and not due to error) may be formed. The same applies to other shapes. When referring to a specific layer having a constant thickness, variations in thickness due to manufacturing errors may be tolerated (as long as a constant thickness is intended).

[0011] Whether various dimensions fall within the ranges exemplified in the description of the embodiments (absolute values such as μm or relative values to other dimensions) may be determined reasonably. For example, the dimensions of unique portions may be ignored. More specifically, for example, when determining whether a thickness falls within a predetermined range, chamfered portions may be ignored. Furthermore, for example, in a layer intended to have a constant thickness, if the thickness of the end portion is significantly different (e.g., significantly thinner) than the thickness of the majority of the other portions (e.g., 60% or more or 80% or more of the area), the thickness of the end portion may be ignored. Furthermore, if there is thickness variation across the majority of a given layer intended to have a constant thickness, for example, an average value may be referenced. Of course, if both the minimum and maximum thickness values fall within a numerical range, there is no need to specifically reference an average value.

[0012] With respect to a material (such as a conductive material or an insulating material), a major component may be, for example, a component that accounts for 60% by weight or more, or 80% by weight or more.

[0013] (Outline of the embodiment) FIG. 1 is a perspective view showing a capacitor 1 (an example of an electronic component) according to a first embodiment. For convenience, a Cartesian coordinate system D1D2D3 is used in FIG. 1 and other figures described below. The capacitor 1 may be used with either side designated as the upper or lower side. However, in describing the embodiments, for convenience, the +D3 side may be designated as the upper side, and terms such as upper surface and lower surface may be used.

[0014] The capacitor 1 is, for example, a multilayer ceramic capacitor. The capacitor 1 has a roughly rectangular parallelepiped body 3 and four external electrodes 5 located at the four corners of the body 3 in a plan view (as viewed in the D3 direction). The external electrodes 5 contribute to electrical connection between the capacitor 1 and other electronic components (for example, a circuit board (not shown)).

[0015] Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 3 shows a D1D3 cross section taken through the external electrode 5 on the +D2 side. However, the D1D3 cross section taken through the external electrode 5 on the -D2 side, the D2D3 cross section taken through the external electrode 5 on the -D1 side, and the D2D3 cross section taken through the external electrode 5 on the +D1 side are basically the same. In explaining the embodiments, for convenience, the positional relationship between components may be explained using the terms D1, D2, and D3 without any particular mention, assuming the cross section illustrated in Fig. 3.

[0016] The main body 3 has, for example, a functional part 7 and two covers 9 (an example of a cover part) that overlap the top and bottom surfaces of the functional part 7. The functional part 7 is a part (at least a part thereof) that directly functions as an electronic component (here, a capacitor). The cover 9 contributes to, for example, protecting the functional part 7 and / or improving the strength of the capacitor 1.

[0017] Focus on region R4 in Fig. 3. The cover 9 has two or more (three in the illustrated example) insulator layers 11 (11A to 11C) alternately stacked in the direction D3 and one or more (from another perspective, the number of insulator layers 11 minus one) dummy electrodes 13 (13A and 13B). The cover 9 also has a base electrode 15 overlapping the top surface of the outermost insulator layer 11C.

[0018] The outermost layer here refers to the layer among the multiple insulator layers 11 of each cover 9 that is farthest from the functional unit 7 in the stacking direction. The innermost layer, which will be described later, refers to the layer among the multiple insulator layers 11 of each cover 9 that is closest to the functional unit 7 in the stacking direction.

[0019] Note that while the focus here is on region R4 on the +D1 and +D3 sides, the same applies to other regions equivalent to region R4. For convenience, in the description of the embodiments, region R4 is taken as an example, and the terms upper surface and lower surface are used, and the positive and negative sides of each axis (D1, D2, and D3) may be referred to without special mention.

[0020] The insulator layer 11 contributes to, for example, insulating the functional section 7. The dummy electrode 13 and the base electrode 15 contribute to, for example, depositing the metal that will become the external electrode 5 by plating and / or improving the adhesive strength of the external electrode 5 to the main body section 3. For convenience, FIG. 3 shows the boundary between the insulator layers 11 in the area where they directly overlap each other (areas where no dummy electrode 13 is arranged). In reality, such a boundary does not need to be observable (the same applies to the dielectric layer 17 described below).

[0021] Figure 4 is an enlarged view of region R4. However, for convenience, hatching of the insulator layer 11 has been omitted. Also, the details of the configuration differ between Figure 3 and Figure 4. This difference may be interpreted as being due to the fact that Figure 3 is depicted more schematically than Figure 4, or that Figure 4 illustrates an embodiment that is strictly different from that of Figure 3. Also, Figure 4 does not show the boundary lines in the portions where the insulator layers 11 (and dielectric layers 17) directly overlap each other, which are shown for convenience in Figure 3.

[0022] The insulator layer 11 contains a plurality of voids 21. The number of voids 21 per unit area in a cross section (cross section along the D3 direction) as shown in the figure is referred to as the "void density." The total area of the voids 21 per unit area in the cross section is referred to as the "void occupied area ratio." The range in which the base electrode 15 or the dummy electrode overlaps in the extent of the cover 9 is referred to as the first range A1. In this case, in the first range A1, the void density and / or void occupied area ratio of the innermost insulator layer 11A is smaller than the void density and / or void occupied area ratio of the outermost insulator layer 11C.

[0023] Therefore, for example, the probability of cracks occurring due to voids 21 is reduced in the insulator layer 11A, which is relatively close to the functional section 7. The reduction in cracks near the functional section 7 stabilizes the characteristics of the functional section 7. On the other hand, the outermost insulator layer 11C has a relatively large number of recesses on the top surface formed by the same principle as that for forming voids 21, and therefore the anchor effect improves the adhesion strength of the base electrode 15 and reduces peeling. This makes it easier to balance the reliability of characteristics and the reliability of structural strength.

[0024] Note that the above-described effects do not necessarily have to be achieved. Furthermore, technical ideas different from the above-described viewpoints may be extracted from the present disclosure. In this case, for example, the magnitude relationship of the void density and / or the void-occupied area ratio does not have to be established, and two or more insulator layers 11 and one or more dummy electrodes 13 do not have to be provided in the first area A1.

[0025] The above is an outline of the embodiment. Specifically, the embodiment will be roughly described in the following order. 1. First embodiment (FIGS. 1 to 4) 1.1. Overall structure 1.2. Functional Section 1.3. Cover (excluding void) 1.3.1. Whole cover 1.3.2.Insulator Layer 1.3.3. Dummy electrodes and base electrodes 1.4.External electrode 2. Void 2.1.Voids in general 2.2. Void density and void area ratio 2.3.Other 3. Capacitor manufacturing method 4. Other Embodiments 4.1. Second embodiment (Fig. 5) 4.2. Third embodiment (Fig. 6) 4.3. Unillustrated embodiments 5. Summary of embodiments

[0026] (1. First embodiment) (1.1. Overall structure) 1 is configured as, for example, a surface-mounted chip component. Specifically, for example, the capacitor 1 is placed with its -D3 or +D3 side facing a circuit board (not shown). Then, the four pads on the circuit board are joined to the four external electrodes 5 with a conductive joining material (e.g., solder) (not shown), thereby mounting the capacitor on the circuit board.

[0027] The configuration (internal structure and external shape) of capacitor 1 is, for example, approximately plane-symmetric with respect to a plane of symmetry (not shown) that is parallel to the D1D2 plane and passes through the center of the thickness direction (D3 direction) of capacitor 1. Furthermore, the configuration of capacitor 1 is, for example, 180° rotationally symmetric when viewed in the D3 direction. Of course, capacitor 1 does not have to have such symmetry.

[0028] The shape of the main body 3 is, for example, roughly a thin rectangular parallelepiped. This rectangular parallelepiped may be square (as shown in the example) or rectangular (excluding squares; the same applies below) in plan view. For convenience, in the description of the embodiments, a square shape may be assumed unless otherwise specified.

[0029] Although not specifically shown, the main body 3 may have chamfered corners. This chamfering may be relatively large. For example, a curved or flat chamfered surface may extend over the entire side surface of the cover 9 and also over a portion of the functional part 7 on the cover 9 side. Such a chamfered surface may be obtained, for example, by barrel polishing the main body 3.

[0030] The specific dimensions of the main body 3 (or capacitor 1) are arbitrary. Examples of dimensions for a relatively small capacitor 1 are given below. The lengths of the main body 3 (or capacitor 1) in the D1 and D2 directions may each be 0.3 mm or more and 2.0 mm or less. The thickness in the D3 direction may be 0.030 mm or more and 1.0 mm or less. The example dimensions of each component described below are also for a relatively small capacitor 1. Therefore, dimensions larger (or smaller) than the illustrated dimensions may be adopted.

[0031] Unless otherwise specified or unless a contradiction occurs, multiple components of the same type (e.g., 5, 9, 11, 13, 15, 17, and 19) may basically (except for relatively small differences, for example; the same applies below) be provided with the same (or corresponding) shape, size, material, position, etc. Therefore, unless otherwise specified or unless a contradiction occurs, the description of one component may be considered to be common to multiple components of the same type.

[0032] A single layered (film-like) constituent element (e.g., 5, 11, 13, 15, 17, and 19) may be entirely made of a single material. However, a single layered constituent element may be made of stacked layers made of different materials. Furthermore, a single layered constituent element entirely made of a single material may be made of a single layer, or may be made of a stack of multiple layers made of the same material, when focusing on the manufacturing process.

[0033] (1.2. Functional part) The functional section 7 shown in FIG. 3 has a generally thin rectangular parallelepiped shape, for example. Its planar shape is basically the same as that of the main body section 3. The specific thickness of the functional section 7 is arbitrary. For example, the thickness of the functional section 7 may be 30% or more, 40% or more, or 50% or more of the thickness of the main body section 3, or 90% or less, 80% or less, 70% or less, or 60% or less. The above upper and lower limits may be combined arbitrarily. The thickness of the main body section 3 is, for example, the thickness from the upper surface of the upper base electrode 15 to the lower surface of the lower base electrode 15. The thickness of the functional section 7 is, for example, the thickness from the upper surface of the uppermost internal electrode 19 (described below) to the lower surface of the lowermost internal electrode 19.

[0034] The functional section 7 has a plurality of dielectric layers 17 and a plurality of internal electrodes 19 that are alternately stacked, thereby realizing the function of a capacitor.

[0035] The dielectric layer 17 is essentially a layer having a constant thickness (at least between the internal electrodes 19). The shape and dimensions of the dielectric layer 17 in a planar view are essentially the same as those of the functional section 7 in a planar view. The thickness of the dielectric layer 17 may be appropriately set depending on the characteristics required of the capacitor 1. Examples of relatively thin thicknesses include a thickness between adjacent internal electrodes 19 in the D3 direction of 0.1 μm or more or 0.5 μm or more, and a thickness of 3.0 μm or less, 2.0 μm or less, or 1.0 μm or less. The above lower and upper limits may be combined arbitrarily. The number of laminated dielectric layers 17 (internal electrodes 19) is arbitrary. For example, the number is 10 to 30 layers. The material of the dielectric layer is, for example, ceramics, and the specific type is also arbitrary.

[0036] The internal electrodes 19 are layered and have a constant thickness. The thickness of the internal electrodes 19 is arbitrary, and may be thinner, the same as, or thicker than the thickness of the dielectric layer 17 in the regions between the internal electrodes 19. Examples of relatively thin thicknesses include a thickness of 0.3 μm or more or 0.5 μm or more, and a thickness of 3.0 μm or less, 2.0 μm or less, or 1.0 μm or less. The above lower and upper limits may be combined arbitrarily. The material (e.g., main component) of the internal electrodes 19 is, for example, a metal. The specific type of metal is arbitrary, and for example, the entire metal or the main component is a base metal (e.g., Ni and / or Cu). The material of the internal electrodes 19 may also contain ceramics (common material).

[0037] Fig. 2 is an exploded perspective view of the capacitor 1. Fig. 2 is a schematic view for understanding the planar shapes and relative positions of the internal electrodes 19, etc. Therefore, Fig. 2 shows a smaller number of various layers than Fig. 3.

[0038] The internal electrode 19 has, for example, a rectangular (square in the illustrated example) electrode body 19a in a plan view and a pair of extraction electrodes 19b extending from a pair of opposing corners of the electrode body 19a. The electrode body 19a is located inside the outer edge of the dielectric layer 17 and is not exposed from the side surface of the functional section 7. The pair of extraction electrodes 19b reach the outer edge of the dielectric layer 17 and are connected to a pair of external electrodes 5 located at a pair of opposing corners of the main body 3. Adjacent internal electrodes 19 in the D3 direction are connected to different pairs of external electrodes 5. The dimensions of each portion are arbitrary.

[0039] (1.3. Cover (excluding void)) (1.3.1. Entire cover) The cover 9 shown in FIG. 3 is, for example, a layer having a shape and dimensions that allow it to overlap the functional section 7 without excess or deficiency. The thickness of the cover 9 is approximately constant in both the region where the base electrode 15 is disposed (first area A1) and the region where the base electrode 15 is not disposed. The thickness in the region where the base electrode 15 is disposed is greater than the thickness in the region where the base electrode 15 is not disposed, for example. This is because the conductive paste that becomes the dummy electrode 13 and the base electrode 15 is disposed on a ceramic green sheet of a constant thickness. However, the thickness of the cover 9 may be made approximately constant throughout its entirety by, for example, making the thickness of the ceramic green sheet non-uniform or by adopting another manufacturing method.

[0040] The thickness range of the cover 9 exemplified below may be applied to the thickness in the region where the base electrode 15 is disposed, the thickness in the region where the base electrode 15 is not disposed, or the entire cover 9 (average value). When focusing on region R4, the thickness in the region where the base electrode 15 is disposed can be defined as the thickness from the inner surface (bottom surface, top surface of the functional portion 7) of the innermost insulator layer 11A to the top surface of the base electrode 15. In the illustrated example, when the internal electrode 19 overlaps most of the area of the base electrode 15, the thickness of the region overlapping with the internal electrode 19 may be referred to as the thickness in the region where the base electrode 15 is disposed. Similarly, the thickness in the region where the internal electrode 19 is disposed may be referred to as the thickness of the functional portion 7.

[0041] The ratio of the thickness of the cover 9 to the thickness of the main body 3 may be roughly the reverse of the ratio (as described above) of the thickness of the functional part 7 to the thickness of the main body 3. For example, in a mode in which covers 9 are provided on both sides in the D3 direction, the thickness of one cover 9 may be, for example, 5% or more, 10% or more, 15% or more, or 20% or more of the thickness of the main body 3, or 35% or less, 30% or less, or 25% or less. The above lower and upper limits may be combined arbitrarily.

[0042] Furthermore, the thickness of one cover 9 may be 1 / 18 or more, 1 / 8 or more, 3 / 14 or more, 1 / 5 or more, or 1 / 3 or more of the thickness of the functional portion 7, and may be 7 / 6 or less, 3 / 4 or less, 1 / 3 or less, or 1 / 2 or less. The above lower and upper limits may be combined arbitrarily.

[0043] The thickness of one cover 9 may be, for example, 5 μm or more, 10 μm or more, or 15 μm or more, or 50 μm or less, 30 μm or less, 25 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. The above lower and upper limits may be arbitrarily combined as long as no contradiction occurs.

[0044] (1.3.2. Insulator Layer) The insulator layer 11 is a layer having a substantially constant thickness, excluding variations in thickness due to the presence or absence of overlap with the conductor layers (13, 15, and 19). The planar shape of the insulator layer 11 is, for example, basically the same as the planar shape of the dielectric layer 17.

[0045] The number of insulator layers 11 (or, from another perspective, the number of dummy electrodes 13 in one first area A1) is arbitrary. When extracting the technical idea that the void density and / or void-occupied area ratio between the outermost layer and the innermost layer satisfy a predetermined magnitude relationship as described in the overview of the embodiment, the number of insulator layers 11 is two or more (the number of dummy electrodes 13 is one or more). In FIGS. 3 and 4, three insulator layers 11 are illustrated as the number of insulator layers 11. Unlike the illustrated example, the number of insulator layers 11 may be two or four or more. When extracting a technical idea different from the above (for example, the magnitude relationship between the void density and / or void-occupied area ratio in the second area A2 to the fourth area A4 described later), the number of insulator layers 11 may be one.

[0046] The thickness of the insulator layer 11 (for example, the thickness in the first range A1; the same applies hereinafter in this paragraph and the next paragraph) is arbitrary. For example, the thickness of the insulator layer 11 may be thicker (in the illustrated example) than the thickness of the dielectric layer 17 (between the internal electrodes 19), or may be the same as or thinner than the thickness of the dielectric layer 17. Also, for example, the thicknesses of the multiple insulator layers 11 may be the same as or different from each other.

[0047] Furthermore, for example, the thickness of the insulator layer 11 may be two or more, three or more, or five or more times the thickness of the dielectric layer 17 (between the internal electrodes 19), and may be 20 or less, 10 or less, or 5 or less times the thickness. The above lower and upper limits may be combined arbitrarily. For example, the thickness of the insulator layer 11 may be 1.0 μm or more or 2.0 μm or more, and may be 10.0 μm or less or 5.0 μm or less. The above lower and upper limits may be combined arbitrarily.

[0048] The material of the insulator layer 11 is arbitrary. For example, the material of the insulator layer 11 may be the same as or different from the material of the dielectric layer 17. The materials of the multiple insulator layers 11 may be the same as or different from each other. The material of the insulator layer 11 may be ceramic or a material other than ceramic (e.g., resin). Examples of ceramics (whole or mainly composed of ceramics) include barium titanate (BaTiO3), titanium dioxide (TiO2), strontium titanate (SrTiO3), calcium titanate (CaTiO3), and calcium zirconate (CaZrO3).

[0049] (1.3.3. Dummy Electrode and Base Electrode) The dummy electrode 13 and the base electrode 15 may have the same configuration except for their different positions in the D3 direction. Therefore, in this section, for convenience, the dummy electrode 13 will be described and the description of the base electrode 15 may be omitted. Unless otherwise specified or unless a contradiction occurs, the term "dummy electrode 13" may be replaced with the term "base electrode 15."

[0050] The dummy electrodes 13 are, for example, layer-like and have a substantially constant thickness. Each dummy electrode 13 is exposed, for example, on a side surface (more specifically, two side surfaces) of the main body 3. The exposed portion of each dummy electrode 13 is fixed to one external electrode 5. Each base electrode 15 constitutes a partial area of the upper or lower surface of the main body 3. Each base electrode 15 is fixed to one external electrode 5.

[0051] In a plan view, the position, shape, and size of the dummy electrode 13 are arbitrary. In the examples of Figures 2 and 3, the position, shape, and size of the dummy electrode 13 are such that, in a planar perspective view, they overlap approximately exactly with the external electrode 5 (however, the external electrode 5 is slightly wider). In addition, the dummy electrodes 13 are located at the four corners of the rectangular (square in the illustrated example) insulator layer 11, and have a rectangular shape (square in the illustrated example) with four sides parallel to the four sides of the insulator layer 11.

[0052] The length of each dummy electrode 13 in the D1 direction (for example, the maximum length if not constant in the D2 direction; the same applies hereinafter to the dummy electrodes 13 and the insulator layer 11 in this paragraph) may be, for example, 1 / 10 or more or 2 / 10 or more of the length of the insulator layer 11 in the D1 direction, and may be 4 / 10 or less or 3 / 10 or less. The above lower limit and upper limit may be combined arbitrarily. Also, for example, the length of each dummy electrode 13 in the D1 direction may be 50 μm or more, 100 μm or more, or 150 μm or more, and may be 500 μm or less, 300 μm or less, or 200 μm or less. The above lower limit and upper limit may be combined arbitrarily. Although examples of the length in the D1 direction have been given, these lengths may be applied to the length in the D2 direction.

[0053] The area of each dummy electrode 13 may be 1 / 100 or more or 4 / 100 or more of the area of the insulator layer 11, and may be 16 / 10 or less or 9 / 10 or less. The above lower limit and upper limit may be arbitrarily combined. The total area of all dummy electrodes 13 may be 4 / 100 or more or 16 / 100 or more of the area of the insulator layer 11, and may be 64 / 100 or less or 36 / 100 or less. The above lower limit and upper limit may be arbitrarily combined.

[0054] The thickness of the dummy electrode 13 may be, for example, thicker than (in the illustrated example), or may be approximately the same as, or thinner than, the thickness of the internal electrode 19. Furthermore, for example, the thickness of one or more dummy electrodes 13 and the base electrode 15 may be the same as, or different from, each other. Note that FIG. 3 illustrates an example in which the thicknesses of the plurality of dummy electrodes 13 and the base electrode 15 are the same as each other. FIG. 4 illustrates an example in which the thickness of the base electrode 15 is thicker than the thickness of the dummy electrode 13. Furthermore, the thickness of the dummy electrode 13 may be thinner, the same as, or thicker than the thickness of the insulator layer 11 (for example, the thickness in the first range A1).

[0055] Furthermore, for example, the thickness of the dummy electrode 13 (excluding the base electrode 15) may be 1 time or more, 1.5 times or more, or 2 times or more the thickness of the internal electrode 19, or may be 10 times or less, 5 times or less, or 2 times or less. The above lower and upper limits may be arbitrarily combined so as not to cause a contradiction. For example, the thickness of the dummy electrode 13 (excluding the base electrode 15) may be 0.3 μm or more, 0.5 μm or more, 1.0 μm or more, or 2.0 μm or more, or may be 10.0 μm or less, 5.0 μm or less, 3.0 μm or less, or 2.0 μm or less. The above lower and upper limits may be arbitrarily combined so as not to cause a contradiction.

[0056] Furthermore, for example, the thickness of the base electrode 15 may be, for example, 1 time or more, 2 times or more, 3 times or more, or 5 times or more the thickness of the internal electrode 19 and / or the dummy electrode 13, or may be, for example, 20 times or less, 10 times or less, or 5 times or less. The above lower and upper limits may be arbitrarily combined so as not to cause a contradiction. For example, the thickness of the base electrode 15 may be 1.0 μm or more, 2.0 μm or more, 3.0 μm or more, or 5.0 μm or more, or may be, for example, 20.0 μm or less, 10.0 μm or less, or 5.0 μm or less. The above lower and upper limits may be arbitrarily combined so as not to cause a contradiction.

[0057] The material of the dummy electrode 13 is arbitrary. For example, the material of the dummy electrode 13 may be the same as or different from the material of the internal electrode 19. In either case, the description of the material of the internal electrode 19 may be applied to the material of the dummy electrode 13.

[0058] As described above, the dummy electrodes 13 and the base electrodes 15 are located at different positions in the direction D3. Specifically, in region R4, the base electrodes 15 are located on the opposite side of the functional sections 7 with respect to all the dummy electrodes 13. From another perspective, unlike the dummy electrodes 13, the base electrodes 15 form part of the upper surface of the cover 9. Furthermore, the upper surface of the base electrodes 15 is basically not covered with an insulator (insulator layer 11 or other insulators). Consequently, most of the upper surface of the base electrodes 15 (for example, 60% or more, 80% or more, or 100%) is a connection region with other conductors (external electrodes 5).

[0059] (1.4.External electrode) The external electrode 5 is, for example, a layer having a substantially constant thickness. As shown in FIG. 1 , the external electrode 5 covers, for example, roughly the four surfaces (top, bottom, and two side surfaces) of the main body 3, at the corners of the main body 3 in a plan view. This allows one external electrode 5 to be connected to one extraction electrode 19b on two side surfaces of the main body 3, and also allows surface mounting on either the top or bottom surface of the capacitor 1. The shape and dimensions of the portions of the external electrode 5 on each surface are arbitrary. The planar shape of the portion of the external electrode 5 located on the top or bottom surface of the main body 3 is, for example, rectangular (square in the illustrated example). The planar shape and dimensions of the portion of the external electrode 5 located on the side surface of the main body 3 are, for example, rectangular with the same horizontal length as the portion located on the top or bottom surface.

[0060] The thickness of the external electrode 5 is arbitrary. For example, the thickness of the external electrode 5 may be thicker than the thicknesses of the internal electrode 19, the dummy electrode 13, and the base electrode 15. For example, the thickness of the external electrode 5 may be 1.2 times or more, 2 times or more, or 3 times or more the thickness of the base electrode 15, or may be 10 times or less, 5 times or less, or 3 times or less. The above lower and upper limits may be combined arbitrarily. Furthermore, for example, the thickness of the external electrode 5 may be 3 μm or more, 5 μm or more, or 10 μm or more, or may be 30 μm or less, 20 μm or less, or 10 μm or less. The above lower and upper limits may be combined arbitrarily as long as no contradiction occurs.

[0061] The material of the external electrode 5 is, for example, a metal. The specific type of metal is arbitrary, and for example, the entirety or main component thereof is a base metal (e.g., Ni and / or Cu). Furthermore, the external electrode 5 may be formed by laminating different materials as necessary. For example, the external electrode 5 may be formed by laminating Cu, Ni, and Sn from the base electrode 15 side. The material of the external electrode 5 may be the same as or different from the material (e.g., main component) of the internal electrode 19, dummy electrode 13, and / or base electrode 15.

[0062] (2. Void) (2.1. Void in general) In the following, the explanations regarding the voids 21, void density, and void occupied area ratio basically refer to the first area A1. Even if it is not explicitly stated that the explanations are about the voids 21, void density, and void occupied area ratio in the first area A1, they may be understood as explanations about the first area A1, unless a contradiction arises. Furthermore, the explanations about the first area A1 may be applied to the voids 21, void density, and void occupied area ratio in areas other than the first area A1 (areas where the base electrode 15 is not disposed) or in the entire area including the first area A1, unless a contradiction arises.

[0063] Various configurations related to voids 21 in the first area A1 described below (for example, examples of the relative relationship between void densities in the insulator layers 11) may be valid in, for example, all (eight in the example of FIGS. 1 to 3) first areas A1. However, for example, they may only be valid in each of 60% or more or 80% or more of the total number of first areas A1, or may only be valid in each of any one or more first areas A1. Furthermore, the configurations related to voids 21 in the D1D3 cross section described below may be valid in the D2D3 cross section in addition to or instead of the D1D3 cross section.

[0064] The void 21 shown in FIG. 4 is a space where no material is present. The void 21 is usually sealed and does not communicate with the outside of the capacitor 1. A gas may be present in the void 21. The type of gas is arbitrary. The pressure of the gas in the void 21 is also arbitrary, and may be lower than atmospheric pressure at room temperature, for example.

[0065] For example, when the insulator layer 11 is made of ceramics, the voids 21 are formed when the gaps between particles do not completely disappear during the firing process. When the insulator layer 11 is made of another insulating material (e.g., resin), the voids 21 are formed when, for example, gas is entrained during the flow process or the insulating material shrinks during the cooling process. In the description of the embodiments, unless otherwise specified, the insulator layer 11 may be made of ceramics.

[0066] The shape of the voids 21 is not particularly limited. For example, in a cross section such as that shown in FIG. 4, the shape of the voids 21 may be a block shape such as a circle or an ellipse, or may be linear or crack-like. For example, in a cross section such as that shown in FIG. 4, the maximum value of each void 21 is defined as the value obtained by dividing the longer of the lengths in any two mutually perpendicular directions by the shorter, and is referred to as the aspect ratio. In this case, in each insulator layer 11 having at least one void 21 (either the entire layer or the portion located in the first range A1), the number of voids 21 having an aspect ratio of 3.0 or less may be 80% or more, 90% or more, 95% or more, or 100% of the total number of voids 21.

[0067] The dimensions of the voids 21 are not particularly limited. For example, the length of each void 21 in the D3 direction is smaller than the thickness of the insulator layer 11 to which the void 21 belongs (the average thickness of the entire layer, the average thickness in the first range A1, or the thickness at the location of the void 21). For example, the former is 2 / 3 or less, 1 / 2 or less, or 1 / 3 or less of the latter. In each insulator layer 11 (the entire layer or the portion located in the first range A1) having at least one void 21, the number of voids 21 whose length in the D3 direction is less than the thickness of the insulator layer 11 (or any of the above-mentioned various lengths) may be 95% or more or 100% of the total number of voids 21.

[0068] The insulator layer 11 is basically formed so as to reduce the number of voids 21. In this case, the shape of the voids 21 is likely to be clumped, and the shape and dimensions of the voids 21 are likely to be similar to one another. Figure 4 shows a schematic diagram of the voids 21 in such a case.

[0069] (2.2. Void density and void occupied area ratio) As described above, when the shapes and dimensions of the multiple voids 21 are similar to each other, the void density and the void occupied area ratio are correlated. Therefore, unless a contradiction occurs, the description of the void density may be used in reference to the void occupied area ratio by substituting the term void density for the void occupied area ratio. For convenience, in the description of the embodiments, only the void density may be mentioned, and the void occupied area ratio may not be mentioned.

[0070] In the following description, for convenience, the symbol of each portion may be treated as the void density (or void-occupied area ratio) of that portion. For example, as described in the overview of the embodiment, when the void density of the insulator layer 11A is lower than the void density of the insulator layer 11C in the first range A1, it may be expressed as 11A<11C. Also, for example, the ratio of the former to the latter may be expressed as 11A / 11C.

[0071] The void density is a parameter in a predetermined cross section (D1D3 cross section in FIG. 4). Also, in FIG. 4, the width of the first area A1 (the area overlapping the area where the base electrode 15 or the dummy electrode overlaps in the D3 direction) is shown in the direction along the predetermined cross section (D1 direction). However, the first area A1 also has a width in a direction perpendicular to the predetermined cross section (D2 direction in FIG. 4). When a predetermined condition (e.g., 11A<11C) regarding the void density is satisfied in the first area A1, the predetermined condition is satisfied in, for example, a predetermined percentage or more of a predetermined number of cross sections equally dividing the first area A1 in the D2 direction. The predetermined number may be, for example, 3 or more, 5 or more, 10 or more, or 20 or more. The predetermined percentage may be, for example, 60% or more, 80% or more, or 90% or more. While the first area A1 is used as an example, the same applies to other ranges, etc., described later. If it is difficult to observe the predetermined number of cross sections of one sample, the predetermined number of cross sections may be observed in multiple samples intended to have the same configuration. Also, if it is difficult to observe the predetermined number of cross sections of the first range A1, cross sections of ranges other than the first range A1 intended to have the same configuration may be observed.

[0072] The definitions of void density and void area ratio have already been described. To be clear, the void density is obtained by dividing the number of voids 21 in a specified target region in each cross section by the cross-sectional area of the target region. For example, the void density in the insulator layer 11A refers to the value obtained by dividing the number of voids 21 in the insulator layer 11A by the cross-sectional area of the insulator layer 11A. The void density in two or more insulator layers 11 (as a whole) refers to the value obtained by dividing the number of voids 21 in the two or more insulator layers 11 by the cross-sectional area of the two or more insulator layers 11 (the sum of the cross-sectional areas of the two or more insulator layers 11). As can be seen from this example, the void density of two or more insulator layers 11 is not simply the sum of the void densities of each insulator layer 11 divided by the number of insulator layers 11. Similarly, the void area ratio is obtained by dividing the total area of the voids 21 in the target region by the cross-sectional area of the target region.

[0073] When specifying the void density and the void occupied area ratio, the void 21 is, for example, 0.008 μm 2 The size may be equal to or larger than this. This size corresponds to the size of the voids 21 visible in a 1500x image of a cross section such as that shown in FIG. 4 taken with a scanning electron microscope (SEM). In other words, if voids 21 with an area equal to or larger than the above are targeted, it becomes easy to count the number of voids 21 or to calculate the area of the voids 21 by using image processing with an apparatus including an SEM. Note that, for example, linear voids 21 that are so thin that it is difficult to determine their area (for example, their width is smaller than the resolution) may be excluded from the calculation of the void density and void occupied area ratio.

[0074] The void density and void area ratio may be determined using, for example, a JSM-IT500HR manufactured by JEOL Ltd. An image may be acquired under the conditions of a magnification of 1500x, an acceleration voltage of 15 kV, and an irradiation current of 70 (unitless). Based on the image, the number of voids 21 in the target region may be visually determined. Furthermore, a range (target region or voids 21) for measuring the area may be specified based on visual inspection of the image, and the area of the range may be obtained by image processing.

[0075] Furthermore, when determining the void density and the void occupied area ratio, basically, only voids 21 that are closed in the observed cross section may be targeted. This is because the upper or lower surface of the insulator layer 11 is not necessarily smooth, and it may be difficult to distinguish between recesses on the upper or lower surface and voids 21. However, cavities that can be clearly regarded as voids 21 based on their shape, dimensions, etc. may be taken into consideration when determining the void density and the void occupied area ratio. Examples of such cavities include cavities that are generally closed and / or cavities that are clearly larger than recesses.

[0076] As described in the overview of the embodiment, in the first range A1, the void density is 11A<11C. When the number of insulator layers 11 is three or more, the void density of the insulator layer 11 (one insulator layer 11B in the illustrated example) located between the insulator layer 11A and the insulator layer 11C is arbitrary. For example, the void density of the insulator layer 11B (when there are two or more insulator layers 11B, the void density of all or each of them; the same applies hereinafter unless a contradiction occurs) may be smaller, the same, or larger than the void density of the insulator layer 11A (or the insulator layer 11C).

[0077] In the example of Fig. 4, in the first range A1, the void density increases toward the outside of the insulator layer 11. That is, 11A < 11B < 11C. In the illustrated example, 11A < 11B < 11C, and unlike the illustrated example, when the number of insulator layers 11B is two or more, the void density relationship between the insulator layers 11B is arbitrary. For example, the void density may increase toward the outside of the insulator layer 11B, or may be approximately the same.

[0078] The void density in the cover 9 (or, from another perspective, the entire plurality of insulator layers 11) may vary in the D1 direction (and / or the D2 direction; the same applies below) instead of or in addition to the D3 direction. The D1 direction can be said to be the direction in which one side of the cover 9 (the side on the +D1 side in FIG. 4) faces. The D1 direction can also be said to be the direction in which the base electrode 15 extends (and further, the direction in which it is exposed from the side on the +D1 side). The change in void density in the D1 direction may be, for example, such that the value decreases toward the -D1 side (inside), or conversely, the value may increase.

[0079] As shown in Fig. 4, the change in void density in the D1 direction may be understood by the magnitude relationship of the void density among second ranges A2 to fourth ranges A4, which are defined by dividing the first range A1 into three equal parts in the D1 direction. The second range A2 can be said to be the range on the +D1 side (the side on which the base electrode 15 is exposed) of the three ranges. The third range A3 can be said to be the central range of the three ranges. The fourth range A4 can be said to be the range on the opposite side of the +D1 side of the three ranges, and in the illustrated example, can be said to be the range on the central side of the cover 9.

[0080] In the example of FIG. 4, in the plurality of insulator layers 11 (11A to 11C), the void density is such that A4 < A3 and A2 < A3. In this case, the void density in the second range A2 may be smaller than, the same as, or larger than the void density in the fourth range A4. Note that, unlike the above description, only one of A4 < A3 and A2 < A3 may hold. Also, A4 (and / or A2) = A3, or A4 (and / or A2) > A3 may be acceptable.

[0081] In the above description, the change in the void density in the D1 direction has been described with respect to the void density in the first range A1 and the entire plurality of insulator layers 11. However, for example, instead of or in addition to the entire plurality of insulator layers 11, the above change may hold in each of the plurality (all) of the insulator layers 11, or may hold only in each of any one or more of the insulator layers 11.

[0082] In the magnitude relationships exemplified above, the degree of difference (such as difference and ratio) between the two is arbitrary. For example, regarding the void density in the first range A1, when 11A < 11C holds, 11A / 11C may be 9 / 10 or less, 4 / 5 or less, 3 / 4 or less, 1 / 2 or less, or 1 / 3 or less. The lower limit of 11A / 11C is not particularly limited (it may be 0). Also, for example, 11C - 11A is 2 0.005 pieces / μm or more, 2 0.010 pieces / μm or more, 2 0.020 pieces / μm or more, 2 0.050 pieces / μm or more, 2 0.100 pieces / μm or more may be acceptable. The upper limit of 11C - 11A is not particularly limited.

[0083] Also, for example, regarding the void density in the first range A1, in an embodiment where 11A < 11B < 11C holds, 11B / 11C may be 19 / 20 or less, 9 / 10 or less, 7 / 8 or less, 3 / 4 or less, or 2 / 3 or less. The lower limit of 11B / 11C (strictly, the value in the case of 11A < 11B < 11C) may be any value greater than 0. Also, for example, 11A / 11B may be 18 / 19 or less, 8 / 9 or less, 6 / 7 or less, 2 / 3 or less, or 1 / 2 or less. The lower limit of 11A / 11B is not particularly limited (it may be 0). Also, for example, 11C - 11B and / or 11B - 11A is 0.002 pieces / μm 2 or more, 0.005 pieces / μm 2 or more, or 0.010 pieces / μm 2 or more, 0.025 pieces / μm 2 or more, or 0.050 pieces / μm 2 or more, and may be so. The upper limit of 11C - 11B and 11B - 11A is not particularly limited.

[0084] Also, for example, regarding the void density in the first range A1 and the entire plurality of insulator layers 11 (or each insulator layer 11), in an embodiment where A2 < A3 holds, A2 / A3 may be 9 / 10 or less, 4 / 5 or less, 3 / 4 or less, or 1 / 2 or less. The lower limit of A2 / A3 is not particularly limited (it may be 0). Also, for example, A3 - A2 is 0.005 pieces / μm 2 or more, 0.010 pieces / μm 2 or more, or 0.020 pieces / μm 2 or more, 0.050 pieces / μm 2 or more, or 0.100 pieces / μm 2 or more, and may be so. The upper limit of A3 - A2 is not particularly limited. In the description of this paragraph and the next paragraph, A2 may be replaced by A4.

[0085] The above explanation of the example of the void density ratio (11A / 11C, etc.) may be applied to the ratio of the void occupied area ratio. Furthermore, the difference in the void occupied area ratio may be, for example, as follows: When 11A<11C, 11C-11A (void occupied area ratio) may be, for example, 0.005% or more, 0.010% or more, 0.020% or more, or 0.050% or more. When 11A<11B<11C, 11C-11B and / or 11B-11A (void occupied area ratio) may be, for example, 0.002% or more, 0.005% or more, 0.010% or more, or 0.020% or more. A3-A2 (void occupied area ratio) may be, for example, 0.005% or more, 0.010% or more, 0.020% or more, or 0.050% or more. In either case, there is no particular upper limit.

[0086] The absolute value of the void density when various conditions are met is arbitrary. For example, the void density of the first range A1 and the innermost insulating layer 11A (and / or insulating layer 11B) is 0.000 voids / μm 2 More than 0.005 pieces / μm 2 More than 0.010 pieces / μm 2 or more than 0.050 particles / μm 2 It may be 0.200 particles / μm or more. 2 Below, 0.100 pieces / μm 2 Less than or 0.050 pieces / μm 2 The above lower and upper limits may be arbitrarily combined together so long as no contradiction occurs.

[0087] For example, the void density of the first area A1 and the outermost insulating layer 11C (and / or the insulating layer 11B) is 0.020 voids / μm 2 More than 0.050 pieces / μm 2 or more than 0.100 particles / μm 2 It may be 0.500 pieces / μm or more. 2 Below, 0.300 pieces / μm 2 Below, 0.200 pieces / μm 2 Less than or 0.100 pieces / μm 2 The above lower and upper limits may be arbitrarily combined together so long as no contradiction occurs.

[0088] Furthermore, for example, the void-occupied area ratio of the insulator layer 11A (and / or the insulator layer 11B) in the first range A1 may be 0.005% or more, 0.010% or more, or 0.020% or more, or 0.100% or less, 0.080% or more, or 0.060% or less. The above lower and upper limits may be combined arbitrarily.

[0089] Furthermore, for example, the void-occupied area ratio of the insulator layer 11C (and / or the insulator layer 11B) in the first range A1 may be 0.050% or more, 0.080% or more, or 0.100% or more, or 0.300% or less, 0.200% or less, or 0.150% or less. The above lower and upper limits may be combined arbitrarily.

[0090] The above-mentioned examples of the lower limit and / or upper limit of the void density and / or void occupied area ratio of the insulator layer 11A may be applied to the second range A2 and / or the fourth range A4. The above-mentioned examples of the lower limit and / or upper limit of the void density and / or void occupied area ratio of the insulator layer 11C may be applied to the third range A3.

[0091] (2.3. Other) Although not shown in FIG. 4, voids may also be present in portions other than the insulator layer 11. That is, voids may also be present in the dielectric layer 17, the internal electrode 19, the dummy electrode 13, the base electrode 15, and / or the external electrode 5. In this case, for example, the voids in the dielectric layer 17 may (but do not have to) have a smaller average circle-equivalent diameter than the voids 21 in the insulator layer 11. Also, for example, the voids in the internal electrode 19, the dummy electrode 13, the base electrode 15, and the external electrode 5 may (but do not have to) have a larger average circle-equivalent diameter than the voids 21 in the insulator layer 11. The void density and void occupied area ratio are also arbitrary.

[0092] (3. Capacitor manufacturing method The capacitor 1 may be manufactured by various methods. For example, the general procedure may be the same as a known procedure. An example is shown below.

[0093] First, ceramic green sheets that will become the dielectric layers 17 and the insulator layers 11 are prepared. Next, a conductive paste that will become the internal electrodes 19, dummy electrodes 13, or base electrodes 15 is applied (e.g., printed) to the ceramic green sheets. Next, the ceramic green sheets are stacked to prepare a laminate that will become the main body 3. Note that the stacking of the laminate that will become the functional part 7 and the stacking of the portion that will become the cover 9 on the laminate may be performed together or separately.

[0094] The steps up to the production of the laminate are carried out, for example, on a mother substrate the size of which will be used to produce a large number of main body portions 3. After the laminate is produced, the mother substrate including the laminate is diced (e.g., cut) into pieces having a size roughly corresponding to the size of the main body portions 3. Next, the laminate having the size of the main body portions 3 is fired. After that, a metal film is formed on the main body portions 3, and external electrodes 5 are formed.

[0095] Degreasing may be performed before firing. Firing may be performed, for example, in a reducing atmosphere. Re-oxidation heat treatment may be performed after firing. Polishing (e.g., barrel polishing) of the main body portion 3 may be performed before and / or after firing. In polishing, for example, the ridges of the main body portion 3 may be chamfered or the side surfaces of the main body portion 3 may be polished.

[0096] The void density can be adjusted by any method. For example, in the process of stacking the ceramic green sheets to form a laminate, the laminate is pressed without the ceramic green sheet that will become the outermost insulator layer 11C. Then, the ceramic green sheet that will become the outermost insulator layer 11C is placed on the laminate, and pressing is performed again. Since the number of pressings for the insulator layer 11C is smaller than the number of pressings for the other insulator layers 11, voids 21 are more likely to be formed.

[0097] Further, for example, the ratio of the solid content (e.g., ceramic powder) in the ceramic green sheet that becomes the insulator layer 11C is made smaller than that of other ceramic green sheets. As a result, voids 21 are more likely to be formed in the insulator layer 11C than in the other insulator layers 11. Note that the green sheet of the insulating layer may be a single layer or multiple layers.

[0098] In the above, the method of increasing the void density of the insulator layer 11C (the method of realizing 11A < 11C) has been described. However, it is clear that 11A < 11B < 11C and A2 (and / or A4) < A3, etc. can also be realized by applying the above. For example, when realizing A2 < A3 and A4 < A3, when pressing the portion where the base electrode 15 and the dummy electrode 13 are present, pressure may be applied to both ends sides rather than the central part side of these electrodes. Further, a difference in void density may be realized by a method other than the above. For example, a difference in void density may be realized by appropriately setting the temperature conditions during firing.

[0099] The external electrode 5 may be formed by various methods. For example, metal may be deposited on the surface of the base electrode 15, the exposed portion from the side surface of the main body portion 3 of the dummy electrode 13, and the exposed portion from the side surface of the main body portion 3 of the internal electrode 19 by electroless plating and / or electrolytic plating. Further, for example, a thin film forming method such as a dip method, a printing method, CVD (Chemical Vapor Deposition), or PVD (Physical Vapor Deposition) may be employed. As understood from the above, the base electrode 15, the dummy electrode 13, and the internal electrode 19 may or may not contribute to the deposition of metal.

[0100] (4. Other Embodiments) (4.1. Second Embodiment) FIG. 5 is a perspective view of the capacitor 201 according to the second embodiment. FIG. 3 according to the first embodiment may be referred to as a view showing the D1D3 cross section of the capacitor 201. The same applies to FIG. 4.

[0101] Generally speaking, capacitor 201 differs from capacitor 1, which is a four-terminal type, in that it is a two-terminal type. In capacitor 201, the void density and void-occupied area ratio described with reference to FIGS. 3 and 4 may also be set.

[0102] The specific shapes and dimensions of each part of capacitor 201 may differ from those of capacitor 1, since it is a two-terminal type. Specifically, they are as follows.

[0103] The main body 203 (or the capacitor 201) has a shape of, for example, a roughly rectangular parallelepiped. For example, the height (length in the D3 direction) of this rectangular parallelepiped may be equal to (as in the illustrated example) or smaller than (the width (length in the D2 direction). For example, the length (D1 direction) of the rectangular parallelepiped is greater than the width. The dimensions of the main body 203 are arbitrary. The specific examples of the dimensions of the main body 3 in the first embodiment may be applied to the dimensions of the main body 203. The external electrode 5 is generally layer-like and covers the longitudinal ends of the main body 203 over the five faces of the rectangular parallelepiped.

[0104] The planar shape of the internal electrode 19 is, for example, approximately a rectangle having four sides parallel to the four sides of the rectangular main body portion 203 (dielectric layer 17). Of the four sides of the internal electrode 19, two long sides and one short side are, for example, located inside the side surface of the main body portion 203 (not exposed). The remaining short side is exposed from the side surface of the main body portion 203 on the +D1 side or the -D1 side. The region of the internal electrode 19 that overlaps with other internal electrodes 19 in a planar perspective view is the electrode body 19a. The portion extending from the electrode body 19a to the external electrode 5 is the extraction electrode 19b.

[0105] Between two insulator layers 11 adjacent in the D3 direction, for example, two dummy electrodes 13 are provided at both ends of the longitudinal direction of the main body portion 203. The planar shape of the dummy electrode 13 is, for example, a rectangular shape spanning the entire width (length in the D2 direction) of the main body portion 203, and is exposed, for example, from the side surface on the +D1 side or the -D1 side of the main body portion 203 and from the side surface on the +D2 side and the -D2 side. The above description of the configuration of the dummy electrode 13 in a planar view may be applied to the planar shape of the base electrode 15 overlapping the uppermost insulator layer 11C.

[0106] In the capacitor 1 of the first embodiment, the D1D3 cross section and the D2D3 cross section are basically the same. Furthermore, in the explanation of the void density, the D1 direction and the D2 direction are basically reversible. On the other hand, in the capacitor 201 of the second embodiment, the D1D3 cross section and the D1D2 cross section are different.

[0107] In an embodiment such as capacitor 201, the cross section for measuring the void density in the first range A1 may be the D1D3 cross section or the D2D3 cross section. This is because, theoretically, if the number of cross sections for measurement is increased, the values at the multiple D1D3 cross sections and the values at the multiple D2D3 cross sections will approach each other. However, either one of the cross sections may be selected from various viewpoints.

[0108] The second range A2 to the fourth range A4 have different positions and shapes depending on whether the first range A1 is divided into thirds in the D1 direction or the D2 direction. Either the D1 direction or the D2 direction may be selected. When the D1 direction is selected, the fourth range A4 can be said to be a range located closer to the center of the capacitor 201 than the second range A2 and the third range A3, as in the first embodiment. On the other hand, when the D2 direction is selected, the fourth range A4 can be said to be a range adjacent to the side surface of the capacitor 201, as in the second range A2.

[0109] (4.2. Third embodiment) FIG. 6 is a cross-sectional view of a capacitor 401 according to the third embodiment. This cross-sectional view corresponds to FIG. 3 of the first embodiment. In the following description, for convenience, the upper cover 9 will be used as an example unless otherwise specified. Capacitor 401 may be a four-terminal type like the first embodiment, or a two-terminal type like the second embodiment.

[0110] In short, capacitor 401 has a configuration similar to that of capacitor 101 of the first embodiment, except that base electrode 15 is embedded in outermost insulator layer 11C. In Fig. 6, the upper surface of base electrode 15 is generally flush with the upper surface of outermost insulator layer 11. However, the upper surface of base electrode 15 may be located above (or below) the upper surface of outermost insulator layer 11.

[0111] Such an arrangement of the base electrode 15 may be achieved, for example, by making the following modifications to the above-described manufacturing method. Two ceramic green sheets that will become the outermost insulator layer 11C are prepared. A conductive paste that will become the base electrode 15 is placed on the outer surface (upper surface) of the ceramic green sheet that is the inner layer (lower). A hole where the base electrode 15 will be located is formed in the ceramic green sheet on the outer layer (upper).

[0112] Whether two or more layers of ceramic green sheets formed in the manufacturing process constitute a single insulator layer 11 after completion may be determined based on the presence or absence of a dummy electrode 13 interposed therebetween. For example, even if the insulator layer 111C is made of two layers of ceramic green sheets as described above, the insulator layer 11C may be regarded as a single insulator layer because no dummy electrode 13 is interposed therebetween.

[0113] In the above manufacturing method, the conductive paste that becomes the base electrode 15 is placed on the upper surface of the ceramic green sheet on the inner layer side, but after completion, the base electrode 15 still overlaps the upper surface of the outermost insulator layer 11C. In addition, the base electrode 15 still overlaps the outermost insulator layer 11C from the +D3 side.

[0114] When the above-described manufacturing method is employed, the outer ceramic green sheets may cover the edges of the base electrode 15 due to manufacturing errors or intentionally. In this case, the two ceramic green sheets are not separated by the dummy electrode 13, so the insulator layer 11C may be considered as a single insulator layer. Furthermore, the base electrode 15 (strictly speaking, the portion not covered by the outer ceramic green sheets) still overlaps the top surface of the outermost insulator layer 11C, and the base electrode 15 still overlaps the outermost insulator layer 11C from the +D3 side.

[0115] 6, the outermost insulator layer 11C is recessed relatively deeply in the region where the base electrode 15 is located. In this case, the base electrode 15 still overlaps the upper surface of the outermost insulator layer 11C, and the base electrode 15 still overlaps the outermost insulator layer 11C from the +D3 side.

[0116] The above explanation that the insulator layer 11C may be made of two or more ceramic green sheets and that a relatively large recess may be formed in the insulator layer 11C may also be applied to other insulator layers 11. Although it has been mentioned that the boundaries between the multiple insulator layers 11 may be defined by the dummy electrodes 13, the boundaries between the multiple insulator layers 11 may be vague in areas where no dummy electrodes 13 are arranged in a planar perspective view.

[0117] 4 illustrates an example in which the base electrode 15 is slightly embedded in the insulator layer 11C. In this example, it is assumed that the base electrode 15 (conductive paste) disposed on the upper surface of the outermost ceramic green sheet is pressed into the ceramic green sheet. In both the examples of FIG. 4 and FIG. 6, the embedding depth of the base electrode 15 in the insulator layer 11 is arbitrary. Furthermore, regardless of the embedding depth, the embedding method is arbitrary.

[0118] (4.3. Unillustrated embodiment) Although not specifically shown, still another embodiment will be described.

[0119] The cover 9 may be provided on only one of the upper and lower surfaces of the functional portion 7. The capacitor 1 may be distributed from one factory to another without the external electrodes 5 (i.e., the main body portion 3).

[0120] The capacitor may have an exterior resin that covers the entire structure illustrated in FIG. 1 or 5, and lead wires that are connected to the external electrodes 5 and extend from the exterior resin. From another perspective, the capacitor may be a through-hole mount type rather than a surface mount type. In such a configuration, one external electrode 5 may only cover one side surface. Furthermore, the number of terminals (external electrodes 5) of the capacitor is not limited to two or four, and may be three or five or more.

[0121] Two types of internal electrodes 19 connected to different external electrodes 5 may be alternately stacked two by two, rather than one by one. In this case, for example, the thickness of the dielectric layer 17 between the internal electrodes 19 connected to the same external electrode 5 and facing each other may be thinner than the thickness of the dielectric layer 17 between the internal electrodes 19 connected to different external electrodes 5 and facing each other. As can be understood from this, the multiple dielectric layers 17 do not need to have the same shape and size.

[0122] Furthermore, two types of internal electrodes 19 connected to different external electrodes 5 do not have to face each other. For example, two types of internal electrodes 19 connected to different external electrodes 5 may be provided in the same layer, and an internal electrode 19 facing the two types of internal electrodes 19 may be provided, thereby forming a circuit in which two parallel plate capacitors are connected in series. Also, a circuit in which three or more parallel plate capacitors are connected in series may be formed.

[0123] 5, the rectangular internal electrode 19 is sandwiched between dielectric layers 17 that extend beyond the two long sides of the internal electrode 19 parallel to the D1 direction on both sides (outside) in the D2 direction, so that the two long sides are not exposed from the -D2 side and +D2 side of the main body 203. However, the configuration in which the long sides are not exposed may be achieved by overlaying other dielectric layers on the -D2 side and +D2 side of the laminate formed of the dielectric layers 17 and the insulator layers 11. From another perspective, the entire main body 203 does not need to have a laminated structure.

[0124] The electronic component is not limited to a capacitor. For example, the electronic component may be a multilayer electronic component other than a capacitor, or may be a non-multilayer electronic component. Examples of multilayer electronic components include multilayer inductors, multilayer varistors, multilayer ferrite beads, multilayer thermistors, and multilayer filters. Non-multilayer electronic components are diverse, and include, for example, ICs (integrated circuits).

[0125] The multilayer electronic component has, for example, a functional section (7) in which non-conductors (e.g., dielectric layers 17) and conductors (e.g., internal electrodes 19) are alternately laminated. In such a configuration, the cover 9 having two or more insulator layers 11 can be formed, for example, as an extension of the process of forming the functional section. Therefore, even if the configuration of the cover 9 according to the embodiment is adopted, the likelihood of the manufacturing process becoming complicated is reduced.

[0126] The multilayer ceramic filter may have, for example, an LC circuit. As can be seen from this example, the multilayer electronic component may perform two or more functions (a capacitor and an inductor). The portions performing different functions may be different portions when viewed from a plan perspective and / or may be different portions when viewed from a side perspective.

[0127] (5. Summary of embodiments) Below, the configuration of the electronic component according to the embodiment is extracted, and the effects of the extracted configuration are illustrated. However, the effects illustrated below do not necessarily have to be achieved. Furthermore, for convenience, the symbols of the first embodiment are used below. However, the matters described below also apply to other embodiments unless a contradiction arises. Furthermore, to reiterate, unless a contradiction arises, the term "void density" may be replaced with the term "void occupied area ratio" (or the term "void density and void occupied area ratio").

[0128] The capacitor 1 (an example of an electronic component) has a functional section 7 and a cover 9 (an example of a cover section). The functional section 7 has an upper surface (an example of a first surface) facing the +D3 side (an example of a first side) in the D3 direction (an example of a first direction). The cover 9 overlaps the upper surface of the functional section 7. The cover 9 also has two or more (three in the example of FIG. 4) insulator layers 11 and one or more dummy electrodes 13 (two in the example of FIG. 4) that are alternately overlapped in the D3 direction, and also has a base electrode 15 that overlaps the +D3 side surface (upper surface) of the outermost insulator layer 11C.

[0129] The area of the cover 9 where the base electrode 15 is located is referred to as the first area A1. The number of voids 21 per unit area in the cross section along the D3 direction is referred to as the void density. In this case, in the first area A1, the void density of the innermost insulator layer 11A is smaller than the void density of the outermost insulator layer 11C.

[0130] And / or, when the total area of voids 21 per unit area in a cross section along the D3 direction is referred to as the void occupied area ratio, in the first range A1, the void occupied area ratio of the innermost insulator layer 11A is smaller than the void occupied area ratio of the outermost insulator layer 11C.

[0131] Therefore, for example, as described in the overview of the embodiment, it is possible to improve the peel strength between the outermost insulator layer 11C and the base electrode 15 while reducing cracks in the insulator layer 11A that is relatively close to the functional section 7. More specifically, reducing the void density in the insulator layer 11A contributes to, for example, reducing the number of voids 21 that can become the starting point of cracks. Reducing the void occupied area ratio in the insulator layer 11A contributes to, for example, reducing stress concentrated around the voids 21. However, as described above, in reality, the void density and the void occupied area ratio are often correlated.

[0132] The number of insulator layers 11 may be three or more. In the first range A1, the void density of one or more insulator layers 11B (not individually but as a whole) located between the outermost insulator layer 11C and the innermost insulator layer 11A may be smaller than the void density of the outermost insulator layer 11C, or may be larger than the void density of the innermost insulator layer 11A (the void density may be 11A<11B<11C).

[0133] In this case, for example, the probability of a sudden change in void density from insulator layer 11A to insulator layer 11C is reduced. As a result, for example, the mechanical properties of the insulator layers 11 adjacent to each other in the D3 direction become closer to each other, and it is expected that the stress generated between them will be reduced.

[0134] In the first range A1, the void density of the innermost insulator layer 11A may be ¾ or less of the void density of the outermost insulator layer 11C.

[0135] In this case, for example, the difference in void density between the insulating layers 11A and 11C is relatively large, and as a result, the above-mentioned effects are more likely to be achieved.

[0136] The cover 9 may have a side surface (for example, a side surface on the +D1 side shown in FIG. 4) facing a D1 direction (an example of a second direction) intersecting the D3 direction. The base electrode 15 may extend in the D1 direction to reach the side surface on the +D1 side. Assuming that the first area A1 is divided into three equal parts in the D1 direction, a second area A2 on the +D1 side, a central third area A3, and a fourth area A4 on the -D1 side are defined. In this case, in two or more (all) insulator layers 11 (not individually, but overall), the void density in each of the fourth area A4 and the second area A2 may be smaller than the void density in the third area A3.

[0137] In this case, for example, the second area A2 and the fourth area A4 are located at the ends of the base electrode 15, and therefore moisture is likely to penetrate therein. However, the small number of voids 21 at these ends reduces moisture penetration, improving reliability. This also reduces the likelihood of cracks occurring at positions relatively close to the ends of the external electrodes 5 on the -D1 side (the fourth area A4 side relative to the third area A2). In multilayer ceramic capacitors, cracks often occur at the ends of the external electrodes on the -D1 side. By improving the reliability at these ends, the reliability of the capacitor 1 can be effectively improved.

[0138] The thickness of the cover 9 in the first area A1 may be 25 μm or less.

[0139] In this case, for example, the thickness of the cover 9 is relatively thin, and therefore cracks in the insulator layer 11A have a relatively large effect on the electrical and / or mechanical reliability of the capacitor 1. Therefore, the effect of reducing the void density of the insulator layer 11A is effectively achieved.

[0140] The thickness of the cover 9 in the first area A1 may be ⅕ or more of the thickness of the functional part 7.

[0141] In this case, for example, the thickness of cover 9 accounts for a relatively large proportion of the thickness of capacitor 1, so the mechanical reliability of cover 9 has a relatively large effect on the mechanical and / or electrical reliability of capacitor 1. Therefore, the effect of reducing the void density of insulator layer 11A is effectively achieved.

[0142] The capacitor 1 may further include an external electrode 5. The external electrode 5 may extend across the upper surface and side surfaces of the cover 9 along the D3 direction, and the side surfaces of the functional section 7 along the D3 direction. The functional section 7 may include a plurality of dielectric layers 17 (an example of a non-conductor layer) and a plurality of internal electrodes 19 (an example of a conductor) alternately stacked in the D1 direction. The external electrode 5 may be bonded to at least a portion of the internal electrode 19 on the side surfaces of the functional section 7, or may be bonded to a dummy electrode 13 on the side surfaces of the cover 9, and may further be bonded to a base electrode 15 on the upper surface of the cover 9.

[0143] In this case, for example, as described above, the cover 9 according to the embodiment can be realized as an extension of the process of forming the laminated functional unit 7. Also, for example, the internal electrode 19 and the external electrode 5 can be directly connected to each other on the side surface of the main body 3 without the base electrode 15 therebetween, thereby reducing electrical resistance. On the other hand, the external electrode 5 is fixed to the upper surface of the main body 3 via the base electrode 15, thereby improving the bonding strength. The relatively high void density of the insulator layer 11C effectively contributes to this improvement in bonding strength.

[0144] In the above embodiments, capacitors 1 and 201 are each an example of an electronic component. The D3 direction is an example of a first direction. The +D3 side is an example of a first side. The top surface of the functional unit 7 is an example of a first surface. The D1 direction is an example of a second direction. The side surface of the cover 9 on the +D3 side is an example of a first side. The dielectric layer 17 is an example of a non-conductor layer. The internal electrode 19 is an example of a conductor. The technology according to the present disclosure is not limited to the above embodiments and may be implemented in various forms. For example, the above-described embodiments may be combined as appropriate.

[0145] The following concepts may be extracted from the present disclosure. An electronic component has a functional section and a cover section. The functional section has a first surface facing a first side in a first direction. The cover section overlaps the first surface. The cover section also has one or more insulator layers overlapping the first surface and a base electrode overlapping the first side surface of the outermost insulator layer, and has a first side surface facing a second direction intersecting the first direction. The base electrode extends in the second direction to reach the first side surface. Assuming that the first range is divided into three equal parts in the second direction, a second range on the side of the first side surface, a central third range, and a fourth range opposite the first side surface are defined. In the one or more insulator layers, the void density in the second range and / or the fourth range is lower than the void density in the third range. [Explanation of symbols]

[0146] 1...capacitor (electronic component), 7...functional part, 9...cover (cover part), 11...insulating layer, 13...dummy electrode, 15...base electrode, 21...void.

Claims

1. a functional portion having a first surface facing a first side in a first direction; a cover portion overlapping the first surface; It has The cover portion is two or more insulating layers and one or more dummy electrodes alternately stacked in the first direction; a base electrode overlapping the outermost insulator layer from the first side, the base electrode is exposed on the first surface of the cover portion, the one or more dummy electrodes are exposed on a first side surface of the cover portion facing a second direction intersecting the first direction, the innermost insulating layer is located between the functional section and a dummy electrode that is located closest to the functional section among the one or more dummy electrodes, a range of the cover portion that overlaps with the base electrode or the dummy electrode in a planar perspective view from the first direction is referred to as a first range, and the number of voids per unit area in a cross section along the first direction is referred to as a void density. In the first range, the void density of the innermost insulating layer is smaller than the void density of the outermost insulating layer, Assuming that the first range is divided into three equal parts in the second direction, a second range on the first side surface side, a third range in the center, and a fourth range on the opposite side of the first side surface are defined, in the two or more insulator layers, the void density of each of the fourth range and the second range is smaller than the void density of the third range. Electronic components.

2. the number of the insulator layers is three or more; In the first range, the void density of one or more of the insulator layers located between the outermost insulator layer and the innermost insulator layer is smaller than the void density of the outermost insulator layer and larger than the void density of the innermost insulator layer. The electronic component according to claim 1 .

3. In the first range, the void density of the innermost insulating layer is 3 / 4 or less of the void density of the outermost insulating layer. The electronic component according to claim 1 .

4. When the total area of voids per unit area in the cross section is referred to as a void occupied area ratio, in the first range, the void occupied area ratio of the innermost insulating layer is smaller than the void occupied area ratio of the outermost insulating layer. The electronic component according to claim 1 .

5. a functional portion having a first surface facing a first side in a first direction; a cover portion overlapping the first surface; It has The cover portion is two or more insulating layers and one or more dummy electrodes alternately stacked in the first direction; a base electrode overlapping the outermost insulator layer from the first side, the base electrode is exposed on the first surface of the cover portion, the one or more dummy electrodes are exposed on a first side surface of the cover portion facing a second direction intersecting the first direction, the innermost insulating layer is located between the functional section and a dummy electrode that is located closest to the functional section among the one or more dummy electrodes, a range of the cover portion that overlaps with the base electrode or the dummy electrode in a planar perspective view from the first direction is referred to as a first range, and a total area of voids per unit area in a cross section along the first direction is referred to as a void occupied area ratio, in the first range, the void occupied area ratio of the innermost insulating layer is smaller than the void occupied area ratio of the outermost insulating layer, Assuming that the first range is divided into three equal parts in the second direction, a second range on the first side surface side, a third range in the center, and a fourth range on the opposite side of the first side surface are defined, in the two or more insulator layers, the void occupied area ratio of each of the fourth range and the second range is smaller than the void occupied area ratio of the third range. Electronic components.

6. The thickness of the cover portion in the first region is 25 μm or less. The electronic component according to any one of claims 1 to 5.

7. The thickness of the cover portion in the first region is equal to or greater than 1 / 5 of the thickness of the functional portion. The electronic component according to any one of claims 1 to 5.

8. The thickness of the base electrode is between 2 and 20 times the thickness of each of the one or more dummy electrodes. The electronic component according to any one of claims 1 to 5.

9. an external electrode that contacts the base electrode from the first side and contacts the one or more dummy electrodes from a side facing the first side surface; The electronic component according to any one of claims 1 to 5.

10. The external electrodes are formed by plating. The electronic component according to claim 9.

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