Resistance element and its manufacturing method

Abstract

To provide a resistance element that enables high resistance while ensuring ESD resistance without changing a mounting area.SOLUTION: A resistance element includes resistance layers 31a, 31c, 91a, 91c provided on semiconductor substrates 1, 11 via field insulating films 2, 12, pad forming electrodes 21, 51 electrically connected to one end sides of the resistance layers 31a, 31c, 91a, 91c, relay wiring 22a, 22c, 52a, 52c having one terminal electrically connected to the other end sides of the resistance layers 31a, 31c, 91a, 91c and the other terminal in ohmic contact with the semiconductor substrates 1, 11, and rear electrodes 9, 19 provided under the semiconductor substrates 1, 11, where a plurality of resistor chips 10a and 10b having the same chip size are stacked, the resistor layers 31a, 31c, 91a and 91c of the resistor chips 10a and 10b are connected in series, and an electrical path between the pad forming electrode 51 of the resistor chip 10a and the rear electrode 19 of the resistor chip 10b is a resistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a resistor element used as a gate resistor element of a switching element, and a method for manufacturing the same. [Background technology]

[0002] A known resistor element for semiconductor devices such as semiconductor integrated circuits (ICs) is one that has an insulating layer formed on a silicon substrate and a thin-film resistive layer formed on the insulating layer. In this resistor element, two electrodes connected to opposing sides of the resistive layer are located on the top surface of the resistive layer. This increases the chip size and requires two bonding wires to connect the two electrodes.

[0003] Therefore, Patent Document 1 discloses a vertical resistor element in which the electrical path between the pad-forming electrode on the upper surface side and the back surface electrode on the lower surface side serves as a resistor. With the resistor element described in Patent Document 1, there is only one pad area on the upper surface side, which allows the number of bonding wires to be reduced to one, and also reduces the area occupied by the pad area on the upper surface side, thereby enabling a reduction in chip size.

[0004] Patent Document 2 discloses a stacked integrated circuit including a lower chip including a lower semiconductor element and an upper chip including an upper semiconductor element. Patent Document 3 discloses a semiconductor module in which a semiconductor substrate, which is an IC chip on which a protective element is formed, is stacked on a semiconductor substrate, which is a driver IC chip. Patent Document 4 discloses a power semiconductor device in which a power IC chip and an integrated circuit chip larger in chip size than the power IC chip are arranged so that their main surfaces face each other. Patent Document 5 discloses a semiconductor device in which a semiconductor chip on which a power FET is formed and a semiconductor chip on which a comparator is formed are connected via bumps. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-106485 [Patent Document 2] Japanese Patent Application Publication No. 2019-145547 [Patent Document 3] JP 2019-12800 A [Patent Document 4] Patent No. 6371122 [Patent Document 5] Patent No. 3973491 Summary of the Invention [Problem to be solved by the invention]

[0006] The resistive element described in Patent Document 1 is configured as one vertical resistor on one chip. Therefore, it is necessary to design a resistive element with an appropriate resistance value for each semiconductor module, resulting in a large number of series. Furthermore, if the chip size of the resistive element is changed, the mounting area in the semiconductor module must also be changed. Furthermore, when increasing the resistance of a resistive element on a single chip, narrowing the width of the resistor makes it difficult to achieve both high resistance and electrostatic discharge (ESD) resistance.

[0007] In view of the above problems, an object of the present invention is to provide a resistor element that can achieve high resistance while ensuring ESD resistance without changing the mounting area, and a method for manufacturing the same. [Means for solving the problem]

[0008] One aspect of the present invention is a resistor element comprising: (a) a semiconductor substrate; (b) a field insulating film provided on the semiconductor substrate; (c) a resistive layer provided on the field insulating film; (d) an interlayer insulating film provided so as to cover the field insulating film and the resistive layer; (e) a pad-forming electrode provided on the interlayer insulating film and electrically connected to one end of the resistive layer; (f) a relay wiring provided on the interlayer insulating film and spaced apart from the pad-forming electrode, the relay wiring having one terminal electrically connected to the other end of the resistive layer and the other terminal in ohmic contact with the semiconductor substrate; and (g) a back surface electrode provided below the semiconductor substrate and in ohmic contact with the semiconductor substrate; wherein a plurality of resistor chips having the same chip size are stacked, the resistive layers of the plurality of resistor chips are connected in series, and the electrical path between the pad-forming electrode of the uppermost resistor chip and the back surface electrode of the lowermost resistor chip serves as a resistor.

[0009] Another aspect of the present invention is summarized as a method for manufacturing a resistor element, including: (a) a step of preparing a plurality of resistor chips each having the same chip size, each of which includes: a semiconductor substrate; a field insulating film provided on the semiconductor substrate; a resistive layer provided on the field insulating film; an interlayer insulating film provided so as to cover the field insulating film and the resistive layer; a pad-forming electrode provided on the interlayer insulating film and electrically connected to one end of the resistive layer; relay wiring provided on the interlayer insulating film and spaced apart from the pad-forming electrode, the relay wiring having one terminal electrically connected to the other end of the resistive layer and the other terminal in ohmic contact with the semiconductor substrate; and a back electrode provided below the semiconductor substrate and in ohmic contact with the semiconductor substrate; and (b) a step of stacking the plurality of resistor chips to connect the resistive layers of the plurality of resistor chips in series, and forming an electrical path between the pad-forming electrode of the uppermost resistor chip and the back electrode of the lowermost resistor chip as a resistor. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a resistor element that can be made to have a high resistance while ensuring ESD resistance without changing the mounting area, and a method for manufacturing the same. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a plan view of a resistance element according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 3] FIG. 2 is a cross-sectional view seen from the direction BB in FIG. [Figure 4] FIG. 2 is another plan view of the resistance element according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along the AA direction in FIG. 4. [Figure 6] FIG. 10 is a circuit diagram showing an application example of the resistance element according to the embodiment. [Figure 7] 1 is a cross-sectional view of a semiconductor module according to an embodiment. [Figure 8] 1A and 1B are plan views of a method for manufacturing a semiconductor module according to an embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along the AA′ direction in FIG. 8. [Figure 10] 5A to 5C are cross-sectional views of a method for manufacturing a semiconductor module according to an embodiment. [Figure 11] FIG. 10 is a plan view of a resistance element according to a first modified example of the embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along the AA direction in FIG. [Figure 13] FIG. 10 is a plan view of a resistance element according to a second modified example of the embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along the AA direction in FIG. [Figure 15] FIG. 10 is a plan view of a resistance element according to a third modified example of the embodiment. [Figure 16] FIG. 10 is a plan view of a resistance element according to a fourth modified example of the embodiment. [Figure 17] FIG. 10 is a plan view of a resistance element according to a fifth modified example of the embodiment. [Figure 18] FIG. 10 is a plan view of a resistance element according to a sixth modified example of the embodiment. [Figure 19] FIG. 19 is a cross-sectional view taken along the AA direction in FIG. 18. [Figure 20] FIG. 13 is a plan view of a resistance element according to a seventh modified example of the embodiment. [Figure 21] FIG. 13 is an equivalent circuit diagram of a resistance element according to a seventh modified example of the embodiment. [Figure 22] FIG. 13 is a plan view of a resistance element according to an eighth modified example of the embodiment. [Figure 23] FIG. 23 is a cross-sectional view taken along the AA direction in FIG. 22. [Figure 24] FIG. 13 is a plan view of a resistance element according to a ninth modified example of the embodiment. [Figure 25] FIG. 23 is a plan view of a resistance element according to a tenth modification of the embodiment. [Figure 26] FIG. 23 is a plan view of a resistance element according to an eleventh modification of the embodiment. [Figure 27] FIG. 23 is a plan view of a resistance element according to a twelfth modification of the embodiment. [Figure 28] FIG. 23 is a plan view of a resistance element according to a thirteenth modified example of the embodiment. [Figure 29] FIG. 23 is a cross-sectional view of a resistance element according to a fourteenth modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention and their modifications will be described with reference to the drawings. In the drawings, identical or similar parts will be designated by identical or similar reference numerals, and redundant description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios. Furthermore, the embodiments shown below are merely examples of devices and methods embodying the technical concept of the present invention. The technical concept of the present invention does not limit the materials, shapes, structures, arrangements, and the like of the components to those described below. Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as being converted to left and right, and if it is rotated 180 degrees and observed, up and down are read as being reversed.

[0013] (Embodiment) <Resistance element> FIG. 1 is a plan view of a resistor element according to an embodiment of the present invention, and a cross-sectional view taken along the AA direction in FIG. 1 corresponds to FIG. 2, and a cross-sectional view taken along the BB direction in FIG. 1 corresponds to FIG. 3. As shown in FIGS. 1 to 3, the resistor element according to the embodiment of the present invention includes a plurality of (two) vertical resistor chips 10a, 10b having the same chip size stacked and connected in series, and an electrical path between the pad-forming electrode 51 of the resistor chip 10a, which is the uppermost of the resistor chips 10a, 10b, and the back electrode 19 of the resistor chip 10b, which is the lowermost, is used as a resistor. In FIGS. 1 to 3, since two resistor chips 10a, 10b are stacked, the upper resistor chip (hereinafter also referred to as the "upper resistor chip") 10a is the uppermost, and the lower resistor chip (hereinafter also referred to as the "lower resistor chip") 10b is the lowermost.

[0014] As shown in Fig. 1, the upper resistor chip 10a has a rectangular planar pattern. However, the planar pattern of the upper resistor chip 10a is not limited to a rectangle. The chip size of the upper resistor chip 10a is, for example, about 3 mm x 3 mm, but can be set appropriately. The upper resistor chip 10a has resistive layers 31a to 31d provided along each side of the rectangle of the upper resistor chip 10a.

[0015] 2, the upper resistor chip 10a includes a low-resistivity semiconductor substrate 1, a field insulating film (first insulating film) 2 disposed on the semiconductor substrate 1, and resistive layers 31a and 31c made of thin films disposed on the field insulating film 2. Although omitted in the cross-sectional structure of FIG. 2, the resistive layers 31b and 31d shown in FIG. 1 are disposed on the field insulating film 2, similar to the resistive layers 31a and 31c shown in FIG. 2.

[0016] The thickness of the semiconductor substrate 1 is, for example, about 350 μm. As the semiconductor substrate 1, a substrate with low resistivity, such as a silicon substrate doped with a high concentration of n-type impurities, can be used. The resistance component of the semiconductor substrate 1 is preferably small enough to be negligible compared to the resistance components of the resistive layers 31a to 31d. In other words, the resistance component of the semiconductor substrate 1 is preferably about 1 / 100 or less of the resistance components of the resistive layers 31a to 31d. The resistivity of the semiconductor substrate 1 may be, for example, about 2 mΩ·cm to 60 mΩ·cm. Note that as the semiconductor substrate 1, a silicon substrate doped with a high concentration of p-type impurities or a semiconductor substrate other than silicon may also be used.

[0017] The thickness of the field insulating film 2 is, for example, about 800 nm. By thickening the field insulating film 2, the parasitic capacitance can be reduced. The field insulating film 2 can be a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film of these. The field insulating film 2 can also be an insulating film (TEOS film) formed by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) gas, an organosilicon compound.

[0018] As shown in FIG. 1, the resistive layers 31a to 31d have a rectangular planar pattern. The resistive layers 31a to 31d have a thickness of, for example, about 500 nm, and a sheet resistance of, for example, about 150 Ω / □. For example, an n-type doped polysilicon (DOPOS) layer can be used as the resistive layers 31a to 31d. An n-type DOPOS layer can be formed by ion-implanting n-type impurities such as phosphorus (P) into polycrystalline silicon (polysilicon) or by adding polycrystalline silicon during deposition using a CVD apparatus. The resistance values of the resistive layers 31a to 31d can be controlled by adjusting the width W1 and length L1 of the resistive layers 31a to 31d. When a DOPOS layer is used for the resistive layers 31a to 31d, the resistance values of the resistive layers 31a to 31d can also be controlled by adjusting the amount of impurity element added to the polysilicon.

[0019] It is preferable that the temperature coefficient of the resistance layers 31a to 31d is 0 ppm / °C or less (in other words, the temperature coefficient of the resistance layers 31a to 31d is 0 or the resistance layers 31a to 31d have a negative temperature coefficient). This makes it possible to suppress an increase in resistance value during high temperature operation. For example, when the resistance element according to the embodiment is applied as a gate resistance element of an insulated gate bipolar transistor (IGBT), it is possible to suppress loss when the IGBT is on. The temperature coefficient of DOPOS can be controlled, for example, by adjusting the dose amount when ion-implanting impurities into polysilicon. For example, when the dose amount is 7.0×10 15 cm -2 or less, the temperature coefficient of DOPOS can be set to approximately 0 ppm / ° C. or less. The temperature coefficient of the resistive layers 31a to 31d is not necessarily limited to 0 ppm / ° C. or less, and the resistive layers 31a to 31d may have a positive temperature coefficient.

[0020] The resistance layers 31a to 31d may be p-type DOPOS layers. The p-type DOPOS layers can also be formed by ion-implanting p-type impurities such as boron (B) into polysilicon. The resistance layers 31a to 31d are not limited to DOPOS layers, and may be formed of tantalum nitride (TaN x The resistive layers 31a to 31d may be a film of a nitride of a transition metal such as Cr, Ni, or a laminated film of a high-melting point metal film laminated in this order: chromium (Cr), nickel (Ni), and manganese (Mn). The resistive layers 31a to 31d may be thin films of silver palladium (AgPd), ruthenium oxide (RuO), or the like. Although different from the structure shown in FIGS. 1 and 2, the resistive layers 31a to 31d may also be realized by p-type diffusion layers or n-type diffusion layers formed on the semiconductor surface.

[0021] As shown on the left side of Fig. 1, dummy layers 32a and 32b are arranged spaced apart from resistive layer 31a to sandwich the resistive layer 31a. As shown on the upper side of Fig. 1, dummy layers 32c and 32d are arranged spaced apart from resistive layer 31b to sandwich the resistive layer 31b. As shown on the right side of Fig. 1, dummy layers 32e and 32f are arranged spaced apart from resistive layer 31c to sandwich the resistive layer 31c. As shown on the lower side of Fig. 1, dummy layers 32g and 32h are arranged spaced apart from resistive layer 31d to sandwich the resistive layer 31d.

[0022] The dummy layers 32a-32h are made of the same material as the resistive layers 31a-31d, such as n-type DOPOS, and have the same thickness as the resistive layers 31a-31d. The width and length of the dummy layers 32a-32h may be the same as or different from the widths W1 and L1 of the resistive layers 31a-31d. The dummy layers 32a-32h are not necessarily provided.

[0023] Although not shown in FIG. 1, as shown in FIGS. 2 and 3, an interlayer insulating film (second insulating film) 4 is disposed to cover the field insulating film 2 and the resistive layers 31a-31d. The thickness of the interlayer insulating film 4 is, for example, approximately 1500 nm. The interlayer insulating film 4 may be a single-layer film of a silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with phosphorus and boron (BPSG film), or a silicon nitride film (Si3N4 film), or a composite film that combines two or more of these. For example, the interlayer insulating film 4 may be a composite film formed by stacking an approximately 770 nm NSG film and an approximately 650 nm PSG film. The NSG film may suppress resistance variations. The PSG film may also ensure the strength of wire bonding.

[0024] As shown in FIGS. 2 and 3, the pad-forming electrode 51 is located above the field insulating film 2. As shown in FIG. 1, the pad-forming electrode 51 has a rectangular planar pattern. The center O of the rectangular planar pattern of the pad-forming electrode 51 is located at the center of the chip. As shown in FIGS. 1 and 2, the left end of the pad-forming electrode 51 overlaps one end of the right side of the resistance layer 31a in the depth direction. The pad-forming electrode 51 is connected to one end of the resistance layer 31a via an electrode contact region 61a.

[0025] As shown in FIG. 1, an upper end of the pad-forming electrode 51 overlaps one end of the resistance layer 31b in the depth direction. The pad-forming electrode 51 is connected to one end of the resistance layer 31b via an electrode contact region 61b. As shown in FIGS. 1 and 2, a right end of the pad-forming electrode 51 overlaps one end of the resistance layer 31c in the depth direction. The pad-forming electrode 51 is connected to one end of the resistance layer 31c via an electrode contact region 61c. As shown in FIG. 1, a lower end of the pad-forming electrode 51 overlaps one end of the resistance layer 31d in the depth direction. The pad-forming electrode 51 is connected to one end of the resistance layer 31d via an electrode contact region 61d.

[0026] 1 to 3, relay wirings 52a to 52d are arranged on the interlayer insulating film 4 at a distance from the pad-forming electrode (surface electrode) 51 so as to surround the central pad-forming electrode 51. The planar patterns of the pad-forming electrode 51, the resistive layers 31a to 31d, and the relay wirings 52a to 52d are four-fold rotationally symmetric with respect to the center O of the chip. This allows the resistive element according to the embodiment to be rotated by 90° or 180° when mounted, facilitating assembly work.

[0027] 2, the position of the right end of the relay wiring 52a overlaps with the other end of the resistive layer 31a in the depth direction. A resistive layer connection terminal, which is one end (first end) of the relay wiring 52a, contacts the other end of the resistive layer 31a via the wiring contact region 62a. The position of the left end of the relay wiring 52c overlaps with the other end of the resistive layer 31c in the depth direction. A resistive layer connection terminal, which is one end (first end) of the relay wiring 52c, contacts the other end of the resistive layer 31c via the wiring contact region 62c.

[0028] Although not shown, at the back side of the paper in Fig. 2, the position of the end of the relay wiring 52b overlaps in the depth direction with the other end of the resistive layer 31b. A resistive layer connection terminal, which is one end (first end) of the relay wiring 52c, contacts the other end of the resistive layer 31b via the wiring contact region 62b. At the front side of the paper in Fig. 2, the position of the end of the relay wiring 52d overlaps in the depth direction with the other end of the resistive layer 31d. A resistive layer connection terminal, which is one end (first end) of the relay wiring 52d, contacts the other end of the resistive layer 31d via the wiring contact region 62d.

[0029] 1 and 2, the substrate connection terminals, which are the other ends (second ends) of the relay wirings 52a to 52d, are in ohmic contact with the semiconductor substrate 1 through the substrate contact regions 63a to 63d with low contact resistance. A contact region having a higher impurity concentration (lower resistivity) than the semiconductor substrate 1 and the same conductivity type as the semiconductor substrate may be provided on the upper part of the semiconductor substrate 1, which is the contact point between the substrate contact regions 63a to 63d and the semiconductor substrate 1.

[0030] The pad forming electrode 51 and the relay wirings 52a-52d have a thickness of, for example, about 3 μm. The pad forming electrode 51 and the relay wirings 52a-52d can be configured, for example, with a laminated film of titanium / titanium nitride (Ti / TiN) as a barrier metal of about 120 nm, aluminum-silicon (Al-Si) of about 3 μm, and TiN / Ti as an anti-reflection film of about 45 nm. Instead of Al-Si, Al or an Al alloy such as Al-Cu-Si or Al-Cu may be used. A bonding wire 74 made of a metal such as aluminum (Al) and having a diameter of about 300 μm is connected to the pad forming electrode 51.

[0031] Although not shown in FIG. 1, as shown in FIGS. 2 and 3, a guard ring layer 53 is disposed on the interlayer insulating film 4. The guard ring layer 53 is disposed in a ring shape on the outer periphery of the chip constituting the resistive element according to the embodiment. The guard ring layer 53 contacts the semiconductor substrate 1 via peripheral contact regions 64a and 64b. The guard ring layer 53 is made of the same material as the pad forming electrode 51 and the relay wirings 52a to 52d. The guard ring layer 53 can have the function of preventing moisture from entering from the side surfaces of the chip.

[0032] 2 and 3, a protective insulating film (third insulating film) 7 is disposed on the pad-forming electrode 51, the relay wirings 52a to 52d, and the guard ring layer 53. The protective insulating film 7 can be formed of a composite film in which, for example, a TEOS film, a Si3N4 film, and a polyimide film are laminated in this order. An opening 7a is provided in the protective insulating film 7. In FIG. 1, the protective insulating film 7 is not shown, and only the opening 7a of the protective insulating film 7 is shown by a dashed dotted line. The portion of the pad-forming electrode 51 exposed from the opening 7a becomes a pad region to which a bonding wire can be connected.

[0033] 2 and 3, a back electrode (counter electrode) 9 is disposed on the lower surface of the semiconductor substrate 1. The back electrode 9 can be formed, for example, of a single layer film made of gold (Au) or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au). The outermost layer of the back electrode 9 can be formed of a solderable material. The upper resistor chip 10a has four resistor layers 31a to 31d connected in parallel between the pad-forming electrode 51 and the back electrode 9, and the electrical path between the pad-forming electrode 51 and the back electrode 9 serves as a resistor.

[0034] The upper resistor chip 10a is provided with four resistive layers 31a-31d, but the resistive layers 31a-31d can be selectively used by changing the presence or absence of the electrode contact regions 61a-61d, the wiring contact regions 62a-62d, and the substrate contact regions 63a-63d. For example, when selectively using one resistive layer 31a of the four resistive layers 31a-31d, it is sufficient to provide at least the electrode contact region 61a, the wiring contact region 62a, and the substrate contact region 63a among the electrode contact regions 61a-61d, the wiring contact regions 62a-62d, and the substrate contact regions 63a-63d.

[0035] If the resistance value of each of the resistor layers 31a to 31d is 120Ω, connecting any one of the resistor layers 31a to 31d will result in a resistance value of 120Ω for the upper resistor chip 10a. If any three of the resistor layers 31a to 31d are connected in parallel, the resistance value of the upper resistor chip 10a will be 40Ω. If any two of the resistor layers 31a to 31d are connected in parallel, the resistance value of the upper resistor chip 10a will be 60Ω. If four resistor layers 31a to 31d are connected in parallel as shown in FIGS. 1 and 2, the resistance value of the upper resistor chip 10a will be 30Ω. In this way, the resistance value of the upper resistor chip 10a can be adjusted by increasing or decreasing the number of resistor layers 31a to 31d connected in parallel.

[0036] 2 and 3, in the resistor element according to the embodiment, the lower resistor chip 10b has the same structure as the upper resistor chip 10a and has the same resistance value as the upper resistor chip 10a. The planar pattern of the lower resistor chip 10b is not shown, but is the same as the upper resistor chip 10a shown in FIG. 1. The upper resistor chip 10a and the lower resistor chip 10b may have different numbers of resistor layers to provide different resistance values.

[0037] In the cross-sectional structure shown in Fig. 2, the lower resistor chip 10b includes a low-resistivity semiconductor substrate 11, a field insulating film (first insulating film) 12 disposed on the semiconductor substrate 11, and resistive layers 91a and 91c made of thin films disposed on the field insulating film 12. Although omitted in the cross-sectional structure of Fig. 2, two more resistive layers are disposed on the field insulating film 12, similar to the upper resistor chip 10a. In addition, as shown in Fig. 3, dummy layers 92b and 92d are disposed on the field insulating film 12.

[0038] As shown in FIG. 2, an interlayer insulating film (second insulating film) 14 is disposed so as to cover the field insulating film 12 and the resistive layers 91a and 91c. A pad-forming electrode 21 is disposed above the field insulating film 12. The left end of the pad-forming electrode 21 overlaps with one right end of the resistive layer 91a in the depth direction. The pad-forming electrode 21 is connected to one end of the resistive layer 91a via an electrode contact region 81a. The right end of the pad-forming electrode 21 overlaps with one left end of the resistive layer 91c in the depth direction. The pad-forming electrode 21 is connected to one end of the resistive layer 91c via an electrode contact region 81c.

[0039] On the interlayer insulating film 14, relay wirings 22a and 22c are arranged to surround the central pad-forming electrode (surface electrode) 21 and spaced apart from the pad-forming electrode 21. The right end of the relay wiring 22a overlaps the other end of the resistive layer 91a in the depth direction. A resistive layer connection terminal, which is one end (first end) of the relay wiring 22a, contacts the other end of the resistive layer 91a via a wiring contact region 82a. The left end of the relay wiring 22c overlaps the other end of the resistive layer 91c in the depth direction. The resistive layer connection terminal, which is one end (first end) of the relay wiring 22c, contacts the other end of the resistive layer 91c via a wiring contact region 82c. Substrate connection terminals, which are the other ends (second ends) of the relay wirings 22a and 22c, are in ohmic contact with the semiconductor substrate 11 with low contact resistance via substrate contact regions 83a and 83c.

[0040] A guard ring layer 23 is disposed on the interlayer insulating film 14. The guard ring layer 23 contacts the semiconductor substrate 1 via peripheral contact regions 84a and 84b.

[0041] A protective insulating film (third insulating film) 17 is disposed on the pad-forming electrode 21, the relay wirings 22a and 22c, and the guard ring layer 23. The protective insulating film 17 has an opening 17a that exposes a portion of the pad-forming electrode 21. A back electrode (counter electrode) 19 is disposed on the lower surface of the semiconductor substrate 11. In the lower resistor chip 10b, two resistive layers 91a and 91c and two other resistive layers not shown are connected in parallel between the pad-forming electrode 21 and the back electrode 19, and the electrical path between the pad-forming electrode 21 and the back electrode 19 serves as a resistor.

[0042] The lower resistor chip 10b further has a plating layer 72 provided on the pad-forming electrodes 21 exposed from the openings 17a of the protective insulating film 17. The plating layer 72 is made of, for example, copper (Cu), nickel (Ni), or tin (Sn). Note that if the pad-forming electrodes 21 of the lower resistor chip 10b can be bonded to bonding layers 71a to 71d (described later), the plating layer 72 does not need to be provided. The thickness of the plating layer 72 is formed to be thinner than the thickness of the protective insulating film 17.

[0043] 1 and 3, the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b are joined by bonding layers 71a to 71d. In Fig. 1, the positions of the bonding layers 71a to 71d between the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b are schematically shown by dashed lines. The bonding layers 71a to 71d are arranged spaced apart from one another.

[0044] The bonding layers 71a to 71d may be made of a conductive material such as solder, a sintered material, or an adhesive. The bonding layers 71a to 71d may be made of, for example, solder balls or bumps. The solder may be made of, for example, a tin-antimony (SnSb)-based or tin-silver (SnAg)-based material. The sintered material may be made of, for example, a silver (Ag)-based or copper (Cu)-based metal particle paste (conductive paste). The resistance of the bonding layers 71a to 71d is much smaller than the resistance of the upper resistor chip 10a and the lower resistor chip 10b, and does not affect the resistance of the resistor element according to the embodiment.

[0045] Although the bonding layers 71a to 71d are provided at four locations in this example, the number and locations of the bonding layers 71a to 71d are not particularly limited. For example, FIG. 4 is another plan view of the resistor element according to the embodiment, and FIG. 5 is a cross-sectional view taken along the line AA in FIG. 4. In FIG. 4, the location of the bonding layer 71 between the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b is schematically indicated by a broken line. As shown in FIGS. 4 and 5, the bonding layer 71 that bonds the upper resistor chip 10a and the lower resistor chip 10b may be provided at a single location in the center of the upper resistor chip 10a and the lower resistor chip 10b.

[0046] 2 and 3, an insulating layer 73 is provided between the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b. The insulating layer 73 is made of an insulating material such as a resin such as polyimide or silicone gel. The resistor element according to the embodiment does not necessarily have to have the insulating layer 73. The insulating layer 73 may be formed as part of a sealing member when the resistor element according to the embodiment is sealed together with a semiconductor chip in a semiconductor module in which the resistor element according to the embodiment is mounted.

[0047] As shown in Fig. 6, the resistance element according to the embodiment can be applied to an inverter module 100 that drives a three-phase motor consisting of, for example, a u-phase, a v-phase, and a w-phase. The inverter module 100 includes main elements TR1 to TR4 that drive the u-phase, main elements TR5 to TR8 that drive the v-phase, and main elements TR9 to TR12 that drive the w-phase. A freewheeling diode (not shown) is connected to each of the main elements TR1 to TR12. An IGBT, a MOSFET, or the like can be used for each of the main elements TR1 to TR12. To suppress oscillation during switching operation, gate resistors R1 to R12 are connected to the gate electrodes of the main elements TR1 to TR12, respectively.

[0048] The resistive element according to the embodiment can be applied to each of the gate resistors R1 to R12. For example, when the resistive element according to the embodiment is applied to the gate resistor R1, the side of the gate resistor R1 connected to the gate electrode of the main element TR1 corresponds to the terminal on the pad-forming electrode 51 side of the upper resistor chip 10a shown in Figures 1 to 3. Also, the side of the gate resistor R1 opposite to the side connected to the gate electrode of the main element TR1 corresponds to the terminal on the back electrode 19 side of the lower resistor chip 10b shown in Figures 2 and 3.

[0049] According to the resistor element of the embodiment, vertical upper resistor chip 10a and lower resistor chip 10b having the same chip size are connected in series, and the electrical path between the back electrode 9 of the upper resistor chip 10a and the pad forming electrode 21 of the lower resistor chip 10b is used as a resistor. This makes it possible to achieve high resistance while ensuring ESD tolerance without changing the mounting area in the semiconductor module. Furthermore, the resistance value can be adjusted by combining the upper resistor chip 10a and the lower resistor chip 10b, thereby improving the flexibility of the resistance value.

[0050] <Manufacturing method of resistor element> Next, an example of a method for manufacturing a resistance element according to an embodiment will be described with reference to Figures 1 to 3. Note that the method for manufacturing a resistance element described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit described in the claims.

[0051] First, an upper resistor chip 10a and a lower resistor chip 10b having the same chip size as shown in Figures 1 to 3 are prepared. Then, a plating layer 72 is formed on the pad forming electrode 21 of the lower resistor chip 10b. Alternatively, the lower resistor chip 10b may be prepared on which the plating layer 72 has been formed in advance.

[0052] Next, the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b are bonded via the bonding layers 71a-71d. For example, the bonding layers 71a-71d made of solder balls are mounted on the plating layer 72 of the lower resistor chip 10b. Subsequently, the back electrode 9 of the upper resistor chip 10a is mounted on the bonding layers 71a-71d. Subsequently, the bonding layers 71a-71d are melted by heat treatment, thereby bonding the back electrode 9 of the upper resistor chip 10a and the plating layer 72 of the lower resistor chip 10b via the bonding layers 71a-71d.

[0053] Next, a gel-like resin or the like is filled between the back electrode 9 of the upper resistor chip 10a and the plating layer 72 and protective insulating film 7 of the lower resistor chip 10b to form the insulating layer 73. This completes the resistor element according to the embodiment shown in FIGS.

[0054] <Semiconductor module> As shown in FIG. 7, a semiconductor module according to an embodiment of the present invention comprises an insulating circuit board 111, semiconductor chips 113a and 113b mounted on the insulating circuit board 111, and a laminated resistor chip 114a mounted on the insulating circuit board 111 at a distance from the semiconductor chips 113a and 113b.

[0055] The insulating circuit board 111 may be, for example, a direct copper bonding (DBC) board or an active matrix brazing (AMB) board. The insulating circuit board 111 is composed of an insulating substrate and conductor layers disposed on the upper and lower surfaces of the insulating substrate. The semiconductor chips 113a and 113b are bonded to the conductor layers on the upper surface of the insulating circuit board 111 via bonding layers 112a and 112b. The semiconductor chip 113a constitutes, for example, a free wheel diode (FWD) connected in anti-parallel to the semiconductor chip 113b. The semiconductor chip 113b constitutes, for example, an IGBT, which is a switching element.

[0056] The laminated resistor chip 114a is bonded to the conductor layer on the upper surface of the insulating circuit board 111 via a bonding layer 112c. The laminated resistor chip 114a is composed of a resistor element formed by laminating the upper resistor chip 10a and the lower resistor chip 10b shown in FIGS.

[0057] The insulating circuit board 111, semiconductor chips 113a and 113b, and multilayer resistor chip 114a are housed in a case 105. A sealing member 107 is filled inside the case 105, and the semiconductor chips 113a and 113b and multilayer resistor chip 114a are sealed therein. External terminals 106a and 106b are attached to the case 105. The insulating circuit board 111, semiconductor chips 113a and 113b, multilayer resistor chip 114a, and external terminals 106a and 106b are connected to one another via bonding wires 108.

[0058] <Semiconductor module manufacturing method> Next, a manufacturing method (assembly method) of a semiconductor module according to an embodiment of the present invention will be described with reference to Figures 7 to 10. First, as shown in Figures 8 and 9, an alignment jig 109 made of carbon or the like is mounted on an insulating circuit board 111. Subsequently, semiconductor chips 113a to 113d and multilayer resistor chips 114a and 114b are mounted in openings of the jig 109 on the insulating circuit board 111 via bonding layers 112a to 112c or the like. For example, the semiconductor chips 113a and 113d form free wheel diodes (FWDs), and the semiconductor chips 113b and 113c form IGBTs.

[0059] Because the multilayer resistor chips 114a and 114b are smaller than the semiconductor chips 113a to 113d, they are prone to tilting due to the surface tension of the bonding layers 112a to 112c after the solder melts. Therefore, as shown in FIG. 10, a jig 110 is used to fix the multilayer resistor chips 114a and 114b, and the tilt of the multilayer resistor chip 114a is suppressed by the protrusion 110a of the jig 110. FIG. 8 shows a planar pattern of the jig 110, schematically illustrated by dashed lines. For example, when the multilayer resistor chip 114a is arranged parallel to the upper surface of the insulating circuit board 111, the protrusion 110a may be spaced apart from the multilayer resistor chip 114a. The protrusion 110a of the jig 110 may be integrally formed with the jig 110 and made of carbon or the like. Alternatively, the protrusion 110a may be made of an elastic material such as rubber. Although not shown, the jig 110 also has a protrusion at a position corresponding to the laminated resistor chip 114b.

[0060] With the jig 110 in place, the insulating circuit substrate 111 is bonded to the semiconductor chips 113a-113d and the laminated resistor chips 114a, 114b via bonding layers 112a-112c, etc., by heat treatment. The bonding layers 112a-112c, etc. may be made of a material having a lower bonding temperature (melting point) than the bonding layers 71a-71d that bond the upper resistor chip 10a and lower resistor chip 10b of each of the laminated resistor chips 114a, 114b. For example, a sintered material may be used for the bonding layers 71a-71d, and solder may be used for the bonding layers 112a-112c. Then, by heating at a temperature lower than the bonding temperature (melting point) of the bonding layers 71a to 71d, the insulating circuit substrate 111 can be bonded to the semiconductor chips 113a to 113d and the laminated resistor chips 114a, 114b via the bonding layers 112a to 112c, etc., without melting the respective bonding layers 71a to 71d of the laminated resistor chips 114a, 114b.

[0061] Next, the insulating circuit board 111, semiconductor chips 113a and 113b, multilayer resistor chip 114a, and external terminals 106a and 106b are connected to one another via bonding wires 108. Subsequently, the insulating circuit board 111, semiconductor chips 113a to 113d, and multilayer resistor chips 114a and 114b are housed in a case 105 to which the external terminals 106a and 106b are attached. Subsequently, the case 105 is filled with a sealing member 107, thereby completing the semiconductor module according to the embodiment of the present invention.

[0062] Instead of mounting the stacked resistor chips 114a, 114b, in which the upper resistor chip 10a and the lower resistor chip 10b are bonded via the bonding layers 71a-71d, on the insulating circuit substrate 111, the lower resistor chip 10b, the bonding layers 71a-71d, and the upper resistor chip 10a may be sequentially mounted on the insulating circuit substrate 111 without being bonded to one another. Then, during the heat treatment for bonding the insulating circuit substrate 111 to the semiconductor chips 113a-113d and the stacked resistor chips 114a, 114b via the bonding layers 112a-112c, etc., the upper resistor chip 10a and the lower resistor chip 10b may be bonded via the bonding layers 71a-71d to form the stacked resistor chips 114a, 114b. In this case, the bonding layers 112a-112c, etc. and the bonding layers 71a-71d may be made of the same material.

[0063] Alternatively, in the above <Method for manufacturing a resistor element>, the insulating layer 73 may not be formed, and when the sealing member 107 is filled into the case 105, the insulating layer 73 may be formed by filling the sealing member 107 between the back electrode 9 of the upper resistor chip 10a and the plating layer 72 and protective insulating film 7 of the lower resistor chip 10b. Furthermore, in the above <Method for manufacturing a resistor element>, the insulating layer 73 may be formed so as to cover the joint portion between the plating layer 72 and the bonding layers 71a to 71d, which is a part between the upper resistor chip 10a and the lower resistor chip 10b, and the remaining part between the upper resistor chip 10a and the lower resistor chip 10b may be filled with the sealing member 107 filled into the case 105, thereby forming the insulating layer 73.

[0064] <First Modification> 11 and 12, a resistor element according to a first modified example of the embodiment of the present invention differs from the resistor element according to the embodiment shown in Figures 1 to 3 in that three resistor layers 31a, 31b, and 31d of the four resistor layers 31a to 31d of the upper resistor chip 10a are selectively used for parallel connection. The resistor element according to the first modified example does not have the electrode contact region 61c connecting the pad forming electrode 51 and the resistor layer 31c, the wiring contact region 62c connecting the resistor layer 31c and the relay wiring 52c, and the substrate contact region 63c connecting the relay wiring 52c and the semiconductor substrate 1 shown in Figures 1 and 2.

[0065] 12 also has a similar structure to the upper resistor chip 10a, and does not include an electrode contact region 81c connecting the pad-forming electrode 21 and the resistive layer 91c, a wiring contact region 82c connecting the resistive layer 91c and the relay wiring 22c, and a substrate contact region 83c connecting the relay wiring 82c and the semiconductor substrate 11. The other configurations of the resistive element according to the first modified example are the same as those of the resistive element according to the embodiment shown in FIGS. 1 to 3, and therefore redundant explanations will be omitted.

[0066] According to the resistance element of the first modified example, the resistance value of the resistance element of the first modified example can be increased by reducing the number of parallel connections of the resistance layers 31a, 31b, 31d, etc., compared to the resistance element of the embodiment shown in Figures 1 to 3.

[0067] <Second Modification> 13 and 14, a resistor element according to a second modified example of the embodiment of the present invention is similar to the resistor element according to the first modified example shown in Figures 11 and 12 in that three resistor layers 31a, 31b, and 31d of the four resistor layers 31a to 31d of the upper resistor chip 10a are selectively used and connected in parallel. However, the resistor element according to the second modified example is different from the resistor element according to the first modified example shown in Figures 11 and 12 in that only the electrode contact region 61c connecting the pad-forming electrode 51 and the resistor layer 31c shown in Figures 1 and 2 is not provided, but a wiring contact region 62c connecting the resistor layer 31c and the relay wiring 52c and a substrate contact region 63c connecting the relay wiring 52c and the semiconductor substrate 1 are provided.

[0068] 14 also has a similar structure to the upper resistor chip 10a, and does not include the electrode contact region 81c connecting the pad-forming electrode 21 and the resistive layer 91c shown in Fig. 2, but does include a wiring contact region 82c connecting the resistive layer 21c and the relay wiring 22c and a substrate contact region 83c connecting the relay wiring 22c and the semiconductor substrate 11. The other configurations of the resistive element according to the second modification are the same as those of the resistive element according to the first modification shown in Figs. 11 and 12, and therefore redundant explanations will be omitted.

[0069] According to the resistor element of the second modification, even if only the electrode contact regions 61c, 81c are not provided, the resistive layers 31c, 91c can be unused. Even if the electrode contact regions 61c, 81c are provided, the resistive layers 31c, 91c can be unused if the wiring contact regions 62c, 82c or the substrate contact regions 63c, 83c are not provided. That is, by omitting at least one of the electrode contact regions 61c, 81c, the wiring contact regions 62c, 82c, and the substrate contact regions 63c, 83c, the resistive layers 31c, 91c can be unused.

[0070] <Third Modification> As shown in FIG. 15, the resistor element according to the third modification of the embodiment of the present invention differs from the resistor element according to the embodiment shown in FIGS. 1 to 3 in that the width W1 of the resistor layers 31a and 31c of the upper resistor chip 10a is different from the width W2 of the resistor layers 31b and 31d. Because the width W1 of the resistor layers 31a and 31c is smaller than the width W2 of the resistor layers 31b and 31d, the resistance values of the resistor layers 31a and 31c are larger than the resistance values of the resistor layers 31b and 31d. Although not shown in FIG. 15, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. Other configurations of the resistor element according to the third modification are similar to those of the resistor element according to the embodiment shown in FIGS. 1 to 3, and therefore, redundant description will be omitted.

[0071] In the resistive element according to the third modification, the width W1 of the resistive layers 31a and 31c is made different from the width W2 of the resistive layers 31b and 31d, thereby making the resistance values of the resistive layers 31a and 31c different from the resistance values of the resistive layers 31b and 31d. Therefore, when selectively using the resistive layers 31a to 31d, the degree of freedom in selecting the resistance value of the resistive element according to the third modification is improved. While the resistive element according to the third modification illustrates a case in which the resistance values of the two resistive layers 31a and 31c are made different from the resistance values of the two resistive layers 31b and 31d, this is not limiting. For example, the resistance values of the four resistive layers 31a to 31d may be made different from each other by making the widths of the four resistive layers 31a to 31d different from each other.

[0072] <Fourth Modification> As shown in FIG. 16, the resistor element according to the fourth modification of the embodiment of the present invention differs from the resistor element according to the embodiment shown in FIGS. 1 to 3 in that two resistor layers 31a and 31b of the upper resistor chip 10a are arranged facing each other with a pad-forming electrode 51 sandwiched therebetween. The planar patterns of the resistor layers 31a and 31b, the pad-forming electrode 51, and the relay wirings 52a and 52b are two-fold rotationally symmetric with respect to the center O of the chip. This allows the resistor element according to the embodiment to be rotated 180° when mounted, facilitating assembly. Although not shown in FIG. 16, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. Other configurations of the resistor element according to the fourth modification are similar to those of the resistor element according to the embodiment shown in FIGS. 1 to 3, and therefore, redundant description will be omitted.

[0073] According to the resistive element of the fourth modified example, even when two resistive layers 31a, 31b are provided, some or all of the resistive layers 31a, 31b can be selectively used by changing the presence or absence of electrode contact regions 61a, 61b, wiring contact regions 62a, 62b, and substrate contact regions 63a, 63b.

[0074] <Fifth Modification> 17, the resistor element according to the fifth modified embodiment of the present invention differs from the resistor element according to the embodiment shown in FIGS. 1 to 3 in that a plurality of (three) resistor layers 31a to 31c are provided on one side of the rectangular planar pattern of the pad formation electrode 51 of the upper resistor chip 10a. Although not shown in FIG. 17, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. The other configurations of the resistor element according to the fifth modified embodiment are similar to those of the resistor element according to the embodiment shown in FIGS. 1 to 3, and therefore redundant explanations will be omitted.

[0075] According to the resistive element of the fifth modified example, even when three resistive layers 31a to 31c are provided on one side of the rectangular planar pattern of the pad-forming electrode 51, some or all of the resistive layers 31a to 31c can be selectively used by changing the presence or absence of the electrode contact regions 61a to 61c, the wiring contact regions 62a to 62c, and the substrate contact regions 63a to 63c.

[0076] <Sixth Modification> As shown in Figures 18 and 19, the resistor element according to the sixth variant of the embodiment of the present invention differs from the resistor element according to the embodiment shown in Figures 1 to 3 in that multiple (two) pad forming electrodes 51a, 51b of the upper resistor chip 10a are arranged spaced apart from each other, and resistor layers 31a to 31f are provided between the pad forming electrodes 51a, 51b.

[0077] The pad-forming electrode 51a is connected to one end of the resistance layers 31a to 31c via electrode contact regions 61a to 61c. The other end of the resistance layers 31a to 31c is connected to relay wirings 52a to 52c via wiring contact regions 62a to 62c. The pad-forming electrode 51b is connected to one end of the resistance layers 31d to 31f via electrode contact regions 61d to 61f. The other end of the resistance layers 31d to 31f is connected to relay wirings 52a to 52c via wiring contact regions 62d to 62f.

[0078] The relay wirings 52a-52c are connected to the semiconductor substrate 1 via the substrate contact regions 63a-63c. A contact region 1a and a peripheral contact region 1b, which have a higher impurity concentration (lower resistivity) than the semiconductor substrate 1 and are of the same conductivity type as the semiconductor substrate 1, are provided on the upper part of the semiconductor substrate 1 at the contact points between the substrate contact regions 63a-63c and the semiconductor substrate 1. The contact region 1a and the peripheral contact region 1b may also be provided in other examples of the embodiment.

[0079] The lower resistor chip 10b shown in FIG. 19 has a similar structure to the upper resistor chip 10a. The lower resistor chip 10b also has a plurality (two) of pad-forming electrodes 21a, 21b spaced apart from each other, and resistor layers 91b, 91e are provided between the pad-forming electrodes 51a, 51b. One end of the resistor layer 91b is connected to the pad-forming electrode 21a via an electrode contact region 81b. The other end of the resistor layer 91b is connected to a relay wiring 22b via a wiring contact region 82b. One end of the resistor layer 91e is connected to the pad-forming electrode 21b via an electrode contact region 81e. The other end of the resistor layer 91e is connected to the relay wiring 22b via a wiring contact region 82e.

[0080] The relay wiring 22b is connected to the semiconductor substrate 11 via a substrate contact region 83b. A contact region 11a and a peripheral contact region 11b are provided on the upper part of the semiconductor substrate 11, which are contact points between the substrate contact regions 83a to 83c and the semiconductor substrate 11. Plating layers 72a and 72b are disposed on the pad forming electrodes 21a and 21b, respectively. The plating layers 72a and 72b are bonded to the back surface electrode 9 of the upper resistor chip 10a by bonding layers 71a and 71b.

[0081] The resistance element according to the sixth modification can be applied to, for example, the pair of gate resistors R1 and R2 in Fig. 6. Other configurations of the resistance element according to the sixth modification are similar to those of the resistance element according to the embodiment shown in Figs. 1 to 3, and therefore redundant explanations will be omitted.

[0082] According to the resistive element of the sixth modified example, even when multiple (two) pad-forming electrodes 51a, 51b, etc. are provided, some or all of the resistive layers 31a-31f, etc. can be selectively used by changing the presence or absence of electrode contact regions 61a-61f, wiring contact regions 62a-62f, and substrate contact regions 63a-63f, etc.

[0083] <Seventh Modification> As shown in FIG. 20 , the resistor element according to the seventh modification of the embodiment of the present invention differs from the resistor element according to the embodiment shown in FIGS. 1 to 3 in that it includes auxiliary pads 65a to 65d electrically connected to the relay wirings 63a to 63d of the upper resistor chip 10a. In FIG. 20 , the protective insulating film is omitted, and only the openings 7b to 7e of the protective insulating film are indicated by dashed lines. The auxiliary pads 65a to 65d are exposed through the openings 7b to 7e of the protective insulating film. The auxiliary pads 65a to 65d are made of the same material as the relay wirings 63a to 63d and can be formed simultaneously when forming the relay wirings 63a to 63d. Although not shown in FIG. 20 , the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. Other configurations of the resistor element according to the seventh modification are similar to those of the resistor element according to the embodiment shown in FIGS. 1 to 3 , and therefore, redundant description will be omitted.

[0084] 21 shows an equivalent circuit of the upper resistor chip 10a. In FIG. 21, the pad forming electrode 51 corresponds to the pad side terminal 101, the back surface electrode 9 corresponds to the back surface side terminal 102, and the auxiliary pads 65a to 65d correspond to the auxiliary terminals 103a to 103d. Between the pad side terminal 101 and the back surface side terminal 102, there are parallel-connected resistors R poly1 ~R poly4 and the resistance R of the semiconductor substrate 1 sub The auxiliary terminals 103a to 103d are connected in series with the resistors R corresponding to the resistor layers 31a to 31d. poly1 ~R poly4 and the resistance R of the semiconductor substrate 1 sub and .

[0085] According to the resistance element of the seventh modification, by arranging the auxiliary pads 65a to 65d, the resistance R of the semiconductor substrate 1 is sub The resistance R corresponding to the resistance layers 31a to 31d excluding the component poly1 ~R poly4 The electrical properties of the material can be measured.

[0086] <Eighth Modification> The resistance element according to the eighth variant of the embodiment of the present invention differs from the resistance element according to the embodiment shown in Figures 1 to 3 in that, as shown in Figures 22 and 23, an auxiliary film 33 that is spaced apart from the resistance layers 31a to 31d and is in a floating state in terms of potential is arranged on the field insulating film 2 of the upper resistor chip 10a.

[0087] The auxiliary film 33 is disposed below the pad-forming electrode 51 and spaced apart from the resistive layers 31a-31d. The auxiliary film 33 is made of the same material as the resistive layers 31a-31d, such as n-type DOPOS, and has the same thickness as the resistive layers 31a-31d. The auxiliary film 33 has, for example, a rectangular planar pattern.

[0088] The lower resistor chip 10b shown in Fig. 23 has a structure similar to that of the upper resistor chip 10a. In the cross section shown in Fig. 23, an auxiliary film 93 that is spaced apart from the resistive layers 91a and 91c and is in a floating state in terms of potential is disposed on the field insulating film 12 of the lower resistor chip 10b. The other configurations of the resistive element according to the eighth modification are similar to those of the resistive element according to the embodiment shown in Fig. 1, and therefore, redundant explanations will be omitted.

[0089] According to the resistor element of the eighth modification, by disposing the auxiliary films 33, 93, which are in a floating state in terms of potential, on the field insulating films 2, 12, it is possible to reduce the parasitic capacitance below the pad-forming electrodes 21, 51, in the same way as in the case of increasing the thickness of the field insulating films 2, 12. This makes it possible to suppress the reduction in total resistance due to a drop in impedance during high-frequency operation, and to suppress the oscillation phenomenon.

[0090] <Ninth Variation> As shown in Fig. 24, the resistor element according to the ninth modified example of the embodiment of the present invention differs from the resistor element according to the embodiment shown in Figs. 1 to 3 in that the resistor element further includes resistive layers 34a-34h and relay wirings 54a-54h of the upper resistor chip 10a. The resistive layers 34a and 34b are arranged to sandwich the resistive layer 31a. The resistive layers 34c and 34d are arranged to sandwich the resistive layer 31b. The resistive layers 34e and 34f are arranged to sandwich the resistive layer 31c. The resistive layers 34g and 34h are arranged to sandwich the resistive layer 31d.

[0091] The relay wirings 54a and 54b are arranged to sandwich the relay wiring 52a. The relay wirings 54c and 54d are arranged to sandwich the relay wiring 52b. The relay wirings 54e and 54f are arranged to sandwich the relay wiring 52c. The relay wirings 54g and 54h are arranged to sandwich the relay wiring 52d. Although not shown in FIG. 24, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. The other configurations of the resistor element according to the ninth modification are similar to those of the resistor element according to the embodiment shown in FIGS. 1 to 3, and therefore redundant description will be omitted.

[0092] According to the resistive element of the ninth modification, by changing the presence or absence of electrode contact regions, wiring contact regions, and substrate contact regions for connecting the resistive layers 34a to 34h in parallel, it is possible to increase or decrease the number of parallel connections of the resistive layers 31a to 31d as well as the number of parallel connections of the resistive layers 34a to 34h, thereby making it possible to more precisely adjust the resistance value of the resistive element of the ninth modification. As with the resistive element of the ninth modification, the number and arrangement positions of the resistive layers are not limited and can be set appropriately.

[0093] <Tenth Modification> 25, the resistive element according to the tenth modified example of the embodiment of the present invention differs from the resistive element according to the embodiment shown in FIGS. 1 to 3 in that protrusions 51x to 51z are provided on one side of the rectangular planar pattern of the pad-forming electrode 51 of the upper resistor chip 10a. The protrusions 51x to 51z are connected to one end of the resistive layers 31a to 31c via electrode contact regions 61a to 61c, respectively. The other end of the resistive layers 31a to 31c are connected to relay wires 52a to 52c via wiring contact regions 62a to 62c, respectively. The relay wires 52a to 52c are connected to the semiconductor substrate 1 via substrate contact regions 63a to 63c, respectively.

[0094] In the resistor element according to the tenth modification, three resistor layers 31a-31c are connected in parallel. Therefore, as shown by arrows in FIG. 25, first current paths I1-I3 are formed, through which current flows from the convex portions 51x-51z of the pad-forming electrode 51 to the semiconductor substrate 1 via the resistor layers 31a-31c and the relay wirings 52a-52c. Although not shown in FIG. 25, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a similar structure to the upper resistor chip 10a. Other configurations of the resistor element according to the tenth modification are similar to those of the resistor element according to the embodiment shown in FIGS. 1-3, and therefore, redundant description will be omitted.

[0095] According to the resistive element of the tenth modification, when three resistive layers 31a to 31c are provided, some or all of the resistive layers 31a to 31c can be selectively used by changing the presence or absence of electrode contact regions 61a to 61c, wiring contact regions 62a to 62c, and substrate contact regions 63a to 63c.

[0096] <Eleventh Modification> As shown in FIG. 26, the resistor element according to the eleventh modification of the embodiment of the present invention differs from the resistor element according to the tenth modification shown in FIG. 25 in that the protrusions 51x and 51z are separated from the pad-forming electrode 51 of the upper resistor chip 10a. In the upper resistor chip 10a, a current path I1 is formed through which a current flows from the protrusion 51y of the pad-forming electrode 51 to the semiconductor substrate 1 via the resistive layer 31b and the relay wiring 52b. Although not shown in FIG. 26, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. Other configurations of the resistor element according to the eleventh modification are similar to those of the resistor element according to the tenth modification shown in FIG. 25, and therefore, redundant description will be omitted.

[0097] According to the resistive element of the eleventh variant, even if the presence or absence of the electrode contact regions 61a to 61c, the wiring contact regions 62a to 62c, and the substrate contact regions 63a to 63c remains unchanged, by selectively separating the convex portions 51x to 51z from the pad-forming electrode 51, it is possible to selectively use part or all of the resistive layers 31a to 31c.

[0098] <Twelfth Modification> As shown in Fig. 27, a resistor element according to a twelfth modification of the embodiment of the present invention differs from the resistor element according to the tenth modification shown in Fig. 25 in that a plurality (three) of resistor layers 31a-31c of an upper resistor chip 10a are connected in series. The resistor element according to the twelfth modification includes an inter-resistor wiring 55a at the positions where the convex portions 51x and 51y shown in Fig. 25 are to be arranged, and an inter-resistor wiring 55b at the positions where the relay wirings 52b and 52c shown in Fig. 25 are to be arranged. The inter-resistor wiring 55a is connected to the resistor layers 31b and 31c via wiring contact regions 62b and 62c. The inter-resistor wiring 55b is connected to the resistor layers 31a and 31b via electrode contact regions 61a and 61b.

[0099] In the resistor element according to the twelfth modification, as shown by the arrows in Fig. 27, a first current path I1 is formed through which a current flows from the protrusion 51z of the pad-forming electrode 51 to the semiconductor substrate 1 via the resistor layer 31c, the inter-resistor wiring 55a, the resistor layer 31b, the inter-resistor wiring 55b, the resistor layer 31c, and the relay wiring 52a. Although not shown in Fig. 27, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. Other configurations of the resistor element according to the twelfth modification are similar to those of the resistor element according to the tenth modification shown in Fig. 25, and therefore redundant description will be omitted.

[0100] In the resistive element according to the twelfth modification, the inter-resistor wirings 55a and 55b are arranged to connect the plurality of resistive layers 31a to 31c in series, thereby increasing the resistance value.

[0101] <13th Modification> As shown in Fig. 28, a resistor element according to a thirteenth modified example of the embodiment of the present invention differs from the resistor element according to the tenth modified example shown in Fig. 25 in that a plurality of (two) resistor layers 31a, 31c of the upper resistor chip 10a are connected in series. The upper resistor chip 10a has an inter-resistor wiring 55 at a position where the convex portions 51x, 51y and the relay wirings 52b, 52c shown in Fig. 25 are arranged. The inter-resistor wiring 55 is connected to the resistor layer 31a via an electrode contact region 61a, and is connected to the resistor layer 31c via a wiring contact region 62c.

[0102] In the resistor element according to the thirteenth modification, as shown by the arrows in Fig. 28, a first current path I1 is formed through which a current flows from the convex portion 51z of the pad-forming electrode 51 to the semiconductor substrate 1 via the resistor layer 31c, the inter-resistor wiring 55, the resistor layer 31a, and the relay wiring 52a. Although not shown in Fig. 28, the lower resistor chip 10b stacked below the upper resistor chip 10a also has a structure similar to that of the upper resistor chip 10a. The other configuration of the resistor element according to the twelfth modification is similar to that of the resistor element according to the tenth modification shown in Fig. 25, and therefore a redundant description will be omitted.

[0103] According to the resistive element of the thirteenth variant, by arranging the inter-resistor wiring 55, it is possible to connect multiple resistive layers 31a, 31c in series while avoiding substrate contact near the pad forming electrode 51, thereby increasing the resistance value.

[0104] <14th Modification> 29, the resistor element according to the fourteenth modification of the embodiment of the present invention differs from the resistor element according to the embodiment in that an upper resistor chip 10a of the resistor element according to the embodiment shown in FIG. 2 and a lower resistor chip 10b of the resistor element according to the first modification shown in FIG. 12 are stacked. The upper resistor chip 10a and the lower resistor chip 10b have the same chip size, but have different structures and resistance values. The other configurations of the resistor element according to the fourteenth modification are the same as those of the resistor element according to the embodiment, so redundant explanations will be omitted.

[0105] According to the resistive element of the fourteenth modification, the upper resistor chip 10a and the lower resistor chip 10b having different resistance values are stacked, thereby improving the flexibility of the resistance value. Note that it is also possible to stack one of the upper resistor chip 10a and the lower resistor chip 10b of any of the resistive elements according to the embodiment of the present invention and the first to thirteenth modifications together to form a resistor. Furthermore, in the resistive elements according to the embodiment of the present invention and the first to thirteenth modifications, the upper resistor chip 10a and the lower resistor chip 10b may have different numbers of resistive layers to achieve different resistance values.

[0106] (Other embodiments) As described above, the present invention has been described by way of the embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art.

[0107] 6, the resistive element according to the embodiment is applied to the gate resistors R1 to R12, but the application is not limited to the gate resistors R1 to R12. The resistive element according to the embodiment can be applied as a resistive element for various ICs.

[0108] Furthermore, in the resistive element according to the embodiment, two (two levels) upper resistor chips 10a and two (two levels) lower resistor chips 10b are stacked, but three (three levels) or more resistor chips may be stacked. In this case, the electrical path between the pad forming electrode of the uppermost resistor chip and the back electrode of the lowermost resistor chip is used as the resistor. Increasing the number of stacked resistor chips can achieve higher resistance.

[0109] Furthermore, in the resistor element of the embodiment, the upper resistor chip 10a and the lower resistor chip 10b each have multiple resistor layers, but one or both of the upper resistor chip 10a and the lower resistor chip 10b may have only one resistor layer. [Explanation of symbols]

[0110] 1, 11...Semiconductor substrate 1a, 11a...contact area 1b, 11b...peripheral contact area 2, 12...Field insulating film (first insulating film) 4, 14...Interlayer insulating film (second insulating film) 7, 17...Protective insulating film (third insulating film) 7a~7e,17a...opening 9, 19...Back electrode (counter electrode) 10a, 10b...Resistor chip 21, 21a, 21b, 51, 51a, 51b...Pad forming electrodes (surface electrodes) 22a, 22c, 52a-52d, 54a-54h, 63a-63d...Relay wiring 23,53...Girder ring layer 31a~31f, 34a~34h, 91a~91c, 91e...resistance layer 32a~32h, 92a, 92c...Dummy layer 33,93…Auxiliary membrane 51x~51z...Convex part 55, 55a, 54b...Wiring between resistors 61a to 61f, 81a, 81c...electrode contact areas 62a to 62f, 82a, 82c...wiring contact areas 63a to 63f, 83a, 83c...Substrate contact area 64a, 64b, 84a, 84b...peripheral contact area 65a~65d...Auxiliary pad 71,71a~71d...Joining layer 72, 72a, 72b...plated layer 73...insulating layer 74...Bonding wire 100...Inverter module 101...Pad side terminal 102...Back side terminal 103a~103d...Auxiliary terminals 105…Case 106a, 106b...External terminals 107...Sealing member 108...Bonding wire 109,110...Jig 110a...Convex part 111...Insulated circuit board 112a~112c...Joining layer 113a to 113d...Semiconductor chips 114a, 114b... multilayer resistor chip

Claims

1. a semiconductor substrate; a field insulating film provided on the semiconductor substrate; a resistive layer provided on the field insulating film; an interlayer insulating film provided to cover the field insulating film and the resistive layer; a pad-forming electrode provided on the interlayer insulating film and electrically connected to one end of the resistance layer; a relay wiring provided on the interlayer insulating film and spaced apart from the pad-forming electrode, the relay wiring having one terminal electrically connected to the other end of the resistive layer and the other terminal in ohmic contact with the semiconductor substrate; a backside electrode provided under the semiconductor substrate and in ohmic contact with the semiconductor substrate; a plurality of resistor chips each having the same chip size are stacked, the resistive layers of the plurality of resistor chips are connected in series, and an electrical path between the pad forming electrode of the resistor chip in the top row and the back electrode of the resistor chip in the bottom row is used as a resistor.

2. the resistor chips below the uppermost resistor chip further include a plating layer provided on the pad-forming electrode, The back electrode of the upper resistor chip and the plating layer of the lower resistor chip are joined by a joining layer.

2. The resistor element according to claim 1.

3. 3. The resistor element according to claim 2, wherein the bonding layer is provided at a plurality of locations spaced apart from one another.

4. 3. The resistor element according to claim 2, wherein the bonding layer is provided at the center of the planar patterns of the resistor chips on the upper and lower levels.

5. A resistor element described in any one of claims 2 to 4, characterized in that it further comprises an insulating layer provided in contact with the bonding layer between the back electrode of the upper resistor chip and the plating layer of the lower resistor chip.

6. 6. The resistor element according to claim 1, wherein the plurality of resistor chips have the same structure.

7. 6. The resistor element according to claim 1, wherein the plurality of resistor chips have different resistance values.

8. Each of the resistor chips further includes a protective insulating film provided on the pad forming electrode, the relay wiring, and the interlayer insulating film.

8. The resistor element according to claim 1, wherein the resistance element is a resistance element having a thickness of 100 nm or less.

9. a step of preparing a plurality of resistor chips each having the same chip size, the resistor chips each including: a semiconductor substrate; a field insulating film provided on the semiconductor substrate; a resistive layer provided on the field insulating film; an interlayer insulating film provided so as to cover the field insulating film and the resistive layer; a pad forming electrode provided on the interlayer insulating film and electrically connected to one end of the resistive layer; relay wiring provided on the interlayer insulating film and spaced apart from the pad forming electrode, the relay wiring having one terminal electrically connected to the other end of the resistive layer and the other terminal in ohmic contact with the semiconductor substrate; and a back surface electrode provided below the semiconductor substrate and in ohmic contact with the semiconductor substrate; a step of stacking the plurality of resistor chips and connecting the resistance layers of the plurality of resistor chips in series, and forming an electrical path between the pad forming electrode of the uppermost resistor chip and the back surface electrode of the lowermost resistor chip as a resistor; A method for manufacturing a resistor element, comprising:

10. The step of stacking the plurality of resistor chips includes: forming a plating layer on the pad forming electrode of the resistor chip below the resistor chip in the uppermost row; a bonding step of bonding the back electrode of the upper resistor chip to the plating layer of the lower resistor chip with a bonding layer; 10. The method for manufacturing a resistor element according to claim 9, further comprising:

11. each of the resistor chips includes a pad forming electrode, a relay wiring, and a protective insulating film provided on the interlayer insulating film; a step of forming an insulating layer by filling a sealing material between the back surface electrode of the upper resistor chip and the protective insulating film and the plating layer of the lower resistor chip after the bonding step.

11. The method for manufacturing a resistance element according to claim 10, further comprising:

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