Semiconductor devices, semiconductor device arrays, and wafers

Abstract

To provide such a novel enhanced semiconductor element as to be capable of more easily, more surely or more accurately executing e.g., segmentation of a plurality of semiconductor element parts from a wafer, a semiconductor element array, and the wafer.SOLUTION: A semiconductor element comprises: a body including a substrate, a plurality of semiconductor layers laminated on the substrate in a first direction, an end face in the first direction, and an edge constituting a peripheral edge in a view in an opposite direction of the first direction; an insulation layer covering the end face; an electrode provided at an opposite side to the substrate with respect to the end face; and at least one wire electrically connected with the electrode and extending between the electrode and the edge. A non-formation region of the insulation layer is provided along the edge on the end face, and the insulation layer includes an interposing portion interposed between the end face and the wire at a position displaced from the non-formation region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, semiconductor device arrays, and wafers. [Background technology]

[0002] Conventionally, a technique for manufacturing a plurality of optical semiconductor elements by stacking semiconductor layers, conductor layers, etc. on a wafer to form a plurality of optical semiconductor element portions and then cutting the plurality of optical semiconductor element portions out of the wafer has been known (for example, Patent Document 1).

[0003] In Patent Document 1, adjacent electrodes on a wafer are electrically connected by wiring (conducting wires). This prevents variations in electrode thickness (individual differences) caused by potential differences between different parts when forming electrodes on each optical semiconductor element by electrolytic plating during the manufacturing process of the optical semiconductor element. An insulating layer such as a dielectric layer is provided between the top surface of the semiconductor layer and the wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-139996 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if an insulating layer is provided so as to straddle the boundaries of multiple optical semiconductor element portions on a wafer, the insulating layer may become an obstacle, and there is a risk of undesirable phenomena occurring, such as making it difficult to cut out the optical semiconductor element portions from the wafer, making the cut end faces of the optical semiconductor elements including the active layers more likely to become rough, etc. Furthermore, similar undesirable phenomena can also occur in semiconductor elements other than optical semiconductor elements.

[0006] Therefore, one object of the present invention is to provide new and improved semiconductor elements, semiconductor element arrays, and wafers that, for example, allow for easier, more reliable, or more accurate cutting of multiple semiconductor element portions from a wafer. [Means for solving the problem]

[0007] The semiconductor element of the present invention comprises, for example, a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, a body including an end face in the first direction, and an edge that forms a periphery when viewed in the opposite direction to the first direction, an insulating layer covering the end face, an electrode provided on the side opposite the substrate with respect to the end face, and at least one wiring that is electrically connected to the electrode and extends between the electrode and the edge, wherein a non-formation area of ​​the insulating layer is provided along the edge of the end face, and the insulating layer has an intervening portion interposed between the end face and the wiring at a position offset from the non-formation area.

[0008] The semiconductor element may be configured as an optical semiconductor element including an active layer as the semiconductor layer and the electrode for supplying a current to the active layer.

[0009] The semiconductor element may include a plurality of wirings as the wiring, and the wirings may include a first wiring provided on the non-forming region and a second wiring provided on the intervening portion.

[0010] The semiconductor element may have a first electrode and a second electrode having different polarities as the electrodes, the first wiring being electrically connected to the first electrode, and the second wiring being electrically connected to the second electrode.

[0011] In the semiconductor element, the second electrode may be electrically connected to the substrate.

[0012] The semiconductor element has, as the edges, a first edge located in front and behind a second direction intersecting with the first direction, and a second edge located in front and behind a third direction intersecting with the first direction and the second direction, and as the wiring, the semiconductor element may have wiring extending between the electrode and the first edge, but may not have wiring extending between the electrode and the second edge.

[0013] The semiconductor element may include a third wiring that is not electrically connected to the electrode and extends between the first edge and the second edge.

[0014] The semiconductor element of the present invention comprises, for example, a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, a body including an end face in the first direction and an edge that forms a periphery when viewed in the opposite direction to the first direction, an insulating layer covering the end face, an electrode provided on the end face, and at least one wiring electrically connected to the electrode and extending between the electrode and the edge, wherein the end face has an area where the insulating layer is not formed along the edge, and the edges include a first edge located in front and behind a second direction that intersects with the first direction, and a second edge located in front and behind a third direction that intersects with the first direction and the second direction, and the wiring includes a wiring extending between the electrode and the first edge, but does not include a wiring extending between the electrode and the second edge.

[0015] The semiconductor element array of the present invention is a semiconductor element array comprising, for example, a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, a body including an end face in the first direction, and a first edge located in front and behind a second direction intersecting the first direction when viewed in the opposite direction to the first direction, an insulating layer covering the end face, a plurality of electrodes provided on the end face, and at least one wiring electrically connected to the electrode and extending between the electrode and the first edge, and comprising a plurality of semiconductor element portions arranged in a third direction intersecting the first direction and the second direction, wherein, when viewed in the opposite direction to the first direction, a non-formation region of the insulating layer is provided along the first edge, and the insulating layer has an intervening portion interposed between the end face and the wiring at a position offset from the non-formation region.

[0016] In the semiconductor element array, the plurality of semiconductor element portions may have substantially the same configuration.

[0017] The semiconductor element array may include two first wirings as the wirings, the two first wirings extending between each of the electrodes adjacent to each other in the second direction and one of the first edges at the front and rear in the second direction and aligned at a distance in the third direction; and a fourth wiring located at the other first edge at the front and rear in the second direction and having two ends aligned at a distance in the third direction, extending between the two ends via a position away from the other first edge and aligned at a distance from the two first wirings in the second direction.

[0018] In the semiconductor element array, each of the semiconductor element sections may be configured as an optical semiconductor element section having an active layer as the semiconductor layer and the electrode for supplying a current to the active layer.

[0019] The wafer of the present invention is, for example, a wafer having a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, an end face in the first direction, and a plurality of semiconductor element portions arranged in a matrix in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction, wherein the semiconductor element portions cut out from the wafer are configured to become the semiconductor element or the semiconductor element array, and the plurality of electrodes as the electrodes are electrically connected via the wiring.

[0020] In the wafer, the semiconductor element portions may each be configured as an optical semiconductor element portion having an active layer as the semiconductor layer and the electrode for supplying a current to the active layer. [Effects of the Invention]

[0021] In accordance with the present invention, new and improved semiconductor devices, semiconductor device arrays, and wafers are provided. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is an exemplary schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is an exemplary schematic plan view showing a wafer on which a semiconductor element portion that will become the semiconductor element of the first embodiment is formed, and a part of the wafer. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is an exemplary schematic plan view of the semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is an exemplary schematic plan view of a portion of a wafer according to the third embodiment. [Figure 7] FIG. 7 is an exemplary schematic plan view of a semiconductor device according to the fourth embodiment. [Figure 8] FIG. 8 is an exemplary schematic plan view of a semiconductor device according to the fifth embodiment. [Figure 9] FIG. 9 is an exemplary schematic plan view of a semiconductor device according to the sixth embodiment. [Figure 10] FIG. 10 is an exemplary schematic plan view of a portion of a wafer according to the seventh embodiment. [Figure 11] FIG. 11 is an exemplary schematic plan view of part XI in FIG. [Figure 12] FIG. 12 is an exemplary schematic plan view of a semiconductor element array cut out from a wafer according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0023] Exemplary embodiments of the present invention are disclosed below. The configurations of the embodiments described below, as well as the actions and results (effects) brought about by the configurations, are merely examples. The present invention can also be realized by configurations other than those disclosed in the following embodiments. Furthermore, according to the present invention, it is possible to obtain at least one of the various effects (including derivative effects) obtained by the configurations.

[0024] The following embodiments have similar configurations. Therefore, according to the configurations of each embodiment, similar actions and effects based on the similar configurations can be obtained. Furthermore, in the following, similar configurations are given similar reference numerals, and duplicated descriptions may be omitted.

[0025] In this specification, ordinal numbers are given for convenience to distinguish directions, members, parts, etc., and do not indicate priority or order.

[0026] In each figure, the X direction is represented by an arrow X, the Y direction is represented by an arrow Y, and the Z direction is represented by an arrow Z. The X direction, Y direction, and Z direction intersect with each other and are perpendicular to each other. In the following, the X direction will be referred to as the longitudinal direction or extension direction, the Y direction will be referred to as the lateral direction or width direction, and the Z direction will be referred to as the stacking direction or height direction.

[0027] Furthermore, each figure is a schematic diagram for the purpose of explanation, and the scale and ratio of each figure do not necessarily match those of the actual product.

[0028] [First embodiment] Fig. 1 is a plan view of the semiconductor device 100A (100) of the first embodiment, and Fig. 2 is a cross-sectional view taken along II-II in Fig. 1. The semiconductor device 100A is configured as, for example, a known semiconductor optical amplifier.

[0029] As shown in Figures 1 and 2, the semiconductor element 100A includes a body 11 including a substrate 10 and a plurality of semiconductor layers, an insulating layer 12 and electrodes 31, 32 formed on the body 11, and conductor layers 41, 42 electrically connected to the electrodes 31, 32.

[0030] A second layer 20c serving as an active layer extending in the X direction is also included within the body 11. The second layer 20c extends substantially along the X direction at a substantially fixed position in the Z direction, with a predetermined width in the Y direction and a predetermined height in the Z direction.

[0031] As shown in Fig. 2, the substrate 10 has a substantially constant thickness in the Z direction and extends in a direction intersecting the Z direction. As shown in Fig. 2, the substrate 10 has a surface 10a and a surface 10b. The surface 10a faces the Z direction and intersects the Z direction. The surface 10b is located on the opposite side of the surface 10a, faces the opposite direction to the Z direction, and intersects the Z direction. The substrate 10 is made of, for example, n-InP.

[0032] In the body 11, a plurality of semiconductor layers, such as a first layer 20b to a third layer 20d, current blocking layers 20e and 20f, and a cladding layer 20g, are stacked in the Z direction on the surface 10a of the substrate 10. The Z direction is an example of a first direction.

[0033] The body 11 also has a mesa 21 including a first layer 20b to a third layer 20d. As described above, the second layer 20c included in the mesa 21 is an active layer and functions as an optical waveguide. The body 11 has a buried waveguide structure (BH waveguide structure).

[0034] The first layer 20b is made of, for example, n-InP, and functions as a cladding layer in the mesa 21.

[0035] The second layer 20c has a layered structure containing, for example, n-InGaAsP, and is a so-called quaternary layer. The second layer 20c functions as an active layer, and therefore has a composition that functions appropriately for light in the 1.55 μm wavelength band.

[0036] The third layer 20d is made of, for example, p-InP, and functions as a cladding layer in the mesa 21.

[0037] Within the body 11, the mesa 21 is surrounded by current blocking layers 20e and 20f and a cladding layer 20g adjacent in the Z direction. The current blocking layer 20e is made of, for example, p-InP, the current blocking layer 20f is made of, for example, n-InP, and the cladding layer 20g is made of, for example, p-InP.

[0038] Conductor layers 41 and 42 are provided on cladding layer 20g, i.e., on the opposite side of cladding layer 20g from substrate 10. Furthermore, electrode 31 is provided on conductor layer 41, i.e., on the opposite side of conductor layer 41 from substrate 10, and electrode 32 is provided on conductor layer 42, i.e., on the opposite side of conductor layer 42 from substrate 10. Electrodes 31 and 32 have mutually opposite polarities.

[0039] The electrode 31 is spaced apart from the active layer in the Z direction and constitutes a P-side electrode. It can be said that the conductor layer 41 also constitutes a part of the P-side electrode.

[0040] The end faces (side faces) of the body 11 in the Y direction and the opposite direction to the Y direction, and the end face 11a (top face) in the Z direction are covered with the insulating layer 12, except for an opening on the body 11 through which the conductor layer 41 penetrates. In other words, the conductor layer 41 contacts the end face 11a, and the electrode 31 is electrically connected to the end face 11a via the conductor layer 41. The insulating layer 12 is made of, for example, SiN.

[0041] Furthermore, an insulating layer 12 is interposed between the end surface 11a and the conductor layer 42 and electrode 32. In other words, the conductor layer 42 and electrode 32 are insulated from the end surface 11a. The conductor layer 42 is spaced apart from the conductor layer 41 in the Y direction and extends to the side and bottom surfaces of a recess 11c provided on the body 11. An opening is provided in the insulating layer 12 at the bottom surface of the recess 11c, and the conductor layer 42 is electrically connected to the substrate 10 through this opening.

[0042] A current can be passed through the semiconductor layers by applying a voltage between the electrodes 31 and 32. When the semiconductor device 100 is configured as an optical semiconductor device such as a semiconductor optical amplifier, the current can activate the second layer 20c.

[0043] As shown in FIG. 1 , the body 11 has a rectangular shape in a plan view when viewed in the direction opposite the Z direction. The body 11 has edges 11d1, 11d2, 11d3, and 11d4 that form a periphery in the plan view. The edge 11d1 extends along the Y direction at its end in the X direction. The edge 11d2 extends along the Y direction at its end in the opposite direction to the X direction. The edge 11d3 extends along the X direction at its end in the Y direction. The edge 11d4 extends along the X direction at its end in the opposite direction to the Y direction. The edges 11d1 and 11d2 are examples of first edges, and the edges 11d3 and 11d4 are examples of second edges. The X direction is an example of a second direction, and the Y direction is an example of a third direction.

[0044] The end face 11a is covered with an insulating layer 12. The insulating layer 12 has a covering portion 12a that covers the end face 11a except for openings through which the above-mentioned conductor layers 41 and 42 penetrate. The peripheral portion of the covering portion 12a is spaced apart from the edges 11d1, 11d2, 11d3, and 11d4. In other words, the end face 11a has a covered region Ac that is covered with the covering portion 12a and a non-forming region Ae along the edges 11d1, 11d2, 11d3, and 11d4 where the covering portion 12a (insulating layer 12) is not formed. The non-forming region Ae extends with a substantially constant width along the edges 11d1, 11d2, 11d3, and 11d4, but the width does not have to be constant. The non-forming region Ae may also be referred to as an exposed region.

[0045] 3 is an enlarged plan view showing a wafer W and a portion of the wafer W. As shown in FIG. 3, a plurality of semiconductor element portions S arranged in a matrix are formed collectively on a substrate 10 of the wafer W by a semiconductor process. Thereafter, the semiconductor element portions S are cut out from the wafer W along cutting lines CLx extending in the X direction and CLy extending in the Y direction, thereby obtaining semiconductor elements 100A (100). That is, the semiconductor element portions S have substantially the same configuration as the semiconductor element 100. The cutting lines CLx become edges 11d1 and 11d2 in the semiconductor element 100, and the cutting lines CLy become edges 11d3 and 11d4 in the semiconductor element 100. The cutting lines CLx and CLy may also be referred to as planned cutting lines or imaginary boundary lines.

[0046] If the cutting lines CLx and CLy were covered with the insulating layer 12, the presence of the insulating layer 12 could cause problems, such as making it difficult to cut the wafer W along the cutting lines CLx and CLy or causing the edges 11d1, 11d2, 11d3, and 11d4 of the cut end faces of the semiconductor elements 100A to become rough and uneven. For this reason, in this embodiment, a strip-shaped region Ae where the insulating layer 12 is not formed is provided on the end face 11a of the wafer W along the cutting lines CLx and CLy, centered on the cutting lines CLx and CLy. This prevents problems caused by the insulating layer 12 when cutting along the cutting lines CLx and CLy.

[0047] Similarly to other components of the semiconductor device 100A (100), the electrodes 31 and 32 are formed when the semiconductor device portion S is integrated with the wafer W. The electrodes 31 and 32 are formed by electroplating in predetermined positions and shapes on the conductor layers 41 and 42 provided on each semiconductor device portion S. When forming the electrodes 31 and 32 by electroplating, if there is a large potential difference between the multiple conductor layers 41 or the multiple conductor layers 42 on the wafer W, variations (individual differences) may occur in the thickness of the electrodes 31 and 32 in the Z direction. Such variations in the shapes of the electrodes 31 and 32 may contribute to variations (individual differences) in the performance of the semiconductor device 100.

[0048] Therefore, in this embodiment, as shown in FIG. 3 , wiring portions 41b, 42b are provided on the conductor layers 41, 42 of each semiconductor element portion S (semiconductor element 100). The wiring portion 41b electrically connects the plurality of covering portions 41a adjacent to each other in the X direction on the wafer W. The wiring portion 42b electrically connects the plurality of covering portions 42a adjacent to each other in the X direction on the wafer W. As a result, in a row of the plurality of semiconductor element portions S aligned in the X direction on the wafer W, the plurality of covering portions 41a are electrically connected to each other via the wiring portion 41b, and the plurality of covering portions 42a are electrically connected to each other via the wiring portion 42b. Therefore, according to this embodiment, in the electrolytic plating for forming the electrodes 31, 32, the potential difference between the plurality of conductor layers 41 and the plurality of conductor layers 42 between the plurality of semiconductor element portions S can be further reduced. This makes it possible to suppress variations in the specifications of the electrodes 31, 32 between the plurality of semiconductor elements 100, and thereby variations in the performance of the semiconductor elements 100. In the semiconductor element 100, the wiring portion 41b extends between the electrode 31 and the edge 11d1 or the edge 11d2, and the wiring portion 42b extends between the electrode 32 and the edge 11d1 or the edge 11d2. The wiring portions 41b and 42b are examples of wiring.

[0049] As described above, the insulating layer 12 is not provided in the non-forming region Ae along the cutting lines CLx and CLy in the wafer W, whereas the wiring portions 41b and 42b straddle the cutting line CLy. If the wiring portions 41b and 42b, which are electrically connected to the electrodes 31 and 32, respectively, and which have opposite polarities, were both in contact with the non-forming region Ae of the end surface 11a, a short circuit of current may occur between the wiring portions 41b and 42b.

[0050] Therefore, the semiconductor element portion S (semiconductor element 100) of this embodiment is provided with a configuration for preventing a short circuit of current between the wiring portions 41b and 42b via the non-formation region Ae of the insulating layer 12. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. As shown in FIG. 4, in this embodiment, an intervening portion 12b is provided in the non-formation region Ae, corresponding to one of the wiring portions 41b and 42b (for example, the wiring portion 42b in this embodiment). The intervening portion 12b is interposed between the wiring portion 42b and the end face 11a. As shown in FIG. 1, the intervening portion 12b extends forward in the X direction and backward in the X direction from the covering portion 12a of the insulating layer 12 at the position where the wiring portion 42b is provided, thereby dividing the non-formation region Ae. In other words, the intervening portion 12b is interposed between the wiring portion 42b and the end face 11a at a position offset from the non-formation region Ae. The wiring portion 41b is provided on the non-forming region Ae and is an example of a first wiring. The wiring portion 42b is provided on the intervening portion 12b and is an example of a second wiring. The electrode 31 is an example of a first electrode, and the electrode 32 is an example of a second electrode.

[0051] As described above, in this embodiment, the intervening portion 12b is provided as the insulating layer 12 at the position where the wiring portion 42b is provided. However, the section of the cutting lines CLx, CLy where the intervening portion 12b is provided is relatively short, and the insulating layer 12 is not provided in other sections of the cutting lines CLx, CLy. Therefore, when cutting along the cutting lines CLx, CLy, it is possible to avoid the above-described inconvenience caused by the insulating layer 12.

[0052] As described above, according to this embodiment, by providing the non-forming regions Ae of the insulating layer 12 along the cutting lines CLx, CLy, it is possible to avoid undesirable events caused by the insulating layer 12 when cutting the wafer W, while providing the wiring portions 41b, 42b makes it possible to suppress variations in the electrodes 31, 32 formed by electroplating on the wafer W. Furthermore, by partially providing the intervening portions 12b as the insulating layer 12 corresponding to the wiring portions 42b, it is possible to prevent a short circuit of current between the wiring portions 41b, 42b provided to suppress variations in the electrodes 31, 32 in the semiconductor element 100, while avoiding undesirable events caused by the insulating layer 12 when cutting the wafer W.

[0053] As described above, in this embodiment, the wiring portion 42b (conductor layer 42) is electrically connected to the substrate 10. In this configuration, if the wiring portion 42b contacts the non-formation region Ae of the end face 11a, an unintended short circuit of current occurs between the end face 11a and the substrate 10 via the conductor layer 42, bypassing the semiconductor layer including the second layer 20c. In this regard, according to this embodiment, the intervening portion 12b is provided between the wiring portion 42b electrically connected to the substrate 10 and the non-formation region Ae, thereby preventing an unintended short circuit of current between the end face 11a and the substrate 10.

[0054] Furthermore, a semiconductor element array (not shown) can be obtained by cutting out a plurality of semiconductor element portions S adjacent in the Y direction, while they are integrated, from the wafer W. This configuration is suitable for application to optical elements having a plurality of semiconductor optical amplifiers, such as an optical matrix switch.

[0055] [Second embodiment] 5 is a plan view of a semiconductor element 100B (100) according to the second embodiment. As shown in FIG. 5, in this embodiment, an intervening portion 12b is provided not only between the wiring portion 42b and the end face 11a, but also between the wiring portion 41b and the end face 11a. This embodiment also achieves the same effects as the first embodiment. Note that the intervening portion 12b may be provided at a position away from the intervening portion 12b, as long as it is possible to avoid any undesirable events caused by the insulating layer 12 when cutting the wafer W. In other words, the length of the non-forming region Ae along the edges 11d1 to 11d4 may be shorter.

[0056] [Third embodiment] Fig. 6 is a plan view of a wafer W according to the third embodiment. As shown in Fig. 6, the wafer W according to this embodiment is provided with wiring portions 41c and 42c in addition to wiring portions 41b and 42b similar to those of the above-described embodiment. The wiring portions 41c and 42c electrically connect the electrodes 31 and 32 adjacent to each other in the Y direction in two semiconductor element portions S adjacent to each other in the Y direction.

[0057] Specifically, the wiring portion 41c extends in the Y direction from the covered portion 41a of the conductor layer 41 to the cutting line CLx, and the wiring portion 42c extends in the opposite direction to the Y direction from the covered portion 42a of the conductor layer 42 to the cutting line CLx. In the wafer W, the end of the wiring portion 41c and the end of the wiring portion 42c at the cutting line CLx face each other and are electrically connected to each other. With this configuration, in the semiconductor element 100C cut from the wafer W, the end of the wiring portion 41c at the edge 11d3 and the end of the wiring portion 42c at the edge 11d4 are aligned in the Y direction.

[0058] According to this embodiment, in the electrolytic plating for forming the electrodes 31 and 32, the wiring portions 41b, 42b, 41c, and 42c electrically connect more of the covering portions 41a and 42a, thereby further reducing the potential difference between these covering portions 41a and 42a. Therefore, according to this embodiment, it is possible to further suppress variations in the specifications of the electrodes 31 and 32 among multiple semiconductor elements 100, and thus variations in the performance of the semiconductor elements 100. In this embodiment, the wiring portions 41c and 42c are both provided on the intervening portion 12b and are an example of second wiring.

[0059] [Fourth embodiment] 7 is a plan view of a semiconductor device 100D (100) according to a fourth embodiment. As shown in FIG. 7, the semiconductor device 100D according to this embodiment has a U-shaped waveguide including two second layers 20c and one passive portion 20u that are arranged at approximately the same position in the Z direction. The two second layers 20c each extend in the X direction and are arranged approximately parallel to each other with a gap in the Y direction. The passive portion 20u is curved in a shape that is convex in the opposite direction in the X direction, and connects the ends of the two second layers 20c that are located at opposite ends in the X direction.

[0060] The semiconductor element 100D of this embodiment also has the non-forming region Ae, wiring portions 41b and 42b, and interposed portion 12b, similar to those of the first embodiment. Therefore, this embodiment also provides the same effects as those of the first embodiment.

[0061] [Fifth embodiment] Fig. 8 is a plan view of a semiconductor device 100E (100) according to the fifth embodiment. As shown in Fig. 8, the semiconductor device 100E according to this embodiment has two second layers 20c, each of which has the same configuration as that shown in Figs. 1 and 2. In other words, the semiconductor device 100E has two sets of configurations similar to those of the first embodiment. The two second layers 20c can be operated independently.

[0062] The semiconductor element 100E of this embodiment also has the non-forming region Ae, wiring portions 41b and 42b, and intervening portion 12b, similar to those of the first embodiment. Therefore, this embodiment also provides the same effects as those of the first embodiment. Note that a semiconductor element 100 having three or more sets of second layer 20c and configurations corresponding to the second layer 20c also provides the same effects as those of the first embodiment when it has the non-forming region Ae, wiring portions 41b and 42b, and intervening portion 12b, similar to those of the first embodiment.

[0063] [Sixth embodiment] 9 is a plan view of a semiconductor device 100F (100) according to the sixth embodiment. As shown in FIG. 9, the semiconductor device 100F according to the sixth embodiment also has two second layers 20c, similar to the fifth embodiment. However, in this embodiment, the electrode 32 is shared for the operation of the two second layers 20c. Therefore, the semiconductor device 100F has two electrodes 31 and one electrode 31.

[0064] The semiconductor element 100E of this embodiment also has the non-forming region Ae, wiring portions 41b and 42b, and interposed portion 12b, similar to those of the first embodiment. Therefore, this embodiment also provides the same effects as those of the first embodiment.

[0065] [Seventh embodiment] Fig. 10 is a plan view of a wafer W according to the seventh embodiment, and Fig. 11 is an enlarged view of a portion XI in Fig. 10.

[0066] 10, the plurality of semiconductor element portions S-1 to S-4 (semiconductor element 100G) formed on the wafer W have substantially the same configuration as the semiconductor element 100F of the sixth embodiment. However, the wafer W of this embodiment is provided with wiring portions 41d and 43 in addition to the wiring portions 41b and 42b similar to those of the above embodiment. The wiring portions 41d and 43 electrically connect the electrodes 31G (31) adjacent to each other in the Y direction in two semiconductor element portions S-1 and S-2 adjacent to each other in the Y direction. The wiring portions 41d and 43 pass through the four semiconductor element portions S-1 to S-4.

[0067] As shown in FIGS. 10 and 11, the wiring portions 41d provided on the semiconductor element portions S-1 and S-2 each extend from the electrode 31 in the opposite direction to the X-direction to the cutting line CLy (edge ​​11d2). On the other hand, the wiring portions 43 provided on the semiconductor element portions S-3 and S-4 each have an L-shape and extend between the cutting line CLy (edge ​​11d1) and the cutting line CLx (edge ​​11d3 or edge 11d4). In the wafer W, the end 41d1 of the wiring portion 41d and the end 43a of the wiring portion 43 at the cutting line CLy face each other and are electrically connected to each other. Furthermore, the end portions 43b of the two wiring portions 43 at the cutting line CLx face each other and are electrically connected to each other. Therefore, in the semiconductor element 100G cut out from the wafer W, the end 43a of the wiring portion 43 at the edge 11d1 and the end 41d1 of the wiring portion 41d at the edge 11d2 are aligned in the X direction, while the end 43b of the wiring portion 43 at the edge 11d3 and the end 43b of the wiring portion 43 at the edge 11d4 are aligned in the Y direction.

[0068] In this embodiment, as in the third embodiment, in the electrolytic plating for forming the electrodes 31 and 32, the potential difference between these covering portions 41 a and 42 a can be reduced by electrically connecting more covering portions 41 a and 42 a using the wiring portions 41 b, 42 b, 41 d, and 43. Therefore, this embodiment can further reduce variations in the specifications of the electrodes 31 and 32 among multiple semiconductor elements 100, and thus variations in the performance of the semiconductor elements 100.

[0069] 12 is a plan view of a semiconductor element array 200 integrally including a plurality of semiconductor element portions S of this embodiment aligned in the Y direction. As shown in FIG. 12, the semiconductor element array 200 includes wiring portions 41b, 42b, 41d, and 43, and a wiring portion 44 that integrally includes wiring portions 43 adjacent to each other in the Y direction. Wiring portions 41b, 42b, and 41d extend between electrode 31 or electrode 32 and edge 11d1 or edge 11d2. On the other hand, wiring portions 43 and 44 are not connected to either electrode 31 or 32, and are U-shaped or L-shaped, extending between edge 11d1 and edge 11d1 or edges 11d3 and 11d4. Here, if a semiconductor element array were to be constructed that integrally includes multiple semiconductor element portions S (see FIG. 6) of the third embodiment aligned in the Y direction, the electrodes 31 and 32 adjacent to each other in the Y direction would be electrically connected and short-circuited via the wiring portions 41c and 42c, making it unusable. This is because the wiring portions 41c and 42c electrically connecting the electrodes 31 and 32 in the wafer W extend only along the cutting line CLx, which is not used when constructing the semiconductor element array. In contrast, in the wafer W of this embodiment, the wiring portions 41d, 43, and 44 extending between the electrodes 31 and 32 adjacent to each other in the Y direction extend along the cutting line CLy, which is used when constructing the semiconductor element array 200, as shown in FIG. 11, and are separated at the cutting line CLy. This allows for the semiconductor element array 200 to be obtained in which the electrodes 31 and 32 are not short-circuited by the wiring portions 41d, 43, and 44.

[0070] To enable the configuration of such a semiconductor element array 200, the semiconductor element section S (semiconductor element 100G) of this embodiment has wiring portions 41b, 42b, and 41d extending between electrodes 31 and 32 and edges 11d1 and 11d2, but does not have wiring portions extending between electrodes 31 and 32 and edges 11d3 and 11d4. Furthermore, the semiconductor element 100G has a wiring portion 43 that is electrically insulated from electrodes 31 and 32 and extends between edge 11d1 and edge 11d3 or edge 11d4. Wiring portion 43 is an example of a third wiring.

[0071] The semiconductor element array 200 of this embodiment also has a U-shaped wiring portion 44 (see FIG. 12) that extends between two end portions 43a that are spaced apart in the Y direction and that face the edge 11d1 (see FIG. 11). The wiring portion 44 is substantially aligned in the X direction with the two wiring portions 41d that face the edge 11d2. The wiring portion 44 is an example of a fourth wiring.

[0072] While the embodiments of the present invention have been described above, they are merely examples and are not intended to limit the scope of the invention. The above embodiments can be implemented in various other forms, and various omissions, substitutions, combinations, and modifications can be made without departing from the spirit of the invention. Furthermore, the specifications of each configuration, shape, and the like (structure, type, direction, model, size, length, width, thickness, height, number, arrangement, position, material, etc.) can be modified as appropriate.

[0073] For example, the optical semiconductor element can be applied to a laser light emitting element such as a DFB type semiconductor laser, or a semiconductor element that is not an optical semiconductor element. [Explanation of symbols]

[0074] 10...Substrate 10a...side 10b...side 11...Body 11a...end face 11c...recess 11d1, 11d2...Edge (first edge) 11d3, 11d4...Edge (second edge) 12...Insulating layer 12a...Covering part 12b...Intervention site 20b...First layer (semiconductor layer) 20c...Second layer (semiconductor layer) 20d...Third layer (semiconductor layer) 20e...Current blocking layer (semiconductor layer) 20f...Current blocking layer (semiconductor layer) 20g: Cladding layer (semiconductor layer) 20u...passive section 21...Mesa 31,31G,32…electrode 41...Conductor layer 41a...Covering part 41b...Wiring section (wiring, first wiring) 41c...Wiring section (wiring, second wiring) 41d...Wiring section 41d1...end 42...Conductor layer 42a...Covering part 42b...Wiring section (wiring, second wiring) 42c...Wiring section (wiring, second wiring) 43...Wiring section (wiring, third wiring) 43a, 43b...end 44...Wiring section (wiring, fourth wiring) 100, 100A~100G...Semiconductor elements 200...Semiconductor element array Ac...covered area Ae…unformed area CLx,CLy…cutting line S, S-1 to S-4: Semiconductor element section W...wafer X…direction (second direction) Y…direction (third direction) Z…direction (first direction)

Claims

1. a body including a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, an end face in the first direction, and an edge that forms a periphery when viewed in a direction opposite to the first direction; an insulating layer covering the end surface; an electrode provided on the opposite side of the end surface from the substrate; at least one wiring electrically connected to the electrode and extending between the electrode and the edge; Equipped with an area where the insulating layer is not formed is provided along the edge of the end surface; The insulating layer has an intervening portion interposed between the end surface and the wiring at a position displaced from the non-forming region.

2. 2. The semiconductor element according to claim 1, wherein the semiconductor element is configured as an optical semiconductor element, and includes an active layer as the semiconductor layer, and the electrode for supplying a current to the active layer.

3. The wiring includes a plurality of wirings, 3. The semiconductor element according to claim 1, wherein the wiring includes a first wiring provided on the non-forming region and a second wiring provided on the intervening portion.

4. The electrodes include a first electrode and a second electrode having different polarities, the first wiring is electrically connected to the first electrode, The semiconductor element according to claim 3 , wherein the second wiring is electrically connected to the second electrode.

5. The semiconductor device according to claim 4 , wherein the second electrode is electrically connected to the substrate.

6. The edges include first edges positioned in front and rear in a second direction intersecting with the first direction, and second edges positioned in front and rear in a third direction intersecting with the first direction and the second direction, The semiconductor element according to any one of claims 1 to 5, wherein the wiring includes wiring extending between the electrode and the first edge, but does not include wiring extending between the electrode and the second edge.

7. The semiconductor element according to claim 6 , further comprising a third wiring that is not electrically connected to the electrode and extends between the first edge and the second edge.

8. a body including a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, an end face in the first direction, and an edge that forms a periphery when viewed in a direction opposite to the first direction; an insulating layer covering the end surface; an electrode provided on the end surface; at least one wiring electrically connected to the electrode and extending between the electrode and the edge; Equipped with The end surface is provided with an area along the edge where the insulating layer is not formed, The edges include first edges positioned in front and rear in a second direction intersecting with the first direction, and second edges positioned in front and rear in a third direction intersecting with the first direction and the second direction, A semiconductor element comprising, as the wiring, a wiring extending between the electrode and the first edge, but not a wiring extending between the electrode and the second edge.

9. a body including a substrate, a plurality of semiconductor layers stacked on the substrate in a first direction, an end face in the first direction, and first edges positioned at the front and rear in a second direction intersecting the first direction when viewed in a direction opposite to the first direction; an insulating layer covering the end surface; a plurality of electrodes provided on the end surface; at least one wiring electrically connected to the electrode and extending between the electrode and the first edge; Equipped with a semiconductor element array including a plurality of semiconductor element portions arranged in a third direction intersecting the first direction and the second direction, When viewed in a direction opposite to the first direction, an area where an insulating layer is not formed is provided along the first edge of the end surface; The insulating layer has an intervening portion interposed between the end surface and the wiring at a position displaced from the non-forming region.

10. 10. The semiconductor element array according to claim 9, wherein the plurality of semiconductor element portions have substantially the same configuration.

11. two first wirings as the wirings, the two first wirings extending between the electrodes adjacent to each other in the second direction and the first edge at one of the front and rear in the second direction and arranged at an interval in the third direction; a fourth wiring that is located at the other first edge of the front and rear in the second direction and has two end portions that are spaced apart from each other in a third direction, extends between the two end portions via a position away from the other first edge, and is arranged in the second direction with the two first wirings; 11. The semiconductor element array according to claim 9, comprising:

12. The semiconductor element array according to any one of claims 9 to 11, wherein each of the semiconductor element portions is configured as an optical semiconductor element portion having an active layer as the semiconductor layer and the electrode that supplies current to the active layer.

13. A wafer including a plurality of semiconductor element portions arranged in a matrix in a second direction intersecting the first direction and a third direction intersecting the first direction and the second direction, wherein the semiconductor element portions cut out from the wafer are configured to be the semiconductor element according to any one of claims 1 to 8 or the semiconductor element array according to any one of claims 9 to 12, A wafer in which a plurality of electrodes as the electrodes are electrically connected via the wiring.

14. 14. The wafer according to claim 13, wherein each of the semiconductor element portions is configured as an optical semiconductor element portion having an active layer as the semiconductor layer and the electrode for supplying a current to the active layer.

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