Analog-to-Digital Converter

Abstract

The analog-to-digital converter (ADC) circuit includes a signal input terminal (101), a sample-and-hold circuit (110), and a successive approximation register (SAR) ADC (112). The sample-and-hold circuit (110) includes an input terminal (110A) coupled to the signal input terminal (101). The SAR ADC (112) includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to the output terminal of the sample-and-hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal and an output terminal coupled to the second input terminal of the comparator.

Description

[Technical Field]

[0001] A variety of analog-to-digital data converters and conversion techniques are available for converting electrical signals from the analog domain to the digital domain. Generally, the process of analog-to-digital conversion involves sampling an analog signal and comparing the sampled analog signal to a threshold. Depending on the outcome of the comparison, a binary result is recorded. The process of comparing the sample to the threshold may be repeated multiple times, with each successive comparison using a different threshold and sample remainder. The number of iterations is typically determined by the noise level in a particular iteration, as well as the resolution of the final digital signal.

[0002] A successive approximation register (SAR) converter is an example of an analog-to-digital converter (ADC). A SAR ADC performs a binary search for the digital value that best corresponds to the voltage of the analog signal. In a SAR ADC, a voltage input is compared to one-half the voltage reference. If the voltage input is greater than one-half the voltage reference, a logic "1" is stored in the register. Alternatively, if the voltage input is less than one-half the voltage reference, a logic "0" is stored in the register. Next, if the previous comparison indicated that the voltage input was greater than one-half the voltage reference, the voltage input is compared to three-quarters the voltage reference. Again, if the comparison indicates a greater than condition, a logic "1" is stored in the register. In contrast, if the comparison indicates a less than condition, a logic "0" is stored in the register. Alternatively, if the previous comparison indicated that the voltage input was less than one-half the voltage reference, the voltage input is compared to one-quarter the voltage reference. Again, if the comparison indicates a greater than condition, a logic "1" is stored in the register. In contrast, if the comparison indicates a less-than condition, a logic "0" is stored in the register. This process continues for lower multiples of the voltage reference. As can be seen, the above process can provide high-resolution ADC results in a relatively short amount of time. Notably, only one iteration can be used to generate each bit of resolution. For example, for 10-bit resolution, 10 iterations are theoretically required, and for 20-bit resolution, 20 iterations are theoretically required. Summary of the Invention

[0003] Disclosed herein is a two-step successive approximation register (SAR) analog-to-digital converter (ADC) that improves coarse SAR ADC resolution through dynamic error correction. In one example, an analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to the output terminal of the sample-and-hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal and an output terminal coupled to the second input terminal of the comparator.

[0004] In another example, an analog-to-digital converter (ADC) circuit includes a sample-and-hold circuit and a SAR ADC. The sample-and-hold circuit is configured to sample an input signal to be digitized. The SAR ADC is coupled to the sample-and-hold circuit and configured to digitize the input signal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC is coupled to a first input of the comparator and configured to sample the input signal to be digitized and to sample an output of the sample-and-hold circuit. The second CDAC is coupled to a second input of the comparator and configured to sample the input signal to be digitized.

[0005] In a further example, an ADC circuit includes a first signal input terminal, a second signal input terminal, a first sample and hold circuit, a second sample and hold circuit, and a SAR ADC. The first sample and hold circuit includes an input terminal coupled to the first signal input terminal. The second sample and hold circuit includes an input terminal coupled to the second signal input terminal. The SAR ADC includes a comparator, a first CDAC, and a second CDAC. The first CDAC includes a first input terminal coupled to the first signal input terminal, a second input terminal coupled to the output terminal of the first sample and hold circuit, and an output terminal coupled to the first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the second signal input terminal, a second input terminal coupled to the output terminal of the second sample and hold circuit, and an output terminal coupled to the second input terminal of the comparator.

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a block diagram for a two-step successive approximation register (SAR) analog-to-digital converter (ADC) in accordance with the present description.

[0008] [Figure 2] 1 shows a schematic diagram for a sample and hold circuit and buffer in accordance with the present description.

[0009] [Figure 3] 1 shows a block diagram for a first stage of a two-step SAR ADC with dynamic error coupling in accordance with the present description.

[0010] [Figure 4] 1 shows a schematic diagram for a coarse SAR ADC in accordance with the present description.

[0011] [Figure 5]1 illustrates a timing diagram for digitization in a coarse SAR ADC in accordance with the present description.

[0012] [Figure 6] 1 shows a block diagram for a differential input two-step SAR ADC in accordance with the present description.

[0013] [Figure 7] 1 shows a schematic diagram for a differential input coarse SAR ADC in accordance with the present description. DETAILED DESCRIPTION OF THE INVENTION

[0014] As used herein, the term "couple" means either an indirect or direct wired or wireless connection. Thus, when a first device couples to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. Also, as used herein, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, X may be a function of Y and any number of other factors.

[0015] In a two-step successive approximation register (SAR) analog-to-digital converter (ADC), the resolution of the coarse-stage SAR ADC is limited by sampling bandwidth mismatch, clock skew, and other factors. Some two-step SAR ADCs attempt to provide improved resolution by using a sample-and-hold amplifier or by merging the coarse ADC's capacitive analog-to-digital converter (CDAC) with the main CDAC. However, the sample-and-hold amplifier consumes excessive power, and merging the coarse ADC CDAC with the main CDAC limits the conversion speed.

[0016] The two-step SAR ADC disclosed herein increases the coarse ADC resolution by reducing errors associated with sampling bandwidth mismatch without adding a sample-and-hold amplifier or merging the coarse ADC CDAC and the primary CDAC. The disclosed two-step SAR ADC modifies the search target of the coarse SAR ADC during conversion to compensate for signal-dependent residual errors in the different sampling paths. In implementation, a downscaled replica of the primary CDAC is used to generate a sampled input voltage for the primary CDAC, and the sampled input voltage is applied at the coarse ADC CDAC to adjust the search target of the coarse SAR ADC. The adjusted search target compensates for errors in the different sampling paths.

[0017] 1 shows a block diagram for a two-step successive approximation register (SAR) analog-to-digital converter (ADC) 100 according to the present description. The two-step SAR ADC 100 includes a first stage 102, a second stage 104, and output circuitry 106. The two-step SAR ADC 100 generates an M-bit digital output representative of an analog signal received at a signal input terminal 101. The first stage 102 generates a predetermined number of the M most significant bits, and the second stage 104 generates the remaining M bits. For example, in an implementation of the two-step SAR ADC 100 that generates a 16-bit output, the first stage 102 generates the 6 most significant bits (with one or more additional redundant bits), and the second stage 104 generates the 10 least significant bits. Output circuitry 106 receives the digital values ​​produced by first stage 102 and second stage 104 and combines (e.g., overlapping concatenation) these digital values ​​to produce a digital output value. The two-step architecture allows for reduced size of the capacitors used in first stage 102 and second stage 104.

[0018] First stage 102 includes sample and hold circuit 108, sample and hold circuit 110, SAR ADC 112, digital-to-analog converter (DAC) 114 (main DAC), subtraction circuitry 116, and residue amplifier 118. Sample and hold circuit 108, sample and hold circuit 110, and SAR ADC 112 are coupled to signal input terminal 101. Sample and hold circuit 108 includes input terminal 108A coupled to signal input terminal 101, sample and hold circuit 110 includes input terminal 110A coupled to signal input terminal 101, and SAR ADC 112 includes input terminal 112A coupled to signal input terminal 101. Each of sample and hold circuit 108, sample and hold circuit 110, and SAR ADC 112 obtains samples of input signal 103 to be digitized as provided at signal input terminal 101. An output terminal 112B of the SAR ADC 112 is coupled to the output circuitry 106 and an input terminal 114A of the DAC 114. The SAR ADC 112 digitizes acquired samples and provides digital values ​​120 to the output circuitry 106 and the DAC 114. The DAC 114 converts the digital values ​​120 to an analog voltage 122. The subtraction circuitry 116 is coupled to the sample and hold circuit 108, the DAC 114, and a residue amplifier 118. The subtraction circuitry 116 subtracts the analog voltage 122 from the samples 124 provided by the sample and hold circuit 108 to generate a residue signal 126 that represents the sum of the unadjusted errors of the SAR ADC 112. The residue amplifier 118 is coupled to the subtraction circuitry 116 and amplifies the residue signal 126 to generate an amplified residue signal 128.

[0019] The second stage 104 includes a SAR ADC 130. The SAR ADC 130 is coupled to the residue amplifier 118 and digitizes the amplified residue signal 128 to generate a digital value 132. The SAR ADC 130 provides the digital value 132 to the output circuitry 106 for combination with the digital value 120.

[0020] The sample and hold circuit 110 is a downscaled version of the sample and hold circuit 108. The sample and hold circuit 110 includes an input terminal 110A coupled to the signal input terminal 101 and an output terminal 110B coupled to the input terminal 112C of the SAR ADC 112. For any given sample 124 acquired by the sample and hold circuit 108, the sample and hold circuit 110 acquires a sample 134 having the same voltage as the sample 124. FIG. 2 shows a schematic diagram for an implementation of the sample and hold circuit 110 according to the present description. The sample and hold circuit 108 and the SAR ADC 112 are also shown in FIG. 2 for reference. In FIG. 2, the sample and hold circuit 108 includes a higher capacitance and a lower resistance than the sample and hold circuit 110. The ratio of the capacitance and resistance of the sample and hold circuit 110 to the capacitance and resistance of the sample and hold circuit 108 varies in different implementations of the two-step SAR ADC 100.

[0021] The sample and hold circuit 110 includes a sampling capacitor 202, a resistor 204 (representing a switch resistance), a resistor 206 (representing a switch resistance), a switch 208, a switch 210, an amplifier 212, a switch 214, a switch 216, and a switch 218. Switches 208 and 210 are closed when sampling the input signal 103 and open when sampling is complete and the sample and hold circuit 110 is in a hold state. Amplifier 212 buffers the voltage across the sampling capacitor 202 for provision to the SAR ADC 112. During sampling (e.g., during a sample interval), switches 214 and 216 are open, and switch 218 is closed, disconnecting amplifier 212 from the sampling capacitor 202. Similarly, when the sample and hold circuit 110 is in a hold state (e.g., a hold interval), switches 214 and 216 are closed, and switch 218 is open, connecting amplifier 212 from the sampling capacitor 202.

[0022] The amplifier 212 includes an input terminal 212A coupled to the sampling capacitor 202 via a switch 214, and an output terminal 212B coupled to the input terminal 112C of the SAR ADC 112. The switch 214 includes a terminal 214A coupled to the terminal 202B of the sampling capacitor 202 and a terminal 214B coupled to the input terminal 212A of the amplifier 212. The switch 216 includes a terminal 216A coupled to the terminal 202A of the sampling capacitor 202 and a terminal 216B coupled to the output terminal 212B of the amplifier 212. The switch 218 includes a terminal 218A coupled to the output terminal 212B of the amplifier 212 and a terminal 218B coupled to the input terminal 212A of the amplifier 212.

[0023] 3 shows a block diagram of a coarse SAR ADC 300. The coarse SAR ADC 300 is an implementation of the SAR ADC 112. The coarse SAR ADC 300 includes a sampling network 302 for sampling the input signal 103. The sampled signal 308 (V n2 ) is provided at the output of the sampling network 302. However, due to differences in sampling bandwidth, the sampled signal 308 may be different from the samples 134 (V n1 ) As explained above, samples 134 are the same as samples 124 from which residual signal 126 is derived. Coarse SAR ADC 300 compensates for the difference between samples 134 and sampled signal 308 by taking the difference between samples 134 and sampled signal 308 and subtracting that difference from sampled signal 308 to produce a voltage 304 that is the same as the voltage of samples 134 for use as a reference in digitization.

[0024] 4 shows a schematic diagram of a coarse SAR ADC 400 according to the present description. SAR ADC 400 is an implementation of SAR ADC 112 and SAR ADC 300. SAR ADC 400 includes CDAC 402, CDAC 404, comparator 406, SAR control circuit 408, switch 410, and switch 412. CDAC 402 includes a binary weighting capacitor 414 and switch 416. Switch 416 is controllable to connect the bottom plate of binary weighting capacitor 414 to input terminal 112A or input terminal 112C, thereby charging binary weighting capacitor 414 to input signal 103 or samples 134. CDAC 402 includes an output terminal 402A coupled to input terminal 406A of comparator 406, an input terminal 402b coupled to input terminal 112C of SAR ADC 112, and an input terminal 402C coupled to input terminal 112A of SAR ADC 112. The top plate of binary weighted capacitor 414 is coupled to output terminal 402A.

[0025] Similarly, the CDAC 404 includes a binary-weighted capacitor 418 and a switch 420. The switch 420 is controllable to connect the bottom plate of the binary-weighted capacitor 418 to the input terminal 112A, a reference voltage source, or a common voltage source (e.g., ground). The switches 410 and 412 are controllable to connect the top plates of the binary-weighted capacitor 414 and the binary-weighted capacitor 418 to ground, respectively. The CDAC 404 includes an output terminal 404A coupled to an input terminal 406B of the comparator 406 and an input terminal 404C coupled to the input terminal 112A of the SAR ADC 112. The top plate of the binary-weighted capacitor 418 is coupled to the output terminal 404A.

[0026] Comparator 406 compares the voltage on the top plate of binary-weighted capacitor 418 with the voltage on the top plate of binary-weighted capacitor 414 and provides the result of the comparison to SAR control circuit 408. SAR control circuit 408 is coupled to comparator 406, CDAC 402, and CDAC 404, and sets bits of digital value 120 based on the result of the comparison. SAR control circuit 408 generates switch control signal 422 that controls switch 410, switch 412, switch 416, and switch 420. SAR control circuit 408 determines how switch 420 should be set based on the output of comparator 406 and activates switch control signal 422 accordingly.

[0027] At the start of the digitization of each sample (acquisition phase), the SAR control circuit 408 sets the switch 416 and the switch 420 to connect the bottom plates of the binary weighted capacitor 414 and the binary weighted capacitor 418 to the input terminal 112A of the SAR ADC 112, resulting in the binary weighted capacitor 414 and the binary weighted capacitor 418 being charged to the input signal 103. After the SAR control circuit 408 selects a value for one or more bits of the digital value 120 (the number of bits is based on the redundancy required to correct for dynamic errors), the SAR control circuit 408 sets the switch 416 of the CDAC 402 to connect the bottom plate of the binary weighted capacitor 414 to the input terminal 112C of the SAR ADC 112, thereby applying the sample 134 to the bottom plate of the binary weighted capacitor 414. As a result, the voltage on the top plate of the binary weighted capacitor 414 is From the voltage of sample 134 From input terminal 112A of Previously sampled voltage I drew Voltage (i.e., V n1 -V n2 ) Therefore, the reference voltage applied to the comparator 406 is set to V n1 -V n2 The shift to digitalization continues. n1 -V n2By shifting the input voltage to 134, the voltage digitized by the SAR ADC 400 is essentially the voltage of the sample 134, rather than the voltage sampled by the binary weighted capacitor 418 from the input terminal 112A.

[0028] 5 shows a timing diagram for digitization using SAR ADC 400 as a coarse SAR ADC in two-step SAR ADC 100. During interval 502, sample and hold circuit 108, sample and hold circuit 110, CDAC 402, and CDAC 404 sample input signal 103. At the end of interval 502, switches 214 and 216 are closed, and the output of amplifier 212 settles over interval 504. At the end of interval 502, switch 416 is set to disconnect signal input terminal 101 from binary-weighted capacitor 414. During interval 514, the bottom plate of capacitor 416 is floating. At the end of interval 504, before the DEC bit interval, switch 416 is set to connect output terminal 110B of sample and hold circuit 110 to binary-weighted capacitor 414, so that the top plate of binary-weighted capacitor 414 is connected to V n1 -V n2 In interval 504, the error of the selected bit is determined (the error associated with using zero as a reference on interval 504). In some embodiments, the error is digitally corrected after digitization by the two-step SAR ADC 100 is complete. In interval 508, the remaining bit decisions are digitally corrected using V as the reference voltage (not conventionally zero) applied at 406A of comparator 406. n1 -V n2 This is done in the SAR ADC 400 using

[0029] 6 shows a block diagram for a differential input two-step SAR ADC 600 according to the present description. The differential input two-step SAR ADC 600 includes a first stage 602, a second stage 604, and output circuitry 606. The first stage 602 includes a sample-and-hold circuit 608, a sample-and-hold circuit 609, a sample-and-hold circuit 610, a sample-and-hold circuit 611, a SAR ADC 612, a digital-to-analog converter (DAC) 614 (main DAC), subtraction circuitry 616, and a residue amplifier 618. The sample-and-hold circuit 608, the sample-and-hold circuit 610, and the SAR ADC 612 are coupled to a signal input terminal 601. The sample-and-hold circuit 609, the sample-and-hold circuit 611, and the SAR ADC 612 are coupled to a signal input terminal 603. Sample and hold circuit 608 includes an input terminal 608A coupled to signal input terminal 601, sample and hold circuit 610 includes an input terminal 610A coupled to signal input terminal 601, and SAR ADC 612 includes an input terminal 612A coupled to signal input terminal 601. Each of sample and hold circuit 608, sample and hold circuit 610, and SAR ADC 612 receives an input signal 605 (V IN+ ) to obtain a sample.

[0030] Sample and hold circuit 609 includes an input terminal 609A coupled to signal input terminal 603, sample and hold circuit 611 includes an input terminal 611A coupled to signal input terminal 603, and SAR ADC 612 includes an input terminal 612E coupled to signal input terminal 603. Each of sample and hold circuit 609, sample and hold circuit 611, and SAR ADC 612 receives an input signal 607 (V IN- ) to obtain a sample.

[0031] Sample and hold circuit 608 and sample and hold circuit 609 are implementations of sample and hold circuit 108. Sample and hold circuit 610 and sample and hold circuit 611 are implementations of sample and hold circuit 110. Sample and hold circuit 610 is a downscaled version of sample and hold circuit 608, and sample and hold circuit 611 is a downscaled version of sample and hold circuit 609. Sample and hold circuit 610 includes an input terminal 610A coupled to signal input terminal 601 and an output terminal 610B coupled to input terminal 612C of SAR ADC 612. For any given sample 624 taken by sample and hold circuit 608, sample and hold circuit 610 takes a sample 634 having the same voltage as sample 624. Sample and hold circuit 611 includes an input terminal 611A coupled to signal input terminal 603 and an output terminal 611B coupled to input terminal 612D of SAR ADC 612. For any given sample 644 taken by sample and hold circuit 609, sample and hold circuit 611 takes a sample 635 having the same voltage as sample 644.

[0032] 7 shows a schematic diagram for a differential input coarse SAR ADC 700 according to the present description. The differential input coarse SAR ADC 700 is an implementation of the SAR ADC 612. The differential input coarse SAR ADC 700 includes a CDAC 702, a CDAC 704, a CDAC 714, a CDAC 716, a comparator 706, a SAR control circuit 708, a switch 710, a switch 712, a switch 718, and a switch 720. The SAR control circuit 708 is coupled to the comparator 706, the CDAC 702, the CDAC 704, the CDAC 714, and the CDAC 716. The CDACs 702, the CDAC 704, the CDAC 714, and the CDAC 716 include binary weighted capacitors and switches. In CDAC 702, a switch is controllable to connect the bottom plate of a capacitor to either input terminal 612E or input terminal 612D, thereby charging the capacitor to the voltage of input signal 607 or sample 635. CDAC 702 includes an output terminal 702A coupled to input 706D of comparator 706, an input terminal 702B coupled to input terminal 612D, and an input terminal 702C coupled to input terminal 612E. The top plate of the capacitor of CDAC 702 is coupled to output terminal 702A. In CDAC 702, a switch is controllable to connect the bottom plate of the capacitor of CDAC 702 to either input terminal 612E or input terminal 612D, thereby charging the capacitor to the voltage of input signal 607 or sample 635.

[0033] CDAC 716 includes an output terminal 716A coupled to input 706C of comparator 706, an input terminal 716B coupled to input terminal 612C, and an input terminal 716C coupled to input terminal 612A of SAR ADC 612. The top plate of a capacitor in CDAC 716 is coupled to output terminal 716A. In CDAC 716, a switch is controllable to connect the bottom plate of the capacitor in CDAC 716 to input terminal 612A or input terminal 612C, thereby charging the capacitor to the voltage of input signal 605 or sample 634.

[0034] CDAC 704 includes an output terminal 704A coupled to input 706B of comparator 706 and an input terminal 704B coupled to input terminal 612E. The top plate of a capacitor in CDAC 704 is coupled to output terminal 704A. A switch in CDAC 704 is controllable to connect the bottom plate of the capacitor to input terminal 612E, a reference voltage source, or a common voltage source (e.g., ground).

[0035] CDAC 714 includes an output terminal 714A coupled to input 706A of comparator 706 and an input terminal 714B coupled to input terminal 612A. The top plate of a capacitor in CDAC 714 is coupled to output terminal 714A. A switch in CDAC 714 is controllable to connect the bottom plate of the capacitor to input terminal 612A, a reference voltage source, or a common voltage source (e.g., ground).

[0036] At the start of digitization of each sample, SAR control circuit 708 sets the switches of CDAC702 and CDAC704 to connect the bottom plates of the capacitors of CDAC702 and CDAC704 to signal input terminal 603, charging the capacitors of CDAC702 and CDAC704 to the voltage of input signal 607. After SAR control circuit 708 selects the value of one or more bits of digital value 620, SAR control circuit 708 sets the switch of CDAC702 via switch control signal 722 to disconnect the bottom plate of the capacitor of CDAC702 from signal input terminal 603 and connect the bottom plate of the capacitor of CDAC702 to output 611B of sample and hold circuit 611, charging the capacitor to the voltage of sample 635. As a result, the voltage on the top plate of the capacitor of CDAC702 is From the voltage of sample 635 The previously sampled voltage of the input signal 607 I drew The voltage is set to

[0037] Similarly, at the start of digitization of each sample, SAR control circuit 708 sets the switches of CDAC 714 and CDAC 716 to connect the bottom plates of the capacitors of CDAC 714 and CDAC 716 to signal input terminal 601, charging the capacitors of CDAC 714 and CDAC 716 to the voltage of input signal 605. After SAR control circuit 708 selects a value for one or more bits of digital value 620, SAR control circuit 708 sets the switches of CDAC 716 to disconnect the bottom plate of the capacitor of CDAC 716 from signal input terminal 601 and connect the bottom plate of the capacitor of CDAC 716 to output 610B of sample and hold circuit 610, charging the capacitor to the voltage of sample 634. As a result, the voltage on the top plate of the capacitor of CDAC 716 is From the voltage of sample 634 The previously sampled voltage of the input signal 605 I drew The voltage is set to

[0038] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. An analog-to-digital converter (ADC) circuit, comprising: A signal input terminal; a first sample and hold circuit having an input terminal coupled to the signal input terminal and an output terminal; a first successive approximation register (SAR) ADC, a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC) having a first input terminal coupled to the signal input terminal, a second input terminal coupled to the output terminal of the first sample and hold circuit, and an output terminal coupled to the first input terminal of the comparator, the first CDAC being configured to provide at its output terminal a difference between a voltage on the first input terminal and a voltage on the second input terminal; a second CDAC having a first input terminal coupled to the signal input terminal and an output terminal coupled to a second input terminal of the comparator; the first SAR ADC, 1. An ADC circuit comprising:

2. 2. The ADC circuit of claim 1, the first sample and hold circuit a sampling capacitor having a first terminal and a second terminal; an amplifier having an input terminal coupled to the sampling capacitor and an output terminal coupled to a second input terminal of the first CDAC; 1. An ADC circuit comprising:

3. 3. The ADC circuit of claim 2, the first sample and hold circuit a first switch having a first terminal coupled to the first terminal of the sampling capacitor and a second terminal coupled to the input terminal of the amplifier; a second switch having a first terminal coupled to the second terminal of the sampling capacitor and a second terminal coupled to the output terminal of the amplifier; a third switch having a first terminal coupled to the output terminal of the amplifier and a second terminal coupled to the input terminal of the amplifier; The ADC circuit further comprises:

4. 2. The ADC circuit of claim 1, The ADC circuit further includes a second sample and hold circuit having an input terminal coupled to the signal input terminal.

5. 5. The ADC circuit of claim 4, a main digital-to-analog converter (DAC) having an input coupled to the output of the first SAR ADC; subtraction circuitry coupled to the main DAC and to the second sample and hold circuit; The ADC circuit further comprises:

6. 6. The ADC circuit of claim 5, a residue amplifier coupled to the subtraction circuitry; a second SAR ADC coupled to the residue amplifier; The ADC circuit further comprises:

7. 2. The ADC circuit of claim 1, the first CDAC includes a plurality of capacitors; the first SAR ADC is a SAR control circuit coupled to the comparator and the first CDAC, wherein in a given bit decision cycle: disconnecting the bottom plates of the plurality of capacitors of the first CDAC from the signal input terminal; connecting the bottom plate to the first sample and hold circuit; The ADC circuit further comprises the SAR control circuit configured to:

8. 1. An analog-to-digital converter (ADC) circuit, comprising: a first sample and hold circuit configured to sample the input signal to be digitized; a first successive approximation register (SAR) ADC coupled to the first sample and hold circuit and configured to digitize the input signal, a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC) coupled to a first input terminal of the comparator, sampling the input signal to be digitized; sampling the output of the first sample and hold circuit; providing a difference between a sample of the input signal and a sample of the output of the first sample and hold circuit; the first CDAC configured as follows: a second CDAC coupled to a second input terminal of the comparator, the second CDAC configured to sample the input signal to be digitized; the first SAR ADC, 1. An ADC circuit comprising:

9. 9. The ADC circuit of claim 8, a SAR control circuit coupled to the comparator, the first CDAC, and the second CDAC, setting a switch of the first CDAC to charge a capacitor of the first CDAC to a voltage of the input signal to be digitized during selection of a first bit; setting a switch of the first CDAC to charge a capacitor of the first CDAC to a voltage of the output of the first sample and hold circuit during selection of a second bit; The ADC circuit further comprises the SAR control circuit configured to:

10. 10. The ADC circuit of claim 9, The ADC circuit, wherein the first CDAC is further configured to provide a voltage to the comparator equal to a difference between a voltage of the input signal to be digitized and a voltage of an output of the first sample and hold circuit.

11. 9. The ADC circuit of claim 8, a second sample and hold circuit configured to sample the input signal to be digitized; An ADC circuit, wherein the first sample and hold circuit is a downscaled version of the second sample and hold circuit.

12. 9. The ADC circuit of claim 8, the first sample and hold circuit A sampling capacitor; An amplifier; a switch configured to disconnect the amplifier from the sampling capacitor during a sample interval and connect the amplifier to the sampling capacitor during a hold interval; 1. An ADC circuit comprising:

13. 12. The ADC circuit of claim 11, a main DAC coupled to the first SAR ADC, the main DAC configured to generate a voltage corresponding to a digital value generated by the SAR ADC; subtraction circuitry coupled to the main DAC, the subtraction circuitry configured to generate a difference between an output of the second sample and hold circuit and a voltage generated by the main DAC; The ADC circuit further comprises:

14. 14. The ADC circuit of claim 13, a residue amplifier coupled to the subtraction circuitry, the residue amplifier configured to amplify an output of the subtraction circuitry; a second SAR ADC coupled to the residue amplifier, the second SAR ADC configured to digitize an output of the residue amplifier; and The ADC circuit further comprises:

15. An ADC circuit, a first signal input terminal; a second signal input terminal; a first sample and hold circuit having an input terminal coupled to the first signal input terminal and an output terminal; a second sample and hold circuit having an input terminal coupled to the second signal input terminal and an output terminal; 1. A successive approximation register (SAR) ADC, comprising: a comparator having a first input terminal and a second input terminal; a first capacitive digital-to-analog converter (CDAC) having a first input terminal coupled to the first signal input terminal, a second input terminal coupled to the output terminal of the first sample and hold circuit, and an output terminal coupled to the first input terminal of the comparator, the first CDAC being configured to provide at an output terminal a difference between a voltage on the first input terminal and a voltage on the second input terminal; a second CDAC having a first input terminal coupled to the second signal input terminal, a second input terminal coupled to an output terminal of the second sample and hold circuit, and an output terminal coupled to the second input terminal of the comparator; a SAR ADC including:

1. An ADC circuit comprising:

16. 16. The ADC circuit of claim 15, The SAR ADC is a third CDAC having a first input terminal coupled to the first signal input terminal and an output terminal coupled to a third input terminal of the comparator; a fourth CDAC having a first input terminal coupled to the second signal input terminal and an output terminal coupled to a fourth input terminal of the comparator; and The ADC circuit further comprises:

17. 16. The ADC circuit of claim 15, the first sample and hold circuit a first sampling capacitor having a first terminal and a second terminal; a first amplifier having an input terminal and an output terminal coupled to the second input terminal of the first CDAC; a first switch having a first terminal coupled to the first terminal of the first sampling capacitor and a second terminal coupled to the input terminal of the first amplifier; a second switch having a first terminal coupled to the second terminal of the first sampling capacitor and a second terminal coupled to the output terminal of the first amplifier; a third switch having a first terminal coupled to the output terminal of the first amplifier and a second terminal coupled to the input terminal of the first amplifier; 1. An ADC circuit comprising:

18. 18. The ADC circuit of claim 17, the second sample and hold circuit a second sampling capacitor having a first terminal and a second terminal; a second amplifier having an input terminal and an output terminal coupled to the second input terminal of the second CDAC; a third switch having a first terminal coupled to the first terminal of the second sampling capacitor and a second terminal coupled to the input terminal of the second amplifier; a fourth switch having a first terminal coupled to the second terminal of the second sampling capacitor and a second terminal coupled to the output terminal of the second amplifier; a fifth switch having a first terminal coupled to the output terminal of the second amplifier and a second terminal coupled to the input terminal of the second amplifier; 1. An ADC circuit comprising:

19. 16. The ADC circuit of claim 15, a third sample and hold circuit coupled to the first signal input terminal, the first sample and hold circuit being a downscaled version of the third sample and hold circuit; a fourth sample and hold circuit coupled to the second signal input terminal, the second sample and hold circuit being a downscaled version of the fourth sample and hold circuit; The ADC circuit further comprises:

20. 16. The ADC circuit of claim 15, a SAR control circuit coupled to the comparator, the first CDAC, and the second CDAC, wherein in a given bit decision cycle: disconnecting a bottom plate of a capacitor of the first CDAC from the first signal input terminal; connecting a bottom plate of the capacitor of the first CDAC to the first sample and hold circuit; disconnecting the bottom plate of the capacitor of the second CDAC from the second signal input terminal; connecting the bottom plate of the capacitor of the second CDAC to the second sample and hold circuit; The ADC circuit further comprises the SAR control circuit configured to:

Images