Transimpedance Amplifier Circuit

Abstract

To provide a transimpedance amplifier circuit that prevents fluctuations of an AGC band due to amplitude setting.SOLUTION: A transimpedance amplifier circuit comprises: an amplifier circuit that amplifies an input current signal and converts it into a voltage signal according to a gain set according to a control signal; and a gain control circuit that generates the control signal according to the amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal according to a reference voltage, a voltage control current source circuit that generates a differential current signal based on a differential voltage in which the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal is corrected according to an output amplitude setting signal, and a variable capacitance circuit that is connected with output of the voltage control current source circuit, has a capacitance value set according to the output amplitude setting signal, and is charged and discharged according to the differential current signal. The gain control circuit generates the control signal according to a charging voltage of the variable capacitance circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a transimpedance amplifier circuit. [Background technology]

[0002] In optical transmission systems, a wavelength division multiplexing system is known, in which an optical signal multiplexed with multiple optical signals having different wavelengths is transmitted and received using two optical fibers. Coherent reception is also known as a method for efficiently receiving multiplexed optical signals. For example, in an optical receiving device receiving one of the multiple optical signals (a single optical signal), an amplifier circuit that amplifies a current signal converted from the single optical signal includes a transimpedance amplifier and an AGC (Auto Gain Control) circuit that variably controls the gain of the transimpedance amplifier and keeps the amplitude of the amplified signal constant. This type of amplifier circuit is capable of outputting a linear output signal with a wide input dynamic range thanks to the variable gain function of the AGC circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 004828 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-220567 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-084474 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-217226 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when a setting signal that sets the amplitude of an output signal from an amplifier circuit is supplied to an AGC circuit, the loop gain and AGC band of the AGC circuit may fluctuate depending on the set amplitude. Here, the AGC band is calculated as the frequency when the gain of the loop gain characteristic of the AGC loop is "1" (0 dB in decibels).

[0005] Therefore, an object of the present disclosure is to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band caused by amplitude settings. [Means for solving the problem]

[0006] The transimpedance amplifier circuit of the present disclosure includes an amplifier circuit that amplifies an input current signal in accordance with a gain set by a control signal and converts the input current signal into a voltage signal, and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal in accordance with a reference voltage, and a setting circuit that generates an amplitude reference signal in accordance with a voltage difference between the amplitude detection signal and the amplitude reference signal. The amplified differential signal Depending on the output amplitude setting signal a differential amplifier circuit that generates a differential voltage by adding the generated offset voltage; a voltage-controlled current source circuit that generates a differential current signal based on a differential voltage; and a variable capacitance circuit that is connected to the output of the voltage-controlled current source circuit, has a capacitance value that is set according to the output amplitude setting signal, and is charged and discharged by the differential current signal, and the gain control circuit generates the control signal according to the charging voltage of the variable capacitance circuit. death , The offset voltage increases as the output amplitude setting signal increases, the amplitude of the voltage signal is set to decrease as the output amplitude setting signal decreases and to increase as the output amplitude setting signal increases, the differential current signal decreases as the differential voltage increases and to increase as the differential voltage decreases, and the capacitance value monotonically increases as the output amplitude setting signal increases and to decrease as the output amplitude setting signal decreases. . [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude settings. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the AGC control circuit of FIG. [Figure 3] FIG. 3 is an explanatory diagram showing an example of setting a capacitance value by the thermocode generating unit of FIG. [Figure 4] FIG. 4 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. [Figure 5] FIG. 5 is a characteristic diagram showing the characteristics shown in FIG. 4 as an AGC band relative to the output amplitude. [Figure 6] FIG. 6 is a circuit diagram showing another example of the configuration of the AGC control circuit mounted on the transimpedance amplifier circuit of FIG. [Figure 7] FIG. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. [Figure 8] FIG. 8 is a characteristic diagram showing the characteristics shown in FIG. 7 as an AGC band relative to the output amplitude. [Figure 9] FIG. 9 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit and the amplitude detection signal when the feedback function of the AGC control circuit in FIG. 2 or 6 is disabled. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A transimpedance amplifier circuit according to one aspect of the present disclosure includes an amplifier circuit that amplifies an input current signal in accordance with a gain set by a control signal and converts it into a voltage signal, and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal in accordance with a reference voltage, a voltage-controlled current source circuit that generates a differential current signal based on a differential voltage obtained by correcting the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal in accordance with an output amplitude setting signal, and a variable capacitance circuit that is connected to the output of the voltage-controlled current source circuit, has a capacitance value set in accordance with the output amplitude setting signal, and is charged and discharged by the differential current signal, and the gain control circuit generates the control signal in accordance with the charging voltage of the variable capacitance circuit.

[0011] In this transimpedance amplifier circuit, the AGC band can be kept constant regardless of the amplitude of the set voltage signal. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting.

[0012] [2] In the above [1], the gain control circuit may include a switch control section that generates a switch control signal in response to the output amplitude setting signal, the variable capacitance circuit may have a plurality of capacitance elements that are connected to the output of the voltage controlled current source circuit via switches that are turned on and off in response to the switch control signal, and the switch control section may generate the switch control signal such that the number of capacitance elements connected to the output of the voltage controlled current source circuit increases as the amplitude indicated by the output amplitude setting signal increases. This makes it possible to change the charge accumulated at the output node of the voltage controlled current source circuit in response to the set amplitude, and to compensate for fluctuations in the AGC band due to the amplitude setting.

[0013] [3] In the above [2], the switch control section may generate the switch control signal so as to turn on only one of the switches that connect and disconnect the plurality of capacitive elements that is in an off state when the digital value of the output amplitude setting signal increases by 1. This makes it possible to set a capacitance value corresponding to the output amplitude setting signal to the output of the voltage controlled current source circuit by a simple means.

[0014] [4] In any one of the above [1] to [3], the gain control circuit may further include a current generating unit that generates an offset current corresponding to a value indicated by the output amplitude setting signal, and a differential amplifier circuit that differentially amplifies the amplitude detection signal and the amplitude setting signal and adds a voltage corresponding to the offset current to a voltage obtained by amplifying the amplitude detection signal. This makes it possible to reflect the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal in the output of the differential amplifier circuit, and to set the amplitude of the voltage signal to the amplitude indicated by the output amplitude setting signal.

[0015] [Details of the embodiments of the present disclosure] Specific examples of transimpedance amplifier circuits according to the present disclosure will be described below with reference to the accompanying drawings. In the following description, identical or corresponding elements will be designated by the same reference numerals, and descriptions of these elements may be omitted. Furthermore, the reference numerals for input terminals, output terminals, and nodes will also be used to indicate signals, voltages, or currents.

[0016] [First embodiment] [Circuit configuration of transimpedance amplifier circuit] Fig. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to Embodiment 1. The transimpedance amplifier circuit 100 shown in Fig. 1 includes a TIA (TransImpedance Amplifier) ​​10, a VGA (Variable Gain Amplifier) ​​20, a BUF (Buffer) 30, a CML (Current Mode Logic) 40, and an AGC control circuit 50.

[0017] For example, the transimpedance amplifier circuit 100 is used in a coherent optical receiver that receives optical signals, and receives, at input terminals InP and InN, differential current signals converted from single-wavelength optical signals by photodiodes. The transimpedance amplifier circuit 100 amplifies the received current signals and outputs them as differential voltage signals from output terminals OutP and OutN. The voltage signals output from the output terminals OutP and OutN are output to a signal processing circuit such as a DSP (Digital Signal Processor).

[0018] The TIA 10 converts the differential input current signal received at input terminals InP and InN into a voltage signal and outputs it to the VGA 20. For example, the gain of the TIA 10 varies in response to a control signal CNTL1 received from the AGC control circuit 50. Note that the gain of the TIA 10 is expressed in units of impedance, such as 1000 Ω, because it converts current into voltage. The TIA 10 includes, for example, an INV (INVerting amplifier) ​​11 and resistor elements R11 and R12. For example, the INV11 is an example of an inverting amplifier circuit that amplifies a differential signal.

[0019] INV11, for example, inverts and amplifies a differential voltage signal input between a non-inverting input terminal and an inverting input terminal, and outputs the inverted and amplified differential voltage signal from an inverting output terminal and a non-inverting output terminal. Resistor R11 is connected, for example, between the non-inverting input terminal and the inverting output terminal of INV11. Resistor R12 is connected, for example, between the inverting input terminal and the non-inverting output terminal of INV11. The gain of TIA10 varies in response to a control signal CNTL1. Alternatively, TIA10 may use variable resistors for resistors R11 and R12, changing the resistance values ​​of resistors R11 and R12 in response to the control signal CNTL1.

[0020] The VGA 20 amplifies the differential voltage signal received from the TIA 10 and outputs it to the BUF 30. For example, the gain of the VGA 20 varies in response to the control signals CNTL2, CNTL3, and CNTL4 received from the AGC control circuit 50. The VGA 20 performs, for example, non-inverting amplification, but may also perform inverting amplification to invert the logic of the differential voltage signal it outputs. The differential voltage signal is composed of a positive-phase signal (positive-phase component) and a negative-phase signal (negative-phase component). The positive-phase signal and the negative-phase signal are 180 degrees out of phase with each other, forming a pair of complementary signals.

[0021] For example, when the voltage of the positive-phase signal increases, the voltage of the negative-phase signal decreases, and when the voltage of the positive-phase signal decreases, the voltage of the negative-phase signal increases. Furthermore, when the positive-phase signal reaches its peak value, the negative-phase signal reaches its bottom value, and when the positive-phase signal reaches its bottom value, the negative-phase signal reaches its peak value. It is preferable that the positive-phase signal and the negative-phase signal have the same amplitude and the same average value (DC component). By swapping the pair of positive-phase and negative-phase signals, the logic of the differential voltage signal can be inverted. Therefore, in a circuit that amplifies a differential voltage signal, switching between non-inverting amplification and inverting amplification can be easily performed by reconnecting the positive-phase signal wiring and the negative-phase signal wiring. The VGA 20 can also be included in the TIA 10 to amplify the differential voltage signal output from the TIA 10.

[0022] The BUF 30 amplifies the differential voltage signals received from the VGA 20 and outputs the resulting voltage signals IP and IN to the AGC control circuit 50 and the CML 40. The CML 40 amplifies the voltage signals IP and IN and outputs the amplified voltage signals to the output terminals OutP and OutN. The voltage signals IP and IN and the voltage signals output to the output terminals OutP and OutN are all differential voltage signals (hereinafter referred to as differential voltage signals). For example, the voltage signal IP is a positive-phase signal of the differential voltage signal, and the voltage signal IN is a negative-phase signal of the differential voltage signal. Note that, for example, if the voltage gain and driving capability of the VGA 20 are sufficiently large, the BUF 30 may be omitted and the VGA 20 may supply the differential voltage signals IP and IN.

[0023] The AGC control circuit 50 generates control signals CNTL1-CNTL4 that adjust the gain of the TIA 10 and the VGA 20 to set the amplitude of the differential voltage signals IP and IN received from the BUF 30 to the amplitude indicated by the output amplitude setting signal OA. The AGC control circuit 50 is an example of a gain control circuit. An example of the AGC control circuit 50 is shown in FIG. 2. The amplitudes of the differential voltage signals IP and IN are controlled by the AGC control circuit 50. For example, if the CML 40 performs linear amplification with a constant gain, the amplitudes of the differential voltage signals IP and IN can be kept constant by controlling the amplitudes of the differential voltage signals IP and IN to be constant.

[0024] [AGC control circuit configuration] FIG. 2 is a circuit diagram showing an example of the AGC control circuit 50 of FIG. 1. The AGC control circuit 50 includes bipolar transistors Q1P and Q1N that receive differential voltage signals IP and IN output from the BUF 30 of FIG. 1. For example, the bipolar transistor Q1P receives a positive-phase signal IP of the differential voltage signals IP and IN, and the bipolar transistor Q1N receives a negative-phase signal IN of the differential voltage signals IP and IN. The AGC control circuit 50 also includes a current source I51 and a resistor R51 connected to the emitters of the bipolar transistors Q1P and Q1N, and a capacitor C51 connected to the resistor R51. The bipolar transistors Q1P and Q1N have the same electrical characteristics, for example, within the range of allowable manufacturing variations.

[0025] Hereinafter, the bipolar transistor will also be referred to simply as a transistor. Transistors Q1P and Q1N, current source I51, resistor R51, and capacitor C51 function as a detection circuit that detects the amplitude of voltage signals IP and IN. An amplitude detection signal PH, set to a voltage corresponding to the amplitude detected by the detection circuit, is output to the gate of p-channel MOS transistor M1P of the differential amplifier circuit. Resistor R51 and capacitor C51 form a low-pass filter, and the amplitude detection signal PH is averaged and output from the connection node between resistor R51 and capacitor C51. For example, when the amplitudes of differential voltage signals IP and IN are constant, the amplitude detection signal PH becomes a DC signal having a voltage value corresponding to the magnitude of the amplitude. Hereinafter, the p-channel MOS transistor will also be referred to simply as a transistor.

[0026] The AGC control circuit 50 also includes a bipolar transistor Q2 that receives a reference voltage Vref, and a current source I52, a resistor R52, and a capacitor C52 connected to the emitter of the transistor Q2. The transistor Q2, the current source I52, the resistor R52, and the capacitor C52 have a circuit configuration similar to that of the detection circuit that detects the amplitude of the voltage signals IP and IN, and for example, the electrical characteristics and size of each circuit element are similar to those of the detection circuit within the allowable range of manufacturing variations.

[0027] For example, the reference voltage Vref is set to the center voltage of the amplitudes of the differential voltage signals IP and IN. The center voltage of the amplitudes of the differential voltage signals IP and IN is equal to the time average value (DC component) of each voltage signal. Note that the reference voltage Vref may be set to the average value obtained by dividing the voltage signals IP and IN output from the BUF30 in FIG. 1 and applying them to a resistor string. For example, the voltage signal IP may be applied to one end of a series resistor circuit consisting of two resistors, and the voltage signal IN may be applied to the other end of the series resistor circuit, and the voltage at the midpoint where the two resistors are connected may be used as the reference voltage Vref.

[0028] Transistor Q2, current source I52, resistor R52, and capacitor C52 function as a setting circuit that converts the level of reference voltage Vref and generates the converted voltage as amplitude reference signal AH. The amplitude reference signal AH is output to the gate of p-channel MOS transistor M1N of the differential amplifier circuit. Resistor R52 and capacitor C52 form a low-pass filter, and the level-converted reference voltage Vref is stabilized and output from the connection node between resistor R52 and capacitor C52. For example, amplitude reference signal AH is a DC signal having a voltage value corresponding to reference voltage Vref. Thus, amplitude detection signal PH and amplitude reference signal AH are each output as DC signals to the differential amplifier circuit. For example, transistors Q1P, Q1N, and Q2 are heterojunction bipolar transistors.

[0029] The differential amplifier circuit includes, for example, transistors M1P and M1N, a current source I53 connected to the sources of the transistors M1P and M1N, and resistors R53, R54, R55, and R56. The resistors R53 and R54 are connected in series between the drain of the transistor M1P and the ground line GND. The resistors R55 and R56 are connected in series between the drain of the transistor M1N and the ground line GND. For example, the resistors R53 and R55 have the same resistance within an allowable manufacturing variation range, and the resistors R54 and R56 have the same resistance within an allowable manufacturing variation range. The transistors M1P and M1N have the same electrical characteristics within an allowable manufacturing variation range, for example.

[0030] The connection node of the resistor elements R53 and R54 receives an offset current Ioffset from a DAC (Digital-to-Analog Converter) 52. As a result, an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of the resistor element R54 is added to the drain voltage of the transistor M1P relative to the ground potential.

[0031] The DAC 52 generates an offset current Ioffset corresponding to the digital value indicated by the output amplitude setting signal OA. For example, as the digital value of the output amplitude setting signal OA increases, the current value of the offset current Ioffset increases. The output amplitude setting signal OA is provided, for example, from outside the transimpedance amplifier circuit 100. The DAC 52 is an example of a current generating unit that generates the offset current Ioffset according to the digital value indicated by the output amplitude setting signal OA.

[0032] For example, the digital value of the output amplitude setting signal OA is set to a small value when the set amplitude is small, and is set to a large value when the set amplitude is large. Note that, although Fig. 2 shows an example in which the digital value A of the output amplitude setting signal OA is a two-digit binary value (A[1:0]), the digital value A may be any binary value having one or more digits.

[0033] For example, when the set amplitude is relatively small, the DAC 52 receives an output amplitude setting signal OA with a relatively small value and outputs a relatively small offset current Ioffset. When the set amplitude is relatively large, the DAC 52 receives an output amplitude setting signal OA with a relatively large value and outputs a relatively large offset current Ioffset. The DAC 52 is, for example, a current DAC (IDAC) that outputs a current.

[0034] The differential amplifier circuit outputs differential voltage signals VIN and VIP, which are generated in response to the voltages of the amplitude detection signal PH, the amplitude reference signal AH, and the offset current Ioffset, from the drains of the transistors M1P and M1N. The differential amplifier circuit and DAC52 are an example of a differential voltage generation circuit that generates a differential signal by correcting the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal in response to the output amplitude setting signal OA. The correction in response to the output amplitude setting signal OA is performed, for example, as described above, by adding an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of the resistor R54 to one of the voltages of the generated differential signal.

[0035] The differential voltage signals VIP and VIN are supplied to the differential inputs of an OTA (Operational Transconductance Amplifier) ​​51. By supplying the differential voltage signals VIP and VIN to the OTA 51, the signal-to-noise (SNR) ratio can be improved compared to when the amplitude detection signal PH and the amplitude reference signal AH are directly supplied to the OTA 51, thereby improving the accuracy of the AGC function. Furthermore, by adding an offset voltage due to the offset current Ioffset to one of the voltage signals VIP and VIN (opposite phase signal), VIN, the amplitude of the differential voltage signals IP and IN can be set to be equal to the amplitude value set by the output amplitude setting signal OA when the voltage values ​​of the voltage signals VIP and VIN become equal.

[0036] The OTA 51 outputs a differential current signal from an output node in response to differential voltage signals VIN and VIP. The OTA 51 is an example of a voltage-controlled current source circuit. For example, the OTA 51 outputs a current (differential current signal) corresponding to the difference between the voltages of voltage signals VIP and VIN. For example, the greater the voltage value of voltage signal VIP than the voltage value of voltage signal VIN, the smaller the differential current signal becomes, and the smaller the voltage value of voltage signal VIP than the voltage value of voltage signal VIN, the larger the differential current signal becomes. For example, when the voltage value of voltage signal VIP is the same as the voltage value of voltage signal VIN, the differential current signal becomes zero. A capacitance element C2,1 is connected to the output node of the OTA 51, and capacitance elements C2,2, ..., C2,n are connected via switches SW (n is an integer greater than or equal to 2). The n capacitance elements C2,1, C2,2, ..., C2,n are connected in parallel to each other when all n-1 switches SW are turned on. In the following description, when there is no need to distinguish between the capacitive elements C2,1, C2,2, . . . , C2,n, they will be referred to as capacitive element C2.

[0037] The OTA 51 functions as an integrator circuit together with the capacitance element C2 connected to the output of the OTA 51, and generates a voltage at the output node corresponding to the differential current signal output from the OTA 51 and the capacitance value of the capacitance element C2. The time constant defined by the output impedance of the OTA 51 and the capacitance element C2 forms the dominant pole of the gain characteristic of the AGC loop. Hereinafter, the symbols C2,1, C2,2, etc. will also be used to refer to the capacitance values ​​of the capacitance elements C2,1 and C2,2, respectively. Note that the AGC loop in the first embodiment is composed of a TIA 10 that changes its gain in response to a control signal CNTL1, a VGA 20 that changes its gain in response to control signals CNTL2-CNTL4, a BUF 30, and an AGC control circuit 50 that receives the differential voltage signals IP and IN and generates control signals CNTL1-CNTL4.

[0038] The on / off (ON / OFF) of each switch SW is controlled by a thermocode generator 53. As illustrated in the truth table in the figure, the thermocode generator 53 outputs an output signal X[2:0], which is a thermocode, in accordance with the digital value A[1:0] of the output amplitude setting signal OA. This allows the number of capacitive elements C2 connected to the output node of the OTA 51 to be increased by one each time the logical value of the output amplitude setting signal OA increases. Therefore, the capacitance value of the output node of the OTA 51 can be easily set in accordance with the logical value of the output amplitude setting signal OA.

[0039] More specifically, when the number of binary digits of the digital value A is m (m is an integer equal to or greater than 2), the number of output signals X corresponding to the digital value A[m-1:0] is 2. mThe output signal X is set to -1. With the thermocode, the number of switches SW that are turned on increases by one as the digital value A increases by one. Therefore, when the digital value A increases or decreases by one, only one switch SW is turned on or off accordingly, and the capacitance value of the capacitive element C2 can be monotonically increased or decreased without being affected by the timing of the output signal X. For example, when two switches SW are controlled simultaneously without using a thermocode, specifically when one switch SW is changed from an off state to an on state while the other switch SW is changed from an on state to an off state, the timing of each output signal X may differ, which may cause the monotonous change in the charging voltage of the capacitive element C2 to be lost. This may result in the control signals CNTL1-CNTL4 not being generated properly.

[0040] The switches SW and the capacitance elements C2 are an example of a variable capacitance circuit that is charged and discharged by a differential current signal. The output signal X[2:0] is an example of a switch control signal that controls the switches SW, and the thermocode generator 53 is an example of a switch control unit that generates the output signal X[2:0] in response to the output amplitude setting signal OA.

[0041] The capacitance element C2 is set to compensate for fluctuations in the AGC band caused by the amplitude setting indicated by the output amplitude setting signal OA, so that the AGC band set by the AGC control circuit 50 can be kept constant regardless of the setting of the output amplitude setting signal OA, as shown in FIG.

[0042] A gain control unit 54 is connected to the output of the OTA 51. The gain control unit 54 generates control signals CNTL1-CNTL4 that control the gains of the TIA 10 and VGA 20 according to the charging voltage of the capacitive element C2 connected to the output node of the OTA 51.

[0043] For example, when the voltage at the output node of the OTA 51 is relatively low, the gain control unit 54 generates control signals CNTL1-CNTL4 that increase the gain of the TIA 10 and the VGA 20. When the voltage at the output node of the OTA 51 is relatively high, the gain control unit 54 generates control signals CNTL1-CNTL4 that decrease the gain of the TIA 10 and the VGA 20.

[0044] When the amplitude detection signal PH and the amplitude reference signal AH are constant, a decrease in the offset current Ioffset reduces the voltage value of the voltage signal VIN, and an increase in the offset current Ioffset increases the voltage value of the voltage signal VIN. The transimpedance amplifier circuit 100 operates by the negative feedback of the AGC loop described above so that the difference between the voltage value of the voltage signal VIP input to the OTA 51 and the voltage value of the voltage signal VIN becomes "0," thereby canceling the offset voltage due to the offset current Ioffset. As a result, an AGC control circuit 50 can be configured that can set the amplitude using the digital value of the output amplitude setting signal OA.

[0045] [Capacitance value setting example] FIG. 3 is an explanatory diagram showing an example of setting the capacitance value of the capacitance element C2 by the thermocode generation unit 53 of FIG. 2. For example, as shown in FIG. 6 (described later), when a capacitance element C2 with a fixed capacitance value is connected to the output node of the OTA 51, the relationship between the output amplitude of the differential voltage signal output from the output terminals OutP and OutN and the AGC band is shown in FIG. 8. Let the AGC band values ​​at four points in FIG. 8 be F1, F2, F3, and F4, respectively, and consider adjusting F1 to F4 to a constant band Ftarget regardless of the amplitude setting. For example, the band Ftarget is 300 kHz. Hereinafter, the circuit of FIG. 6 will be referred to as the pre-compensation circuit, and the circuit of FIG. 2 will be referred to as the compensated circuit.

[0046] If the parasitic capacitance parasitic on the output node of the OTA 51 is Cp (e.g., 5 pF) and the capacitance value of the capacitive element C2 in Fig. 6 before compensation is C2F (e.g., 12 pF), the capacitance value in the circuit before compensation is constant (Cp + C2F). Here, the parasitic capacitance Cp is the sum of the output capacitance of the output node of the OTA 51, the input capacitance of the input to which the charging voltage of the capacitive element C2 of the gain control unit 54 is input, the capacitance of the wiring connecting the OTA 51 and the gain control unit 54, etc. The parasitic capacitance Cp is a fixed value determined depending on the embodiment.

[0047] As shown in Figure 8, the AGC bandwidth increases as the set output amplitude increases. Therefore, to maintain a constant AGC bandwidth, the larger the set amplitude, the greater the capacitance value of capacitive element C2 must be increased to lower the AGC bandwidth. The capacitance value of capacitive element C2 and the AGC bandwidth are inversely proportional, and the parasitic capacitance Cp does not change before or after compensation. Therefore, the capacitance value Cn (n is a positive integer) after compensation for each output amplitude setting can be calculated using equation (1).

[0048] Cn=(C2F+Cp)·Fn / Ftarget-Cp ‥(1) In equation (1), when the value of the AGC band Fn is equal to the fixed band Ftarget, Cn = C2F. Also, when the value of the AGC band Fn is greater than the fixed band Ftarget, Cn is greater than C2F, and when the value of the AGC band Fn is smaller than the fixed band Ftarget, Cn is smaller than C2F.

[0049] Figure 3 shows Cn calculated using equation (1). The four points in Figure 3 correspond to the four points in Figure 8. The compensated capacitance value Cn is the sum of the capacitance value C(n-1) of the previous amplitude setting and the capacitance value C2,n when n is greater than 2, as shown below.

[0050] C2,1=C1 C2,2=C2-C2,1=C2-C1 C2,3=C3-(C2,1+C2,2)=C3-C2 ... C2,n=Cn-(C2,1+...+C2,(n-1))=Cn-C(n-1)

[0051] [Loop Gain of the First Embodiment] Fig. 4 is a characteristic diagram showing an example of the loop gain of the AGC loop according to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50 of Fig. 2. Fig. 4 shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (for example, -15 dBm).

[0052] The numbers at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in Figure 4 correspond to the magnitude of the amplitude that is set, and the larger the number, the larger the output amplitude setting signal OA that is supplied to the DAC 52 and the thermocode generation unit 53.

[0053] As described above, the AGC band can be determined as the frequency at which the gain is "1" (0 dB in decibels) in the loop gain characteristics of the AGC loop. For example, the appropriate range of the AGC band is 100 kHz to 1 MHz. In this embodiment, the capacitance value of the capacitive element C2 connected to the output node of the OTA 51 is changed according to the amplitude setting, so that the AGC band can be set to about 300 kHz regardless of the amplitude setting. 300 kHz is located near the center of the appropriate range of the AGC band, and desired communication performance can be ensured even when the optical input signal power fluctuates.

[0054] Fig. 5 is a characteristic diagram showing the characteristics shown in Fig. 4 as the AGC band relative to the output amplitude. As shown in Fig. 5, the AGC band can be made almost constant regardless of the amplitude set by the output amplitude setting signal OA.

[0055] As described above, in this embodiment, by changing the capacitance value of the capacitive element C2 connected to the output node of the OTA 51 according to the amplitude setting, the AGC band can be kept constant regardless of the set output amplitude. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting. As a result, sufficient communication performance can be ensured even when the optical input signal power fluctuates.

[0056] By connecting the capacitor C2 to the output node of the OTA 51 via a switch SW that is turned on and off in response to the output amplitude setting signal OA, the accumulated charge can be changed according to the set amplitude. This makes it possible to compensate for fluctuations in the AGC band caused by the amplitude setting. By generating an output signal X[2:0] that indicates a thermocode in response to the output amplitude setting signal OA, a capacitance value corresponding to the output amplitude setting signal OA can be stably set at the output of the OTA 51, without being affected by the on / off timing of the output signal X[2:0].

[0057] By supplying the offset current Ioffset to the connection node of the resistor elements R53 and R54 of the differential amplifier circuit, the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal OA can be reflected in the output of the differential amplifier circuit, thereby setting the amplitude of the differential voltage signals IP and IN to the amplitude indicated by the output amplitude setting signal OA.

[0058] [Other AGC control circuit configurations] Figure 6 is a circuit diagram showing another example of the configuration of an AGC control circuit mounted on the transimpedance amplifier circuit 100 of Figure 1. Elements similar to those in Figure 2 are given the same reference numerals, and detailed description will be omitted. An AGC control circuit 50A shown in Figure 6 is mounted on the transimpedance amplifier circuit 100 shown in Figure 1, in place of the AGC control circuit 50 of Figure 1.

[0059] The AGC control circuit 50A has the thermocode generation unit 53 and switch SW removed from the AGC control circuit 50 in Fig. 2, and has a capacitance element C2 instead of capacitance elements C2,1 to C2,n. The other configuration of the AGC control circuit 50A is the same as that of the AGC control circuit 50 in Fig. 2. The AGC control circuit 50A operates in the same manner as the AGC control circuit 50 in Fig. 2, except that the capacitance value is not adjusted by the output amplitude setting signal OA.

[0060] [Loop gain of other AGC control circuits] Fig. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50A of Fig. 6. Fig. 7 corresponds to Fig. 4, and shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (for example, -15 dBm).

[0061] If the capacitance value is not adjusted using the output amplitude setting signal OA, the AGC band fluctuates according to the set output amplitude. In Figure 7, the AGC band fluctuates from about 180 kHz to about 1 MHz, which is a small margin relative to the appropriate range of 100 kHz to 1 MHz. Therefore, if the optical input signal power fluctuates, there is a risk that the desired communication performance cannot be ensured.

[0062] Fig. 8 is a characteristic diagram showing the characteristics shown in Fig. 7 as the AGC band relative to the output amplitude. In Fig. 8, the AGC band varies depending on the amplitude set by the output amplitude setting signal OA.

[0063] [Characteristics when feedback function is disabled] 9 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit 100 and the differential voltage PH-AH between the amplitude detection signal PH and the amplitude reference signal AH when negative feedback by the AGC control circuit of FIG. 2 or 6 is disabled. As shown in FIG. 9, when negative feedback is disabled, the differential voltage PH-AH increases nonlinearly, in a bow shape, as the set amplitude increases. When the reference voltage Vref is set to the average value of the differential voltage signals IP and IN in the setting circuit of the AGC control circuit 50, the differential voltage PH-AH becomes a voltage corresponding to the amplitude (half the peak-to-peak value) of the differential voltage signals IP and IN.

[0064] The change in AGC bandwidth shown in Figure 8 occurs because the AGC loop gain varies with the amplitude setting, and is due to two main reasons. First, because the TIA 10 and VGA 20 are included in the AGC loop, fluctuations in the gain of the TIA 10 and VGA 20 due to AGC control cause the AGC loop gain to fluctuate. Second, the transistors Q1P and Q1N (e.g., HBTs) in Figures 2 and 6 have diode characteristics between their bases and emitters, resulting in nonlinear input characteristics. For example, the nonlinear relationship between the differential voltage PH-AH and the actual output amplitude in Figure 9 is due to the nonlinear characteristics of the transistors Q1P and Q1N.

[0065] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These changes also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0066] 10 TIA 20 VGA 30 BUF 40 CML 50, 50A AGC control circuit 51 OTA 52 DAC 53 Thermocode generator 54 Gain control section 100 Transimpedance amplifier circuit AH Amplitude Reference Signal C2 Capacitor element C51, C52 capacitance elements CNTL1-CNTL4 control signals I51, I52, I53 current source InN, InP input terminal IN, IP voltage signal M1N, M1P transistors OA output amplitude setting signal OutN, OutP output terminals PH amplitude detection signal Q1N, Q1P transistors Q2 transistor R11, R12 resistor elements R51, R52, R53, R54, R55, R56 resistor elements SW switch VIN, VIP voltage signals Vref Reference voltage

Claims

1. an amplifier circuit that amplifies an input current signal in accordance with a gain set by a control signal and converts the input current signal into a voltage signal; a gain control circuit that generates the control signal in response to the amplitude of the voltage signal; Equipped with The gain control circuit a detection circuit for generating an amplitude detection signal in accordance with the amplitude of the voltage signal; a setting circuit for generating an amplitude reference signal in response to a reference voltage; a differential amplifier circuit that generates a differential voltage by adding an offset voltage generated in accordance with an output amplitude setting signal to a differential signal that is generated by amplifying a difference between a voltage of the amplitude detection signal and a voltage of the amplitude reference signal; a voltage-controlled current source circuit that generates a differential current signal based on the differential voltage; a variable capacitance circuit connected to the output of the voltage controlled current source circuit, having a capacitance value set in accordance with the output amplitude setting signal, and charged and discharged by the differential current signal; Equipped with the gain control circuit generates the control signal in response to a charging voltage of the variable capacitance circuit; the offset voltage increases as the output amplitude setting signal increases, the amplitude of the voltage signal is set to be smaller when the output amplitude setting signal is smaller, and is set to be larger when the output amplitude setting signal is larger; the differential current signal decreases as the differential voltage increases, and increases as the differential voltage decreases; the capacitance value monotonically increases as the output amplitude setting signal increases, and monotonically decreases as the output amplitude setting signal decreases; Transimpedance amplifier circuit.

2. The gain control circuit a switch control unit that generates a switch control signal in response to the output amplitude setting signal; the variable capacitance circuit has a plurality of capacitance elements connected to the output of the voltage controlled current source circuit via switches that are turned on and off in response to the switch control signal, The switch control section generates the switch control signal such that the number of the capacitance elements connected to the output of the voltage controlled current source circuit increases as the amplitude indicated by the output amplitude setting signal increases.

2. The transimpedance amplifier circuit of claim 1.

3. The switch control unit generates the switch control signal so that, when the digital value of the output amplitude setting signal increases by 1, only one of the switches that are in an off state and that connect and disconnect the plurality of capacitive elements is turned on.

3. The transimpedance amplifier circuit according to claim 2.

4. the gain control circuit further includes a current generating unit that generates an offset current according to a value indicated by the output amplitude setting signal; the differential amplifier circuit includes a first transistor electrically connected to the detection circuit, a first resistor element electrically connected to the first transistor, and a second resistor element connected between the first resistor element and a ground line; the offset voltage is generated by the offset current flowing through the second resistor element. The transimpedance amplifier circuit according to any one of claims 1 to 3.

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