Rail-to-rail amplifier circuit

Abstract

The invention provides a rail-to-rail amplifier circuit, which comprises a detection unit configured to respond to a power supply voltage, a first driving signal and a second driving signal, and generate a feedback control voltage based on voltages corresponding to the first driving signal and the second driving signal when being gated; the substrate potential generation unit is configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage; the amplification unit is provided with a first differential module, a second differential module and an amplification module, and the first differential module is configured to output a first differential signal according to the first driving signal, the second driving signal and the first potential signal; the second differential module is configured to output a second differential signal according to the first driving signal, the second driving signal and a second potential signal; the amplification module is configured to be based on the first differential signal or the second differential signal. By adopting the technical scheme, the flatness of the gain in the whole input voltage range can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a rail-to-rail amplifier circuit. Background Art

[0002] Rail-to-rail amplifiers (Rail-to-Rail Operational Amplifiers) are able to process signals over the entire supply voltage range and are crucial in low-voltage, single-supply systems.

[0003] However, when the input or output stage of a rail-to-rail amplifier switches between operating regions under varying common-mode input voltages or load conditions, the open-loop gain often varies significantly. This gain instability introduces nonlinear errors, severely impacting signal amplification accuracy. Therefore, achieving constant high gain across the entire input / output range is a core challenge and a key requirement in high-performance rail-to-rail amplifier design. Summary of the Invention

[0004] In view of this, the present invention provides a rail-to-rail amplifier circuit, which can ensure gain flatness in the entire input voltage range and improve the linearity and accuracy of a device applied to the rail-to-rail amplifier circuit.

[0005] The present invention provides a rail-to-rail amplifier circuit, comprising: a detection unit configured to generate a feedback control voltage based on voltages corresponding to the first drive signal and the second drive signal, respectively, in response to a power supply voltage, a first drive signal, and a second drive signal when the detection unit is enabled; a substrate potential generating unit, coupled to the detection unit, and configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage; wherein the preset voltage is determined by the power supply voltage; An amplification unit is coupled to the substrate potential generating unit and has a first differential module, a second differential module and an amplification module, wherein the first differential module is configured to output a first differential signal to the amplification module according to the first drive signal, the second drive signal and the first potential signal; the second differential module is configured to output a second differential signal to the amplification module according to the first drive signal, the second drive signal and the second potential signal; and the amplification module is configured to generate and output an amplified signal for the first differential signal or the second differential signal.

[0006] Optionally, the detection unit includes: a common mode input module, wherein a first input terminal of the common mode input module inputs the first drive signal, and a second input terminal of the common mode input module inputs the second drive signal, and when the common mode input module is enabled, a differential current signal is generated; a mirror module, coupled to the common mode input module and inputting the power supply voltage and the first bias voltage, and configured to perform mirror processing on the differential current signal; a conversion module, coupled to the mirror module and the common mode input module respectively, and configured to convert the type of the differential current signal to generate the feedback control voltage; The tail current source providing module is coupled to the common mode input module and is configured to provide a tail current corresponding to a second bias voltage to the common mode input module.

[0007] Optionally, the detection unit satisfies one or more of the following requirements: The common-mode input module includes: a first transistor and a second transistor, wherein a control terminal of the first transistor inputs the first drive signal, a first terminal of the first transistor is coupled to the mirror module and the conversion module respectively, a second terminal of the first transistor is coupled to the tail current source providing module, a third terminal of the first transistor is coupled to the third terminal of the second transistor and is grounded; a control terminal of the second transistor inputs the second drive signal, a first terminal of the second transistor is coupled to the mirror module and the conversion module respectively, and a second terminal of the second transistor is coupled to the tail current source providing module; The mirror module includes a third transistor and a fourth transistor, wherein a control terminal of the third transistor is coupled to a control terminal of the fourth transistor and connected to the first bias voltage, a first terminal and a third terminal of the third transistor are coupled to a first terminal and a third terminal of the fourth transistor and connected to the power supply voltage, a second terminal of the third transistor is coupled to the common-mode input module and the conversion module respectively; and a second terminal of the fourth transistor is coupled to the common-mode input module and the conversion module respectively. The conversion module includes a first resistor and a second resistor, wherein a first end of the first resistor is coupled to the mirror module and the common-mode input module respectively, and a second end of the first resistor is coupled to the second end of the second resistor and serves as an output end; a first end of the second resistor is coupled to the mirror module and the common-mode input module respectively; The tail current source providing module includes a fifth transistor, the control end of the fifth transistor inputs the second bias voltage, the first end of the fifth transistor is coupled to the common mode input module, the second end and the third end of the fifth transistor are coupled and grounded.

[0008] Optionally, the substrate potential generating unit includes: a first comparison module, coupled to the detection unit and the first differential module respectively, and configured to generate the first potential signal according to the feedback control voltage and a first preset voltage, where the first preset voltage is determined by the power supply voltage; a second comparison module, coupled to the detection unit and the second difference module respectively, and configured to generate the second potential signal according to the feedback control voltage and a second preset voltage, where the second preset voltage is determined by the power supply voltage; The first preset voltage and the second preset voltage are the same and are the preset voltages.

[0009] Optionally, the first comparison module includes: a first voltage divider branch consisting of a third resistor and a fourth resistor, and a first comparator, wherein the first end of the third resistor is input with the power supply voltage, the second end of the third resistor is coupled to the first end of the fourth resistor and the first input end of the first comparator, respectively; the second end of the fourth resistor is grounded; the second input end of the first comparator is input with the feedback control voltage, and the output end of the first comparator outputs the first potential signal; the third resistor and the fourth resistor have the same resistance value; The second comparison module includes: a second voltage divider branch composed of a fifth resistor and a sixth resistor, and a second comparator, the first end of the fifth resistor inputs the power supply voltage, the second end of the fifth resistor is coupled to the first end of the sixth resistor and the first input end of the second comparator, respectively; the second end of the sixth resistor is grounded; the second input end of the second comparator inputs the feedback control voltage, and the output end of the second comparator outputs the second potential signal; the fifth resistor and the sixth resistor have the same resistance value.

[0010] Optionally, the first differential module and the second differential module use transistors of different types, and within the working range of the amplifying unit, the first differential module and the second differential module are turned on in a time-sharing manner.

[0011] Optionally, the first differential module includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein the control terminal of the sixth transistor inputs the first drive signal, the first terminal of the sixth transistor is coupled to the amplifying unit, the second terminal of the sixth transistor is coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor, respectively, the third terminal of the sixth transistor is coupled to the third terminal of the seventh transistor, and is connected to the first potential signal; the control terminal of the seventh transistor inputs the second drive signal, the first terminal of the seventh transistor is coupled to the amplifying unit; the input terminal of the eighth transistor inputs the third bias voltage, the second terminal of the eighth transistor is coupled to the third terminal, and is grounded; The second differential module includes: a ninth transistor, a tenth transistor, and an eleventh transistor, the control end of the ninth transistor inputs the second drive signal, the first end of the ninth transistor is coupled to the second end of the eleventh transistor and the first end of the tenth transistor respectively, the second end of the ninth transistor is coupled to the amplification unit, the third end of the ninth transistor is coupled to the third end of the tenth transistor, and inputs the second potential signal; the control end of the tenth transistor inputs the first drive signal, the second end of the tenth transistor is coupled to the amplification unit; the control end of the eleventh transistor inputs the fourth bias voltage, the first end and the third end of the eleventh transistor are coupled, and inputs the power supply voltage.

[0012] Optionally, the sixth transistor, the seventh transistor and the eighth transistor are one of a PMOS transistor and an NMOS transistor, and the ninth transistor, the tenth transistor and the eleventh transistor are the other of a PMOS transistor and an NMOS transistor.

[0013] Optionally, the amplification module includes: a first amplifying branch, coupled to the first differential module, and configured to amplify the first differential signal to generate the amplified signal when the first differential module is enabled; The second amplifying branch is coupled to the second differential module and is configured to amplify the second differential signal to generate the amplified signal when the second differential module is enabled; wherein the second amplifying branch and the first amplifying branch share an output node.

[0014] Optionally, the first amplifying branch includes a first cascode structure circuit consisting of a twelfth transistor and a thirteenth transistor, and a second cascode structure circuit consisting of a fourteenth transistor and a fifteenth transistor, wherein the control terminals of the twelfth transistor and the thirteenth transistor are coupled and input with a fifth bias voltage, the first terminal and the third terminal of the twelfth transistor and the thirteenth transistor are coupled, and are coupled with the third terminals of the fourteenth transistor and the fifteenth transistor, the second terminal of the twelfth transistor is coupled with the first terminal of the fourteenth transistor and the output terminal of the first differential module; the second terminal of the thirteenth transistor is coupled with the first terminal of the fifteenth transistor and the output terminal of the first differential module respectively; the control terminals of the fourteenth transistor and the fifteenth transistor are coupled and input with a sixth bias voltage; the second terminal of the fourteenth transistor is coupled with the second amplifying branch; and the second terminal of the fifteenth transistor serves as the output node; The second amplifying branch includes a third cascode structure circuit consisting of a sixteenth transistor and a seventeenth transistor, and a fourth cascode structure circuit consisting of an eighteenth transistor and a nineteenth transistor. The control ends of the sixteenth transistor and the seventeenth transistor are coupled and input with a seventh bias voltage. The first end of the sixteenth transistor is coupled to the first amplifying branch, the control ends of the eighteenth transistor and the nineteenth transistor, respectively. The second end of the sixteenth transistor is coupled to the first end of the eighteenth transistor and the output end of the second differential module, respectively. It is also coupled to the third ends of the eighteenth transistor, the nineteenth transistor and the seventeenth transistor, and the second ends of the eighteenth transistor and the nineteenth transistor, and is grounded. The first end of the seventeenth transistor serves as an output node, and the second end of the seventeenth transistor is coupled to the first end of the nineteenth transistor and the output end of the second differential module, respectively.

[0015] Compared with the prior art, the technical solution of the embodiment of the invention has the following advantages: In the rail-to-rail amplifier circuit provided by an embodiment of the present invention, the detection unit can respond in real time to the voltages corresponding to the first drive signal and the second drive signal, respectively, to generate a feedback control voltage to the substrate potential generating unit. In this way, the potentials of the first potential signal and the second potential signal can be adjusted in real time through the substrate potential generating unit. The first differential module and the second differential module are based on the first drive signal, the second drive signal, the first potential signal, and the second potential signal, so that the first potential signal and the second potential signal can act on the amplification process. This feedback mechanism can ensure gain flatness across the entire input voltage range, thereby improving the linearity and accuracy of the device applied to the rail-to-rail amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0017] Figure 1 A schematic structural diagram of a rail-to-rail amplifier is shown; Figure 2 shows a gain diagram of a rail-to-rail amplifier; Figure 3 A schematic structural diagram of a rail-to-rail amplifier circuit according to an embodiment of the present invention is shown; Figure 4 A schematic structural diagram of a detection unit according to an embodiment of the present invention is shown; Figure 5 A schematic structural diagram of a substrate potential generating unit according to an embodiment of the present invention is shown; Figure 6 A schematic diagram showing changes in the output signal of the substrate potential generating unit in an embodiment of the present invention is shown; Figure 7 A schematic diagram of the specific structure of an amplifying unit in an embodiment of the present invention is shown; Figure 8 A gain diagram of a rail-to-rail amplifier circuit in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0019] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it may be directly coupled or connected to the other element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0020] In the present invention, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. In a P-type MOSFET, the first current terminal, the second current terminal, and the control terminal are the source, the drain, and the gate, respectively, and the third terminal is the substrate. In an N-type MOSFET, the first current terminal, the second current terminal, and the control terminal are the drain, the source, and the gate, respectively, and the third terminal is the substrate.

[0021] As described in the background art, the gain of existing rail-to-rail amplifiers is non-constant, which may introduce nonlinear errors and seriously affect the accuracy of signal amplification.

[0022] See also Figure 1 A schematic diagram of the structure of a rail-to-rail amplifier is shown in FIG. Figure 1 As shown, Figure 1As shown, the rail-to-rail amplifier in the existing solution adds an NMOS input pair (i.e., NMOS transistors NM1, NM2, and NM3) to the traditional PMOS input pair (i.e., PMOS transistors PM1, PM2, and PM3). The PMOS input pair controls two sets of cascode circuits consisting of NMOS transistors NM4, NM5, NM6, and NM7, while the NMOS input pair controls two sets of cascode circuits consisting of PMOS transistors M4, M5, M6, and M7, to achieve time-sharing output of the amplified voltage Vout.

[0023] However, see Figure 2 The gain diagram of a rail-to-rail amplifier is shown in Figure 2 As shown in FIG, since the amplification regions of the NMOS transistor and the PMOS transistor have overlapping gains near VDD / 2 (eg, the gain gmn of the NMOS transistor and the gain gmp of the PMOS transistor), the amplifier gain is not flat.

[0024] To address the above-mentioned technical problems, the present invention provides a rail-to-rail amplifier circuit, in which a detection unit can respond in real time to the voltages corresponding to the first drive signal and the second drive signal, respectively, to generate a feedback control voltage to the substrate potential generating unit. In this way, the potentials of the first potential signal and the second potential signal can be adjusted in real time by the substrate potential generating unit. The first differential module and the second differential module, in turn, are based on the first drive signal, the second drive signal, the first potential signal, and the second potential signal, so that the first potential signal and the second potential signal can act on the amplification process. This feedback mechanism can ensure gain flatness across the entire input voltage range, thereby improving the linearity and accuracy of devices applied to the rail-to-rail amplifier circuit.

[0025] In order to enable those skilled in the art to better understand and implement the present disclosure, the specific schemes, principles, advantages and effects of the present invention are described in detail below through specific embodiments with reference to the accompanying drawings.

[0026] See also Figure 3 The schematic diagram of the structure of a rail-to-rail amplifier circuit in an embodiment of the present invention is shown in FIG. Figure 3 As shown, a rail-to-rail amplifier circuit may include: The detection unit 110 is configured to generate a feedback control voltage Vc based on voltages corresponding to the first drive signal Vp and the second drive signal Vn, respectively, in response to a power supply voltage VDD, a first drive signal Vp, and a second drive signal Vn when the detection unit 110 is enabled; The substrate potential generating unit 120 is coupled to the detection unit 110 and is configured to generate a first potential signal S1 and a second potential signal S2 according to the feedback control voltage Vc and a preset voltage Vth; wherein the preset voltage Vth is determined by the power supply voltage VDD; The amplification unit 130 is coupled to the substrate potential generating unit 120, and has a first differential module 131, a second differential module 132 and an amplification module 133, wherein the first differential module 131 is configured to output a first differential signal to the amplification module 133 according to the first drive signal Vp, the second drive signal Vn and the first potential signal S1; the second differential module 132 is configured to output a second differential signal to the amplification module according to the first drive signal Vp, the second drive signal Vn and the second potential signal S2; the amplification module 133 is configured to generate an amplified signal Vout for the first differential signal or the second differential signal and output it.

[0027] Combine Figure 3 , briefly explain the working principle of the rail-to-rail amplifier circuit in this scheme: The detection unit 110 can generate a feedback control voltage Vc to the substrate potential generating unit 120 in real time in response to the voltages corresponding to the first driving signal Vp and the second driving signal Vn.

[0028] The potentials of the first potential signal S1 and the second potential signal S2 can be adjusted in real time through the substrate potential generating unit 120. The first differential module 131 is enabled based on the first drive signal Vp, the second drive signal Vn, and the first potential signal S1, and the second differential module 132 is enabled based on the first drive signal Vp, the second drive signal Vn, and the second potential signal S2, so that the first potential signal S1 and the second potential signal S2 can act on the amplification process in a time-sharing manner.

[0029] In this way, when the first differential module 131 is enabled, the amplifying module 133 can amplify the first differential signal; and when the second differential module 132 is enabled, the amplifying module 133 can amplify the second differential signal to generate and output the amplified signal Vout.

[0030] Thus, through this feedback adjustment mechanism, gain flatness can be ensured in the entire input voltage range, thereby improving the linearity and accuracy of the device applied to the rail-to-rail amplifier circuit.

[0031] In some embodiments, combined Figure 3 , see Figure 4 The schematic diagram of the structure of a detection unit in an embodiment of the present invention is shown in FIG. Figure 4 As shown, the detection unit 110 may include: a common-mode input module 111 , wherein a first input terminal of the common-mode input module 111 inputs the first drive signal Vp, and a second input terminal of the common-mode input module 111 inputs the second drive signal Vn, and when the common-mode input module 111 is enabled, a differential current signal is generated; The mirror module 112 is coupled to the common mode input module 111 and inputs the power supply voltage VDD and the first bias voltage V bias11 , configured to perform mirror processing on the differential current signal; a conversion module 113 , coupled to the mirror module 112 and the common mode input module 111 , and configured to convert the type of the differential current signal to generate the feedback control voltage Vc; The tail current source providing module 114 is coupled to the common mode input module 111 and is configured to provide the common mode input module with a second bias voltage V bias12 The corresponding tail current.

[0032] In some embodiments, the detection unit 110 can determine the feedback control voltage Vc through the input first driving signal Vp and the second driving signal Vn.

[0033] The feedback control voltage Vc may be half of the sum of the voltages corresponding to the first drive signal Vp and the second drive signal Vn.

[0034] In some embodiments, the detection unit 110 may satisfy one or more of the following: The common-mode input module 111 includes: a first transistor NM11 and a second transistor NM112, the control end of the first transistor NM11 inputs the first drive signal Vp, the first end of the first transistor NM11 is coupled to the mirror module 112 and the conversion module 113 respectively, the second end of the first transistor NM11 is coupled to the tail current source providing module 114, the third end of the first transistor NM11 is coupled to the third end of the second transistor NM12 and is grounded; the control end of the second transistor NM12 inputs the second drive signal Vn, the first end of the second transistor NM12 is coupled to the mirror module 112 and the conversion module 113 respectively, and the second end of the second transistor NM12 is coupled to the tail current source providing module 114.

[0035] In other words, the first transistor NM11 and the second transistor NM112 serve as differential input transistors.

[0036] The mirror module 112 may include a third transistor PM11 and a fourth transistor PM12, wherein the control terminal of the third transistor PM11 is coupled to the control terminal of the fourth transistor PM12 and is connected to the first bias voltage V bias11The first end and the third end of the third transistor PM11 are coupled to the first end and the third end of the fourth transistor PM12, and are connected to the power supply voltage VDD. The second end of the third transistor PM11 is coupled to the common-mode input module 111 and the conversion module 113 respectively; the second end of the fourth transistor PM14 is coupled to the common-mode input module 111 and the conversion module 113 respectively.

[0037] In other words, the third transistor PM11 and the fourth transistor PM12 function as a current mirror.

[0038] The conversion module 113 may include a first resistor R1 and a second resistor R2, wherein the first end of the first resistor R1 is coupled to the mirror module 112 and the common-mode input module 111, respectively, and the second end of the first resistor R1 is coupled to the second end of the second resistor R2 and serves as an output end; the first end of the second resistor R2 is coupled to the mirror module 112 and the common-mode input module 111, respectively.

[0039] In other words, the first resistor R1 and the second resistor R2 can convert the mirror current into the feedback control voltage Vc.

[0040] In some embodiments, the resistance values ​​of the first resistor R1 and the second resistor R2 may be the same.

[0041] The tail current source providing module 114 may include a fifth transistor NM13, a control terminal of which inputs the second bias voltage V bias12 The first end of the fifth transistor NM13 is coupled to the common-mode input module 111 , and the second end and the third end of the fifth transistor NM13 are coupled to each other and grounded.

[0042] The total differential pair current provided by the fifth transistor NM13 enables the first transistor NM11 and the second transistor NM112 to operate at a static operating point.

[0043] In some embodiments, combined Figure 3 , see Figure 5 The schematic structural diagram of a substrate potential generating unit in an embodiment of the present invention is shown in FIG. Figure 5 As shown, the substrate potential generating unit 120 may include: a first comparison module 121, coupled to the detection unit 110 and the first difference module 131, and configured to generate the first potential signal S1 according to the feedback control voltage Vc and a first preset voltage Vth1, where the first preset voltage Vth1 is determined by the power supply voltage VDD; The second comparison module 122 is coupled to the detection unit 110 and the second difference module 132 respectively, and is configured to generate the second potential signal S2 according to the feedback control voltage Vc and a second preset voltage Vth2, where the second preset voltage Vth2 is determined by the power supply voltage VDD.

[0044] In other words, by providing the substrate potential generating unit 120 with the first comparison module 121 and the second comparison module 122 , the first potential signal S1 and the second potential signal S2 can be output respectively to drive the amplifying unit 130 in a time-sharing manner.

[0045] In some embodiments, the first preset voltage Vth1 and the second preset voltage Vth2 are the same and are the preset voltages.

[0046] In some embodiments, the first comparison module 121 may include: a first voltage divider branch composed of a third resistor R3 and a fourth resistor R4, and a first comparator 1211, the first end of the third resistor R3 is input with the power supply voltage VDD, the second end of the third resistor R3 is coupled to the first end of the fourth resistor R4 and the first input end of the first comparator 1211, respectively; the second end of the fourth resistor R4 is grounded; the second input end of the first comparator 1211 is input with the feedback control voltage Vc, and the output end of the first comparator outputs the first potential signal S1.

[0047] The third resistor R3 and the fourth resistor R4 have the same resistance value, that is, Vth1 = 0.5 VDD.

[0048] The second comparison module 122 may include: a second voltage divider branch composed of a fifth resistor R5 and a sixth resistor R6, and a second comparator 1221, the first end of the fifth resistor R5 is input with the power supply voltage VDD, the second end of the fifth resistor R5 is coupled to the first end of the sixth resistor R6 and the first input end of the second comparator 1221 respectively; the second end of the sixth resistor R6 is grounded; the second input end of the second comparator 1221 is input with the feedback control voltage Vc, and the output end of the second comparator 1221 outputs the second potential signal S2.

[0049] The fifth resistor R5 and the sixth resistor R6 have the same resistance value, that is, Vth2 = 0.5 VDD.

[0050] For further information, see Figure 6 FIG. 1 is a schematic diagram showing a change in an output signal of a substrate potential generating unit according to an embodiment of the present invention. Figure 6As shown, when the amplitude of the feedback control voltage Vc is low, the feedback control voltage Vc is less than the first preset voltage Vth1, and the amplitude of the first potential signal S1 output by the substrate potential generating unit is high, which will cause the gm of the NMOS tube in the first differential module 131 to decrease; when the feedback control voltage Vc is greater than the first preset voltage Vth1, the amplitude of the first potential signal S1 slowly decreases.

[0051] When the amplitude of the feedback control voltage Vc is low, the feedback control voltage Vc is less than the second preset voltage Vth2, and the amplitude of the second potential signal S2 output by the substrate potential generating unit is high, which will cause the gm of the PMOS tube in the second differential module 132 to decrease; when the feedback control voltage Vc is greater than the second preset voltage Vth2, the amplitude of the second potential signal S1 decreases rapidly.

[0052] In some embodiments, the first differential module 131 and the second differential module 132 use transistors of different types, and within the operating range of the amplifying unit 130 , the first differential module 131 and the second differential module 132 are turned on in a time-sharing manner.

[0053] Specifically, the first differential module 131 is composed of NMOS transistors, and the second differential module 131 is composed of PMOS transistors; or, the first differential module 131 is composed of PMOS transistors, and the second differential module 131 is composed of NMOS transistors.

[0054] In some embodiments, combined Figure 3 , see Figure 7 The specific structural diagram of an amplifying unit in an embodiment of the present invention is shown in FIG. Figure 7 As shown, the first difference module 131 may include: A sixth transistor NM14, a seventh transistor NM15, and an eighth transistor NM16, wherein a control terminal of the sixth transistor NM14 is input with the first drive signal Vp, a first terminal of the sixth transistor NM14 is coupled to the amplification module 133, a second terminal of the sixth transistor NM14 is coupled to the second terminal of the seventh transistor NM15 and the first terminal of the eighth transistor NM16, respectively, a third terminal of the sixth transistor NM14 is coupled to the third terminal of the seventh transistor NM15, and is connected to the first potential signal S1; a control terminal of the seventh transistor NM15 is input with the second drive signal Vn, a first terminal of the seventh transistor NM15 is coupled to the amplification module 133; an input terminal of the eighth transistor NM16 is input with the third bias voltage V bias13 The second terminal of the eighth transistor NM16 is coupled to the third terminal and grounded.

[0055] The second differential module 132 may include: a ninth transistor PM13, a tenth transistor PM14 and an eleventh transistor PM15, the control end of the ninth transistor PM13 inputs the second drive signal Vn, the first end of the ninth transistor PM13 is coupled to the second end of the eleventh transistor PM15 and the first end of the tenth transistor PM14 respectively, the second end of the ninth transistor PM13 is coupled to the amplification module 133, the third end of the ninth transistor PM13 is coupled to the third end of the tenth transistor PM14, and inputs the second potential signal S2; the control end of the tenth transistor PM14 inputs the first drive signal Vp, the second end of the tenth transistor PM14 is coupled to the amplification module 133; the control end of the eleventh transistor PM14 inputs the fourth bias voltage V bias14 The first terminal and the third terminal of the eleventh transistor PM15 are coupled to each other and input the power supply voltage VDD.

[0056] In some embodiments, the sixth transistor NM14 , the seventh transistor NM15 , and the eighth transistor NM16 are one of PMOS transistors and NMOS transistors, and the ninth transistor PM13 , the tenth transistor PM14 , and the eleventh transistor PM15 are the other of PMOS transistors and NMOS transistors.

[0057] In the present invention, the sixth transistor NM14 , the seventh transistor NM15 , and the eighth transistor NM16 are NMOS transistors, and the ninth transistor PM13 , the tenth transistor PM14 , and the eleventh transistor PM15 are NMOS transistors.

[0058] See next Figure 7 , the amplification module 133 may include: a first amplification branch ( Figure 7 not marked), coupled to the first differential module 131, and configured to amplify the first differential signal to generate the amplified signal Vout when the first differential module 131 is enabled; The second amplifying branch ( Figure 7 not marked), coupled to the second differential module 132, and configured to amplify the second differential signal to generate the amplified signal Vout when the second differential module 132 is enabled; wherein the second amplifying branch and the first amplifying branch share an output node.

[0059] In some embodiments, the first amplifying branch includes a first cascode structure circuit composed of a twelfth transistor PM16 and a thirteenth transistor PM17, and a second cascode structure circuit composed of a fourteenth transistor PM18 and a fifteenth transistor PM19, wherein the control terminals of the twelfth transistor PM16 and the thirteenth transistor PM17 are coupled and input with a fifth bias voltage V bias15 The first and third terminals of the twelfth transistor PM16 and the thirteenth transistor PM17 are coupled, and are coupled to the third terminals of the fourteenth transistor PM18 and the fifteenth transistor PM19. The second terminal of the twelfth transistor PM16 is coupled to the first terminal of the fourteenth transistor PM18 and the output terminal of the first differential module 131. The second terminal of the thirteenth transistor PM17 is coupled to the first terminal of the fifteenth transistor PM19 and the output terminal of the first differential module 131 respectively. The control terminals of the fourteenth transistor PM18 and the fifteenth transistor PM19 are coupled, and a sixth bias voltage V is input. bias16 The second end of the fourteenth transistor PM18 is coupled to the second amplifying branch; the second end of the fifteenth transistor PM19 serves as the output node.

[0060] The second amplifying branch includes a third cascode structure circuit composed of a sixteenth transistor NM17 and a seventeenth transistor NM18, and a fourth cascode structure circuit composed of an eighteenth transistor NM19 and a nineteenth transistor NM20. The control terminals of the sixteenth transistor NM17 and the seventeenth transistor NM18 are coupled and input with a seventh bias voltage V bias17 The first ends of the sixteenth transistor NM17 and the seventeenth transistor NM18 are respectively coupled to the control ends of the first amplifying branch, the eighteenth transistor NM19, and the nineteenth transistor NM20. The second end of the sixteenth transistor NM17 is respectively coupled to the first end of the eighteenth transistor NM19 and the output end of the second differential module 132. The third ends of the sixteenth transistor NM17, the eighteenth transistor NM19, the nineteenth transistor NM20, and the seventeenth transistor NM18, and the second ends of the eighteenth transistor NM19 and the nineteenth transistor NM20 are respectively coupled and grounded. The first end of the seventeenth transistor NM18 serves as an output node. The second end of the seventeenth transistor NM18 is respectively coupled to the first end of the nineteenth transistor NM20 and the output end of the second differential module 132.

[0061] Therefore, by using the rail-to-rail amplifier circuit in the above example, it is possible to ensure gain flatness over the entire input voltage range, thereby improving the linearity and accuracy of a device to which the rail-to-rail amplifier circuit is applied.

[0062] For example, see Figure 8 FIG. 1 is a schematic diagram showing a gain of a rail-to-rail amplifier circuit according to an embodiment of the present invention. Figure 8 As shown, since the gains of the amplification regions of the NMOS transistor and the PMOS transistor (eg, the gain gmn of the NMOS transistor and the gain gmp of the PMOS transistor) overlap less near VDD / 2, the amplifier gain is flatter.

[0063] It can be understood that the above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined with each other and cross-referenced without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as disclosed and disclosed embodiment schemes of the present disclosure.

[0064] Although the embodiments of the present disclosure are disclosed above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A rail-to-rail amplifier circuit, characterized in that: include: a detection unit configured to generate a feedback control voltage based on voltages corresponding to the first drive signal and the second drive signal, respectively, in response to a power supply voltage, a first drive signal, and a second drive signal when the detection unit is enabled; a substrate potential generating unit, coupled to the detection unit, and configured to generate a first potential signal and a second potential signal according to the feedback control voltage and a preset voltage; wherein the preset voltage is determined by the power supply voltage; An amplification unit is coupled to the substrate potential generating unit and has a first differential module, a second differential module and an amplification module, wherein the first differential module is configured to output a first differential signal to the amplification module according to the first drive signal, the second drive signal and the first potential signal; the second differential module is configured to output a second differential signal to the amplification module according to the first drive signal, the second drive signal and the second potential signal; and the amplification module is configured to generate and output an amplified signal for the first differential signal or the second differential signal.

2. The rail-to-rail amplifier circuit according to claim 1, wherein: The detection unit comprises: a common-mode input module, wherein a first input terminal of the common-mode input module inputs the first driving signal, and a second input terminal of the common-mode input module inputs the second driving signal, and when the common-mode input module is enabled, a differential current signal is generated; a mirror module, coupled to the common mode input module and inputting the power supply voltage and the first bias voltage, and configured to perform mirror processing on the differential current signal; a conversion module, coupled to the mirror module and the common mode input module respectively, and configured to convert the type of the differential current signal to generate the feedback control voltage; The tail current source providing module is coupled to the common mode input module and is configured to provide a tail current corresponding to a second bias voltage to the common mode input module.

3. The rail-to-rail amplifier circuit according to claim 2, wherein: The detection unit satisfies one or more of the following: The common-mode input module includes: a first transistor and a second transistor, wherein a control terminal of the first transistor inputs the first drive signal, a first terminal of the first transistor is coupled to the mirror module and the conversion module respectively, a second terminal of the first transistor is coupled to the tail current source providing module, a third terminal of the first transistor is coupled to the third terminal of the second transistor and is grounded; a control terminal of the second transistor inputs the second drive signal, a first terminal of the second transistor is coupled to the mirror module and the conversion module respectively, and a second terminal of the second transistor is coupled to the tail current source providing module; The mirror module includes: a third transistor and a fourth transistor, wherein a control terminal of the third transistor is coupled to a control terminal of the fourth transistor and connected to the first bias voltage, a first terminal and a third terminal of the third transistor are coupled to a first terminal and a third terminal of the fourth transistor and connected to the power supply voltage, a second terminal of the third transistor is coupled to the common mode input module and the conversion module respectively; and a second terminal of the fourth transistor is coupled to the common mode input module and the conversion module respectively. The conversion module includes: a first resistor and a second resistor, wherein a first end of the first resistor is coupled to the mirror module and the common mode input module respectively, and a second end of the first resistor is coupled to the second end of the second resistor and serves as an output end; a first end of the second resistor is coupled to the mirror module and the common mode input module respectively; The tail current source providing module includes: a fifth transistor, the control end of the fifth transistor inputs the second bias voltage, the first end of the fifth transistor is coupled to the common mode input module, the second end and the third end of the fifth transistor are coupled and grounded.

4. The rail-to-rail amplifier circuit according to claim 1, wherein: The substrate potential generating unit includes: a first comparison module, coupled to the detection unit and the first differential module respectively, and configured to generate the first potential signal according to the feedback control voltage and a first preset voltage, where the first preset voltage is determined by the power supply voltage; a second comparison module, coupled to the detection unit and the second difference module respectively, and configured to generate the second potential signal according to the feedback control voltage and a second preset voltage, where the second preset voltage is determined by the power supply voltage; The first preset voltage and the second preset voltage are the same and are the preset voltages.

5. The rail-to-rail amplifier circuit according to claim 4, wherein: The first comparison module includes: a first voltage divider branch composed of a third resistor and a fourth resistor, and a first comparator, wherein a first end of the third resistor is input with the power supply voltage, a second end of the third resistor is coupled to the first end of the fourth resistor and the first input end of the first comparator, respectively; a second end of the fourth resistor is grounded; a second input end of the first comparator is input with the feedback control voltage, and an output end of the first comparator outputs the first potential signal; the third resistor and the fourth resistor have the same resistance value; The second comparison module includes: a second voltage divider branch composed of a fifth resistor and a sixth resistor, and a second comparator, the first end of the fifth resistor inputs the power supply voltage, the second end of the fifth resistor is coupled to the first end of the sixth resistor and the first input end of the second comparator, respectively; the second end of the sixth resistor is grounded; the second input end of the second comparator inputs the feedback control voltage, and the output end of the second comparator outputs the second potential signal; the fifth resistor and the sixth resistor have the same resistance value.

6. The rail-to-rail amplifier circuit according to claim 1, wherein: The first differential module and the second differential module use transistors of different types, and within the working range of the amplifying unit, the first differential module and the second differential module are turned on in a time-sharing manner.

7. The rail-to-rail amplifier circuit according to claim 1 or 6, characterized in that: The first differential module includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein the control terminal of the sixth transistor inputs the first drive signal, the first terminal of the sixth transistor is coupled to the amplifying unit, the second terminal of the sixth transistor is coupled to the second terminal of the seventh transistor and the first terminal of the eighth transistor, respectively, the third terminal of the sixth transistor is coupled to the third terminal of the seventh transistor, and is connected to the first potential signal; the control terminal of the seventh transistor inputs the second drive signal, the first terminal of the seventh transistor is coupled to the amplifying unit; the input terminal of the eighth transistor inputs the third bias voltage, the second terminal of the eighth transistor is coupled to the third terminal, and is grounded; The second differential module includes: a ninth transistor, a tenth transistor, and an eleventh transistor, the control end of the ninth transistor inputs the second drive signal, the first end of the ninth transistor is coupled to the second end of the eleventh transistor and the first end of the tenth transistor respectively, the second end of the ninth transistor is coupled to the amplification unit, the third end of the ninth transistor is coupled to the third end of the tenth transistor, and inputs the second potential signal; the control end of the tenth transistor inputs the first drive signal, the second end of the tenth transistor is coupled to the amplification unit; the control end of the eleventh transistor inputs the fourth bias voltage, the first end and the third end of the eleventh transistor are coupled, and inputs the power supply voltage.

8. The rail-to-rail amplifier circuit according to claim 7, wherein: The sixth transistor, the seventh transistor, and the eighth transistor are one of a PMOS transistor and an NMOS transistor, and the ninth transistor, the tenth transistor, and the eleventh transistor are the other of a PMOS transistor and an NMOS transistor.

9. The rail-to-rail amplifier circuit according to claim 1, wherein: The amplification module includes: a first amplifying branch, coupled to the first differential module, and configured to amplify the first differential signal to generate the amplified signal when the first differential module is enabled; The second amplifying branch is coupled to the second differential module and is configured to amplify the second differential signal to generate the amplified signal when the second differential module is enabled; wherein the second amplifying branch and the first amplifying branch share an output node.

10. The rail-to-rail amplifier circuit according to claim 9, wherein: The first amplifying branch includes a first cascode structure circuit consisting of a twelfth transistor and a thirteenth transistor, and a second cascode structure circuit consisting of a fourteenth transistor and a fifteenth transistor. The control terminals of the twelfth transistor and the thirteenth transistor are coupled and input with a fifth bias voltage. The first and third terminals of the twelfth and thirteenth transistors are coupled and coupled with the third terminals of the fourteenth and fifteenth transistors. The second terminal of the twelfth transistor is coupled with the first terminal of the fourteenth transistor and the output terminal of the first differential module. The second terminal of the thirteenth transistor is coupled with the first terminal of the fifteenth transistor and the output terminal of the first differential module respectively. The control terminals of the fourteenth and fifteenth transistors are coupled and input with a sixth bias voltage. The second terminal of the fourteenth transistor is coupled with the second amplifying branch. The second terminal of the fifteenth transistor serves as the output node. The second amplifying branch includes a third cascode structure circuit consisting of a sixteenth transistor and a seventeenth transistor, and a fourth cascode structure circuit consisting of an eighteenth transistor and a nineteenth transistor. The control ends of the sixteenth transistor and the seventeenth transistor are coupled and input with a seventh bias voltage. The first end of the sixteenth transistor is coupled to the first amplifying branch, the control ends of the eighteenth transistor and the nineteenth transistor, respectively. The second end of the sixteenth transistor is coupled to the first end of the eighteenth transistor and the output end of the second differential module, respectively. It is also coupled to the third ends of the eighteenth transistor, the nineteenth transistor and the seventeenth transistor, and the second ends of the eighteenth transistor and the nineteenth transistor, and is grounded. The first end of the seventeenth transistor serves as an output node, and the second end of the seventeenth transistor is coupled to the first end of the nineteenth transistor and the output end of the second differential module, respectively.

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