Transimpedance Amplifier Circuit

Abstract

To provide a transimpedance amplifier circuit that prevents fluctuations of an AGC band due to amplitude setting.SOLUTION: A transimpedance amplifier circuit comprises: an amplifier circuit that amplifies an input current signal and converts it into a voltage signal according to a first gain set according to a control signal; and a gain control circuit that generates the control signal according to the amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude detection signal according to the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal according to a reference voltage, a differential voltage generation circuit that corrects the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal according to an output amplitude setting signal to generate a differential signal, a voltage control current source circuit that amplifies the voltage difference of the differential signal to generate a differential current signal according to a second gain set according to the output amplitude setting signal, and a capacitive element that is charged and discharged according to the differential current signal. The gain control circuit generates the control signal according to the charge voltage of the capacitive element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a transimpedance amplifier circuit. [Background technology]

[0002] In optical transmission systems, a wavelength division multiplexing system is known, in which an optical signal multiplexed with multiple optical signals having different wavelengths is transmitted and received using two optical fibers. Coherent reception is also known as a method for efficiently receiving multiplexed optical signals. For example, in an optical receiving device receiving one of the multiple optical signals (a single optical signal), an amplifier circuit that amplifies a current signal converted from the single optical signal includes a transimpedance amplifier and an AGC (Auto Gain Control) circuit that variably controls the gain of the transimpedance amplifier and keeps the amplitude of the amplified signal constant. This type of amplifier circuit is capable of outputting a linear output signal with a wide input dynamic range thanks to the variable gain function of the AGC circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 004828 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-220567 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-084474 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-217226 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when a setting signal that sets the amplitude of an output signal from an amplifier circuit is supplied to an AGC circuit, the loop gain and AGC band of the AGC circuit may fluctuate depending on the set amplitude. Here, the AGC band is calculated as the frequency when the gain of the loop gain characteristic of the AGC loop is "1" (0 dB in decibels).

[0005] Therefore, an object of the present disclosure is to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band caused by amplitude settings. [Means for solving the problem]

[0006] The transimpedance amplifier circuit of the present disclosure includes an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts the input current signal into a voltage signal, and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal, the gain control circuit including a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal in accordance with a reference voltage, and a difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal. is amplified and the resulting differential amplified signal is According to the output amplitude setting signal a differential amplifier circuit that generates a differential voltage by adding the generated offset voltage; The differential amplifier is configured to output a second gain set by the output amplitude setting signal. Voltage The voltage controlled current source circuit amplifies and generates a differential current signal, and a capacitance element is charged and discharged by the differential current signal, and the gain control circuit generates the control signal according to the charging voltage of the capacitance element. The offset voltage increases as the output amplitude setting signal increases, the amplitude of the voltage signal is set to decrease as the output amplitude setting signal decreases, and is set to increase as the output amplitude setting signal increases, the differential current signal decreases as the differential voltage increases, and is set to increase as the differential voltage decreases, and the second gain decreases as the output amplitude setting signal increases, and is set to increase as the output amplitude setting signal decreases. . [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude settings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to the first embodiment. [Figure 2]FIG. 2 is a circuit diagram showing an example of the AGC control circuit of FIG. [Figure 3] FIG. 3 is a circuit diagram illustrating an example of the OTA of FIG. [Figure 4] FIG. 4 is an explanatory diagram showing an example of a gain control voltage that is set in accordance with an amplitude setting signal. [Figure 5] FIG. 5 is a characteristic diagram showing an example of an output current output from an output terminal of an OTA in accordance with a set gain control voltage. [Figure 6] FIG. 6 is a circuit diagram illustrating an example of the gain control section of FIG. [Figure 7] FIG. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. [Figure 8] FIG. 8 is a characteristic diagram showing the characteristics shown in FIG. 7 as an AGC band relative to the output amplitude. [Figure 9] FIG. 9 is a circuit diagram showing another example of the configuration of the AGC control circuit mounted on the transimpedance amplifier circuit of FIG. [Figure 10] FIG. 10 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. [Figure 11] FIG. 11 is a characteristic diagram showing the characteristics shown in FIG. 10 as an AGC band with respect to the output amplitude. [Figure 12] FIG. 12 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit and the amplitude detection signal when the feedback function of the AGC control circuit in FIG. 2 or FIG. 9 is disabled. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A transimpedance amplifier circuit according to one aspect of the present disclosure includes an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts it into a voltage signal, and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal in accordance with a reference voltage, a differential voltage generation circuit that corrects the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal in accordance with an output amplitude setting signal to generate a differential signal, a voltage-controlled current source circuit that amplifies the voltage difference of the differential signals in accordance with a second gain set by the output amplitude setting signal to generate a differential current signal, and a capacitive element that is charged and discharged by the differential current signal, and the gain control circuit generates the control signal in accordance with the charging voltage of the capacitive element.

[0011] In this transimpedance amplifier circuit, the AGC band can be kept constant regardless of the amplitude of the set voltage signal. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting.

[0012] [2] In the above [1], the gain control circuit may further include a gain control section that generates a gain control voltage for setting a second gain in response to the output amplitude setting signal, and the voltage controlled current source circuit may include a pair of transistors that amplify the differential signal, and a variable resistor section that is connected between the drains of the pair of transistors and has a resistance value that changes in response to the gain control voltage. By changing the resistance value of the variable resistor section that is connected between the drains of the pair of transistors in response to the gain control voltage, the gain of the voltage controlled current source circuit can be changed in response to the gain control voltage by a simple means, and fluctuations in the AGC band due to amplitude setting can be compensated for.

[0013] [3] In the above [2], the gain control section may include a voltage output node that outputs the gain control voltage, a resistive element connected to the voltage output node, a plurality of current sources connected in parallel, a thermocode generation section that generates an output signal according to the value of the output amplitude setting signal, and a switch that changes the number of the plurality of current sources connected to the voltage output node according to the output signal, wherein the gain control voltage is generated when currents supplied by the plurality of current sources connected to the voltage output node via the switch flow into the resistive element, and the output signal may increase or decrease the number of the plurality of current sources connected to the voltage output node by one when the value of the output amplitude setting signal increases or decreases by one. This makes it possible to generate a gain control voltage according to the output amplitude setting signal using a simple means.

[0014] [4] In any one of [1] to [3] above, the differential voltage generation circuit may include a current generation unit that generates an offset current corresponding to a value indicated by the output amplitude setting signal, and a differential amplifier circuit that differentially amplifies the amplitude detection signal and the amplitude reference signal and adds a voltage corresponding to the offset current to a voltage obtained by amplifying the amplitude detection signal. This allows the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal to be reflected in the output of the differential amplifier circuit, and the amplitude of the voltage signal can be set to the amplitude indicated by the output amplitude setting signal.

[0015] [Details of the embodiments of the present disclosure] Specific examples of transimpedance amplifier circuits according to the present disclosure will be described below with reference to the accompanying drawings. In the following description, identical or corresponding elements will be designated by the same reference numerals, and descriptions of these elements may be omitted. Furthermore, the reference numerals for input terminals, output terminals, and nodes will also be used to indicate signals, voltages, or currents.

[0016] [First embodiment] [Circuit configuration of transimpedance amplifier circuit] Fig. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to Embodiment 1. The transimpedance amplifier circuit 100 shown in Fig. 1 includes a TIA (TransImpedance Amplifier) ​​10, a VGA (Variable Gain Amplifier) ​​20, a BUF (Buffer) 30, a CML (Current Mode Logic) 40, and an AGC control circuit 50.

[0017] For example, the transimpedance amplifier circuit 100 is used in a coherent receiver that receives optical signals, and receives, at input terminals InP and InN, differential current signals converted from single-wavelength optical signals by photodiodes. The transimpedance amplifier circuit 100 amplifies the received current signals and outputs them as differential voltage signals from output terminals OutP and OutN. The voltage signals output from the output terminals OutP and OutN are output to a signal processing circuit such as a DSP (Digital Signal Processor).

[0018] The TIA 10 converts the differential input current signal received at input terminals InP and InN into a voltage signal and outputs it to the VGA 20. For example, the gain of the TIA 10 varies in response to a control signal CNTL1 received from the AGC control circuit 50. Note that the gain of the TIA 10 is expressed in impedance units, such as 1000 Ω, because the current signal is converted into a voltage signal. The TIA 10 includes, for example, an INV (INVerting amplifier) ​​11 and resistor elements R11 and R12. The INV11 is an example of an inverting amplifier circuit. For example, the INV11 is an inverting amplifier circuit that amplifies a differential signal.

[0019] For example, INV11 inverts and amplifies a differential voltage signal input between the non-inverting input terminal and the inverting input terminal, and outputs the inverted and amplified differential voltage signal from the inverting output terminal and the non-inverting output terminal. Resistor R11 is connected, for example, between the non-inverting input terminal and the inverting output terminal of INV11. Resistor R12 is connected, for example, between the inverting input terminal and the non-inverting output terminal of INV11. The gain of TIA10 varies in response to a control signal CNTL1. Note that TIA10 may use variable resistors for resistors R11 and R12, for example, and vary the resistance values ​​of resistors R11 and R12 in response to the control signal CNTL1 to change the gain of TIA10.

[0020] The VGA 20 amplifies the differential voltage signal received from the TIA 10 and outputs it to the BUF 30. For example, the gain of the VGA 20 varies in response to the control signals CNTL2, CNTL3, and CNTL4 received from the AGC control circuit 50. The VGA 20 performs, for example, non-inverting amplification, but may also perform inverting amplification to invert the logic of the differential voltage signal it outputs. The differential voltage signal is composed of a positive-phase signal (positive-phase component) and a negative-phase signal (negative-phase component). The positive-phase signal and the negative-phase signal are 180 degrees out of phase with each other, forming a pair of complementary signals.

[0021] For example, when the voltage of the positive-phase signal increases, the voltage of the negative-phase signal decreases, and when the voltage of the positive-phase signal decreases, the voltage of the negative-phase signal increases. Furthermore, when the positive-phase signal reaches its peak value, the negative-phase signal reaches its bottom value, and when the positive-phase signal reaches its bottom value, the negative-phase signal reaches its peak value. It is preferable that the positive-phase signal and the negative-phase signal have the same amplitude and the same average value (DC component). By swapping the pair of positive-phase and negative-phase signals, the logic of the differential voltage signal can be inverted. Therefore, in a circuit that amplifies a differential voltage signal, switching between non-inverting amplification and inverting amplification can be easily performed by reconnecting the positive-phase signal wiring and the negative-phase signal wiring. The VGA 20 can also be included in the TIA 10 to amplify the differential voltage signal output from the TIA 10.

[0022] The BUF 30 amplifies the differential voltage signals received from the VGA 20 and outputs the resulting voltage signals IP and IN to the AGC control circuit 50 and the CML 40. The CML 40 amplifies the voltage signals IP and IN and outputs the amplified voltage signals to the output terminals OutP and OutN. The voltage signals IP and IN and the voltage signals output to the output terminals OutP and OutN are all differential voltage signals (hereinafter referred to as differential voltage signals). For example, the voltage signal IP is a positive-phase signal of the differential voltage signal, and the voltage signal IN is a negative-phase signal of the differential voltage signal. Note that, for example, if the voltage gain and driving capability of the VGA 20 are sufficiently large, the BUF 30 may be omitted and the VGA 20 may supply the differential voltage signals IP and IN.

[0023] The AGC control circuit 50 generates control signals CNTL1-CNTL4 that adjust the gain of the TIA 10 and the VGA 20 to set the amplitude of the differential voltage signals output from the output terminals OutP and OutN to the amplitude indicated by the output amplitude setting signal OA. The gains of the TIA 10 and the VGA 20 set by the control signals CNTL1-CNTL4 are an example of a first gain. The AGC control circuit 50 is an example of a gain control circuit. An example of the AGC control circuit 50 is shown in FIG. 2. The AGC control circuit 50 detects the amplitude of the differential voltage signals IP and IN. For example, if the CML 40 performs linear amplification with a constant gain, the amplitude of the differential voltage signals output from the output terminals OutP and OutN changes linearly with the amplitude of the differential voltage signals IP and IN. Therefore, by controlling the amplitude of the differential voltage signals IP and IN, the output amplitude of the differential voltage signals output from the output terminals OutP and OutN can be set to a predetermined value.

[0024] [AGC control circuit configuration] FIG. 2 is a circuit diagram showing an example of the AGC control circuit 50 of FIG. 1. The AGC control circuit 50 includes bipolar transistors Q1P and Q1N that receive differential voltage signals IP and IN output from the BUF 30 of FIG. 1. For example, the bipolar transistor Q1P receives a positive-phase signal IP of the differential voltage signals IP and IN, and the bipolar transistor Q1N receives a negative-phase signal IN of the differential voltage signals IP and IN. The AGC control circuit 50 also includes a current source I51 and a resistor R51 connected to the emitters of the bipolar transistors Q1P and Q1N, and a capacitor C51 connected to the resistor R51. The bipolar transistors Q1P and Q1N have the same electrical characteristics, for example, within the range of allowable manufacturing variations.

[0025] Hereinafter, the bipolar transistor will also be referred to simply as a transistor. Transistors Q1P and Q1N, current source I51, resistor R51, and capacitor C51 function as a detection circuit that detects the amplitude of the differential voltage signals IP and IN. An amplitude detection signal PH, set to a voltage corresponding to the amplitude detected by the detection circuit, is output to the gate of a p-channel MOS transistor M1P in the differential amplifier circuit. Resistor R51 and capacitor C51 form a low-pass filter, and the amplitude detection signal is averaged and output from the connection node between resistor R51 and capacitor C51. For example, when the amplitudes of the differential voltage signals IP and IN are constant, the amplitude detection signal PH becomes a DC signal having a voltage value corresponding to the magnitude of the amplitude. Hereinafter, the p-channel MOS transistor will also be referred to simply as a transistor.

[0026] The AGC control circuit 50 also includes a bipolar transistor Q2 that receives a reference voltage Vref, a current source I52 and a resistor R52 connected to the emitter of the transistor Q2, and a capacitor C52 connected to the resistor R52. The transistor Q2, the current source I52, the resistor R52, and the capacitor C52 have a circuit configuration similar to that of the detection circuit that detects the amplitude of the voltage signals IP and IN, and for example, the electrical characteristics and size of each circuit element are similar to those of the detection circuit within the allowable range of manufacturing variations.

[0027] For example, the reference voltage Vref is set to the center voltage of the amplitudes of the differential voltage signals IP and IN. The center voltage of the amplitudes of the differential voltage signals IP and IN is equal to the temporal average value (DC component) of each voltage signal. Note that the reference voltage Vref may be set to the average value obtained by dividing the voltage signals IP and IN output from the BUF30 in FIG. 1 and applying them to a resistor string. For example, the voltage signal IP may be applied to one end of a series resistor circuit consisting of two resistor elements, and the voltage signal IN may be applied to the other end of the series resistor circuit, and the voltage at the midpoint where the two resistor elements are connected may be used as the reference voltage Vref.

[0028] Transistor Q2, current source I52, resistor R52, and capacitor C52 function as a setting circuit that converts the level of reference voltage Vref and generates the converted voltage as an amplitude reference signal. The amplitude reference signal AH is output to the gate of p-channel MOS transistor M1N of the differential amplifier circuit. Resistor R52 and capacitor C52 form a low-pass filter, and the level-converted reference voltage Vref is stabilized and output from the connection node between resistor R52 and capacitor C52. For example, amplitude reference signal AH is a DC signal having a voltage value corresponding to reference voltage Vref. In this way, the amplitude detection signal and amplitude reference signal are each output as DC signals to the differential amplifier circuit. For example, transistors Q1P, Q1N, and Q2 are heterojunction bipolar transistors.

[0029] The differential amplifier circuit includes, for example, transistors M1P and M1N, a current source I53 connected to the sources of the transistors M1P and M1N, and resistors R53, R54, R55, and R56. The resistors R53 and R54 are connected in series between the drain of the transistor M1P and the ground line GND. The resistors R55 and R56 are connected in series between the drain of the transistor M1N and the ground line GND. For example, the resistors R53 and R55 have the same resistance within an allowable manufacturing variation range, and the resistors R54 and R56 have the same resistance within an allowable manufacturing variation range. The transistors M1P and M1N have the same electrical characteristics within an allowable manufacturing variation range, for example.

[0030] The connection node of the resistor elements R53 and R54 receives an offset current Ioffset from a DAC (Digital-to-Analog Converter) 52. As a result, an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of the resistor element R54 is added to the drain voltage of the transistor M1P relative to the ground potential.

[0031] The DAC 52 generates an offset current Ioffset corresponding to the digital value indicated by the output amplitude setting signal OA. For example, as the digital value of the output amplitude setting signal OA increases, the current value of the offset current Ioffset increases. The output amplitude setting signal OA is provided, for example, from outside the transimpedance amplifier circuit 100. As described above, in the transimpedance amplifier circuit 100 according to the first embodiment, the output amplitude set by the output amplitude setting signal OA is the output amplitude of the differential voltage signals output from the output terminals OutP and OutN, but the amplitude detected by the detection circuit is the amplitude of the differential voltage signals IP and IN. Therefore, the amplitudes of the differential voltage signals IP and IN are set by the offset current Ioffset so that the output amplitude of the differential voltage signals output from the output terminals OutP and OutN becomes a predetermined value. The DAC 52 is an example of a current generating unit that generates the offset current Ioffset according to the digital value indicated by the output amplitude setting signal OA.

[0032] For example, the digital value of the output amplitude setting signal OA is set to a small value when the set amplitude is small, and is set to a large value when the set amplitude is large. The output amplitude setting signal OA is also output to the gain control unit 53.

[0033] For example, when the set amplitude is relatively small, the DAC 52 receives an output amplitude setting signal OA with a relatively small value and outputs a relatively small offset current Ioffset. When the set amplitude is relatively large, the DAC 52 receives an output amplitude setting signal OA with a relatively large value and outputs a relatively large offset current Ioffset. The DAC 52 is, for example, a current DAC (IDAC) that outputs a current.

[0034] The output amplitude setting signal OA is also output to the gain control unit 53. The gain control unit 53 generates a gain control voltage VG according to the digital value of the output amplitude setting signal OA. For example, when the value of the output amplitude setting signal OA is relatively small (when the set amplitude is small), the gain control unit 53 outputs a relatively low gain control voltage VG. When the value of the output amplitude setting signal OA is relatively large (when the set amplitude is large), the gain control unit 53 outputs a relatively high gain control voltage VG. The gain of the OTA 51, which is controlled by the gain control voltage VG, is an example of a second gain. The OTA 51 will be described later.

[0035] The differential amplifier circuit outputs differential voltage signals VIP and VIN from the drains of transistors M1N and M1P, which are generated in response to the voltages of the amplitude detection signal PH, the amplitude reference signal AH, and the offset current Ioffset. The differential amplifier circuit and DAC52 are an example of a differential voltage generation circuit that generates a differential signal by correcting the difference between the voltage of the amplitude detection signal PH and the voltage of the amplitude reference signal in response to the output amplitude setting signal OA. The correction in response to the output amplitude setting signal OA is performed, for example, as described above, by adding an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of resistor R54 to one of the voltages of the generated differential signal.

[0036] The differential voltage signals VIP, VIN are supplied to the differential inputs of an OTA (Operational Transconductance Amplifier) ​​51. By supplying the differentially amplified voltage signals VIP, VIN to the OTA 51, the signal-to-noise (SNR) ratio can be improved compared to when the amplitude detection signal PH and the amplitude reference signal AH are directly supplied to the OTA 51, thereby improving the accuracy of the AGC function. Furthermore, by adding an offset voltage due to the offset current Ioffset to one of the differential voltage signals VIP, VIN, the amplitude of the differential voltage signals IP, IN can be set to be equal to the amplitude value set in response to the output amplitude setting signal OA when the voltage values ​​of the voltage signals VIP and VIN become equal.

[0037] OTA 51 receives a gain control voltage VG from gain control unit 53 and outputs a differential current signal OUT from the output node in response to the differential voltage signals VIP and VIN. OTA 51 operates as a variable-gain OTA in response to the gain control voltage VG and controls its gain in response to the value of the output amplitude setting signal OA. Because OTA 51 outputs a current signal in response to the input voltage signal, the gain of OTA 51 is expressed in units of conductance, such as 100S. By adjusting the gain of OTA 51, fluctuations in the AGC band that depend on the output amplitude can be compensated for, making the AGC band constant regardless of the value of the output amplitude setting signal OA. A specific circuit example of OTA 51 is shown in Figure 3. OTA 51 is an example of a voltage-controlled current source circuit.

[0038] A capacitive element C2 is connected to the output node of the OTA 51. The OTA 51 and capacitive element C2 function as an integrating circuit, generating an output voltage OUT at the output node in response to the differential current signal output from the OTA 51 and the capacitance value of the capacitive element C2. The time constant defined by the output impedance of the OTA 51 and the capacitive element C2 forms a dominant pole in the gain characteristic of the AGC loop. The AGC loop in the transimpedance amplifier circuit 100 is composed of a TIA 10 that changes its gain in response to a control signal CNTL1, a VGA 20 that changes its gain in response to control signals CNTL2-CNTL4, a BUF 30, and an AGC control circuit 50 that receives the differential voltage signals IP and IN and generates the control signals CNTL1-CNTL4.

[0039] A gain control unit 54 is connected to the output of the OTA 51. The gain control unit 54 generates control signals CNTL1-CNTL4 that control the gains of the TIA 10 and the VGA 20 in accordance with an output voltage OUT, which is the charging voltage of a capacitive element C2 connected to the output node of the OTA 51.

[0040] For example, when the output voltage OUT is relatively low, the gain control unit 54 generates control signals CNTL1-CNTL4 that increase the gain of the TIA 10 and the VGA 20. When the output voltage OUT is relatively high, the gain control unit 54 generates control signals CNTL1-CNTL4 that decrease the gain of the TIA 10 and the VGA 20.

[0041] When the amplitude detection signal PH and the amplitude reference signal AH are constant, a decrease in the offset current Ioffset reduces the voltage value of the voltage signal VIN, and a large increase in the offset current Ioffset increases the voltage value of the voltage signal VIN. The transimpedance amplifier circuit 100 operates by the negative feedback of the AGC loop described above to make the difference between the voltage signals VIN and VIP input to the OTA 51 zero, thereby canceling the offset voltage due to the offset current Ioffset. As a result, an AGC control circuit 50 can be configured that can set the amplitude using the digital value of the output amplitude setting signal OA.

[0042] [OTA circuit example] Fig. 3 is a circuit diagram showing an example of the OTA 51 of Fig. 2. The OTA 51 includes, for example, p-channel MOS transistors PM1, PM2, PM3, PM4, and PM5, n-channel MOS transistors NM1, NM2, NM3, and NM4, and current sources I11 and I12.

[0043] The gates of the transistors PM1 and PM2 receive the differential voltage signals VIN and VIP from the differential amplifier circuit of Fig. 2. A current source I11 is connected to the source of the transistor PM1, and a current source I12 is connected to the source of the transistor PM2. sauce The source of the transistor PM5 is connected to the sauce The drain of transistor PM5 is connected to transistor PM1. The gate of transistor PM5 receives gain control voltage VG. Since transistor PM5 functions as a variable resistance element as will be described later, the source and drain of transistor PM5 may be interchanged. That is, the source of transistor PM1 may be connected to the drain of transistor PM5, and the source of transistor PM2 may be connected to the source of transistor PM5.

[0044] The drain of transistor PM1 is connected to the common gate of the current mirror circuit formed by transistors NM1 and NM3. The drain of transistor PM2 is connected to the common gate of the current mirror circuit formed by transistors NM2 and NM4. Furthermore, the drain of transistor NM3 is connected to the common gate of the current mirror circuit formed by transistors PM3 and PM4. The drains of transistors PM4 and NM4 are connected to the output terminal OUT of the OTA 51.

[0045] The gate of transistor PM1 receives, for example, one (negative phase signal) VIN of the differential voltage signals VIP and VIN. The gate of transistor PM2 receives, for example, the other (positive phase signal) VIP of the differential voltage signals VIN and VIP. Transistors PM1 and PM2 generate differential output current signals in response to the differential voltage signals VIP and VIN. For example, the drain current of transistor PM1 flows through transistor NM1, and the drain current of transistor PM2 flows through transistor NM2. The difference current between the drain current of transistor NM1 and the drain current of transistor NM2 changes in response to the difference voltage between voltage signals VIP and VIN.

[0046] One of the differential output current signals flowing through transistor NM1 is supplied to the output terminal OUT via a two-stage current mirror circuit formed by transistors NM1, NM3, PM3, and PM4. The other of the differential output current signals flowing through transistor NM2 is supplied to the output terminal OUT via a current mirror circuit formed by transistors NM2 and NM4. One of the differential current signals is supplied to the output terminal OUT so as to push a current outward, and the other of the differential current signals is supplied so as to pull a current from the outside to the output terminal OUT. In this way, the difference current obtained by subtracting the other differential current signal from one of the differential current signals is output from the output terminal OUT as a differential current signal. Transistors PM4 and NM4 form a push-pull circuit.

[0047] The transistor PM5 functions as a variable resistor section whose resistance value between the source and drain changes in response to the gain control voltage VG, so that the gain (gm) of the OTA 51 can be controlled by the gain control voltage VG.

[0048] FIG. 4 is an explanatory diagram showing an example of a gain control voltage VG set in response to the output amplitude setting signal OA. The numerical values ​​at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in FIG. 4 correspond to the amplitude to be set. The larger the numerical value, the larger the output amplitude setting signal OA is supplied to the DAC 52 and the gain control unit 53. The horizontal axis in FIG. 4 represents the output amplitude of the differential output voltage output from the output terminals OutP and OutN. In this example, the gain control voltage VG is set so that it increases as the output amplitude increases. When the voltage value of the gain control voltage VG is relatively small, the on-resistance of the p-channel MOS transistor PM5 decreases, and the gain of the OTA 51 increases. When the voltage value of the gain control voltage VG is relatively large, the on-resistance of the p-channel MOS transistor PM5 increases, and the gain of the OTA 51 decreases. An example of the gain control unit 53 that sets the gain control voltage VG is shown in FIG. 6.

[0049] FIG. 5 is a characteristics diagram showing an example of the output current differential current signal Iout output from the output terminal OUT of the OTA 51 in response to the differential input voltage VIP-VIN with respect to a set gain control voltage VG. FIG. 5 shows the input / output characteristics of the OTA 51 with respect to four gain control voltages VG indicated by symbols VG1 to VG4. The horizontal axis of FIG. 5 represents the differential input voltage VIP-VIN, and the vertical axis represents the differential current signal Iout. The current value of the differential current signal Iout is positive when it flows out from the output terminal OUT to the outside, and negative when it flows into the output terminal OUT from the outside. The dashed lines indicating the four gain control voltages VG1 to VG4 correspond to the dashed lines attached to symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in FIG. 7, which will be described later.

[0050] For example, the gain control voltage VG1 is generated when receiving an output amplitude setting signal OA that sets the smallest output amplitude. The gain control voltage VG2 is generated when receiving an output amplitude setting signal OA that sets the second smallest output amplitude. The gain control voltage VG3 is generated when receiving an output amplitude setting signal OA that sets the second largest output amplitude. The gain control voltage VG4 is generated when receiving an output amplitude setting signal OA that sets the largest output amplitude.

[0051] The gain control voltages VG1, VG2, VG3, and VG4 increase sequentially in this order (VG1 < VG2 < VG3 < VG4). In FIG. 5, the slope of each broken line corresponding to the gain control voltages VG1 to VG4 corresponds to the gain of the OTA51. Therefore, the gain of the OTA51 becomes smaller as the gain control voltage VG is higher, and becomes larger as the gain control voltage VG is lower. That is, the gain of the OTA51 can be made larger as the output amplitude set by the output amplitude setting signal OA is smaller, and can be made smaller as the output amplitude set by the output amplitude setting signal OA is larger.

[0052] FIG. 6 is a circuit diagram showing an example of the gain control unit 53 in FIG. 2. The gain control unit 53 includes a thermocode generation unit 531, n current sources I1 to In (n is an integer of 2 or more) connected in parallel to each other, n switches SW connecting the current sources I1 to In to a gain control voltage line (voltage output node) VG, and a resistance element RL connected between the gain control voltage line VG and a ground line GND. For example, the current source I1 is connected to the gain control voltage line VG via the first switch SW, and the current source In is connected to the gain control voltage line VG via the nth switch SW. When all the switches SW are in the on state, the n current sources I1 to In are connected in parallel to the gain control voltage line VG, and current is supplied from each of the n current sources I1 to In to the resistance element RL. The gain control voltage is generated when the current supplied by the current source connected to the voltage output node via the switch SW among the n current sources I1 to In flows through the resistance element. The gain control voltage VG is output from the voltage output node.

[0053] The thermocode generation unit 531 generates n output signals that respectively control the on / off state (on / off) of the switches SW according to the value of the output amplitude setting signal OA. For example, the first output signal controls the on / off state of the first switch SW, the second output signal controls the on / off state of the second switch SW, and the nth output signal controls the on / off state of the nth switch SW. When a switch SW is turned off, the switch SW is in a non-conductive state (off state). When a switch SW is turned on, the switch SW is in a conductive state (on state). For example, as described with reference to FIGS. 4 and 5, assume that there are four values ​​of the output amplitude setting signal OA to set four amplitudes. In this case, the thermocode generation unit 531 generates output signals such that the number of switches SW that are turned on increases as the value of the output amplitude setting signal OA increases.

[0054] For example, when the output amplitude setting signal OA is set to a value that sets the smallest amplitude, only the first output signal is set to turn on the switch SW, and the other output signals are set to turn off the switches SW connected to them. When the output amplitude setting signal OA is set to a value that sets the second smallest amplitude, only the first and second output signals are set to turn on the switches SW connected to them, and the other output signals are set to turn off the switches SW connected to them. In this way, for example, when the value of the output amplitude setting signal OA increases by 1 or to the next largest value, only one switch SW changes from the off state to the on state.

[0055] For example, the thermocode can be set to 2 according to the value of m (m is an integer equal to or greater than 1) of the output amplitude setting signal OA. mThis allows the generation of output signals. For example, with a thermocode, the number of switches SW turned on increases by one as the digital value A of the output amplitude setting signal OA increases by one. Therefore, when the digital value A increases or decreases by one, only one switch SW is turned on or off accordingly, and the current value flowing through the resistor element RL can be monotonically increased or decreased without being affected by the timing of the output signal X. For example, when two switches SW are controlled simultaneously without using a thermocode, specifically when one switch SW is changed from an off state to an on state and the other switch SW is changed from an on state to an off state, the timing of each output signal X may differ, potentially jeopardizing the monotonic change of the gain control voltage VG generated by the resistor element RL. By adjusting the gain of the OTA 51 in accordance with the output amplitude setting signal OA, the AGC bandwidth can be kept constant regardless of the value of the output amplitude setting signal OA.

[0056] In addition, when n amplitude settings are used, if the gain control voltages VG that provide a desired AGC band are V1 to Vn, I1 to In can be found as follows. I1=V1 / RL I2=V2 / RL-I1 ... In=Vn / RL-Σ(k=1,n-1)Ik Here, the symbol Σ indicates the current Ik when k is changed from "1" to "n-1", and the symbol Σ indicates that the current Ik is integrated.

[0057] [Loop Gain of the First Embodiment] 7 is a characteristic diagram showing an example of the loop gain of the AGC loop in response to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50 of FIG. 2. FIG. 7 shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (for example, -15 dBm). When the optical input signal power is kept constant, the magnitude of the differential input current signal received at the input terminals InP and InN is constant. The numbers at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in FIG. 7 correspond to the value of the output amplitude setting signal OA, as explained in FIG. 4.

[0058] As described above, the AGC band can be determined as the frequency at which the gain is "1" (0 dB in decibels) in the loop gain characteristics of the AGC loop. For example, the optimum range of the AGC band is 100 kHz to 1 MHz. In this embodiment, the gain of the OTA 51 is changed according to the amplitude setting, so the AGC band can be set to about 300 kHz regardless of the amplitude setting. 300 kHz is located near the center of the optimum range of the AGC band, and desired communication performance can be ensured even when the optical input signal power fluctuates.

[0059] Fig. 8 is a characteristic diagram showing the characteristics shown in Fig. 7 as the AGC band versus the output amplitude. As shown in Fig. 8, the AGC band can be stabilized to a nearly constant value regardless of the output amplitude set by the output amplitude setting signal OA.

[0060] As described above, in this embodiment, by changing the gain of the OTA 51 according to the amplitude setting, it is possible to stabilize the AGC band at a constant level regardless of the magnitude of the set output amplitude. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude setting. As a result, it is possible to ensure sufficient communication performance even when a desired output amplitude is set in response to fluctuations in the optical input signal power, and it is possible to improve the reliability of the transimpedance amplifier circuit 100.

[0061] Transistor PM5, whose source-drain resistance changes in response to gain control voltage V, is connected between the sources of transistors PM1 and PM2, which receive differential voltage signals VIP and VIN. This allows the gain of the voltage-controlled current source circuit to be changed in response to gain control voltage V by a simple means, thereby compensating for fluctuations in the AGC band that depend on the output amplitude.

[0062] By using a thermocode to set the number of current sources I1 to In connected to the gain control voltage line VG according to the value of the output amplitude setting signal OA, a stable gain control voltage VG can be generated using a simple means without being affected by the timing of the output signal that turns the current sources I1 to In on and off.

[0063] By supplying an offset current Ioffset to the connection node of the resistor elements R53 and R54 of the differential amplifier circuit in response to the output amplitude setting signal OA, the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal OA can be reflected in the output of the differential amplifier circuit, thereby setting the amplitude of the differential voltage signals IP and IN to the output amplitude indicated by the output amplitude setting signal OA.

[0064] [Other AGC control circuit configurations] Figure 9 is a circuit diagram showing another example of the configuration of an AGC control circuit mounted on the transimpedance amplifier circuit 100 of Figure 1. Elements similar to those in Figure 2 are given the same reference numerals, and detailed description will be omitted. An AGC control circuit 50A shown in Figure 9 is mounted on the transimpedance amplifier circuit 100 shown in Figure 1 in place of the AGC control circuit 50 of Figure 1.

[0065] The AGC control circuit 50A is obtained by eliminating the gain control unit 53 from the AGC control circuit 50 in Fig. 2. Furthermore, the OTA 51 is obtained by eliminating the transistor PM5 from the OTA 51 shown in Fig. 3. Other configurations of the AGC control circuit 50A are the same as those of the AGC control circuit 50 in Fig. 2. The AGC control circuit 50A operates in the same manner as the AGC control circuit 50 in Fig. 2, except that the gain of the OTA 51 is not adjusted by the output amplitude setting signal OA.

[0066] [Loop gain of other AGC control circuits] Fig. 10 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50A of Fig. 9. Fig. 10 corresponds to Fig. 7 and shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (for example, -15 dBm). When the optical input signal power is kept constant, the magnitude of the differential input current signal received at the input terminals InP and InN is constant.

[0067] If the capacitance value is not adjusted using the output amplitude setting signal OA, the AGC band fluctuates according to the set amplitude. In Fig. 10, the AGC band fluctuates from about 180 kHz to about 1 MHz, which is a small margin relative to the appropriate range of 100 kHz to 1 MHz. Therefore, if the optical input signal power fluctuates, the desired communication performance may not be ensured.

[0068] Fig. 11 is a characteristic diagram showing the characteristics shown in Fig. 10 as the AGC band relative to the output amplitude. In Fig. 11, the AGC band varies depending on the amplitude set by the output amplitude setting signal OA.

[0069] [Characteristics when feedback function is disabled] 12 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit 100 and the differential voltage PH-AH between the amplitude detection signal PH and the amplitude reference signal AH when negative feedback by the AGC control circuit of FIG. 2 or 9 is disabled. As shown in FIG. 12, when negative feedback is disabled, the differential voltage PH-AH increases nonlinearly in a bow shape as the set amplitude increases. When the setting circuit of the AGC control circuit 50 sets the reference voltage Vref to the average value of the differential voltage signals IP and IN, the differential voltage PH-AH becomes a voltage corresponding to the amplitude (half the peak-to-peak value) of the differential voltage signals IP and IN.

[0070] The change in AGC bandwidth shown in Figure 11 occurs because the AGC loop gain varies depending on the amplitude setting, and is due to two main reasons. First, because the TIA 10 and VGA 20 are included in the AGC loop, fluctuations in the gain of the TIA 10 and VGA 20 due to AGC control cause the AGC loop gain to fluctuate. Second, the transistors Q1P and Q1N (e.g., HBTs) in Figures 2 and 9 have diode characteristics between their bases and emitters, resulting in nonlinear characteristics with respect to the input. For example, the nonlinear relationship between the difference voltage PH-AH and the actual output amplitude in Figure 12 is due to the nonlinear characteristics of the transistors Q1P and Q1N.

[0071] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These changes also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0072] 10 TIA 20 VGA 30 BUF 40 CML 50, 50A AGC control circuit 51 OTA 52 DAC 53, 54 Gain control section 100 Transimpedance amplifier circuit 531 Thermocode Generator AH Amplitude Reference Signal C2 Capacitor element C51, C52 capacitance elements CNTL1-CNTL4 control signals I1, In current source I11, I12 current source I51, I52, I53 current source InN, InP input terminal IN, IP voltage signal M1N, M1P transistors MP1, PM2, PM3, PM4, PM5 transistors NM1, NM2, NM3, NM4 transistors OA output amplitude setting signal OUT output terminal OutN, OutP output terminals PH amplitude detection signal Q1N, Q1P transistors Q2 transistor R11, R12 resistor elements R51, R52, R53, R54, R55, R56 resistor elements SW switch VG Gain control voltage VIP, VIN voltage signals Vref Reference voltage

Claims

1. an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts the input current signal into a voltage signal; a gain control circuit that generates the control signal in response to the amplitude of the voltage signal; Equipped with The gain control circuit a detection circuit for generating an amplitude detection signal in accordance with the amplitude of the voltage signal; a setting circuit for generating an amplitude reference signal in response to a reference voltage; a differential amplifier circuit that generates a differential voltage by adding an offset voltage generated in accordance with an output amplitude setting signal to a differential amplified signal that is generated by amplifying a difference between a voltage of the amplitude detection signal and a voltage of the amplitude reference signal; a voltage controlled current source circuit that amplifies the differential voltage in accordance with a second gain set by the output amplitude setting signal to generate a differential current signal; a capacitance element that is charged and discharged by the differential current signal; Equipped with the gain control circuit generates the control signal in response to a charging voltage of the capacitance element; the offset voltage increases as the output amplitude setting signal increases, the amplitude of the voltage signal is set to be smaller when the output amplitude setting signal is smaller, and is set to be larger when the output amplitude setting signal is larger; the differential current signal decreases as the differential voltage increases and increases as the differential voltage decreases; the second gain is set to be smaller as the output amplitude setting signal increases, and to be larger as the output amplitude setting signal decreases. Transimpedance amplifier circuit.

2. The gain control circuit a gain control section that generates a gain control voltage for setting the second gain in response to the output amplitude setting signal; The voltage controlled current source circuit comprises: a pair of transistors for amplifying the differential voltage; a variable resistor section connected between the sources of the pair of transistors, the resistance value of which varies in response to the gain control voltage; Equipped with 2. The transimpedance amplifier circuit of claim 1.

3. The gain control unit a voltage output node that outputs the gain control voltage; a first resistor element connected to the voltage output node; n current sources (n is an integer of 2 or more); a thermocode generating unit that generates an output signal in accordance with the value of the output amplitude setting signal; n switches for changing the number of current sources connected to the voltage output node among the n current sources in response to the output signal; Equipped with the gain control voltage is generated by a current supplied from one of the n current sources connected to the voltage output node via the n switches in response to the output signal flowing through the first resistor element; the output signal increases the number of the n current sources connected to the voltage output node by one when the value of the output amplitude setting signal increases by one, and decreases the number of the n current sources connected to the voltage output node by one when the value of the output amplitude setting signal decreases by one.

3. The transimpedance amplifier circuit according to claim 2.

4. The gain control circuit further includes a current generating unit that generates an offset current according to a value indicated by the output amplitude setting signal, the differential amplifier circuit includes a second resistor element for generating the differential voltage; the offset voltage is generated by the offset current flowing through the second resistor element. The transimpedance amplifier circuit according to any one of claims 1 to 3.

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