a digital input circuit for receiving a digital input signal from at least one signal generator;

Abstract

To provide a digital input circuit for receiving digital input signals from at least one signal generator.SOLUTION: A digital input circuit (100) comprises a combined test and current increasing apparatus (20) to generate a control signal such that a function test of two subcircuits (14, 14') is conducted simultaneously with the control signal and such that an input current of digital inputs (10, 10') is increased.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a digital input circuit for receiving a digital input signal from at least one signal generator, the digital input circuit comprising: a first subcircuit, and at least one second sub-circuit; the first sub-circuit comprises a first digital input via which a first digital input signal can be supplied to the first sub-circuit; and a first threshold element capable of determining a state of the first sub-circuit, the first sub-circuit assuming a first state when the first digital input signal reaches or is below a lower threshold and a second state when the first digital input signal reaches or is above an upper threshold; at least one second sub-circuit comprises a second digital input via which a second digital input signal can be provided to the second sub-circuit, and a second threshold element by which a state of the second sub-circuit can be determined; At least one second sub-circuit assumes a first state when the second digital input signal reaches or is below a lower threshold and assumes a second state when the second digital input signal reaches or is above an upper threshold. [Background technology]

[0002] Digital input circuits of the type mentioned at the outset can be used, for example, in switching devices or safety switching devices that are provided for safety-related applications, in particular in automated technical systems. Such digital input circuits have at least two digital inputs via which they can receive the digital input signals of at least one signal generator. These digital input signals originate, for example, from a sensor device or a signal device, such as an emergency stop button, a safety door or a switch mat, which may be a signal generator within the meaning of the present invention.

[0003] The digital input signal received by the digital input circuit is a binary signal that can be distinguished by two defined states, which can be defined, for example, by two static potentials. These binary states are characterized by different voltage states. The first state is assumed when a defined voltage threshold is reached or dropped below. This is the so-called low-level state. The second state is assumed when a defined voltage threshold is reached or exceeded. This is the so-called high-level state.

[0004] Digital input circuits for receiving digital input signals from at least one signal generator are known from the prior art in a wide variety of embodiments. Typically, for current-drawing digital input circuits operating at an operating voltage of 24 V (DC), three different types (Type 1, Type 2, and Type 3) are distinguished according to the EN61131-2:2007 standard. These three types of digital input circuits differ from one another in particular with regard to their high level, low level, and current consumption.

[0005] A Type 1 digital input circuit must detect a high level at an input voltage of at least 15V. Therefore, in practice, this high level is already detected at input voltages below 15V. A Type 1 digital input circuit must also detect a high level across the entire input voltage range from 15V to 30V. The current consumption must be ≥ 2mA for a high level and can reach 15mA. Furthermore, a Type 1 digital input circuit (and similarly Types 2 and 3 below) must be able to detect a low level across the entire range from -3V to 5V. Therefore, in practice, a low level is already detected at input voltages above 5V. Between -3V and 5V, the input current can be between 0mA and 15mA. For input voltages between 5V and 15V, a 0.5mA current limit is appropriate. In this range, the input must detect a low level as long as the input current is 0.5mA or less. Such Type 1 digital input circuits are particularly used for electromechanical switching devices such as pushbuttons and relay contacts, or for three-wire sensor devices. A typical application example for a Type 1 digital input circuit is an emergency stop switching device.

[0006] Type 2 digital input circuits are suitable for example for two-wire sensor devices or semiconductor sensors that require a relatively high quiescent current for operation. In the high-level range between 11 V and 30 V, the current consumption is typically ±6 mA, with a maximum of 30 mA possible.

[0007] Type 3 digital input circuits are characterized by lower power consumption and heat dissipation than Type 2 digital input circuits. Therefore, more digital input circuits, and therefore more physical digital inputs, can be integrated into a digital input module than with Type 2 digital input circuits. Type 3 digital input circuits must detect high levels within an input voltage range of 11V to 30V. Current consumption is typically 2mA in the high-level range between 11V and 30V, and can be up to 15mA. Type 3 digital input circuits must detect low levels within an input voltage range of -3V to 5V, with an allowable current of 0mA to 15mA. Furthermore, they must detect low levels when the input voltage is 5V to 11V and the input current is 1.5mA or less.

[0008] In many safety-related applications, digital input circuits with digital inputs are used, which include at least one test device that periodically checks whether the subcircuit assigned to the digital input can still detect a low-level input signal corresponding to a safe state. Such digital input circuits are known, for example, from DE 10 2013 106 739 A1.

[0009] In principle, it would be desirable for a digital input circuit having a test device of the type described above to further comprise a current increasing device for temporarily increasing the input current at the digital input without reducing the security level. This problem of reducing the security level arises particularly when implementing several secure digital inputs in one module at low cost.

[0010] The advantages of a short-term increase in input current, especially in the case of an open circuit at a digital input, are described in detail in DE 10 2013 101 932 A1. From this document, it is known that periodically increasing the input current proactively counters potential faults at the input. Therefore, the current increase is not continuous but only at defined times. The corresponding current increase device ensures safe and rapid evaluation of the digital input upon startup. The current increase device is preferably activated when a fault in the evaluation of the digital input, caused by, for example, crosstalk at the input, is anticipated. The increase in current flow at the digital input allows for faster establishment of a binary state in the form of a defined voltage level. In particular, the digital OFF state, where a zero potential (i.e., a low-level signal) is normally expected, can be detected more quickly and, above all, more reliably.

[0011] A possible solution for implementing a digital input circuit with at least two safe digital inputs in a module with both test and current boosting functions can be realized by combining the test device described in DE 10 2013 106 739 A1 with the current boosting device disclosed in DE 10 2013 101 932 A1. However, as will be explained below, this combination entails very serious practical drawbacks.

[0012] 1 shows such a digital input circuit 200, which comprises two digital inputs I1, I2, a test device 201, and a current increasing device 202. Some essential aspects of this digital input circuit 200 are described below, but the details of the circuit structure are not described in detail.

[0013] To implement the digital input circuit 200 shown in FIG. 1, the test device 201 was designed according to FIG. 3 of DE 10 2013 106 739 A1, and the current boosting device 202 was designed according to FIG. 7 of DE 10 2013 101 932 A1. A crucial drawback of this implementation is that a component failure, i.e., a short circuit of the decoupling diodes 203 and 204 in the current boost path of one of the two digital inputs I1 and I2, can lead to a dangerous situation. A short circuit of the decoupling diode 203 of the second input I2 is graphically represented in FIG. 1 by the bridge F1 shown there. In this case, a dangerous situation exists if there is a high-level signal at the first input I1 and a (high-resistance) low-level signal at the second input I2 (e.g., via an activated emergency stop switch). In this case, the high-level signal at the first input I1 would lead to a current flow through the current-increasing path of the first input I1 and the short circuit F1 to the subcircuit for the second digital input I2. This would result in the low-level signal actually present at the second digital input I2 being "overwritten" to some extent by the high-level signal at the first digital input I1. The subcircuit assigned to the second digital input I2 would also detect a high-level state. This would result in an imminent hazardous condition that would not be detected even when testing the subcircuits for the two digital inputs I1 and I2 using test equipment 201. During testing, the subcircuits for both inputs I1 and I2 would continue to detect a low-level state, as would be expected when the subcircuits for the two digital inputs are in a fault-free state, regardless of the component defect in decoupling diode 203. No component defect, and therefore no hazardous condition, was detected.

[0014] When detecting a two-channel sensor signal using the digital inputs I1 and I2 of the digital input circuit 200, an undetectable short circuit F1 of the decoupling diode 203 of the second input I2 cancels the two-channel structure of the subcircuit of the two digital inputs I1, I2. As a result, an additional so-called "high level fault" (i.e., a sustained high level state) at the first digital input I1 is sufficient to "overwrite" the low level signal of the signal generator at the second digital input I2 with the faulty high level signal at the first digital input I1. This means that even in two-channel operation, two faults are sufficient to lead to a dangerous state.

[0015] 2 shows a digital input circuit 300 with a test device 301 according to FIG. 3 of DE 10 2013 106 739 A1, in which decoupling diodes 303, 304 according to FIG. 7 of DE 10 2013 101 932 A1 are inserted in the current-increasing paths of the digital inputs I1, I2, respectively. The digital input circuits 200, 300 shown in FIGS. 1 and 2 have different connections or connection points of the current-increasing devices 202, 302 to the respective input circuits 200, 300. A closer look reveals that this embodiment also has significant practical drawbacks.

[0016] For this variant to become dangerous, three or four component defects must exist, depending on the dimensions. These include, for example, a blocked base of transistor T1 in the partial circuit of the first digital input I1 (defect F1), a short circuit of the decoupling diode 303 in the partial circuit of the second digital input I2 (defect F2), a blocked collector of the optocoupler 305 in the current increasing device 302 (defect F3), and, depending on the dimensions, a short circuit of resistor 306 between the collector and base of transistor T1 in the partial circuit of the first digital input I1 (defect F4). If these defects occur, a high signal at the first digital input I1 will conduct current through the two current increasing connections and the optocoupler in the partial circuit of the second digital input I2. In this case, too, if a fault occurs, a low signal at one input (in this case, the second digital input I2) can be "overwritten" by a high signal at another input (in this case, the first digital input I1). The drawback remains that none of the defects F1 to F4 can be detected by testing the partial circuits of the two digital input sections I1 and I2. Therefore, the accumulation of defects can lead to a dangerous situation in both single-channel and two-channel operation of the digital input circuit 300 shown in FIG. Summary of the Invention

[0017] The present invention therefore aims to provide a digital input circuit of the type mentioned at the outset, which allows a current increase at the digital input, achieves a high level of security in the event of a fault, in particular in the event of a component fault in the circuit architecture, and is simply constructed.

[0018] The solution to this problem is provided by a general digital input circuit with the features of the characterizing portion of claim 1. The dependent claims relate to advantageous developments of the invention.

[0019] The digital input circuit according to the invention has a combined test device and current increase device, which is configured to generate a control signal such that the input current of the digital input section is increased while functional tests of two subcircuits are performed simultaneously with this control signal. The digital input circuit according to the invention, equipped with a combined test device and current increase device, advantageously allows the input current at the digital input section to be increased, in particular periodically, while simultaneously performing functional tests of the subcircuits of the digital input section. The combination of the test device with the current increase device according to the invention, resulting in a single test device and current increase device according to the invention, advantageously maintains a very high safety level of the digital input circuit, even in the presence of potentially dangerous (component) defects. Potentially dangerous (component) defects are reliably detected by tests performed simultaneously during the increase phase. Furthermore, it is advantageously possible to omit components that may be isolated and potentially defective, which contributes to a simplification of the circuit structure and a reduction in potential sources of defects. The essential feature of the proposed digital input circuit, with its correspondingly configured test and current increase devices, is that when a fault current high enough to cause one of the two subcircuits to detect a high-level state occurs, this fault current continues to flow, even with the presence of a low-level signal at its input, and with an active test and active current increase. In this way, at least potentially dangerous component defects are revealed by the test. The present invention also allows for the implementation of Type 3 digital input circuits in accordance with the IEC 61131-2 standard.

[0020] In a preferred embodiment, the digital input circuit is configured such that the sub-circuits of the digital input section are mutually identical. Connection ofThe digital input circuit is configured to have only a connection to the at least two subcircuits. This advantageously further reduces the risk that one or more (component) defects in one of the at least two subcircuits will affect the other subcircuit. This improvement is made possible in particular in that, according to the invention, the digital input circuit has a combined test device and current boosting device, but does not have at least one test device and a current boosting device separate therefrom.

[0021] In a particularly preferred embodiment, the subcircuits are configured such that, when a control signal for the combined test device and current increasing device for testing the subcircuit is received, the level of the digital input signal supplied to the subcircuit via the digital input is significantly lowered internally, corresponding to a first state of the subcircuit involved. Thus, each subcircuit assigned to the two inputs must detect a low state of the subcircuit involved, corresponding to the first state, during testing, even if a high signal representing a second state is present at the digital input. If this first state (low state) is not detected by at least one of the subcircuits, a fault has occurred.

[0022] In an advantageous embodiment, the first sub-circuit comprises a first electronic switching element, in particular a first switching transistor, whereby the combined test device and current increasing device are connected to the first sub-circuit.

[0023] In a further advantageous embodiment, the second sub-circuit comprises a second electronic switching element, in particular a second switching transistor, whereby the combined test device and current increasing device are connected to the second sub-circuit.

[0024] The electronic switching elements, preferably implemented as switching transistors, can be controlled by control signals of the combined test device and current increasing device. In a preferred embodiment, the electronic switching elements, in particular the switching transistors, of the first and second sub-circuits can be connected in parallel with one another.

[0025] In a particularly advantageous embodiment, each of the two subcircuits has at least two voltage stabilizing elements and two current sources, which are preferably cross-switched so that, at least for an input signal defining the second state of the subcircuit, the current flowing through the voltage stabilizing element of the first current source essentially consists of the stabilizing current of the second current source, and the current flowing through the voltage stabilizing element of the second current source essentially consists of the stabilizing current of the first current source, thereby achieving two parallel constant or substantially constant currents flowing through the regions of the first and second current sources of each of the two subcircuits.

[0026] In a particularly preferred embodiment, the combined test device and current increasing device comprises a clock reference device configured to modulate the control signal of the current increasing device. The clock reference device is thus used to generate a modulated (clocked) control signal, which allows current increase at the two digital inputs, making it possible to simultaneously test the functionality of at least two subcircuits. The clock reference device can, for example, be synchronized to the clock of an interference signal periodically occurring at the digital inputs.

[0027] According to a further aspect, the invention relates to a safety switching device for switching on and off the power supply of a load, in particular of a technical system, the safety switching device having a digital input circuit with at least two digital inputs for receiving digital input signals from at least one signal generator. The safety switching device according to the invention is characterized in that the digital input circuit is configured according to any one of claims 1 to 8.

[0028] More particularly, the present invention provides a digital input circuit (100) for receiving a digital input signal from at least one signal generator (502), comprising: a first partial circuit (14), and at least one second partial circuit (14'); the first sub-circuit (14) comprises a first digital input (10) via which a first digital input signal can be provided to the first sub-circuit (14) and a first threshold element (16) capable of determining a logic state of the first sub-circuit (14); The first sub-circuit (14) assumes a first state when the first digital input signal reaches or is below a lower threshold, and assumes a second state when the first digital input signal reaches or is above an upper threshold; At least one second sub-circuit (14') comprises a second digital input (10') via which a second digital input signal can be provided to the second sub-circuit (14') and a second threshold element (16') capable of determining the logic state of the second sub-circuit (14'); At least one second sub-circuit (14') assumes a first state when the second digital input signal reaches or is below a lower threshold, and assumes a second state when the second digital input signal reaches or is above an upper threshold, in a digital input circuit (100); The digital input circuit (100) has a combined test device and current increasing device (20), a combined test device and current increasing device (20) configured to generate a control signal, and a functional test of the two sub-circuits (14, 14') is performed simultaneously with this control signal, increasing the input current of the digital input section (10, 10'); The first sub-circuit (14) further comprises a first current limiting device (15) for determining a maximum current at the first digital input (10), the first current limiting device (15) being connected to a first threshold element (16), and a first switching transistor (23) configured as an npn bipolar transistor, the collector of the first switching transistor (23) being connected between the first current limiting device (15) and the first threshold element (16), and the emitter of the first switching transistor (23) being grounded; The second sub-circuit (14') further comprises a second current limiting device (15') for determining a maximum current at the second digital input (10'), the second current limiting device (15') being connected to the second threshold element (16'), and a second switching transistor (23') configured as an npn bipolar transistor, the collector of the second switching transistor (23') being connected between the second current limiting device (15') and the second threshold element (16') and the emitter of the second switching transistor (23') being grounded; the first switching transistor (23) of the first partial circuit (14) and the second switching transistor (23') of the second partial circuit (14') are connected in parallel with each other; The base of the first switching transistor (23) and the base of the second switching transistor (23') are connected by a single connection part (213), The combined test and current increasing device (20) is connected to the first subcircuit (14) and the second subcircuit (14') by a single connection (213). 、 The detection of whether or not there is a defect in at least the first switching transistor (23) and the second switching transistor (23') is performed by a control signal from the combined test device and current increasing device (20). The digital input circuit (100) is characterized by:

[0030] In accordance with the present invention, the sub-circuits (14, 14') are characterized in that, when a control signal of the combined test and current increasing device (20) for testing the sub-circuits (14, 14') is received, the level of the digital input signal supplied to the sub-circuits (14, 14') via the digital inputs (10, 10') is internally significantly reduced to correspond to a first state of the associated sub-circuits (14, 14').

[0034] In accordance with the present invention, the combined test device and current multiplier (20) is characterized by a clock reference device (24) configured to modulate the control signal of the current multiplier (20).

[0036] The present invention relates to a safety switching device (500) for switching on and off the power supply of a load (501), in particular of a technical system, the safety switching device (500) having a digital input circuit (100) with at least two digital inputs (10, 10') for receiving digital input signals from at least one signal generator (502), the digital input circuit (100) being mentioned above Either Configuration The safety switching device (500) is characterized by being configured in accordance with the above.

[0037] Further features and advantages of the present invention will become apparent from the following description of preferred embodiments, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0038] [Figure 1] 1 shows an example of a digital input circuit that is not the subject of the present invention. [Figure 2] 2 shows another example of a digital input circuit that is not the subject of the present invention. [Figure 3] 1 illustrates a digital input circuit implemented in accordance with a preferred embodiment of the present invention. [Figure 4] 4 is a highly simplified schematic representation of a safety switching device with a digital input circuit configured according to FIG. 3; DETAILED DESCRIPTION OF THE INVENTION

[0039] A preferred embodiment of the digital input circuit 100 is described in detail below with reference to FIG.

[0040] The digital input circuit 100 has a first circuit part I, which forms the primary side of the digital input circuit 100 and comprises a first digital input 10 and a second digital input 10', via which the digital input circuit 100 can be supplied with a binary input signal of at least one signal generator, not explicitly shown here. The at least one signal generator capable of providing a digital input signal to the digital input circuit 100 can be in particular a sensor or signaling device, such as an emergency-off button, an emergency-stop button, a protective door, a switch mat, a two-hand switch, a limit switch or a position switch. The signaling device can also function without contact, for example, and can be configured as or include a light curtain or a light barrier, for example.

[0041] The digital input signal provided by at least one signal generator is a binary signal, distinguished by two defined states, which can be provided in particular by two static potentials. As mentioned above, these two states are characterized by different voltage levels. They are determined by the input voltage U IN The first state, where the input voltage U is below a defined threshold and is often called the low-level state, IN A low-level state occurs when the input voltage U exceeds a defined threshold, and a second state is often called a high-level state. IN ≦U Low,max and the input current I IN ≦I Low,max The high-level state is characterized by the input voltage U High , min ≦U IN ≦U High , max and the input current I IN ≧I High,min is defined by

[0042] Furthermore, the digital input circuit 100 has a second circuit part II that forms the secondary side of the digital input circuit 100. Three coupling elements 11, 11', 21, which will be described in detail below, provide a complete galvanic isolation 13 between the two circuit parts I and II. This galvanic isolation 13 can in particular protect the electronic components provided in the second circuit part II from damage due to overvoltages and can prevent errors in detecting the off state.

[0043] The digital input circuit 100 includes a subcircuit 14, 14' for each of the two digital input sections 10, 10'. The digital input signal of the first input section 10 is supplied to the first subcircuit 14, and the digital input signal of the second input section 10' is supplied to the second subcircuit 14'. In the embodiment shown here, both subcircuits 14, 14' have the same circuit structure, which will be described in more detail below. The subcircuits 14, 14' are divided into a first circuit section I and a second circuit section II.

[0044] Each of the two partial circuits 14, 14' comprises an input resistor 17, 17' and at least one input filter means 12, 12', which are provided to improve electromagnetic compatibility (EMC for short). In general, the input filter means 12, 12' can have one or more components to improve electromagnetic compatibility. These components can be, in particular, capacitors, resistors, and diodes (such as Z-diodes) for smoothing the input signal or limiting a defined input voltage. The input filter means 12, 12' of the two partial circuits 14, 14' are represented in this case by capacitors.

[0045] Connected to the input filter means 12, 12' of the two subcircuits 14, 14' are current limiting devices 15, 15' which in this example are configured as series regulators and include transistors 150, 150' implemented as bipolar transistors (npn transistors), Z diodes 151, 151' and series resistors 152, 152' for the Z diodes 151, 151'. The current limiting devices 15, 15' determine the maximum current at the digital inputs 10, 10' assigned to them.

[0046] Finally, the current limiting device 15 of the first digital input 10 is followed by a first coupling element 11 and a first threshold element 16. In this embodiment, the first coupling element 11 is a photocoupler with a light-emitting diode 110 on the primary side of the first circuit part I and a collector-emitter path 111 on the secondary side of the second circuit part II. This provides galvanic isolation 13 for this circuit part. The first coupling element 11 transmits the input signal provided via the first digital input 10 to the second circuit part II, where a defined threshold value that the digital input signal provided via the first digital input 10 must exceed is set via the first threshold element 16, allowing the signal to be transmitted by the first coupling element 11 to the second circuit part II. The first coupling element 11 and the first threshold element 16 are therefore capable of detecting the respective state (high or low) of the input signal at the first digital input 10. They are therefore primarily responsible for detecting the low state (OFF state).

[0047] In this case, the first threshold element 16 is a Z-diode arranged directly on the cathode of the optocoupler light-emitting diode 110, so that a defined voltage level is set there as a threshold. Only if the input signal at the first digital input 10 exceeds this voltage level will current flow through the optocoupler light-emitting diode 110, so that the collector-emitter path 111 of the optocoupler becomes conductive. As a result, a high-level signal can be detected at the first digital input 10.

[0048] Similarly, the current limiting device 15' of the second digital input 10' is followed by a second coupling element 11' and a second threshold element 16'. In this embodiment, the second coupling element 11' is also a photocoupler comprising a primary-side light-emitting diode 110' in the first circuit part I and a secondary-side collector-emitter path 111' in the second circuit part II. As a result, this circuit part also has galvanic isolation 13. The input signal provided via the second digital input 10' is transmitted to the second circuit part II via the second coupling element 11'. In this case, a predetermined threshold that the input signal provided via the second digital input 10' must exceed is set above the second threshold element 16', thereby enabling the signal to be transmitted to the second circuit part II using the second coupling element 11'. Thus, the second coupling element 11' and the second threshold element 16' then detect the respective states of the input signal at the second digital input 10', and are therefore essentially responsible for detecting a low-level state (off state).

[0049] In the case of the second threshold element 16', it is a Z-diode arranged directly at the cathode of the optocoupler light-emitting diode 110', whereby a defined voltage level is set as a threshold there. Only if the input signal at the second digital input 10 exceeds this voltage level, will current flow through the optocoupler light-emitting diode 110', as a result of which the collector-emitter path 111' of the optocoupler becomes conductive.

[0050] Via two outputs 18, 18′, each connected to one of the two collector-emitter paths 111, 111′, the digital input signal reaches at least one downstream logic unit (not explicitly shown). Preferably, a separate logic unit is provided for each of the two outputs 18, 18′. The logic unit can be, for example, an integrated semiconductor component, in particular a microcontroller, an ASIC, an FPGA, or other integrated logic component, and preferably has two channels to ensure reliable signal processing. The logic unit can be part of the digital input circuit 100 or part of a switching device, in particular a safety switching device, by which a load connected thereto can be switched on and safely switched off. Depending on the input signal, the logic unit generates one or more output signals for controlling a load, in particular a technical system. Alternatively, it is also possible to provide only a single logic unit for both outputs 18, 18′.

[0051] Furthermore, digital input circuit 100, in the embodiment shown here, comprises a combined test arrangement and current increasing device 20, which is implemented partly in first circuit portion I and partly in second circuit portion II. Combined test arrangement and current increasing device 20 comprises a third coupling element 21, which provides coupling to first circuit portion I and thus to the primary side of digital input circuit 100. In this embodiment, third coupling element 21 is an optocoupler having a light emitting diode 210 in second circuit portion II and a collector-emitter path 211 in first circuit portion I, thereby providing galvanic isolation 13 for this circuit portion.

[0052] The collector-emitter path 211 of the third coupling element 21 has a connection 212, via which the third coupling element 21, which is part of the combined testing device and current increasing device 20, is connected to a first electronic switching element of the sub-circuit 14 of the first digital input 10, which is configured as a first switching transistor 23. Via the connection 212, the third coupling element 21 is also connected to a second electronic switching element of the sub-circuit 14' of the second digital input 10', which in this case is configured as a second switching transistor 23'. The switching transistors 23, 23' of the two sub-circuits 14, 14', which in this case are configured as bipolar transistors (npn transistors), are connected in parallel with each other and a single switching element between the two sub-circuits 14, 14' is connected. Connection of A single that is also a continuation Connection of The third coupling element 21 is coupled to the connection 212 via a common supply line 214. The bases of the two switching transistors 23, 23' are connected to the series resistors 19, 19', respectively.

[0053] The combined test device and current increasing device 20 is configured to generate control signals that enable testing of the sub-circuits 14, 14' assigned to the two digital inputs 10, 10' and also increase the input current at the digital inputs 10, 10'.

[0054] The combined test and current increasing device 20 has a clock reference device 24 connected to a third coupling element 21, so that the third coupling element 21 is switched, i.e., conducting or not, in accordance with the clock reference device 24. A clocked, modulated control signal is thus generated by the clock reference device 24 that enables current increase at the two digital inputs 10, 10', by means of which it is possible to simultaneously test the functionality of the two subcircuits 14, 14'. The control signal controls the bases of the switching transistors 23, 23'.

[0055] In that case, for testing purposes, the level of the digital input signal supplied via the digital input sections 10, 10' is reduced as long as necessary for the subcircuits 14, 14' assigned to the two digital input sections 10, 10' to detect a low level state, even if a high level signal is present at each digital input section 10, 10'.

[0056] When the combined test device and current increasing device 20 is activated and periodically generates a drive signal, the emitter potential of the transistors 150, 150' of the current limiting devices 15, 15' is reduced to a level near 0 V (i.e., a low-level signal corresponding to the first state) by the switching transistors 23, 23' controlled by the control signal of the combined test device and current increasing device 20. This blocks the optocouplers forming the first coupling element 11 and the second coupling element 11', achieving the necessary detection of the low-level state of the subcircuits 14, 14' of the two digital inputs 10, 10', as long as they operate without any defects. At the same time, an increased input current flows through the transistors 150, 150' of the current limiting devices 15, 15' of the two subcircuits 14, 14'. This is essentially limited only by the size of the input resistors 17, 17' for the respective inputs 10, 10'. In the operating state of the combined tester and current booster 20, with control signals generated in the manner described above, if one or both subcircuits 14, 14' do not detect a low state, a fault exists.

[0057] The clock reference device 24 can be synchronized, for example, to the clock pulses of the interference signal that occur periodically at the digital inputs 10, 10'. The current increase (and therefore the test of the two subcircuits 14, 14') can be deactivated again when the interference effect subsides. This deactivation occurs after a defined switching period of the third coupling element 21, which is set here via a control element 25 that is connected to the clock reference device 24 or is active, when a higher-level control / evaluation unit of the control device, in particular of a safety control device, or a logic unit that may be part of the digital input circuit 100 or part of the control device, detects a defined state. It is also possible to integrate the control element 25 for setting the switching period, for example, in the higher-level control / evaluation unit or logic unit.

[0058] A possible safety-related hazard of the two digital inputs 10, 10' is, in particular, an electrical cross-connection between them. If two separate test and current-increasing devices are used for the two (or more) digital inputs 10, 10', at least two separate cross-connections between the digital inputs 10, 10' result. As already explained in detail above, this can lead to a failure to reliably identify possible component defects and can create dangerous situations under certain circumstances. The combined test and current-increasing device 20 shown here, which combines the two functions in a single component, allows a single cross-connection between the subcircuits 14, 14' of the two digital inputs 10, 10'. Connection of There is only a connection portion 213, which is an electrical connection portion that connects the first switching transistor 23 and the second switching transistor 23' to each other. Connection of The connection 213 advantageously preferably allows for particularly timely detection of potentially dangerous component defects in the digital input circuit 100, as will be explained in more detail below.

[0059] The safety-related risk generally arises from a high-level signal at the digital inputs 10, 10' and a voltage source at the third coupling element 21, which is configured here as an optocoupler. In the event of a component defect, this may lead to the breakdown of the existing Single connection A fault current can occur through connection 213, which leads to one of the digital inputs 10, 10' detecting a high state when in fact there is a low signal.

[0060] The effect of different defects, identified by reference characters F1, F2, F3, F4, F5, F6 in Figure 3, on the digital input circuit 100 will be explained in more detail below. During observation, it is assumed that a high level signal is present at the first digital input 10 and a low level signal is present at the second digital input 10'.

[0061] The faults F2 and F4 here represent faulty, in particular broken, ground connections of the first switching transistor 23 and the second switching transistor 23'. The remaining faults F1, F3, F5 and F6 are short circuits in the associated electronic components of the first or second sub-circuit 14, 14', symbolized by corresponding bridges.

[0062] Defects F1 and F2: When the combined test device and current increasing device 20 is not activated and therefore does not generate a control signal to increase the current and test the sub-circuits 14, 14', the fault current flows from the first digital input 10' through the transistor 150 of the current limiting device 15 and the first switching transistor 23 of the first sub-circuit 14 to the switching transistor 23' of the second sub-circuit 14'. As a result, the second switching transistor 23' is turned on, the emitter of the transistor 150' of the current limiting device 15 of the second sub-circuit 14' has a voltage value of 0 V, and thus a safe low state remains present at the second digital input 10' that can be detected appropriately by the second sub-circuit 14'.

[0063] When the combined test and current increasing device 20 is activated, thus increasing the current and generating a control signal for testing the sub-circuits 14, 14', the optocoupler forming the first coupling element 11 of the first sub-circuit 14 is made conductive or cut off depending on the level of the input voltage at the first digital input 10. Fault detection during testing depends on the level of the input voltage at the first digital input 10. However, since there is no dangerous condition, a "safe" detection of the faults F1, F2 is not yet necessary in this case. This is because, despite the faults F1, F2, the second digital input 10' remains in a safe state, since there is still a (safe) low-level state that can be properly detected by the second sub-circuit 14'.

[0064] Defects F1, F2, F4 and F5: When the combined test and current increasing device 20 is not activated, a fault current flows from the first digital input 10 through the transistor 150 of the current limiting device 15, the first switching transistor 23 of the first sub-circuit 14, and the base-collector path of the second switching transistor 23' provided in the second sub-circuit 14' into the optocoupler of the second sub-circuit 14' forming the second coupling element 11'. The fault current may be sufficient for the second sub-circuit 14' assigned to the second digital input 10' to detect a possible dangerous high-level condition.

[0065] When the combined test and current increasing device 20 is activated, the fault current is sufficient for the second sub-circuit 14' assigned to the second digital input 10' to detect possible dangerous high-level conditions, and therefore these faults are detected during testing.

[0066] Defects F2, F4, F5 and F6: When the combined test device and current multiplier 20 is not activated, a fault current flows from the voltage source of the combined test device and current multiplier 20, through the base-collector path of the second switching transistor 23', in the optocoupler forming the third coupling element 21, into the optocoupler of the second sub-circuit 14' forming the second coupling element 11'. As a result, the sub-circuit 14' of the second digital input 10' detects a potentially dangerous high-level condition.

[0067] If the combined test and current increasing device 20 is activated, this fault current will flow even when the test is running. The subcircuit 14' of the second digital input 10' will again detect the potentially dangerous high-level condition. Thus, these faults will be reliably detected during the test. It should be noted here that faults F2 and F4 can occur simultaneously as a so-called common cause fault.

[0068] An essential property of the combined test and current increasing device 20 presented here is that if a fault current occurs that is high enough to cause one of the two subcircuits 14, 14' to detect a high-level state, this fault current will continue to flow even when the test is active and the current increase is active, despite the presence of a low-level signal at the inputs 10, 10'. In this way, at least possible dangerous component defects are revealed by the test. The faulty digital inputs 10, 10', or the entire input module with these (and possibly additional) digital inputs 10, 10', can then be put into a safe state, e.g., safely turned off.

[0069] The effect of the combined test and current ramping device 20 on the response time of the digital inputs 10, 10' is briefly described below. In this implementation, the response time of the digital inputs 10, 10' is increased by the duration of the current ramping phase, because the subcircuits 14, 14' of the digital inputs 10, 10' detect a low state during the current ramping phase. However, this is only a minor drawback, since the current ramping phase and its associated test phase can be kept relatively short (e.g., about 200 μs) by the clock reference device 24.

[0070] The main advantages of the digital input circuit 100 with the combined test device and current booster 20 as described herein compared to separate test devices and current boosters include, inter alia: Maintaining a high level of security for the digital input section 10, 10' even with different circuit configurations, in particular the digital input circuit 100 with current sources. Reliable detection of potentially dangerous (component) defects through testing · Reduce potential insulating components.

[0071] At this point, additional test devices are required at the output of the potential-isolating components, here the first and second coupling elements 11, 11', configured as optocouplers between circuit part I and circuit part II, as described, for example, in DE 10 2013 106 739 A1, although these are not shown in FIG. 3, for the implementation of safe input parts 10, 10'.

[0072] 4 shows, in a highly simplified form, a safety switching device 500 for switching on and fail-safely off a load 501, in particular a technical system. The safety switching device 500 has a digital input circuit 100 with at least two digital inputs 10, 10′ for receiving a digital input signal from a signal generator 502, which may in particular be a signaling device such as an emergency stop switch. The digital input circuit 100 is implemented in the manner described above. For redundancy reasons, the signal generator 502 is configured with two channels. For redundancy reasons, the connection between the safety switching device 500 and the load 501 is also configured with two channels, so that there are two switch-off paths for safely switching off the load 501. [Explanation of symbols]

[0073] 10,10' Digital input section 11,11',21 connecting elements 12,12' Input filter means 13 Galvanic isolation 14,14' partial circuit 15,15' Current Limiting Device 16,16' threshold element 17,17' Input resistor 18,18' output 19,19' Series Resistor 20 Combined Test Device and Current Increasing Device 23,23' Switching transistor 24 Clock Reference Device 25 Control Elements 100 Digital Input Circuit 110,110',210 Light-emitting diode 111,111',211 Collector-emitter path 150,150' transistor 151,151' Z diode 152,152' Series Resistor 212 Connection 213 Single connection sequel 214 Supply Line 500 Safety Switching Device 501 Load 502 Signal Generator

Claims

1. A digital input circuit (100) for receiving a digital input signal from at least one signal generator (502), comprising: a first partial circuit (14), and at least one second sub-circuit (14'); The first sub-circuit (14) comprises a first digital input (10) via which a first digital input signal can be provided to the first sub-circuit (14), and a first threshold element (16) capable of determining a logic state of the first sub-circuit (14); a first sub-circuit (14) that assumes a first state when the first digital input signal reaches or is below a lower threshold, and a second state when the first digital input signal reaches or is above an upper threshold; At least one second sub-circuit (14') comprises a second digital input (10') via which a second digital input signal can be supplied to the second sub-circuit (14') and a second threshold element (16') capable of determining the logic state of the second sub-circuit (14'); At least one second sub-circuit (14') assumes a first state when the second digital input signal reaches or is below a lower threshold, and assumes a second state when the second digital input signal reaches or is above an upper threshold, in a digital input circuit (100); The digital input circuit (100) has a combined test device and current increasing device (20), a combined test device and current increasing device (20) configured to generate a control signal, and a functional test of the two sub-circuits (14, 14') is performed simultaneously with this control signal, increasing the input current of the digital input section (10, 10'); The first sub-circuit (14) further comprises a first current limiting device (15) for determining a maximum current at the first digital input (10), the first current limiting device (15) being connected to a first threshold element (16), and a first switching transistor (23) configured as an npn bipolar transistor, the collector of the first switching transistor (23) being connected between the first current limiting device (15) and the first threshold element (16), and the emitter of the first switching transistor (23) being grounded; The second sub-circuit (14') further comprises a second current limiting device (15') for determining the maximum current at the second digital input (10'), the second current limiting device (15') being connected to the second threshold element (16'), and a second switching transistor (23') configured as an npn bipolar transistor, the collector of the second switching transistor (23') being connected between the second current limiting device (15') and the second threshold element (16') and the emitter of the second switching transistor (23') being grounded; the first switching transistor (23) of the first partial circuit (14) and the second switching transistor (23') of the second partial circuit (14') are connected in parallel with each other; the base of the first switching transistor (23) and the base of the second switching transistor (23') are connected by a single connection (213); The combined test device and current increasing device (20) is connected to the first sub-circuit (14) and the second sub-circuit (14') by a single connection (213); A digital input circuit (100) characterized in that the detection of whether or not a defect exists in at least the first switching transistor (23) and the second switching transistor (23') is performed by a control signal from a combined testing device and current increasing device (20).

2. 2. The digital input circuit (100) of claim 1, wherein the sub-circuits (14, 14') are configured such that when a control signal of a combined test device and current increasing device (20) for testing the sub-circuits (14, 14') is received, the level of the digital input signal supplied to the sub-circuits (14, 14') via the digital input (10, 10') is internally significantly lowered to correspond to a first state of the associated sub-circuit (14, 14').

3. 3. The digital input circuit (100) according to claim 1 or 2, characterized in that the combined test device and current increasing device (20) comprises a clock reference device (24) configured to modulate the control signal of the current increasing device (20).

4. 1. A safety switching device (500) for switching on and off the power supply of a load (501), in particular of a technical system, the safety switching device (500) having a digital input circuit (100) with at least two digital inputs (10, 10') for receiving digital input signals from at least one signal generator (502), characterized in that the digital input circuit (100) is configured according to any one of claims 1 to 3.

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