Temperature-locked loop for optical elements with temperature-dependent response

Abstract

Examples described herein generally relate to temperature-locked loops for optical elements. In one example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a shear circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the shear circuit is coupled to an output node of the DCTS. The processor has an input node coupled to the output node of the shear circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. Both processors are configured to (i) control the DCTS to reduce a DC component of a signal on an output node of the DCTS and (ii) control an output voltage on an output node of the DAC based on a signal output by the shear circuit.

Description

[Technical Field]

[0001] Examples of the present disclosure generally relate to temperature-locked loops for optical elements having temperature-dependent responses. [Background technology]

[0002] Optical devices have been used for communications over fiber optic channels and the like. Optical communications can implement low-loss physical channels and high speeds. Like electrical devices, some optical devices can be used to process or filter signals, albeit optical signals. However, some optical devices can have features that are not present or important in electrical devices. Further growth and implementation of optical devices in future technologies may require these features to be addressed. Summary of the Invention [Means for solving the problem]

[0003] Examples described herein generally relate to devices and methods for a temperature-locked loop for optical elements having a temperature-dependent response. In some examples, setting tracking and temperature locking can be implemented for optical devices operating at high speeds.

[0004] An example described herein is a device. The device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage, a slicer circuit, and a processor. The DC-controllable transimpedance stage has an input node and an output node. The input node of the DC-controllable transimpedance stage is configured to be electrically coupled to a photodiode. The slicer circuit has an input node and an output node. The input node of the slicer circuit is electrically coupled to the output node of the DC-controllable transimpedance stage. The processor has an input node electrically coupled to the output node of the slicer circuit. The processor is configured to control the DC-controllable transimpedance stage to reduce a DC component of a signal on the output node of the DC-controllable transimpedance stage based on a signal on the output node of the slicer circuit. The DAC has an input node electrically coupled to the output node of the processor and an output node configured to be electrically coupled to a heater. The processor is configured to control an output voltage on the output node of the DAC based on a signal on the output node of the slicer circuit.

[0005] Another example described herein is a method for controlling the temperature of a device. A DC setting is generated by a processor, and the DC setting is output from the processor to a DC-controllable transimpedance stage. The DC-controllable transimpedance stage has an input node electrically coupled to a photodiode. The photodiode is configured to receive an optical signal from an optical element. The optical element has a temperature-dependent optical response. The processor generates the DC setting based on a signal on an output node of the DC-controllable transimpedance stage. After generating the DC setting, a temperature setting is generated by the processor. A code output from the processor to a DAC is based on the temperature setting. The DAC has an output node electrically coupled to a heater positioned proximate to the optical element. The processor generates the temperature setting based on the signal on the output node of the DC-controllable transimpedance stage.

[0006] Another example described herein is a device. The device includes an optical element, a photodiode, a heater, a transimpedance stage, a slicer circuit, and a processor. The optical element is configured to pass an optical signal and has a temperature-dependent optical response. The photodiode is positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode. The heater is positioned proximate to the optical element and configured to convert electrical energy into thermal energy. An input node of the transimpedance stage is electrically coupled to the photodiode. The transimpedance stage includes a controllable current source electrically connected between the input node of the transimpedance stage and a power supply node. An input node of the slicer circuit is electrically coupled to an output node of the transimpedance stage. An input node of the processor is electrically coupled to an output node of the slicer circuit. The processor is configured to control a current of the controllable current source based on an output signal on the output node of the slicer circuit and to control an amount of electrical energy provided to the heater based on the output signal on the output node of the slicer circuit.

[0007] These and other aspects can be understood with reference to the following detailed description.

[0008] So that the above features briefly summarized above may be understood in detail, a more particular description can be had by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical illustrative implementations and therefore should not be considered limiting of its scope. [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates a package for a device according to some examples. [Figure 2] 2 is a simplified diagram of at least a portion of the device of FIG. 1 according to some examples. [Figure 3A] 10 is a chart illustrating the effect of the center wavelength of the optical signal being to the right (RHS) and left (LHS) of the peak magnitude of the optical response, according to some examples. [Figure 3B] 10 is a chart illustrating the effect of the center wavelength of the optical signal being to the right (RHS) and left (LHS) of the peak magnitude of the optical response, according to some examples. [Figure 4] FIG. 3 is a more detailed schematic diagram of the simplified schematic diagram of FIG. 2, in accordance with some examples. [Figure 5] 1 is a flowchart of a method for a temperature locked loop according to some examples. [Figure 6] 5 illustrates a schematic diagram of the digital signal processor (DSP) of FIG. 4, according to some examples. [Figure 7] 5 is a timing diagram of various signals of the DSP, the voltage output from the digital-to-analog converter (DAC) of FIG. 4, and the temperature of the heater of FIG. 4, according to some examples. [Figure 8] FIG. 1 is a circuit diagram of a controllable current source according to some examples. [Figure 9] 5 is a timing diagram of the heat code output by the DSP, the voltage output from the DAC of FIG. 4, and the temperature of the heater of FIG. 4, according to some examples. [Figure 10] FIG. 1 is a schematic diagram of a pulse width modulation (PWM) circuit of a DSP in accordance with some examples. [Figure 11A] 5A and 5B are timing diagrams illustrating signals generated in a PWM circuit in different modes, according to some examples. [Figure 11B] 5A and 5B are timing diagrams illustrating signals generated in a PWM circuit in different modes, according to some examples. [Figure 12A] 10 is a flowchart of the operation of a tracking circuit of a DSP in accordance with some examples. [Figure 12B] 10 is a flowchart of the operation of a tracking circuit of a DSP in accordance with some examples. [Figure 13] FIG. 1 is a simplified schematic diagram of a device according to some examples. [Figure 14] 14 is a flowchart of a sequence of operations of the device of FIG. 13 according to some examples. DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, wherever possible, identical reference numbers have been used to indicate identical elements common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.

[0011] Examples described herein generally relate to devices and methods for a temperature-locked loop for an optical element having a temperature-dependent response. Generally, a device according to some examples includes an electrical integrated circuit (IC) die (including an electrical IC) and an optical die (including an optoelectronic circuit). The optical die and the optoelectronic circuit include an optical element, a photodiode, and a heater. The optical element is configured to pass an optical signal, and the optical element has a temperature-dependent optical response. Exemplary optical elements include a ring modulator, a double ring filter, a Mach-Zehnder interferometer (MZI), etc. The photodiode is positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode. The heater is positioned proximate to the optical element. The electrical IC die and the electrical IC include a controller and a first digital-to-analog converter (DAC). The photodiode is electrically coupled to an input node of the controller. An output node of the controller is electrically coupled to an input node of the first DAC, and an output node of the first DAC is electrically coupled to the heater. Generally, the controller is configured to control the temperature of the heater, thereby controlling the temperature of the optical element, so that the optical element has a target optical response at a target wavelength of the optical signal. The controller can cause the first DAC to output a voltage having a dithering duty cycle.

[0012] Further, the controller of the electrical IC may include a transimpedance stage, a slicer circuit, and a processor (e.g., a digital signal processor (DSP)). The transimpedance stage may include a transimpedance amplifier and a controllable current source having a second DAC. The processor is configured to iteratively track a DC setting and a temperature setting. The DC setting may include a code output to the second DAC that causes the second DAC to output a bias voltage to the controllable current source and / or may include one or more select signals that can operatively couple or decouple biased transistors in the controllable current source. The controllable current source is configured to reduce and / or eliminate the DC component of the signal output by the transimpedance stage. The temperature setting may include a level select value and a duty code, and in some examples, a thermal code having a dithering duty cycle is generated based on the level select value and the duty code and output to the first DAC. The voltage output from the first DAC may control a heater to achieve a temperature within the optical die such that the optical element has an optical response, for example, with peaks or valleys that match a target wavelength. The DC and temperature settings can be tracked based on the sampled signal from the slicer circuit and based on the respective signals output from the transimpedance stage. In some examples, tracking and locking can be performed for optical devices operating at high speeds, such as 53 Gb / s or higher.

[0013] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by like reference numerals throughout the drawings. Note that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or as limiting the scope of the claimed invention. Additionally, the illustrated examples need not have all the aspects or advantages shown. An aspect or advantage described in connection with a particular example is not necessarily limited to that example and may be implemented in any other example even if not so illustrated or explicitly described. Furthermore, while methods described herein may be described with a particular order of operations, other methods according to other examples may be implemented with more or fewer operations in various other orders (e.g., including different serial or parallel execution of various operations).

[0014] In the following description, various signals, data, or codes are described in the context of the operation of various circuits. The described signals, data, or codes refer to corresponding nodes to which the signals, data, or codes are applied or propagated, and further refer to nodes that are communicatively coupled and / or electrically connected. For example, a description of a signal, data, or code being output from a first circuit and input to a second circuit indicates that the output node of the first circuit (where the signal, data, or code is output from the first circuit) is communicatively coupled and / or electrically connected to the input node of the second circuit (where the signal, data, or code is input to the second circuit). While explicit descriptions of such nodes may be omitted in the following description, those skilled in the art will readily recognize their existence. Furthermore, a given node may have multiple bit positions, such as multi-bit data or multi-bit code.

[0015] 1 illustrates a device package 100 according to some examples. The package 100 includes an electrical integrated circuit (IC) die 102, an optical die 104, and a package substrate 106. The electrical IC die 102 includes various circuits configured to generate electrical signals that are transmitted to the optical die 104, and includes control circuitry configured to control the optical response of the optical die 104. The optical die 104 is configured to generate an optical signal based on the received electrical signal and transmit the optical signal, for example, via an optical fiber.

[0016] The optical die 104 is mechanically attached and electrically coupled to the electrical IC die 102 (e.g., the backside of the electrical IC die 102) by an external electrical connector 112. The external electrical connector 112 is, in some examples, a minibump. The electrical IC die 102 (e.g., the front side of the electrical IC die 102) is mechanically attached and electrically coupled to a first side of the package substrate 106 by an external electrical connector 114. The external electrical connector 114 is, in some examples, a controlled collapse chip connection (C4). The external electrical connector 116 is on a second side of the package substrate 106 (e.g., the opposite side from the first side of the package substrate 106) and is mechanically attached and electrically coupled to the package substrate 106.

[0017] FIG. 2 is a simplified diagram of at least a portion of the device of FIG. 1 according to some examples. In the illustrated example, the electrical IC die 102 includes an electrical IC 202, and the optical die 104 includes an optoelectronic circuit 204. The electrical IC 202 includes a controller 210 and a DAC 212. Although not shown, the electrical IC 202 further includes circuitry for generating an electrical signal to be transmitted as an optical signal via an optical channel. The optoelectronic circuit 204 includes a light source 220, an optical element 222, an optical output channel 224, a photodiode 226, and a heater 228. The optical element 222 can be any optical element configured to pass an optical signal and having a temperature-dependent optical response, such as a ring modulator, a double ring filter, or a Mach-Zehnder interferometer (MZI). In some examples, the heater 228 is a resistor. However, any heater can be implemented.

[0018] In general, the circuitry of the electrical IC 202 generates an electrical signal that is transmitted to the optoelectronic circuit 204. The light source 220 generates an optical signal based on the received electrical signal and transmits the optical signal to the optical element 222. The optical signal output from the optical element 222 is transmitted via the optical output channel 224. The photodiode 226 is disposed within the optical die 104 such that a portion of the optical signal output from the optical element 222 is incident on the photodiode 226. The photodiode 226 is configured to generate a current in response to the optical signal incident on the photodiode 226 (including, for example, by being electrically coupled to a power supply node such as a VDD node). The photodiode 226 is electrically coupled to the controller 210, which is configured to detect the current generated by the photodiode 226. The controller 210 outputs a digital value to the DAC 212 in response to the detected current. The DAC 212 is configured to convert the digital value into an analog voltage and / or current. The heater 228 is electrically coupled to the DAC 212 and is disposed within the optical die 104 proximate to the optical element 222. The DAC 212 is configured to output an analog voltage and / or current to the heater 228. In response to the received analog voltage and / or current, the heater 228 can control the temperature of the optical element 222.

[0019] In some examples, optical element 222 has an optical response that can change based on the temperature of optical element 222. FIGS. 3A and 3B are charts illustrating the effect of temperature on the optical response of optical element 222 according to some examples. The charts in FIGS. 3A and 3B have wavelength (λ) along the x-axis and the magnitude (|H|) of the optical response of optical element 222 (e.g., as a function of wavelength) along the y-axis. FIGS. 3A and 3B illustrate the effect of temperature on the optical response of optical element 222 based on the center wavelength (λ c ) 302. FIG. 3A shows the center wavelength (λ c ) 302 is on the right side (RHS) of the peak optical response magnitude, and Figure 3B shows the effect of the center wavelength (λ c ) 302 is on the left side (LHS) of the peak optical response magnitude.

[0020] FIG. 3A shows a first response 304 when the optical element 222 is at a first temperature and a second response 306 when the optical element 222 is at a second temperature. The first temperature is lower than the second temperature. In this RHS scenario, the first response 304 is at a center wavelength (λ c ) 302 has a center wavelength (λ ) smaller than the magnitude 316 of the second response 306 c ) 302. When the temperature of the optical element 222 is increased from a first temperature to a second temperature, the center wavelength (λ c ) 302 and the center wavelength (λ c ) 302 approaches the peak of the second response 306. Conversely, decreasing the temperature of the optical element 222 from the second temperature to the first temperature decreases the central wavelength (λ c ) 302, which can result in a decrease in magnitude at the central wavelength (λ c ) 302 further away from the peak of the first response 304.

[0021] FIG. 3B shows a first response 324 when the optical element 222 is at a first temperature and a second response 326 when the optical element 222 is at a second temperature. The first temperature is lower than the second temperature. In this LHS scenario, the first response 324 is at a center wavelength (λ c ) 302 is greater than the magnitude 336 of the second response 326 c ) 302. Increasing the temperature of the optical element 222 from a first temperature to a second temperature increases the center wavelength (λ c ) 302, which results in a decrease in the magnitude of the central wavelength (λ c ) 302 further away from the peak of the second response 326. Conversely, lowering the temperature of the optical element 222 from the second temperature to the first temperature moves the center wavelength (λ c ) 302, which can result in an increase in magnitude at the central wavelength (λ c ) 302 to the peak of the first response 324.

[0022] In general, the examples described herein can use a temperature-locked loop to control the temperature of optical element 222 to control the optical response of optical element 222. Heater 228 is configured to generate thermal energy that is generally localized proximate optical element 222, and heater 228 is controlled by controller 210. In response to an optical signal detected by photodiode 226, controller 210 can control heater 228 to provide thermal energy to increase and / or decrease the temperature of optical element 222, for example, to move a peak or valley in the magnitude of the optical response of optical element 222 closer to the center wavelength of the optical signal.

[0023] In some examples, the heater 228 may not actively reduce the temperature of the optical element 222. Rather, thermal energy can be dissipated from the package 100, such as by using a heat spreader, which, when combined with the reduced amount of thermal energy provided by the heater 228, can result in a reduction in temperature (e.g., a collective reduction in thermal energy) of the optical element 222. In such situations, the temperature can be increased by a heater 228 providing thermal energy at a greater rate than the thermal energy is dissipated, and the temperature can be decreased by a heater providing thermal energy (if any) at a lesser rate than the thermal energy is dissipated.

[0024] 4 is a more detailed schematic diagram of the simplified schematic diagram of FIG. 2, according to some examples. The controller 210 includes a DC-controllable transimpedance stage, a slicer circuit 402, a DAC 404, and a DSP 406. The DC-controllable transimpedance stage includes a current source 410, a resistor 412, a transimpedance amplifier (TIA) 414, a controllable current source 416, and a DAC 418.

[0025] The cathode of the photodiode 226 is electrically connected to a first power supply node (e.g., a VDD node), and the anode of the photodiode 226 is electrically coupled to an input node 420 of the DC-controllable transimpedance stage, which may also be an input node of the controller 210. A current source 410 is electrically connected between the first power supply node (e.g., a VDD node) and the input node 420. The current source 410 may be or include a current mirror biased by a static current such that the current source 410 is configured to provide a static or constant current. A controllable current source 416 is electrically connected between the input node 420 and a second power supply node (e.g., a ground node). A first terminal of a resistor 412 is electrically connected to the input node 420, and a second terminal of the resistor 412 (opposite the first terminal) is electrically connected to an output node 422 of the DC-controllable transimpedance stage. The input node of TIA 414 is electrically connected to input node 420 , and the output node of TIA 414 is electrically connected to output node 422 .

[0026] The signal input node of the slicer circuit 402 is electrically connected to the output node 422 of the DC-controllable transimpedance stage. The reference voltage input node of the slicer circuit 402 is electrically connected to the output node of the DAC 404. The output node of the slicer circuit 402 is electrically connected to the input node of the DSP 406. In some examples, the slicer circuit 402 can be or include a comparator. The input node of the DAC 404 is connected to a reference voltage (V ref ) can be electrically coupled to a memory element (e.g., an electrical fuse (eFuse), etc.) that stores a digital value corresponding to the reference voltage V ref In some cases, V DD / 2.

[0027] The DSP 406 has one or more control output nodes electrically connected to one or more control input nodes of each of the DC-controllable transimpedance stages, including the controllable current source 416 and the DAC 418. The DSP 406 has a control output node electrically connected to the control input node of the controllable current source 416. The DSP 406 has another control output node electrically connected to an input node of the DAC 418. The output node of the DAC 418 is electrically connected to a bias voltage node of the controllable current source 416. In the illustrated example, the controllable current source 416 has two mechanisms by which the controllable current source 416 can be controlled, which are described in more detail below. In other examples, one and / or different mechanisms can be implemented to control the controllable current source 416.

[0028] The DSP 406 has another output node electrically connected to the input node of the DAC 212. The DSP 406 may include, or be any combination of, combinational logic, sequential logic, a state machine, and any other circuitry. The DSP 406 is generally configured to implement the functions described herein, and further, each of the functions may be implemented solely by hardware, by hardware executing machine-executable instructions, or by a combination thereof (e.g., some of the functions are implemented solely by hardware and other parts of the functions are implemented by hardware executing machine-executable instructions).

[0029] The output node of DAC 212 is electrically coupled to the input node of heater 228. In the illustrated example, heater 228 includes or is a resistor 430. Resistor 430 is electrically connected between the input node of heater 228 and a power supply node (e.g., a ground node) in the illustrated example.

[0030] In operation, the photodiode 226 generates a current in response to an optical signal incident on the photodiode 226. The current generated by the photodiode 226 is referred to as an input current I inThe DC-controllable transimpedance stage controls the input current I at the input node 420. in The slicer circuit 402 generates a voltage signal at an output node 422 of the DC-controllable transimpedance stage based on the reference voltage. The slicer circuit 402 generates a logic "1" or a logic "0" based on whether the voltage signal at the output node 422 is greater than a reference voltage output by the DAC 404. The DAC 404 generates the reference voltage based on, for example, a digital value stored in a memory element communicatively coupled to an input node of the DAC 404. The reference voltage may be a static voltage, and thus, in some examples, the digital value stored in the memory element may be static. The DSP 406 samples the logic "1"s and logic "0"s generated by the slicer circuit 402.

[0031] 5, the DSP 406 iteratively tracks the DC setting in block 502 and tracks the temperature setting in block 504. When tracking the DC setting in block 502, the DSP 406 iteratively tracks the input current I at the input node 420. in The current I shunts the DC component of DC , which may result in a reduced and / or eliminated DC component of the voltage signal at output node 422. Reducing and / or eliminating this DC component of the voltage signal may allow slicer circuit 402 and DSP 406 to more accurately capture logic "1"s and logic "0"s for the optical signal incident on photodiode 226.

[0032] Generally, as will be described in more detail below, the DSP 406 responsively controls the current I of the controllable current source 416 based on the number of logic "1"s and the number of logic "0"s captured from the slicer circuit 402. DCThe voltage output from DAC 212 to heater 228 dithers between different duty cycles during the period in which samples from slicer circuit 402 are captured for DC setting tracking in block 502. Generally, for a statistically significant sample size, the optical signal incident on photodiode 226 is assumed to have an equal number of logic "1"s and logic "0"s. Thus, with the voltage output from DAC 212 dithering between different duty cycles, if the number of captured logic "1"s is, for example, significantly greater than the number of captured logic "0"s, a DC component may be present in the voltage signal at output node 422, and DSP 406 accordingly controls current I of controllable current source 416 to reduce and / or eliminate the DC component of the voltage signal at output node 422. DC Conversely, if the number of captured logic "0"s is, for example, significantly greater than the number of captured logic "1"s, the current I of the controllable current source 416 is adjusted. DC is the input current I at the input node 420 in , and the DSP 406 accordingly controls the current I of the controllable current source 416 to restore the diverted AC component of the voltage signal at the output node 422. DC Adjust.

[0033] When tracking the temperature setting in block 504, the DSP 406 sets the code provided to the DAC 212, which in turn provides a voltage and / or current to the heater 228 (e.g., resistor 430). Depending on the voltage and / or current and the rate at which thermal energy dissipates from the package 100, the temperature of the optical element 222 can be maintained, increased, or decreased, thereby adjusting the optical response of the optical element 222. The code has a dithering duty cycle. For example, the code can have one duty cycle while the clock signal is logically low and another, different duty cycle while the clock signal is logically high. As described in more detail below, the DSP 406 responsively increases or decreases the level of the code provided to the DAC 212 and / or the duty cycle of the code based on the number of logic "1"s and the number of logic "0"s sampled at a given time within an individual cycle of the clock signal. Generally, the number of captured logic "1's" and logic "0's" indicates whether the center wavelength of the optical signal is on the RHS or LHS, due in part to the DC setting, of the optical response of the optical element 222. The DSP 406 adjusts the level and / or duty cycle of the code provided to the DAC 212 based on the number of captured logic "1's" and logic "0's", such that the temperature of the optical element 222 is adjusted in response.

[0034] For example, because package 100 may be placed in an environment where the ambient temperature may vary, DSP 406 may iteratively track the DC setting and track the temperature setting to adjust the amount of electrical energy provided to heater 228 that the heater converts to thermal energy. In each iteration, the DC setting adjusts the current I of controllable current source 416. DC can be reset to some predetermined initial amount so that the amount can be determined anew at each iteration. The temperature setting can be adjusted for each iteration. The temperature setting, in some instances, is not reset for each iteration.

[0035] The following figures and descriptions provide more detailed examples that are programmable in some aspects. Other examples may not be programmable, or may be programmable in less, more, or different ways. Those skilled in the art will readily understand how to modify the following examples to omit or include various aspects of programmability.

[0036] 6 shows a schematic diagram of the DSP 406 according to some examples. The DSP 406 includes a clock divider circuit 602, a clock generator circuit 604, multiplexers 606, 614, a max / min calculation circuit 608, a synchronization circuit 610, a tracking circuit 612, and a pulse width modulation (PWM) circuit 616. FIG. 6 also shows the DACs 212, 418, the heater 228, the slicer circuit 402, and the controllable current source 416 to facilitate explanation of the various signals.

[0037] Before describing FIG. 6 in detail, the various signals identified in FIG. 6 will be generally described with respect to the timing diagram of FIG. 7. This general description helps contextualize the operations and functions described in detail later. The DSP clock signal (dsp_clk) is generally the clock signal on which the operation of the DSP 406 is based. The tracking clock signal (track_clk) is a divided clock signal based on dsp_clk. In the example described herein, track_clk has a frequency that is half the frequency of dsp_clk, although the frequency of track_clk can be other divided amounts of the frequency of dsp_clk. In one example, the frequency of dsp_clk is 875 MHz and the frequency of track_clk is 437.5 MHz.

[0038] The sampling clock signal (sampling_clk) and the peak lock signal (slicer_clk_peaklock) have the same frequency and are phase-aligned. Sampling_clk, in part, controls when the DSP 406 is in the DC setting tracking stage in block 502 and when it is in the temperature setting tracking stage in block 504. Sampling_clk may be programmable. Typically, sampling_clk has a frequency several orders of magnitude less than that of dsp_clk. For example, the frequency of sampling_clk may be on the order of tens of kilohertz to tens of megahertz. Slicer_clk_peaklock is typically at a logic "1" level except for a brief period within each cycle when a decision is made by the DSP 406 to increase or decrease the temperature setting, which resets the slicer circuit 402.

[0039] The PWM mode clock signal (pwm_mode_clk) is shown in FIG. 7, but may not be explicitly shown in the DSP 406. pwm_mode_clk indicates the frequency at which the signal is output from the PWM circuit 616. pwm_mode_clk is a divided clock signal based on dsp_clk. pwm_mode_clk has a programmable frequency in the example described below. The frequency of pwm_mode_clk can be any division of the frequency of dsp_clk, whether programmable or non-programmable. In one example, pwm_mode_clk is programmable between two modes, one of which controls pwm_mode_clk to have a frequency that is 1 / 16th the frequency of dsp_clk, and the other of which controls pwm_mode_clk to have a frequency that is 1 / 64th the frequency of dsp_clk.

[0040] An analog output voltage (Vout_thermal_dac) is output from the DAC 212 to the heater 228. Vout_thermal_dac has the same frequency as pwm_mode_clk based on the signal output from the DSP 406. Vout_thermal_dac oscillates between a k-level voltage (v[k]) and a (k+1)-level voltage (v[k+1]). The duty cycle of Vout_thermal_dac is dithered based on sampling_clk. When sampling_clk is logically low, Vout_thermal_dac has a duty cycle DC0, and when sampling_clk is logically high, Vout_thermal_dac has a duty cycle DC1. Duty cycle DC1 is greater than duty cycle DC0.

[0041] Vout_thermal_dac with duty cycle DC0 causes the temperature at heater 228 to be temperature Temp0. Vout_thermal_dac with duty cycle DC1 causes the temperature at heater 228 to be temperature Temp0+deltaTemp. A delay 702 from the change from duty cycle DC0 to duty cycle DC1 can occur before the temperature changes in response.

[0042] The temperature at the heater 228 can be a complex function of the rate at which electrical energy is converted to thermal energy by the heater 228 and the rate at which the thermal energy dissipates from the package 100. When Vout_thermal_dac is larger (e.g., for voltage v[k] versus voltage v[k+1]), more thermal energy is converted at the heater 228. Thus, a larger duty cycle of Vout_thermal_dac allows more thermal energy to be converted at the heater 228 compared to a smaller duty cycle of Vout_thermal_dac (assuming Vout_thermal_dac dithers between the same voltages versus duty cycle). This can result in more thermal energy being produced at the heater 228, which can cause a temperature increase. While the temperature increase can be a logarithmic response, FIG. 7 shows a stepwise increase or decrease for illustrative purposes. In some examples, the delay 702 between the time the duty cycle of Vout_thermal_dac is increased and the time the temperature at the heater 228 reaches the temperature Temp0+deltaTemp is on the order of 6 μs. Multiple cycles of the dithering Vout_thermal_dac can occur between the time the duty cycle is increased and the time the temperature at the heater 228 reaches the temperature Temp0+deltaTemp.

[0043] The temperature at the heater 228 can be controlled by selecting which k-level voltage v[k] and (k+1)-level voltage v[k+1] should be dithered and by selecting the duty cycle for dithering Vout_thermal_dac. Selecting the value of k determines the voltage levels to which Vout_thermal_dac dithers. Selecting these voltage levels can determine the possible range of temperatures that can be achieved at the heater 228 (e.g., from temperature Temp[k] to temperature Temp[k+1]).

[0044] Selecting the duty cycle of Vout_thermal_dac for dithering can achieve a temperature at the heater 228 that is within the range from temperature Temp[k] to temperature Temp[k+1]. The duty cycle can achieve an interpolation of the temperature at the heater 228 that is within the range from temperature Temp[k] to temperature Temp[k+1] due to the accumulation (e.g., integration) of thermal energy converted by the heater 228. A lower duty cycle can bring the temperature at the heater 228 closer to temperature Temp[k], and a higher duty cycle can bring the temperature at the heater 228 closer to temperature Temp[k+1].

[0045] 6, clock divider circuit 602 is configured to divide the frequency of an input clock signal by an amount, in one example, by 2. Clock divider circuit 602 may include a clocked D flip-flop configured to divide the frequency by 2. dsp_clk is input to an input node of clock divider circuit 602, and track_clk is output to an output node of clock divider circuit 602.

[0046] The clock generation circuit 604 is configured to generate sampling_clk and slicer_clk_peaklock based on track_clk, a programmable sampling frequency value (prog_sampling_freq), and a programmable sampling offset value (prog_sampling_offset). The clock generation circuit 604 may include any suitable logic or other circuitry for generating sampling_clk and slicer_clk_peaklock. prog_sampling_freq may select a primary frequency for sampling_clk, and the available primary frequencies may be determined by the architecture and circuitry implemented by the clock generation circuit 604. prog_sampling_offset may select the number of additional cycles of track_clk to include within one cycle for sampling_clk, and the available number of additional cycles may be determined by the architecture and circuitry implemented by the clock generation circuit 604. As an example, assuming that 32,768 cycles of track_clk occur for each cycle of a selected primary frequency indicated by prog_sampling_freq, and the number of additional cycles indicated by prog_sampling_offset is 128, then sampling_clk will have a frequency that achieves 32,896 cycles of track_clk per cycle of sampling_clk (e.g., 32,768 + 128). The frequency of sampling_clk can be expressed mathematically as shown below:

[0047]

number

[0048] where f sampling_clk and f track_clkare the respective frequencies of sampling_clk and track_clk, f(prog_sampling_freq) is the main frequency indicated by prog_sampling_freq, and C(prog_sampling_freq) is the number of additional cycles indicated by prog_sampling_offset. Table 1 below shows the f track_clk , prog_sampling_freq, f(prog_sampling_freq), prog_sampling_offset, C(prog_sampling_freq), and f sampling_clk Example values ​​of

[0049] [Table 1]

[0050] The clock generation circuit 604 further generates slicer_clk_peaklock based on sampling_clk. slicer_clk_peaklock is generally at a logic level that enables the slicer circuit 402 except for a relatively small amount of time during each cycle of sampling_clk, and slicer_clk_peaklock is at a logic level that resets the slicer circuit 402, as described above. The time that slicer_clk_peaklock is at a logic level that resets the slicer circuit 402 allows the DSP 406 to determine, and possibly adjust, the code output to the DAC 212 during the temperature setting tracking phase in block 504.

[0051] Multiplexer 606 is configured to receive track_clk at a "1" selection input node and slicer_clk_peaklock at a "0" selection input node. Multiplexer 606 is configured to selectively output track_clk and slicer_clk_peaklock as the slicer clock signal (slicer_clk) based on a control signal input from multiplexer 614, described below. In general, when DC setting tracking is enabled, slicer_clk is track_clk during the DC setting tracking phase of block 502, and slicer_clk is slicer_clk_peaklock during the temperature setting tracking phase of block 504. When DC setting tracking is disabled, slicer_clk is track_clk.

[0052] The max / min calculation circuit 608 is configured to calculate the maximum and / or minimum number of logic "1"s and / or "0"s targeted for capture during a cycle of sampling_clk. Because the signals captured from the slicer circuit 402 are complementary signals, determining the maximum number of logic "1"s can also indicate the minimum number of logic "0"s, and vice versa. Thus, various logic can be implemented using either or a combination of the maximum and / or minimum number of logic "1"s and / or "0"s. In the example described herein, the max / min calculation circuit 608 is configured to calculate the maximum and minimum number of logic "1"s. The max / min calculation circuit 608 may include any suitable logic or other circuitry for calculating maximum and / or minimum values.

[0053] In the illustrated example, the max / min calculation circuit 608 is configured to calculate a maximum number of logic "1's" (MAX1) and a minimum number of logic "1's" (MIN1) based on a programmable TIA DC error ratio value (prog_tia_dc_ratio), prog_sampling_freq, prog_sampling_offset, and track_clk. The prog_tia_dc_ratio indicates the percentage of error samples that a number of samples captured from the slicer circuit 402 within one cycle of sampling_clk may contain. For example, if 1% of the number of captured samples may be erroneous and the number of samples is 32,896 (e.g., the number of cycles of track_clk per one cycle of sampling_clk in the example above), the number of error samples may be 329 out of 32,896.

[0054] For DC setting tracking, several samples are captured from the slicer circuit 402 based on track_clk during each cycle of sampling_clk. During a cycle of sampling_clk, Vout_thermal_dac has different duty cycles for different portions of sampling_clk, as described above with respect to FIG. 7. After a delay 702, for one cycle of sampling_clk, the temperature at the heater 228 will therefore dither, such that the response of the optical element 222 dithers as well. Under these conditions, the input current I in If the DC component of the input current I is present and not substantially removed, the samples captured from the slicer circuit 402 based on track_clk may have a significantly higher number of logic "1"s compared to the number of logic "0"s, and vice versa. Ideally, the input current I inThe DC component of the signal is removed and the number of logic "1"s equals the number of logic "0"s. The number of logic "1"s in the optical signal incident on the photodiode 226 is assumed to equal the number of logic "0"s, such that for a statistically significant sample size, the number of logic "1"s in the samples captured from the slicer circuit 402 equals the number of logic "0"s. Any deviation from the number of captured logic "1"s equaling the number of captured logic "0"s is therefore assumed to be an error. Thus, MAX1 is calculated as half the number of cycles of track_clk per one cycle of sampling_clk multiplied by one half the ratio indicated by prog_tia_dc_ratio, and MIN1 is calculated as half the number of cycles of track_clk per one cycle of sampling_clk multiplied by one half the ratio indicated by prog_tia_dc_ratio. The number of cycles of track_clk per cycle of sampling_clk can be calculated as the number of cycles of track_clk per cycle of the main frequency indicated by prog_sampling_frequency plus the number of additional cycles indicated by prog_sampling_offset, as described above. MAX1 can be expressed mathematically as shown below:

[0055]

number

[0056] where f track_clk , f(prog_sampling_freq), C(prog_sampling_offset) are as described above, and E(prog_tia_dc_ratio) is the ratio indicated by prog_tia_dc_ratio (divided by 100). If MAX1 is a non-integer, MAX1 is rounded down to the nearest integer. MIN1 can be expressed mathematically as:

[0057]

number

[0058] If MIN1 is a non-integer, MIN1 is rounded up to the nearest integer. Table 2 below lists example values ​​for prog_tia_dc_ratio, E(prog_tia_dc_ratio), and the resulting MIN1 and MAX1, assuming that prog_sampling_freq[1:0]=00 and prog_sampling_offset[3:0]=0000 as shown in Table 1.

[0059] [Table 2]

[0060] Before turning specifically to the tracking circuit 612, the signals output from the tracking circuit 612 to the DAC 418 and the controllable current source 416 will be described. The transimpedance stage DAC digital code (tia_dac_code) is a multi-bit value (e.g., an 8-bit value) output from the tracking circuit 612 to the DAC 418. The DAC 418 converts the multi-bit value of tia_dac_code to an analog bias voltage (v_tia_dac), which is output to the controllable current source 416. The transimpedance stage current select digital code (tia_ictrl) is a multi-bit code (e.g., an 8-bit code) output from the tracking circuit 612 to the controllable current source 416.

[0061] Generally, the controllable current source 416 includes a plurality of series-connected transistor pairs (e.g., channels of transistors electrically connected in series) electrically connected in parallel. For each pair, one of the transistors has a gate node electrically connected to v_tia_dac to bias its resistor and have a resistance, and the other of the transistors has a gate node electrically connected to a respective bit position of tia_ictrl to selectively and operatively electrically connect the transistors of the respective pair in a parallel configuration.

[0062] 8 to illustrate v_tia_dac and tia_ictrl, an exemplary controllable current source 416 is shown. The controllable current source 416 includes i series-connected n-type transistor pairs 802-0, 804-0, 802-1, 804-1, ... 802-(i-1), 804-(i-1) (e.g., n-type field effect transistors FETs).

[0063] For each series-connected pair of n-type transistors 802, 804, the source node of n-type transistor 802 is electrically connected to a power supply node (e.g., a ground node). The drain node of n-type transistor 802 is electrically connected to the source node of n-type transistor 804, and the drain node of n-type transistor 804 is electrically connected to node 810. Thus, the i series-connected n-type transistor pairs 802, 804 are electrically connected in parallel. The gate node of each of n-type transistors 802 is electrically connected to a node to which v_tia_dac is applied. Each gate node of n-type transistor 804 is electrically connected to a node to which an individual bit value of tia_ictrl is applied. For example, the gate node of n-type transistor 804-0 is electrically connected to the node to which tia_ictrl[0] is applied, the gate node of n-type transistor 804-1 is electrically connected to the node to which tia_ictrl[1] is applied, and so on. v_tia_dac can bias n-type transistors 802 to have a desired resistance. To selectively and operatively connect n-type transistors 802 in parallel to achieve an effective resistance, the bit positions of tia_ictrl can selectively place n-type transistors 804 in an individual open (e.g., non-conducting) or closed (e.g., conducting) state. Operatively electrically connecting biased n-type transistors 802 in parallel can cause a current I to flow through node 810. DC can be controlled.

[0064] 6, the synchronization circuit 610 is configured to synchronize the input signal (tia_in) from the slicer circuit 402 to the track_clk. The synchronization circuit 610 can be, or can include, a clock-triggered flip-flop, for example. The synchronization circuit 610 outputs the synchronized tia_in to the tracking circuit 612.

[0065] The tracking circuit 612 is configured to track tia_in and accordingly output various codes (e.g., for DC set point tracking) for controlling the controllable current source 416. The tracking circuit 612 is configured to receive track_clk from the clock divider circuit 602, sampling_clk from the clock generation circuit 604, synchronized tia_in from the synchronization circuit 610, MIN1 and MAX1 from the max / min calculation circuit 608, and a programmable DC tracking confidence vote value (prog_tia_dc_vote). The tracking circuit 612 is further configured to generate and output tia_dac_code, tia_ictrl, and a tracking DC set point phase complete signal (tia_dc_track_done).

[0066] prog_tia_dc_vote is or indicates the number of sampling cycles within a predefined number of cycles of sampling_clk where the number of logic "1"s captured from tia_in (based on track_clk) is greater than or equal to MIN1 and less than or equal to MAX1 to determine if the DC setting tracking phase is complete.

[0067] tia_dc_track_done indicates whether the DC configuration tracking phase is complete. In this example, tia_dc_track_done is logic "0" while the DC configuration tracking phase is in progress and logic "1" when the DC configuration tracking phase is complete.

[0068] If the number of logic "1"s captured based on track_clk for individual cycles of sampling_clk is greater than or equal to MIN1 and less than or equal to MAX1 for a number of cycles of prog_tia_dc_vote before the predetermined number of cycles of sampling_clk occurs, tia_dc_track_done is set to logic "1" to indicate that the DC set tracking phase is complete. Otherwise, after the predetermined number of cycles of sampling_clk occurs, tia_dac_code and / or tia_ictrl are set to logic "1" to indicate that the current I of the controllable current source 416 is reached. DC and another iteration of a predetermined number of cycles is performed to continue the DC set point tracking phase, further details of which will be described later.

[0069] The tracking circuit 612 outputs tia_dc_track_done, which is set to a logic "0" during the DC-set tracking phase and to a logic "1" when the DC-set tracking phase is complete, as described above. tia_dc_track_done is inverted and input to a "1" select input node of a multiplexer 614. A logic "1" is input to a "0" select input node of the multiplexer 614. A select control input node of the multiplexer 614 receives a transimpedance stage DC tracking enable signal (tia_dc_track_en), which may be a user-configurable enable signal. An output node of the multiplexer 614 is communicatively coupled to a select control input node of the multiplexer 606. When DC setting tracking is disabled (such that tia_dc_track_en is set to logic "0"), multiplexer 614 outputs a logic "1" to the select control input node of multiplexer 606, which causes multiplexer 606 to output slicer_clk_peaklock as slicer_clk to slicer circuit 402. When DC set tracking is enabled (such that tia_dc_track_en is set to logic "1"), multiplexer 614 outputs inverted tia_dc_track_done to the select control input node of multiplexer 606, which causes multiplexer 606 to output slicer_clk_peaklock as slicer_clk to slicer circuit 402 when the DC set tracking phase is complete (e.g., when tia_dc_track_done is logic "1"), and to output track_clk as slicer_clk to slicer circuit 402 during the DC set tracking phase (e.g., when tia_dc_track_done is logic "0").

[0070] Before describing the tracking circuit 612 and the PWM circuit 616, the signals output from the PWM circuit 616 to the DAC 212 will be described. The output DAC thermal code (Dout_thermal_code[63:0]) is a multi-bit value (e.g., a 64-bit thermal code in the illustrated example) output from the PWM circuit 616 to the DAC 212. In this example, the DAC 212 converts the thermal code of Dout_thermal_code[63:0] to Vout_thermal_dac, which is output to the heater 228. FIG. 9 illustrates aspects of these signals. In either case, Dout_thermal_code[63:0] can have a selected k-bit position (Dout_thermal_code[k]) with the frequency of pwm_mode_clk, and Dout_thermal_code[k] (and, in some scenarios, Dout_thermal_code[k+1] or Dout_thermal_code[k-1]) can be dithered at a selected duty cycle. One cycle of pwm_mode_clk is, for example, between time t0 and time t1. Furthermore, three cycles of pwm_mode_clk are between time t0 and time t2 for illustrative purposes.

[0071] Dout_thermal_code[k] has a duty cycle DC0 between time t0 and time t2. For illustrative purposes, duty cycle DC0 is 50%. Between time t0 and time t2, bit positions k-1 (Dout_thermal_code[k-1]) through 0 (Dout_thermal_code[0]) are logic "1." Bit positions (k+1) through 63 (Dout_thermal_code

[63] ) are logic "0." Bit positions of Dout_thermal_code[63:0] having these values ​​between time t0 and time t2 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] with a duty cycle corresponding to duty cycle DC0, which causes the temperature at heater 228 to reach temperature Temp0, as described above with respect to FIG. 7 .

[0072] At time t2, the duty cycle of Dout_thermal_code[k] is increased to duty cycle DC1. Dout_thermal_code[k] has duty cycle DC1 between time t2 and time t4. For illustrative purposes, duty cycle DC0 is 70%. From time t2 to time t4, Dout_thermal_code[(k-1):0] is logic "1" and Dout_thermal_code[63:(k+1)] is logic "0". Bit positions of Dout_thermal_code[63:0] having these values ​​between time t2 and time t4 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] at a duty cycle corresponding to duty cycle DC1. Vout_thermal_dac between time t2 and time t4 raises the temperature in heater 228 to temperature Temp0+deltaTemp, as described above with respect to FIG. 7 . As shown, the temperature at heater 228 increases from temperature Temp0 to temperature Temp0+deltaTemp at time t3 following the increase in duty cycle at time t2. In some examples, the delay between the time the duty cycle of Dout_thermal_code[k] is increased (e.g., at time t2) and the time the temperature of heater 228 reaches temperature Temp0+deltaTemp (e.g., at time t3) is on the order of 6 μs. Furthermore, in some examples, a cycle of pwm_mode_clk may be on the order of tens of nanoseconds, and therefore, multiple cycles of oscillating Dout_thermal_code[k] may occur between the time the duty cycle is increased and the time the temperature at heater 228 reaches temperature Temp0+deltaTemp.

[0073] At time t4, the duty cycle of Dout_thermal_code[k] is reduced to duty cycle DC0. Dout_thermal_code[k] has duty cycle DC0 from time t4 onwards in FIG. 9 . From time t4 onwards, Dout_thermal_code[(k-1):0] is logic "1" and Dout_thermal_code[63:(k+1)] is logic "0". Bit positions of Dout_thermal_code[63:0] having these values ​​following time t4 cause Vout_thermal_dac to oscillate between voltage v[k] and voltage v[k+1] with a duty cycle corresponding to duty cycle DC0. Vout_thermal_dac from time t4 onwards reduces the temperature of heater 228 to temperature Temp0. As shown, the temperature at heater 228 decreases from temperature Temp0+deltaTemp to temperature Temp0 at time t5 following the reduction in duty cycle at time t4.

[0074] The temperature in the heater 228 can be controlled by selecting which k-bit position in Dout_thermal_code[63:0] should be toggled and by selecting the duty cycle for dithering Dout_thermal_code[k]. Selecting the value of k determines the voltage level at which Vout_thermal_dac toggles. In the illustrated example, Vout_thermal_dac can be one of 65 possible voltages (v[0], v[1],..v

[64] ) because Dout_thermal_code[63:0] is a 64-bit code. The available voltages increase sequentially such that v[0] < v[1] < v[2] <... < v

[64] . Thus, selecting a larger value of k can result in voltages v[k], v[k+1] which are at a higher level, and conversely, selecting a smaller value of k can result in voltages v[k], v[k+1] which are at a lower level. Selecting these voltage levels can determine the possible range of temperatures (e.g., from temperature Temp[k] to temperature Temp[k+1]) that can be achieved in the heater 228.

[0075] Selecting the duty cycle for dithering Dout_thermal_code[k] can achieve the temperature in the heater 228 within the range from temperature Temp[k] to temperature Temp[k+1]. The duty cycle can achieve interpolation of the temperature in the heater 228 within the range from temperature Temp[k] to temperature Temp[k+1] due to the accumulation (e.g., integration) of the thermal energy converted by the heater 228. A lower duty cycle can bring the temperature in the heater 228 closer to temperature Temp[k], and a higher duty cycle can bring the temperature in the heater 228 closer to temperature Temp[k+1].

[0076] The example in FIG. 9 shows Dout_thermal_code[63:0] where k is not 0 and not 63 (e.g., some bit positions are each logic "1" and other bit positions are each logic "0"), but k can be 0 and 63. Furthermore, the duty cycle of Dout_thermal_code[k] can be 0% and 100%. In some examples, when k is 0 and the duty cycle is 0%, Dout_thermal_code[63:0] is at its saturated minimum value, and in some examples, when k is 63 and the duty cycle is 100%, Dout_thermal_code[63:0] is at its saturated maximum value.

[0077] Furthermore, as shown by some example scenarios below, dithering between different duty cycles can cause multiple bit positions of Dout_thermal_code[63:0] to oscillate with the duty cycle. For example, if the dithering step increment is a 20% duty cycle and the duty cycle of the kth bit position is 90%, the duty cycle can be dithered between Dout_thermal_code[k] oscillating with a 90% duty cycle (where Dout_thermal_code[(k-1):0] is logic "1" and Dout_thermal_code[63:(k+1)] is logic "0") and Dout_thermal_code[k+1] oscillating with a 10% duty cycle (where Dout_thermal_code[k:0] is logic "1" and Dout_thermal_code[63:(k+2)] is logic "0").

[0078] 6, the tracking circuit 612 is configured to track tia_in and output a duty code (duty_code) and a k-level select signal (k_sel) to the PWM circuit 616 accordingly to control the heater 228 (e.g., for temperature setting tracking). The tracking circuit 612 is configured to receive a programmable PWM resolution value (prog_pwm_res) and a programmable PWM step value (prog_pwm_step). prog_pwm_res is a value indicating the frequency at which one or more bit positions of Dout_thermal_code[63:0] oscillate (e.g., the frequency of pwm_mode_clk, discussed above). prog_pwm_step is a value indicating the step size by which duty_code is increased. prog_pwm_res and prog_pwm_step can both be used to explicitly or implicitly determine available values ​​for duty_code. As will be described in more detail below, k_sel indicates which k-bit position of Dout_thermal_code[63:0] is oscillated at the duty cycle indicated by duty_code when sampling_clk is logically low.

[0079] In some examples, prog_pwm_res is a value indicating the number of cycles of dsp_clk per cycle of pwm_mode_clk, and prog_pwm_step indicates the number of cycles of dsp_clk per increment or decrement of duty_code. In one example, dsp_clk has a frequency of 875 MHz, prog_pwm_res indicates 16 or 64 cycles of dsp_clk per cycle of pwm_mode_clk, and prog_pwm_step indicates 1, 2, 4, or 8 cycles of dsp_clk per increment or decrement of duty_code. Table 3 details this example, along with the available values ​​of the resulting duty_code.

[0080] [Table 3]

[0081] The tracking circuit 612 is configured to capture a predetermined number of samples of tia_in at each falling edge of sampling_clk and to increase or decrease k_sel and / or duty_code during temperature setpoint tracking based on the captured samples. In the first iteration for temperature setpoint tracking, k_sel and duty_code can be initialized to several values. During temperature setpoint tracking, the tracking circuit 612 captures a predetermined number n of samples of tia_in. The tracking circuit 612 determines whether the number of logic "1"s is equal to or greater than half of the predetermined number n. If so, the tracking circuit 612 increases duty_code to the next available value unless duty_code is at the highest available value. When duty_code is at the highest available value, the tracking circuit 612 increases k_sel by 1 (unless k_sel is at the highest available value) and resets duty_code to the minimum available value. If k_sel and duty_code are at their highest available values, the output signal from the PWM circuit 616 will saturate and the values ​​of k_sel and duty_code will be maintained. In such a scenario, an error flag may be set.

[0082] The following pseudocode shows how k_sel and duty_code can be incremented based on the example in Table 3 above. This pseudocode mathematically and implicitly determines the next available duty_code, increments k_sel by concatenating k_sel and duty_code, and resets duty_code under appropriate circumstances.

[0083] temp_incr=(k_sel x 2 6 )+duty_code+2 [(2xprog_pwm_res)+prog_pwm_step] / / Concatenate k_sel and duty_code. Add the incremental step size. if(temp_incr<4096){k_sel=temp_incr[11:6];duty_code=temp_incr[5:0]} / / If k_sel and duty_code are not saturated and can be increased, extract the incremented k_sel and duty_code from temp_incr.

[0084] If the number of captured logic "1"s is not equal to or greater than half the predetermined n number, the tracking circuit 612 decreases duty_code to the next available value, unless duty_code is the lowest available value. When duty_code is at its minimum available value, the tracking circuit 612 decreases k_sel by 1 (unless k_sel is at its minimum available value) and resets duty_code to its maximum available value. When k_sel and duty_code are at their minimum available values, the output signal from the PWM circuit 616 saturates, and the values ​​of k_sel and duty_code are maintained. In such a scenario, an error flag may be set.

[0085] The following pseudocode shows how k_sel and duty_code can be decremented based on the example in Table 3 above. This pseudocode mathematically and implicitly determines the next available duty_code, decrements k_sel by concatenating k_sel and duty_code, and resets duty_code under appropriate circumstances.

[0086] temp_incr=(k_sel x 2 6 )+duty_code-2 [(2xprog_pwm_res)+prog_pwm_step] / / Concatenate k_sel and duty_code. Subtract the incremental step size. if(temp_incr>-1){k_sel=temp_incr[11:6]; duty_code=temp_incr[5:0]} / / If k_sel and duty_code are not saturated and can be decreased, extract incremented k_sel and duty_code from temp_incr.

[0087] If either k_sel and / or duty_code are changed (e.g., increased, decreased, or reset) by the tracking circuit 612, the tracking circuit 612 resets tia_dc_track_done to logic "0" and resets tia_dac_code and tia_ictrl to 0. After maintaining the values ​​of k_sel and duty_code or resetting tia_dc_track_done, tia_dac_code, and tia_ictrl, temperature set point tracking is complete and the tracking circuit 612 loops back to DC set point tracking.

[0088] The tracking circuit 612 may implement any logic, state machine (e.g., a finite state machine), and / or other circuitry that can further execute machine-executable instructions to implement DC setting tracking and temperature setting tracking.

[0089] 6, Figure 10 is a schematic diagram of a PWM circuit 616 according to some examples. The PWM circuit 616 is configured to receive dsp_clk, track_clk, prog_pwm_res, a programmable duty cycle dithering step value (prog_pwm_dither_step), sampling_clk, k_sel, and duty_code, and is configured to generate and output Dout_thermal_code[63:0]. The PWM circuit 616 is configured to generate a dithering k level selection value (k_sel_dither) and a dithering duty code value (duty_code_dither) based on k_sel, duty_code, and prog_pwm_dither_step, and is configured to generate and output Dout_thermal_code[63:0] based on k_sel and duty_code when sampling_clk is logically low, and based on k_sel_dither and duty_code_dither when sampling_clk is logically high.

[0090] The PWM circuit 616 generally includes an arithmetic / logic unit (ALU) 1002 configured to generate k_sel_dither and duty_code_dither by adding a duty cycle step size indicated by prog_pwm_dither_step to k_sel and duty_code. The ALU 1002 of the PWM circuit 616 concatenates k_sel and duty_code, where duty_code is in the least significant bit position and k_sel is in the next most significant bit position, and adds the duty cycle step size indicated by prog_pwm_dither_step to the concatenated k_sel and duty_code. After the addition, if the next most significant bit position after the number of bit positions of the concatenated k_sel and duty_code is "1," the remaining less significant bit positions of the result may be cleared. After addition, if the next most significant bit position after the number of bit positions of k_sel and duty_code concatenated is "0", then that bit position and the remaining less significant bit positions of the result corresponding to its placement in k_sel (from the concatenation) are k_sel_dither, and the least significant bit position corresponding to its placement in duty_code (from the concatenation) is duty_code_dither. Additionally, ALU 1002 may include logic to perform a check operation on prog_pwm_dither_step based on prog_pwm_res. As will become apparent, the available duty cycle, and therefore the available duty_code_dither, may be limited based on the mode indicated by prog_pwm_res. In the example of Table 3, if prog_pwm_res is "0", no check is made on prog_pwm_dither_step, but if prog_pwm_dither_step is not a multiple of 4 and prog_pwm_res is "1", a check is made to round prog_pwm_dither_step to the next multiple of 4. The following pseudocode shows an example of this operation of ALU 1002 using various values ​​with a given bit length:

[0091] (prog_pwm_res==1){prog_pwm_dither_step=integer (prog_pwm_dither_step / 4)×4} / / When prog_pwm_dither_step is not a multiple of 4 in the mode indicated by prog_pwm_res=1, round prog_pwm_dither_step to the nearest multiple of 4.

[0092] temp_concat=(k_sel x 2 6 +duty_code / / temp_concat is 13 bits ([12:0]), k_sel and duty_code are each 6 bits ([5:0]), and k_sel and duty_code are concatenated with "0" in temp_concat

[12] .

[0093] temp_accum_dither=temp_concat+prog_pwm_dither_step if(temp_accum_dither

[12] == 1){temp_accum_dither=4096} / / If temp_accum_dither>=4096, set temp_accum_dither=4096(temp_accum_dither

[12] =1 and temp_accum_dither[11:0]= 0) k_sel_dither=temp_accum_dither[12:6] / / Extract k_sel_dither from temp_accum_dither duty_code_dither=temp_accum_dither[5:0] / / Extract duty_code_dither from temp_accum_dither Table 4 below shows some example values ​​produced by the pseudocode above.

[0094] [Table 4]

[0095] The PWM circuit 616 includes a state machine and / or counter 1004 configured to generate and output intermediate signals (PWM_int[m]) having different duty cycles, where PWM_int[m] is based on dsp_clk and prog_pwm_res. For example, for a given m, PWM_int[m] can be generated by asserting a logic "1" as PWM_int[m] for some cycles of dsp_clk based on the m position and prog_pwm_res, and then asserting a logic "0" as PWM_int[m] for the remaining cycles of dsp_clk based on prog_pwm_res. Figures 11A and 11B are timing diagrams of various PWM_int[m] based on different prog_pwm_res, according to some examples.

[0096] FIG. 11A shows the signals when prog_pwm_res=0 as shown in Table 3 (e.g., indicating a pwm_mode_clk frequency of 13.67 MHz or 64 cycles of dsp_clk per cycle of pwm_mode_clk). In FIG. 10, pwm_mode_clk is not explicitly generated but is shown in FIG. 11A for reference. FIG. 11A shows span 1102, which is 64 cycles of dsp_clk, corresponding to each PWM_int[m] and one cycle of pwm_mode_clk in this mode. In this mode, the state machine and / or counter 1004 sets PWM_int[m] to logic "1" at the beginning of each individual PWM_int[m] cycle. The state machine and / or counter 1004 maintains PWM_int[m] at logic "1" for m cycles of dsp_clk (e.g., by counting the number of rising edges of dsp_clk). On the (m+1) cycle of dsp_clk, the state machine and / or counter 1004 sets PWM_int[m] to logic "0" and maintains PWM_int[m] at that value through the remaining number of cycles of dsp_clk in the cycle of PWM_int[m]. By way of example, PWM_int[0] is logic "1" for no cycles of dsp_clk and logic "0" for every cycle of dsp_clk. PWM_int[1] is logic "1" for one initial cycle of dsp_clk within the cycle of PWM_int[1] and logic "0" for 63 subsequent cycles of dsp_clk within the cycle of PWM_int[1]. PWM_int[2] is logic '1' for the two initial cycles of dsp_clk within the cycle of PWM_int[2] and logic '0' for the 62 subsequent cycles of dsp_clk within the cycle of PWM_int[2]. PWM_int

[63] is logic '1' for the first 63 cycles of dsp_clk within the cycle of PWM_int

[63] and logic '0' for the last cycle of dsp_clk within the cycle of PWM_int

[63] .

[0097] FIG. 11B shows the signals when prog_pwm_res=1 as shown in Table 3 (e.g., indicating a pwm_mode_clk frequency of 54.69 MHz or 16 cycles of dsp_clk per cycle of pwm_mode_clk). As in FIG. 11A, pwm_mode_clk is shown in FIG. 11B as a reference. FIG. 11B also shows span 1104, which is 16 cycles of dsp_clk, corresponding to one cycle of each PWM_int[m] and pwm_mode_clk in this mode. In this mode, the state machine and / or counter 1004 sets PWM_int[m] to logic "1" at the beginning of each cycle of a respective PWM_int[m]. The state machine and / or counter 1004 maintains PWM_int[m] as logic "1" (e.g., by counting the number of rising edges of dsp_clk) for (m / 4) cycles of dsp_clk. At ((m / 4)+1) cycle of dsp_clk, the state machine and / or counter 1004 sets PWM_int[m] to logic "0" and maintains PWM_int[m] at that value through the remaining number of cycles of dsp_clk in the cycle of PWM_int[m]. As an example, PWM_int[0] is logic "1" when there are no cycles of dsp_clk and is logic "0" for every cycle of dsp_clk. PWM_int[4] is logic "1" for one initial cycle of dsp_clk in the cycle of PWM_int[4] and logic "0" for 15 subsequent cycles of dsp_clk in the cycle of PWM_int[4]. PWM_int[8] is logic "1" for two initial cycles of dsp_clk in the cycle of PWM_int[8] and logic "0" for 14 subsequent cycles of dsp_clk in the cycle of PWM_int[8]. PWM_int

[60] is logic "1" for the first 15 cycles of dsp_clk in the cycle of PWM_int

[60] and logic "0" for the last cycle of dsp_clk in the cycle of PWM_int

[60] . In this mode, the state machine and / or counter 1004 can disable any PWM_int[m], where m is not a multiple of 4.

[0098] 11A and 11B, the duty cycle of PWM_int[m] increases with increasing values ​​of m. Also, the duty cycle can be distributed differently among the different modes shown in FIG. 11A and 11B. For example, taking PWM_int[4] as an example, in FIG. 11A, PWM_int[4] is logic "1" for the first four cycles of dsp_clk in span 1102 and logic "0" for the remaining 60 cycles of dsp_clk in span 1102, whereas in FIG. 11B, PWM_int[4] is logic "1" for four instances of one cycle of dsp_clk distributed throughout span 1102 and logic "0" for the remaining 60 cycles of dsp_clk in span 1102.

[0099] 10 , the PWM circuit 616 further includes multiplexers 1010, 1020, 1030, and 1032 and flip-flops 1012, 1014, 1022, 1024, and 1034. The multiplexer 1010 has a “0” select input node communicatively coupled to the ALU 1012 and configured to receive duty_code, and a “1” select input node communicatively coupled to the ALU 1002 and configured to receive duty_code_dither. The multiplexer 1010 has a select control input node configured to receive sampling_clk. The multiplexer 1010 has an output node communicatively coupled to an input node of the flip-flop 1012. The flip-flop 1012 has an output node communicatively coupled to an input node of the flip-flop 1014. Flip-flop 1014 has an output node communicatively coupled to the select control input node of multiplexer 1030. Flip-flop 1012 has a clock input node configured to receive track_clk, and flip-flop 1014 has a clock input node configured to receive dsp_clk. As will be apparent, each of the input and output nodes of multiplexer 1010 and flip-flops 1012, 1014 may be multi-bit nodes. Thus, although flip-flop 1012 or flip-flop 1014 is shown schematically as a single, multiple single-bit flip-flops, each corresponding to a separate bit position, may be implemented for the illustrated flip-flop.

[0100] The multiplexer 1020 is communicatively coupled to the ALU 1002 and has a "0" select input node configured to receive k_sel and a "1" select input node communicatively coupled to the ALU 1002 and configured to receive k_sel_dither. The multiplexer 1020 has a select control input node configured to receive sampling_clk. The multiplexer 1020 has an output node communicatively coupled to an input node of a flip-flop 1022. The flip-flop 1022 has an output node communicatively coupled to an input node of a flip-flop 1024. The flip-flop 1024 has an output node communicatively coupled to a select control input node of the multiplexer 1032. The flip-flop 1022 has a clock input node configured to receive track_clk, and the flip-flop 1024 has a clock input node configured to receive dsp_clk. As will be apparent, each input and output node of multiplexer 1020 and flip-flops 1022, 1024 may be a multi-bit node. Thus, although flip-flop 1022 or flip-flop 1024 is shown schematically as a single, multiple single-bit flip-flops, each corresponding to a separate bit position, may be implemented for the flip-flop shown.

[0101] Multiplexer 1030, in the illustrated example, is communicatively coupled to ALU 1002 and has 64 "m" select input nodes configured to receive respective PWM_int[m] signals, where m is from 0 to 63. Multiplexer 1030 has an output node configured to output a PWM duty code signal (pwm_duty_code).

[0102] In the illustrated example, multiplexer 1032 has 65 "q" select input nodes, where q ranges from 0 to 64. Each of the 65 "q" select input nodes is a 64-bit input node configured to receive a respective thermal code (therm[q]). For each therm[q], the pwm_duty_code output from multiplexer 1030 is mapped to the q-bit position of the respective therm[q], with each bit position of the respective therm[q] less than q set to logic "1" and each bit position of the respective therm[q] greater than q set to logic "0." In general, for each therm[q], a 64-bit thermal code is generated, with the q-bit position oscillating at the pwm_duty_code. Each bit position of therm

[64] is set to logic "1" (e.g., each bit position of therm

[64] less than q=64). Therm

[64] can be in a saturation condition. The multiplexer 1032 has an output node communicatively coupled to an input node of a flip-flop 1034. The flip-flop 1034 has an output node that is the output node of the PWM circuit 616 to which Dout_thermal_code[63:0] is supplied. The flip-flop 1034 has a clock input node configured to receive dsp_clk. As will be apparent, each input and output node of the multiplexer 1032 and the flip-flop 1034 is a 64-bit node in the illustrated example. Thus, although the flip-flop 1034 is shown schematically as a single, 64 single-bit flip-flops, each corresponding to a respective bit position, can be implemented for the illustrated flip-flop 1034.

[0103] In describing the further operation of Figure 10, the operation of flip-flops 1012, 1014, 1022, 1024, and 1034 has been omitted. These flip-flops typically synchronize signals to a separate clock, such as track_clk or dsp_clk. Such operation would be readily apparent to one skilled in the art and is therefore omitted for the sake of brevity.

[0104] In operation, ALU 1002 generates and outputs k_sel_dither and duty_code_dither as described above, and state machine and / or counter 1004 generates and outputs PWM_int[m] as described above, where m is from 0 to 63. When sampling_clk is logic low (e.g., corresponding to a "0" selection for multiplexers 1010, 1020), multiplexer 1010 outputs duty_code to the select control input node of multiplexer 1030, causing multiplexer 1030 to output PWM_int[duty_code] as pwm_duty_code. Thus, multiplexer 1030 outputs a signal having the desired duty cycle. Furthermore, when sampling_clk is logic low, multiplexer 1020 outputs k_sel to the select control input node of multiplexer 1032, causing multiplexer 1032 to output therm[k_sel] as Dout_thermal_code[63:0]. Thus, multiplexer 1032 outputs a thermal code having a signal with a desired duty cycle at a desired bit position.

[0105] When sampling_clk is logically high (e.g., corresponding to a "1" selection for multiplexers 1010, 1020), multiplexer 1010 outputs duty_code_dither to the select control input node of multiplexer 1030, which causes multiplexer 1030 to output PWM_int[duty_code_dither] as pwm_duty_code. Thus, multiplexer 1030 outputs a signal having the desired duty cycle. Furthermore, when sampling_clk is logically high, multiplexer 1020 outputs k_sel_dither to the select control input node of multiplexer 1032, which causes multiplexer 1032 to output therm[k_sel_dither] as Dout_thermal_code[63:0]. Thus, multiplexer 1032 outputs a heat code with a signal having a desired duty cycle at the desired bit position, which may differ from the heat code output when sampling_clk was logically low.

[0106] In general, when sampling_clk is logic low: Dout_thermal_code[63:0]=therm[k_sel]= {(63-k_sel)'d0,pwm_duty_code=PWM_int[duty_code],(k_sel)'b1} When sampling_clk is logic high: Dout_thermal_code[63:0]=therm[k_sel_dither]= {(63-k_sel_dither)'d0,pwm_duty_code=PWM_int[duty_code_dither],(k_sel_dither)'b1} 12A and 12B are flowcharts illustrating the operation 1200A, 1200B of the tracking circuit 612 of the DSP 406, according to some examples. The overall operation of the DSP 406 will now be described using the flowcharts of FIGS. 12A and 12B. Generally, FIG. 12A illustrates DC setting tracking, and FIG. 12B illustrates temperature setting tracking.

[0107] First, the user programs the values ​​of the various programmable values. The user can write values ​​to memory, registers, etc. accessible to the DSP 406 for the programmable values. The user writes values ​​for prog_pwm_res, prog_pwm_step, prog_pwm_dither_step, prog_sampling_freq, prog_sampling_offset, prog_tia_dc_ratio, prog_tia_dc_vote, and tia_dc_track_en.

[0108] Additionally, the clock divider circuit 602 generates track_clk from dsp_clk as described above. The clock generation circuit 604 generates sampling_clk and slicer_clk_peaklock based on prog_sampling_freq, prog_sampling_offset, and track_clk as described above. The max / min calculation circuit 608 calculates MAX1 and MIN1 based on prog_tia_dc_ratio, prog_sampling_freq, and prog_sampling_offset as described above.

[0109] 12A , in block 1202, tia_dac_code, tia_ictrl, k_sel, tia_dc_track_done, a majority vote counter (count_majority_vote), and a round track counter (round_dc_track) are set to 0, and duty_code is set to the middle value of the range of available values ​​for duty_code. By setting tia_dac_code and tia_ictrl to 0, the current generated by the controllable current source 416 is reduced to a minimum amount and / or turned off, which results in a current I in and / or reduce the removal of DC components from the current I in10 , pwm_duty_code=PWM_int[duty_code]}} as Dout_thermal_code[63:0]. Furthermore, ALU 1002 generates k_sel_dither and duty_code_dither based on k_sel and duty_code set in block 1202 and prog_pwm_dither_step. The multiplexer 1032 of the PWM circuit 616 outputs therm[k_sel_dither]={(63-k_sel_dither)'d0, pwm_duty_code=PWM_int[duty_code_dither], (k_sel_dither)'b1} as Dout_thermal_code[63:0] when sampling_clk is high. Thus, Dout_thermal_code[63:0] is set to dither between different duty codes based on sampling_clk, which dithers in response to Vout_thermal_dac and the temperature at the heater 228.

[0110] At block 1204, a determination is made as to whether tia_dc_track_done is equal to 0. If tia_dc_track_done is not equal to 0, operation proceeds to temperature setpoint tracking, as described below in FIG. 12B. If tia_dc_track_done is equal to 0, at block 1206, samples of tia_in are captured at each rising edge of track_clk for one cycle of sampling_clk, and the number of logic "1"s is counted. As described above, during one cycle of sampling_clk, the duty cycle of Dout_thermal_code[63:0] dithers, thereby dithering the temperature at the heater 228. Capturing samples of tia_in over one cycle of sampling_clk can result in samples being captured that are in response to different optical responses of the optical element 222 due to different temperatures of the heater 228.

[0111] At block 1208, a determination is made as to whether the number of captured logic "1's" is greater than or equal to MIN1 and less than or equal to MAX1. Generally, the determination at block 1208 indicates whether the number of captured logic "1's" is within the error range indicated by prog_tia_dc_ratio. If the number of captured logic "1's" is within MIN1 and MAX1, then at block 1210, count_majority_vote is incremented by 1. Following block 1210, or if the number of captured logic "1's" is not within MIN1 and MAX1, then at block 1212, a determination is made as to whether count_majority_vote is equal to prog_tia_dc_vote. If count_majority_vote is equal to prog_tia_dc_vote, then at block 1214, tia_dc_track_done is set to 1, and count_majority_vote and round_dc_track are set to 0. Following block 1214 , operation loops back to block 1204 .

[0112] If count_majority_vote is not equal to prog_tia_dc_vote, then at block 1216, a determination is made whether round_dc_track is equal to a predetermined number x. The predetermined number x may be a programmable value or may be coded into the algorithm. If round_dc_track is not equal to the predetermined number x, then at block 1218, round_dc_track is incremented by 1. Following block 1218, operation loops back to block 1204.

[0113] If round_dc_track is equal to the predetermined number x, tia_dac_code and / or tia_ictrl are incremented in block 1220. Incrementing tia_dac_code and / or tia_ictrl increases the current I through the controllable current source 416. DC tia_dac_code and tia_ictrl. An increment of one of tia_dac_code and tia_ictrl can be accompanied by a decrease of the other in some circumstances. The manner in which tia_dac_code and tia_ictrl are changed can be based on considerations such as the structure of the controllable current source 416 and the target step increase for each iteration of block 1220. For example, tia_dac_code can be increased independently in several subsequent iterations of block 1220 without increasing tia_ictrl until tia_dac_code is saturated in another iteration of block 1220, in which tia_dac_code is set to a reduced value and tia_ictrl is increased. Even with a reduced tia_dac_code (and corresponding reduced v_tia_dac), increasing tia_ictrl causes another series-connected pair of n-type transistors 802, 804 to increase the cumulative current (and therefore current I DC) is incremented. Following block 1220, at block 1222, count_majority_vote and round_dc_track are set to 0 and operation loops back to block 1204.

[0114] Generally, the loop of operations by blocks 1204-1222 forms DC setting tracking. round_dc_track counts the number of times a sample is captured in block 1206 before round_dc_track equals x and tia_dac_code and / or tia_ictrl are incremented. count_majority_vote counts the number of times a sample captured in block 1206 falls within the error range indicated by MAX1 and MIN1 while round_dc_track is less than x. When count_majority_vote equals prog_tia_dc_vote, tia_dac_code and tia_ictrl are sufficient such that the captured sample falls within the error range indicated by MAX1 and MIN1 with some degree of confidence. count_majority_vote equaling prog_tia_dc_vote terminates DC setting tracking and causes tia_dc_track_done to be set to 1.

[0115] In general, if after x iterations (e.g., capturing samples for x cycles of sampling_clk) the number of iterations in which the captured samples were within the error range indicated by MIN1 and MAX1 is less than prog_tia_dc_vote, then the current I DCis incremented and subsequent iterations for DC set point tracking continue by resetting count_majority_vote and round_dc_track. If the number of iterations in which the captured samples were within the error range indicated by MIN1 and MAX1 equals prog_tia_dc_vote before x iterations are completed, DC set point tracking is terminated by setting tia_dc_track_done to 1 (causing block 1204 to proceed to temperature set point tracking) and the current I is increased for temperature set point tracking. DC The count_majority_vote and round_dc_tracking are reset for subsequent iterations of DC set point tracking following temperature set point tracking.

[0116] Referring back to operation 1200A of FIG. 12A , if the determination in block 1204 is that tia_dc_track_done is not equal to 0 (e.g., DC setting tracking has ended), then in block 1252, samples of tia_in are captured at each time of the cycles of sampling_clk for y cycles of sampling_clk, and the number of captured logic "1"s and logic "0"s are counted. In some examples, each sample is captured at a time during a discrete cycle before and near the rising edge of sampling_clk while sampling_clk is logically low. For example, each sample can be captured 10 cycles of dsp_clk before a discrete rising edge of sampling_clk. A dedicated signal with a rising or falling edge corresponding to this sample time can be implemented.

[0117] At block 1254, a determination is made whether the total number of counted logic "1"s and logic "0"s is equal to y. If not, an error occurs and temperature setpoint tracking is terminated such that operation loops back to block 1204 for DC setpoint tracking. If the total number of counted logic "1"s and logic "0"s is equal to y, then at block 1256, a determination is made whether the number of counted logic "1"s is greater than or equal to half of y. In general, block 1256 determines whether more logic "1"s or more logic "0"s have been counted.

[0118] If the counted number of logic "1"s is greater than or equal to half of the y times, then in block 1258, a determination is made as to whether k_sel and duty_code are at their respective maximum values. If k_sel and duty_code are both at their respective maximum values ​​(e.g., Dout_thermal_code[63:0] indicates a maximum duty code), then in block 1260, k_sel and duty_code are maintained at their respective values ​​and an error flag may be set. Following block 1260, thermal setpoint tracking is terminated such that operation loops back to block 1204 for DC setpoint tracking. If either or both of k_sel and duty_code are not at their respective maximum values, then in block 1262, k_sel and / or duty_code are incremented, as described above. Following block 1262, in block 1264, tia_dc_track_done, tia_dac_code, and tia_ictrl are set to 0, which ends temperature set point tracking and resets the variables for subsequent DC set point tracking. Following block 1264, operation loops back to block 1204 for DC set point tracking.

[0119] If the counted number of logic "1"s is not equal to or greater than half of the y times, then in block 1266 a determination is made as to whether k_sel and duty_code are at their respective minimum values. If k_sel and duty_code are both at their respective minimum values ​​(e.g., Dout_thermal_code[63:0] indicates that they are at their minimum duty code), then in block 1260, k_sel and duty_code are maintained at their respective values ​​and an error flag can be set. Following block 1260, thermal setpoint tracking is terminated such that operation loops back to block 1204 for DC setpoint tracking. If either or both of k_sel and duty_code are not at their respective minimum values, then in block 1268, k_sel and / or duty_code are decreased as described above. Following block 1268, at block 1270, tia_dc_track_done, tia_dac_code, and tia_ictrl are set to 0, which ends temperature set point tracking and resets the variables for subsequent DC set point tracking. Following block 1270, operation loops back to block 1204 for DC set point tracking.

[0120] Varying k_sel and duty_code causes the PWM circuit 616 to responsively change k_sel_dither and duty_code_dither. Changing k_sel, duty_code, k_sel_dither, and duty_code_dither causes Dout_thermal_code[63:0] to dither between different duty codes, which in turn causes Vout_thermal_dac to dither between different duty cycles and possibly different voltage levels. Changes to Vout_thermal_dac increase or decrease the temperature at the heater 228.

[0121] The DC setting is determined based on the samples captured in block 1206 over the dithering based on sampling_clk between a first temperature and a second temperature (resulting from the dithering duty cycle of Dout_thermal_code[63:0]). In the described example, when sampling_clk is logically high, a first temperature occurs at the optical element 222, and when sampling_clk is logically low, a second temperature higher than the first temperature occurs at the optical element 222. In general, the optical response of the optical element 222 at the first temperature and the second temperature can be as shown in FIG. 3A or 3B.

[0122] In the RHS scenario of FIG. 3A, the optical element 222 is at a second temperature and the center wavelength (λ c The sample captured when the optical element 222 is at a first temperature and has a second response 306 having a magnitude 316 at a center wavelength (λ c ) 302, which has a lower loss for samples captured when sampling_clk is logic low and near the end of the cycle when sampling_clk is low, which allows the optical element 222 to reach or nearly reach the second temperature. When samples are captured when the optical element 222 is at the second temperature, compared to the DC setting, the lower loss of response 306 in magnitude 316 results in more captured samples being logic "1." Thus, the counted number of logic "1"s being more than half of the total number of samples indicates that the optical element 222 is near the center wavelength (λ) of the optical signal, as in FIG. 3A . c ) 302 is on the RHS of the optical response. The temperature settings (e.g., k_sel and / or duty_code) generally align the peak of the optical response of the optical element 222 with the center wavelength (λ c ) 302.

[0123] In the LHS scenario of FIG. 3B, the optical element 222 is at a second temperature and the center wavelength (λ c The sample captured when the optical element 222 is at a first temperature and has a second response 326 having a magnitude 336 at a center wavelength (λ c 3B , the counted number of logic "1"s is not more than half of the total number of samples. c ) 302 is on the LHS of the optical response. The temperature settings (e.g., k_sel and / or duty_code) generally align the peak of the optical response of the optical element 222 with the center wavelength (λ c ) 302.

[0124] Those skilled in the art can readily understand modifications to this temperature setting tracking (e.g., modifications to the implemented logic). For example, in block 1252, if samples are captured when sampling_clk is high, k_sel and / or duty code can be decreased when the counted number of logic "1"s is y half or more, and k_sel and / or duty code can be increased when the counted number of logic "1"s is not y half or more.

[0125] As shown in Figures 12A and 12B, DC setting tracking and temperature setting tracking are performed iteratively, as shown in Figure 5. Before performing each DC setting tracking iteration, tia_dac_code and tia_ictrl are set or reset such that tia_dac_code and tia_ictrl are determined independently of any previous values ​​of tia_dac_code and tia_ictrl. Furthermore, each iteration of temperature setting tracking can be based on the values ​​of k_sel and duty_code generated by a previous iteration of temperature setting tracking. The iteration of DC setting tracking and temperature setting tracking allows the device to be continuously recalibrated, for example, if the ambient temperature of the environment in which the device is placed changes.

[0126] Figure 13 is a simplified schematic diagram of a device according to some examples. The device (which may be in a package such as in Figure 1) includes an electrical IC 1302 on the electrical IC die 102 and an optoelectronic circuit 1304 on the optical die 104. The electrical IC includes controllers 210-1, 210-2, 210-3, DACs 212-1, 212-2, 212-3, and a controller 1303. Each controller 210-1, 210-2, 210-3 and corresponding DACs 212-1, 212-2, 212-3 are configured and generally operate similarly to the controllers 210 and DACs 212 described above. The controller 1303 is communicatively coupled to the controllers 210-1, 210-2, 210-3 and configured to control operation between the controllers 210-1, 210-2, 210-3. Although not shown, electrical IC 1302 further includes circuitry for generating electrical signals that are transmitted as optical signals over optical channels.

[0127] The optoelectronic circuit 1304 includes a light source (not specifically shown), a common channel path 1310, an odd channel path 1312, an even channel path 1314, a Mach-Zehnder interferometer (MZI) wavelength splitter 1320, MZI filters 1322 and 1324, a photodiode 226, and heaters 228-1, 228-2, and 228-3. The heater 228-1 is disposed within the optical die 104 in proximity to the MZI wavelength splitter 1320. The heater 228-2 is disposed within the optical die 104 in proximity to the MZI filter 1322. The heater 228-3 is disposed within the optical die 104 in proximity to the MZI filter 1324.

[0128] Common channel path 1310 is configured to carry odd channel optical signal 1340 and even channel optical signal 1342. MZI wavelength splitter 1320 is configured to receive odd channel optical signal 1340 and even channel optical signal 1342 from common channel path 1310, split odd channel optical signal 1340 to odd channel path 1312, and split even channel optical signal 1342 to even channel path 1314. MZI filter 1322 is configured to receive odd channel optical signal 1340 from odd channel path 1312, suppress spurious even channel optical signals, and transmit odd channel optical signal 1340 on the optical channel. MZI filter 1324 is configured to receive even channel optical signal 1342 from even channel path 1314, suppress spurious odd channel optical signals, and transmit even channel optical signal 1342 on the optical channel.

[0129] The photodiode 226 is disposed within the optical die 104 such that a portion of the optical signal output from the MZI filters 1322, 1324 is incident on the photodiode 226. The photodiode 226 is configured to generate a current in response to the optical signal incident on the photodiode 226.

[0130] An output node 1330 of the photodiode 226 is electrically coupled to respective input nodes 420-1, 420-2, 420-3 of the DC-controllable transimpedance stages of the controllers 210-1, 210-2, 210-3. The heater 228-1 is electrically coupled to the DAC 212-1. The heater 228-2 is electrically coupled to the DAC 212-2, and the heater 228-3 is electrically coupled to the DAC 212-3.

[0131] In operation, the photodiode 226 generates a current in response to an optical signal from the MZI filters 1322, 1324 incident on the photodiode 226. The current generated by the photodiode 226 is divided among the controllers 210-1, 210-2, 210-3 at the input nodes 420-1, 420-2, 420-3 to generate individual input currents I in1 , I in2 , I in3 Each controller 210-1, 210-2, 210-3 receives an individual input current I in1 , I in2 , I in3 The controller 1303 controls the controllers 210-1, 210-2, and 210-3 to sequentially perform DC setting tracking and temperature setting tracking among the controllers 210-1, 210-2, and 210-3.

[0132] 14 is a flowchart of this sequential operation according to some examples. In block 1402, DC setting tracking is performed by controller 210-1, and in block 1404, temperature setting tracking is performed by controller 210-1. In block 1406, DC setting tracking is performed by controller 210-2, and in block 1408, temperature setting tracking is performed by controller 210-2. In block 1410, DC setting tracking is performed by controller 210-3, and in block 1412, temperature setting tracking is performed by controller 210-3. Controller 1303 can coordinate and control which controller starts its DC setting tracking based on which controller has finished its temperature setting tracking. Each DC setting tracking for each controller 210-1, 210-2, 210-3 can be individually as described above, and each temperature setting tracking for each controller 210-1, 210-2, 210-3 can be individually as described above.

[0133] 13 and 14 shows how a single photodiode can be implemented to control multiple, e.g., optical filters. This example shows that sequential operation of multiple controllers using the same photodiode can operate to control the temperature of multiple, e.g., optical filters, within an optical die.

[0134] Some non-limiting examples can be expressed as follows: Example 1. A device comprising: a first controller, a first DC-controllable transimpedance stage having an input node and an output node, the input node of the first DC-controllable transimpedance stage configured to be electrically coupled to the photodiode; a first slicer circuit having an input node and an output node, the input node of the first slicer circuit electrically coupled to the output node of the first DC-controllable transimpedance stage; a first controller comprising: a first processor having an input node electrically coupled to an output node of the first slicer circuit, the first processor configured to control the first DC-controllable transimpedance stage to reduce a DC component of a signal on the output node of the first DC-controllable transimpedance stage based on a signal on the output node of the first slicer circuit; a first digital-to-analog converter (DAC) having an input node electrically coupled to an output node of the first processor and having an output node configured to be electrically coupled to a heater, wherein the first processor is configured to control an output voltage on the output node of the first DAC based on a signal on the output node of the first slicer circuit;

[0135] Example 2. a photodiode electrically coupled to the input node of the first DC controllable transimpedance stage; an optical element configured to pass an optical signal and having a temperature dependent optical response, the optical element being positioned relative to the photodiode such that at least a portion of the optical signal is incident on the photodiode; 10. The device of claim 1, further comprising: a heater electrically coupled to an output node of the first DAC, the heater being positioned proximate to the optical element.

[0136] Example 3. The first DC controllable transimpedance stage comprises: a transimpedance amplifier electrically connected between an input node of the first DC-controllable transimpedance stage and an output node of the first DC-controllable transimpedance stage; 10. The device of example 1, comprising: a controllable current source electrically connected between the input node of the first DC controllable transimpedance stage and the power supply node.

[0137] Example 4. The device of example 1, wherein the first processor is configured to control the output voltage on the output node of the first DAC to dither between different duty cycles.

[0138] Example 5. A first processor: repeatedly, determining a DC setting for controlling the first DC-controllable transimpedance stage to reduce a DC component of a signal on an output node of the first DC-controllable transimpedance stage, the first processor being configured to control the first DC-controllable transimpedance stage to reduce the DC component of the signal on the output node of the first DC-controllable transimpedance stage using the DC setting; 10. The device of claim 1, further comprising: after determining the DC setting, determining a temperature setting for controlling an output voltage on an output node of the first DAC, wherein the first processor is configured to control the output voltage on the output node of the first DAC using the temperature setting.

[0139] Example 6. The first processor: a tracking circuit configured to capture a sample of the signal on the output node of the first slicer circuit, generate a current control setting for the first DC-controllable transimpedance stage based on the first sample captured from the signal on the output node of the first slicer circuit, and generate a duty code and a level select code based on a second sample captured from the signal on the output node of the first slicer circuit after the first sample is captured; and a pulse width modulation circuit configured to generate a dither duty code and a dither level selection code based on the duty code and the level selection code, and to generate a thermal code having a dither duty cycle that is output to an input node of the first DAC.

[0140] Example 7 a second controller, a second DC-controllable transimpedance stage having an input node and an output node, the input node of the second DC-controllable transimpedance stage being electrically connected to the input node of the first DC-controllable transimpedance stage and the input node of the second DC-controllable transimpedance stage being configured to be electrically coupled to the photodiode; a second slicer circuit having an input node and an output node, the input node of the second slicer circuit electrically coupled to the output node of the second DC-controllable transimpedance stage; a second controller comprising: a second processor having an input node electrically coupled to an output node of the second slicer circuit, the second processor configured to control the second DC-controllable transimpedance stage to reduce a DC component of a signal on the output node of the second DC-controllable transimpedance stage based on a signal on the output node of the second slicer circuit; 11. The device of claim 1, further comprising: a second DAC having an input node electrically coupled to the first output node of the second processor and having an output node configured to be electrically coupled to the second heater, wherein the second processor is configured to control an output voltage on the output node of the second DAC based on a signal on the output node of the second slicer circuit.

[0141] Example 8. A method for controlling the temperature of a device, comprising: generating, by the processor, a first DC setting to be output from the processor to a first DC-controllable transimpedance stage having an input node electrically coupled to a photodiode configured to receive an optical signal passed from a first optical element having a temperature-dependent optical response, the first DC-controllable transimpedance stage generating the first DC setting based on a signal on an output node of the first DC-controllable transimpedance stage; and generating, by the processor, after generating the first DC setting, a first temperature setting, wherein a first code output from the processor to a first digital-to-analog converter (DAC) having an output node electrically coupled to a first heater positioned proximate to the first optical element is based on the first temperature setting, and the processor generates the first temperature setting based on a signal on an output node of the first DC-controllable transimpedance stage.

[0142] Example 9. The method of example 8, wherein generating the first DC setting and generating the first temperature setting are performed iteratively.

[0143] Example 10. The method of example 8, further comprising dithering a duty cycle of a voltage on the output node of the first DAC based on the first temperature setting.

[0144] Example 11. Generating a first DC setting comprises: repeatedly until the vote counter is equal to a first predetermined amount; capturing a number of samples based on a signal on an output node of the first DC-controllable transimpedance stage; incrementing a vote counter when the captured samples of the individual iterations are within the error range; incrementing the round counter when the round counter is less than a second predetermined amount; If the round counter is greater than or equal to a second predetermined amount, adjusting a first DC setting; and resetting a vote counter and a round counter.

[0145] Example 12. Generating a first temperature setting comprises: capturing a number of samples based on a signal on an output node of the first DC-controllable transimpedance stage; adjusting the first temperature setting based on whether the captured sample has a majority of logic "1's."

[0146] Example 13. The first DC controllable transimpedance stage comprises: a transimpedance amplifier electrically connected between an input node of the first DC-controllable transimpedance stage and an output node of the first DC-controllable transimpedance stage; 9. The method of example 8, comprising: a controllable current source electrically connected between the input node of the first DC controllable transimpedance stage and the power supply node, wherein the first DC setting controls the current of the controllable current source.

[0147] Example 14. The method of example 8, wherein the first code is a thermal code having a dithering duty cycle.

[0148] Example 15. generating, after generating the first temperature setting, a second DC setting that is output to a second DC-controllable transimpedance stage having an input node electrically coupled to a photodiode further configured to receive an optical signal passed from a second optical element having a temperature-dependent optical response, the second DC setting being generated based on a signal on an output node of the second DC-controllable transimpedance stage; 9. The method of example 8, further comprising: after generating the second DC setting, generating a second temperature setting, wherein a second code output to a second DAC having an output node electrically coupled to a second heater positioned proximate to the second optical element is based on the second temperature setting, the second temperature setting being generated based on the signal on the output node of the second DC-controllable transimpedance stage.

[0149] Example 16. A device comprising: an optical element configured to pass an optical signal and having a temperature dependent optical response; a photodiode positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode; a heater disposed proximate to the optical element and configured to convert electrical energy into thermal energy; a transimpedance stage, an input node of the transimpedance stage electrically coupled to the photodiode, the transimpedance stage comprising a controllable current source electrically connected between the input node of the transimpedance stage and a power supply node; a slicer circuit, the input node of the slicer circuit being electrically coupled to the output node of the transimpedance stage; A device comprising: a processor, an input node of the processor electrically coupled to an output node of a slicer circuit, the processor configured to control a current of a controllable current source based on an output signal on the output node of the slicer circuit, and configured to control an amount of electrical energy provided to a heater based on the output signal on the output node of the slicer circuit.

[0150] Example 17. The device of Example 16, further comprising a digital-to-analog converter (DAC), wherein an input node of the DAC is electrically coupled to an output node of the processor, and an output node of the DAC is electrically coupled to the heater, and wherein the processor is configured to control an amount of electrical energy provided to the heater by controlling an output voltage on the output node of the DAC.

[0151] Example 18. The device of Example 17, wherein the processor is configured to output a thermal code having a dithering duty cycle on an output node of the processor electrically coupled to the input node of the DAC.

[0152] Example 19. A processor is configured to generate a first setting for controlling a current of a controllable current source, the processor being configured to iteratively generate the first setting until a vote counter is equal to a first predetermined amount; capturing several first samples of the output signal on the output node of the slicer circuit; incrementing a vote counter when the captured first sample of the respective iteration is within the error range; incrementing the round counter when the round counter is less than a second predetermined amount; If the round counter is equal to a second predetermined amount, adjusting a first setting; and resetting a vote counter and a round counter.

[0153] Example 20. A processor is configured to generate a heat code for controlling an amount of electrical energy provided to a heater, the heat code being output on an output node of the processor, the processor: capturing several second samples of the output signal on the output node of the slicer circuit; adjusting the selection setting based on whether the captured second sample has a majority of logic "1"s; 20. The device of example 19, configured to generate a thermal code by: generating a thermal code based on the selected settings.

[0154] While the above is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, the scope of which is determined by the examples that follow.

Claims

1. A device, a first controller, a first DC-controllable transimpedance stage having an input node and an output node, the input node of the first DC-controllable transimpedance stage configured to be electrically coupled to a photodiode; a first slicer circuit having an input node and an output node, the input node of the first slicer circuit electrically coupled to the output node of the first DC-controllable transimpedance stage; a first controller comprising: a first processor having an input node electrically coupled to the output node of the first slicer circuit, the first processor configured to control the first DC-controllable transimpedance stage to reduce a DC component of a signal on the output node of the first DC-controllable transimpedance stage based on a signal on the output node of the first slicer circuit; a first digital-to-analog converter (DAC) having an input node electrically coupled to an output node of the first processor and having an output node configured to be electrically coupled to a heater, the first processor being configured to control an output voltage on the output node of the first DAC based on a signal on the output node of the first slicer circuit; The device further comprises: the photodiode electrically coupled to the input node of the first DC-controllable transimpedance stage; an optical element configured to pass an optical signal and having a temperature dependent optical response, the optical element being positioned relative to the photodiode such that at least a portion of the optical signal is incident on the photodiode; the heater electrically coupled to the output node of the first DAC, the heater being positioned proximate to the optical element; A device comprising:

2. the first DC controllable transimpedance stage comprising: a transimpedance amplifier electrically connected between the input node of the first DC-controllable transimpedance stage and the output node of the first DC-controllable transimpedance stage; 10. The device of claim 1, further comprising: a controllable current source electrically connected between the input node of the first DC-controllable transimpedance stage and a power supply node.

3. 2. The device of claim 1, wherein the first processor is configured to control the output voltage on the output node of the first DAC to dither between different duty cycles.

4. The first processor: repeatedly, determining a DC setting for controlling the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage, the first processor being configured to control the first DC-controllable transimpedance stage to reduce the DC component of a signal on the output node of the first DC-controllable transimpedance stage using the DC setting; 2. The device of claim 1, configured to: determine, after determining the DC setting, a temperature setting for controlling the output voltage on the output node of the first DAC, wherein the first processor is configured to control the output voltage on the output node of the first DAC using the temperature setting.

5. The first processor: a tracking circuit configured to capture a sample of the signal on the output node of the first slicer circuit, generate a current control setting for the first DC-controllable transimpedance stage based on a first sample captured from the signal on the output node of the first slicer circuit, and generate a duty code and a level select code based on a second sample captured from the signal on the output node of the first slicer circuit after the first sample is captured; and a pulse width modulation circuit configured to generate a dither duty code and a dither level selection code based on the duty code and the level selection code, and to generate a thermal code having a dither duty cycle that is output to the input node of the first DAC.

6. a second controller, a second DC-controllable transimpedance stage having an input node and an output node, the input node of the second DC-controllable transimpedance stage being electrically connected to the input node of the first DC-controllable transimpedance stage and the input node of the second DC-controllable transimpedance stage being configured to be electrically coupled to the photodiode; a second slicer circuit having an input node and an output node, the input node of the second slicer circuit electrically coupled to the output node of the second DC-controllable transimpedance stage; a second controller comprising: a second processor having an input node electrically coupled to the output node of the second slicer circuit, the second processor configured to control the second DC-controllable transimpedance stage to reduce the DC component of the signal on the output node of the second DC-controllable transimpedance stage based on a signal on the output node of the second slicer circuit; a second DAC having an input node electrically coupled to the first output node of the second processor and having an output node configured to be electrically coupled to a second heater, the second processor being configured to control an output voltage on the output node of the second DAC based on a signal on the output node of the second slicer circuit; The device of claim 1 further comprising:

7. A device, an optical element configured to pass an optical signal and having a temperature dependent optical response; a photodiode positioned relative to the optical element such that at least a portion of the optical signal passing through the optical element is incident on the photodiode; a heater disposed proximate to the optical element and configured to convert electrical energy into thermal energy; a transimpedance stage, an input node of the transimpedance stage electrically coupled to the photodiode, the transimpedance stage comprising a controllable current source electrically connected between the input node of the transimpedance stage and a power supply node; a slicer circuit, an input node of the slicer circuit electrically coupled to an output node of the transimpedance stage; a processor, an input node of the processor electrically coupled to an output node of the slicer circuit, the processor configured to control a current of the controllable current source based on an output signal on the output node of the slicer circuit, and to control an amount of electrical energy provided to the heater based on the output signal on the output node of the slicer circuit.

8. 8. The device of claim 7, further comprising a digital-to-analog converter (DAC), an input node of the DAC electrically coupled to an output node of the processor, an output node of the DAC electrically coupled to the heater, and the processor configured to control an output voltage on the output node of the DAC to control an amount of electrical energy provided to the heater.

9. 10. The device of claim 8, wherein the processor is configured to output a thermal code having a dithering duty cycle on the output node of the processor electrically coupled to the input node of the DAC.

10. the processor is configured to generate a first setting for controlling a current of the controllable current source, the processor being configured to generate the first setting iteratively until a vote counter is equal to a first predetermined amount; capturing several first samples of the output signal on the output node of the slicer circuit; incrementing the vote counter when the captured first sample of an individual iteration is within an error range; incrementing the round counter when the round counter is less than a second predetermined amount; If the round counter is equal to the second predetermined amount, adjusting the first setting; and resetting the vote counter and the round counter.

11. the processor is configured to generate a heat code for controlling an amount of electrical energy provided to the heater, the heat code being output on an output node of the processor, the processor comprising: capturing several second samples of the output signal on the output node of the slicer circuit; adjusting a selection setting based on whether the captured second sample has a majority of logic "1"s; and generating the heat code based on the selected settings.

12. 1. A method for controlling the temperature of a device, comprising: generating, by a processor, a first DC setting to be output from the processor to a first DC-controllable transimpedance stage having an input node electrically coupled to a photodiode configured to receive an optical signal passed from a first optical element having a temperature-dependent optical response, the first DC-controllable transimpedance stage, the first DC-controllable transimpedance stage having an input node electrically coupled to a photodiode configured to receive an optical signal passed from a first optical element having a temperature-dependent optical response, the processor generating the first DC setting based on a signal on an output node of the first DC-controllable transimpedance stage; after generating the first DC setting, generating, by the processor, a first temperature setting, wherein a first code output from the processor to a first digital-to-analog converter (DAC) having an output node electrically coupled to a first heater positioned proximate to the first optical element is based on the first temperature setting, and the processor generates the first temperature setting based on a signal on the output node of the first DC-controllable transimpedance stage.

13. Generating the first DC setting comprises: repeatedly until the vote counter is equal to a first predetermined amount; capturing a number of samples based on the signal on the output node of the first DC-controllable transimpedance stage; incrementing the vote counter when the captured samples of an individual iteration are within an error range; incrementing the round counter when the round counter is less than a second predetermined amount; if the round counter is greater than or equal to the second predetermined amount, adjusting the first DC setting; and resetting the vote counter and the round counter.

14. After generating the first temperature setting, generating a second DC setting that is output to a second DC-controllable transimpedance stage having an input node electrically coupled to a photodiode further configured to receive an optical signal passed from a second optical element having a temperature-dependent optical response, the second DC setting being generated based on a signal on an output node of the second DC-controllable transimpedance stage; generating a second temperature setting after generating the second DC setting, wherein a second code output to a second DAC having an output node electrically coupled to a second heater positioned proximate to a second optical element is based on the second temperature setting generated based on the signal on the output node of the second DC-controllable transimpedance stage; The method of claim 12 further comprising:

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