Differentially Activated Latch for GaN-Based Level Shifters

Abstract

A cross-coupled differentially activated latch circuit with a circuit comprising multiple n-FETs and an inverter that can be implemented entirely in GaN. The circuit prevents a digital latched value on the output of the latch from changing unless the digital input value on the input is different, thus preventing common-mode voltages on the input from corrupting the stored latched value.

Description

[Background technology]

[0001] In the typical half-bridge IC design shown in Figure 1a, the on or off state of the high-side FET 2 is determined by the high-side input signal 4, which is typically referenced to ground. However, when the high-side FET 2 is turned on, the SW node 6, which is the lower supply voltage of the high-side path, is driven by the input voltage V in (see Figure 1B) and the floating supply voltage V ddF is almost V dd -V D +V in where V D is the diode voltage drop of diode 8. V in can range from a few volts to hundreds of volts, a level shifter is needed to level shift the high side input signal 4 from a ground referenced signal to a signal referenced to node 6 at the input of the high side driver.

[0002] FIG. 2 is a block diagram of a typical prior art level shifter. The level shifter includes two components: a level shift driver 10 and a latch 12. To change the logic value of latch 12, a pulse generator 14 in level shift driver 10 generates a pulse on the gate of either FET 16 or FET 18. The drain current (called a differential current) on either FET 16 or FET 18 then pulls down either input 20 or input 22 of latch 12 to generate a differential voltage change on latch input 20 or latch input 22. This differential voltage change causes the desired logic change at outputs 24 and 26 of latch 12. Importantly, for proper operation, a logic change at outputs 24 and 26 should only occur when latch input 20 differs from latch input 22, i.e., when there is a differential voltage change at the latch inputs. Latch outputs 24 and 26 should not change state if latch input 20 and latch input 22 are the same, i.e., both low or both high.

[0003] C20 and C 22 is the parasitic capacitance associated with latch input 20 and latch input 22. The latch is connected between 0V and V in Reference is made to SW node 6, which can have a fast swing between 20 and C 22 Due to the relatively large currents required to rapidly charge / discharge SW node 6, the voltage levels on latch inputs 20 and 22 referenced to SW node 6 may not be maintained when fast positive / negative slope (dv / dt) common-mode changes occur on SW node 6. Thus, rapid changes in voltage on SW node 6 may result in undesirable common-mode voltage changes (i.e., both high or both low) on latch inputs 20 and 22.

[0004] Figure 3 shows the circuit for a simple cross-coupled latch, where the voltage V ddF is the floating supply for SW6. Differential current on latch input 20 and latch input 22 draws current through resistor 30 or resistor 32, thereby generating the desired logic values ​​on latch output 24 and latch output 26. Undesired common-mode current (i.e., both high or both low) on latch input 20 and latch input 22 due to fast positive or negative dv / dt on SW node 6 turns both FET 42 and FET 44 on or off, thereby pulling both latch output 24 and latch output 26 down or up. As a result, the desired logic value stored in the latch may be corrupted.

[0005] 3, diode-connected FETs 34, 36, 38, and 40 are used to protect the gate voltages of main latch FETs 42 and 44 from large positive common-mode voltages. Diode-connected FETs 46 and 48 are used to protect the gate voltages of main latch FETs 42 and 44 from large negative common-mode voltages.

[0006] 4A and 4B show a simple prior art SR flip-flop circuit functioning as a latch. Diode-connected FETs are required at latch inputs 20 and 22 for protection. A pulse filter 50 is typically implemented using digital inverters / buffers, delay circuits, and / or Schmitt triggers to clean up the voltage pulses on latch inputs 20 and 22 and generate clean digital input pulses to the SR flip-flop. As with a cross-coupled latch, a common-mode current on latch inputs 20 and 22 due to a fast positive dv / dt on SW node 6 pulls down both latch inputs 20 and 22. As a result, the desired logic value stored in the latch can be corrupted. Note that with this circuit, the logic value stored in the latch is not corrupted by a fast negative dv / dt on SW node 6 because the output does not change state when both latch inputs 20 and 22 are high.

[0007] FIG. 5 shows an SR flip-flop latch with an analog differential front-end amplifier. Differential amplifier 52 is used to remove common-mode voltages and amplify the differential voltage on latch inputs 20 and 22 for setting the SR flip-flop, thereby avoiding the aforementioned problems of the circuit of FIG. 4 when subjected to fast positive dv / dt on SW node 6. However, differential amplifier 52 may require a wide input common-mode range (e.g., rail-to-rail or greater). Also, high-speed differential amplifiers incur high power dissipation. Finally, as with the cross-coupled latch of FIG. 3, diode-connected FETs are required at latch inputs 20 and 22 for protection.

[0008] Figure 6 shows a prior art circuit for common-mode current rejection using dynamic current sources. FETs 60, 62, 64, and 66 act as a cross-coupled differential load that converts the differential current at latch inputs 20 and 22 into a differential voltage. A common-mode pull-down current at latch inputs 20 and 22 due to a fast positive dv / dt on SW node 6 pulls down both inputs 20 and 22. The pull-down current also activates FETs 68 and 70 (dynamic current sources), which generate a common-mode pull-up current to offset the common-mode pull-down current. However, the circuit of Figure 6 cannot be realized in a GaN process because the required p-FETs are impossible to implement in GaN technology. Summary of the Invention [Problem to be solved by the invention]

[0009] It would therefore be desirable to provide a latch that overcomes the shortcomings of the prior art latches discussed above, i.e., a differentially activated latch circuit that can be implemented using a GaN process. [Means for solving the problem]

[0010] The present invention overcomes the above-mentioned disadvantages and achieves the object by providing a cross-coupled differentially activated latch circuit having first and second latch inputs for receiving first and second digital input values, first and second latch outputs, first and second n-FETs connected in a cross-coupled configuration, and circuitry comprising a plurality of n-FETs and an inverter for preventing the digitally latched values ​​on the first and second outputs from changing unless the digital input values ​​on the first and second inputs are different.

[0011] In a first preferred embodiment, the circuit of the present invention implements the following logic function:

[0012]

number

[0013] Implement.

[0014] In a second preferred embodiment, the circuit of the present invention implements the following logic function:

[0015]

number

[0016] Implement.

[0017] The circuit of the present invention, which can be implemented entirely in GaN, is advantageously designed so that when both logic inputs are the same, i.e., both low or both high, the latch outputs 24 and 26 do not change, thereby preventing common-mode voltages on the inputs from corrupting the stored latch value.

[0018] Although the present invention is designed to be implemented in GaN technology, the present invention can also be implemented in other technologies, such as CMOS, by implementing the above logic functions in such a way that fast positive or negative dv / dt on the SW node 6 in FIG. 1A does not corrupt the logic output of the latch.

[0019] Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1A] FIG. 1 illustrates a typical prior art half-bridge design. [Figure 1B] FIG. 10 is a diagram showing voltages at an SW node as a circuit switch. [Figure 2] FIG. 1 is a block diagram of a typical prior art level shifter. [Figure 3]FIG. 1 shows a circuit diagram of a simple prior art cross-coupled latch. [Figure 4A] FIG. 1 shows a simple prior art SR flip-flop circuit functioning as a latch. [Figure 4B] FIG. 1 shows a simple prior art SR flip-flop circuit functioning as a latch. [Figure 5] FIG. 1 illustrates an SR flip-flop latch with an analog differential front-end amplifier. [Figure 6] FIG. 1 illustrates a prior art circuit for common-mode current rejection using a dynamic current source. [Figure 7] FIG. 1 illustrates a first embodiment of a differentially activated cross-coupled latch of the present invention. [Figure 8] FIG. 2 illustrates a second embodiment of a differentially activated cross-coupled latch of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] 7 illustrates a first embodiment of the circuit of the present invention, a differentially activated cross-coupled latch that does not require p-FETs and can be implemented using a GaN process. The latch value is changed using only differential digital inputs on latch inputs 20 and 22. A common-mode voltage on latch inputs 20 and 22 is treated as a digital input with the same logic value. The circuit is advantageously designed using inverters 72 and 74 and associated circuitry so that latch outputs 24 and 26 do not change when both logic inputs are the same, i.e., both low or both high.

[0022] In particular, when both latch input 20 and latch input 22 are simultaneously at a logic low, n-FETs 76 and 80 are turned off, thereby preventing latch outputs 24 and 26 from pulling down and maintaining the output logic level. A logic high on both latch input 20 and latch input 22 turns on n-FET 76 and n-FET 80, and, via inverters 72 and 74, turns off n-FET 78 and n-FET 82, thereby preventing latch outputs 24 and 26 from pulling down and maintaining the output logic level. As a result, common-mode signals that appear as the same logic signal at the latch inputs due to fast positive and negative dv / dt at SW node 6 in FIG. 1A do not corrupt the latch output. V ddF A pull-down path for current to flow from V to SW6 (thereby pulling latch output 24 low and keeping latch output 26 high) is created only when latch input 20 is high and latch input 22 is low. Similarly, a pull-down path for current to flow from V through resistor 32 to V ddF A pull-down path for current to flow from SW1 to SW6 (thereby pulling latch output 26 low and keeping latch output 24 high) is created only when latch input 20 is low and latch input 22 is high. Thus, the latched value can be changed only using the differential digital input value on latch inputs 20 and 22.

[0023] The differentially activated latch of the first embodiment of the present invention performs the following two logic functions:

[0024]

number

[0025] The complex gate can be thought of as having two feedback-connected complex gates using

[0026] As explained above, the output logic value can be changed only by pulling down either latch output 24 or latch output 26. As in the prior art cross-coupled latch circuit of Figure 3, diode-connected n-FETs are required at inputs 20 and 22 for protection.

[0027] 8 shows a second embodiment of the differentially activated latch of the present invention. The output logic value is changed by turning off n-FET 42 or n-FET 44 and causing resistor 30 or resistor 32 to pull up latch output 24 or latch output 26.

[0028] 8, when both latch input 20 and latch input 22 are simultaneously at a logic low, n-FETs 76 and 80 are turned off, but both n-FETs 78 and 82 are turned on by inverters 74 and 72, respectively. As a result, n-FETs 42 and 44 are connected to SW6, and the logic outputs on 24 and 26 maintain the same output logic level.

[0029] When both latch input 20 and latch input 22 are simultaneously at a logic high, both n-FET 76 and n-FET 80 are turned on, but n-FETs 78 and 82 are turned off by inverters 72 and 74. However, n-FETs 42 and 44 are still connected to SW6, and the latch outputs on 24 and 26 maintain the same logic level. As a result, common-mode signals that appear as the same logic signal at the latch inputs due to fast positive and negative dv / dt at SW node 6 in FIG. 1A do not corrupt the latch output.

[0030] When latch input 20 is low and latch input 22 is high, n-FET 76 and n-FET 82 are both off, thereby disconnecting n-FET 42 from SW6 and resistor 30 pulling up latch output 24. At the same time, n-FET 80 is turned on by a logic high at latch input 22, and n-FET 78 is also turned on by inverter 74 with a logic low at latch input 20, so n-FET 44 is connected to SW6 and latch output 26 is pulled down by n-FET 44.

[0031] When latch input 20 is high and latch input 22 is low, n-FET 80 and n-FET 78 are both off, thereby disconnecting n-FET 44 from SW6 and resistor 32 pulling up latch output 26. At the same time, n-FET 76 is turned on by the logic high at latch input 20 and n-FET 82 is also turned on by inverter 72 with a logic low at latch input 22, so n-FET 42 is connected to SW6 and latch output 24 is pulled down by n-FET 42.

[0032] The differentially activated latch of this second embodiment of the present invention performs two logic functions:

[0033]

number

[0034] The complex gate can be thought of as having two feedback-connected complex gates using

[0035] As in the prior art cross-coupled latch circuit and the first embodiment of the present invention, diode-connected n-FETs for protection are required at the latch inputs 20 and 22. Other implementations are possible for realizing the logic functions in the first and second embodiments of the present invention.

[0036] In both embodiments of the present invention, an optional pulse filter can be added at the latch inputs 20 and 22 .

[0037] The differentially activated latch of the present invention has several advantages over the prior art latch circuits described above. For example, because the prior art approach of Figure 5 using an SR flip-flop with a differential front-end amplifier requires continuous biasing current to achieve high speed operation, the differentially controlled signal activated latch of the present invention dissipates less power than the prior art approach of Figure 5. Furthermore, small differentials on the common mode signals at latch inputs 20 and 22 can cause prior art circuits using differential amplifiers and SR flip-flops to not respond correctly to the common mode signal. The circuit of the present invention rejects these small differential signals when they are smaller than the noise margin of the logic gates.

[0038] Compared to the dynamic current source approach of Figure 6, the circuit of the present invention does not require a p-FET and can be easily realized in a GaN or NMOS-only process. The circuit of the present invention described above is preferably implemented entirely in GaN.

[0039] The circuit of the present invention can theoretically withstand infinite positive or negative dv / dt on SW node 6 as long as the gate-to-source voltage of the n-FETs connected to latch inputs 20 and 22 is clamped by the diode-connected protection FETs to be within the maximum allowable value.

[0040] The above description and drawings are considered to be merely illustrative of specific embodiments that achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Therefore, embodiments of the present invention are not considered to be limited by the above description and drawings. [Explanation of symbols]

[0041] 2 high-side FETs 4 High-side input signals 6 SW Node 6 8. Diodes 10 Level Shift Driver 12 Latch 14 Pulse Generator 16FET 18FET 20 Latch Input 22 Latch Input 24 latch outputs 26 Latch Output 30 resistor 32 resistor 34 Diode-connected FET 36 Diode-connected FET 38 Diode-connected FET 40 Diode-connected FET 42FET 44FET 46 Diode-connected FET 48 Diode-connected FET 50 Pulse Filter 52 Differential Amplifier 60 FET 62 FET 64FET 66 FET 68FET 70 FET 72 Inverter 74 Inverter 76 n-FET 78 n-FET 80 n-FET 82 n-FET

Claims

1. a first input and a second input for receiving a digital input value; a first output and a second output for outputting a digitally latched value; a first n-FET and a second n-FET connected in a cross-coupled configuration; a gate of each of the first n-FET and the second n-FET is electrically connected to a drain of the other of the first n-FET and the second n-FET; a first n-FET and a second n-FET, the drain of the first n-FET being connected to the first output and the drain of the second n-FET being connected to the second output; a first resistor and a second resistor connected between a voltage source and the first output and the second output, respectively, for pulling up the voltage at the first output and the second output, respectively, when the first n-FET and the second n-FET, respectively, are turned off; a node SW having a varying voltage; a circuit comprising: a plurality of n-FETs and a plurality of inverters connected to the first input and the second input, the first output and the second output, the cross-coupled first n-FETs and the cross-coupled second n-FETs, and the node SW to prevent a common mode signal caused by the changing voltage on the node SW from affecting the digitally latched values ​​of the first output and the second output, such that the digitally latched values ​​on the first output and the second output change only when the digital input values ​​on the first input and the second input are opposite to each other; the plurality of n-FETs comprises a third n-FET, a fifth n-FET, and a sixth n-FET; the plurality of inverters comprises a first inverter and a second inverter; The first inverter and the second inverter are inputs connected to said first input and said second input, respectively; outputs connected to the sixth n-FET and the third n-FET, respectively; and the third n-FET and the fifth n-FET are connected to the second n-FET and the first n-FET, respectively, the fifth n-FET is connected to the second input, and the sixth n-FET is connected to the node SW; 1. A cross-coupled differentially activated latch circuit comprising:

2. the plurality of n-FETs further comprising a fourth n-FET; the third n-FET and the fourth n-FET are electrically coupled in series; the drain of the third n-FET is connected to the drain of the second n-FET, and the source of the third n-FET is connected to the drain of the fourth n-FET; a gate of the fourth n-FET connected to the first input and a gate of the third n-FET connected to the output of the second inverter; the fifth n-FET and the sixth n-FET are electrically coupled in series; the drain of the fifth n-FET is connected to the gate of the second n-FET, and the source of the fifth n-FET is connected to the drain of the sixth n-FET; 2. The cross-coupled differentially activated latch circuit of claim 1, wherein a gate of the fifth n-FET is connected to the second input and a gate of the sixth n-FET is connected to the output of the first inverter.

3. The circuit is a logic function [Equation 1] 3. The cross-coupled differentially activated latch circuit of claim 2, wherein First Input is the digital input value received at the first input, Second Input is the digital input value received at the second input, First Output is the digitally latched value output at the first output, and Second Output is the digitally latched value output at the second output.

4. the plurality of n-FETs further comprising a fourth n-FET; the third n-FET and the fourth n-FET are electrically coupled in parallel; the drain of the third n-FET is connected to the drain of the fourth n-FET, and the source of the third n-FET is connected to the source of the fourth n-FET; a gate of the third n-FET connected to the output of the second inverter and a gate of the fourth n-FET connected to the first input; the fifth n-FET and the sixth n-FET are electrically coupled in parallel; the drain of the fifth n-FET is connected to the drain of the sixth n-FET, and the source of the fifth n-FET is connected to the source of the sixth n-FET; 2. The cross-coupled differentially activated latch circuit of claim 1, wherein a gate of the fifth n-FET is connected to the second input and a gate of the sixth n-FET is connected to the output of the first inverter.

5. The circuit is a logic function [Equation 2] 5. The cross-coupled differentially activated latch circuit of claim 4, wherein First Input is the digital input value received at the first input, Second Input is the digital input value received at the second input, First Output is the digitally latched value output at the first output, and Second Output is the digitally latched value output at the second output.

6. 5. The cross-coupled differentially activated latch circuit of claim 2, wherein the first n-FET through the sixth n-FET are GaN n-FETs.

7. 2. The cross-coupled differentially activated latch circuit of claim 1, wherein the first input and the second input are clamped by diode-connected protection n-FETs.

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