Semiconductor Module

Abstract

To provide a semiconductor module capable of restricting current flowing in a transistor.SOLUTION: A semiconductor module comprises: first and second transistors connected in parallel with each other while being connected with a first line to be applied with a power supply voltage; a drive circuit that applies to a second line a first voltage for turning on the first and second transistors depending on an input signal; a first resistor whose one end is connected with the second line and whose the other end is connected with a control electrode of the second transistor; a second resistor whose one end is connected with the other end of the first resistor and whose the other end is connected with a control electrode of the first transistor; a third resistor connected with the second transistor and in which a second voltage depending on current flowing in the second transistor is generated; a third transistor connected with the other end of the second resistor and whose control electrode is applied with the second voltage; and a terminal connected with the first to third transistors, the third resistor, and a load supplied with current from the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] BACKGROUND ART A semiconductor module including a transistor and a protection circuit that protects the transistor from an overcurrent is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 2523678 Summary of the Invention [Problem to be solved by the invention]

[0004] A typical protection circuit turns off a transistor to protect it when an overcurrent flows through the transistor. However, the protection circuit may erroneously turn off the transistor, for example, based on a current that flows transiently through the transistor when the transistor is turned on.

[0005] The present invention has been made in view of the above-mentioned problems in the prior art, and has an object to provide a semiconductor module capable of limiting the current flowing through a transistor. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a semiconductor module comprising: a first transistor connected to a first line to which a power supply voltage is applied; a second transistor connected in parallel to the first transistor and to the first line; a drive circuit that applies a first voltage to a second line to turn on the first transistor and the second transistor in response to an input signal; a first resistor having one end connected to the second line and the other end connected to a control electrode of the transistor; a second resistor having one end connected to the other end of the first resistor and the other end connected to a control electrode of the transistor; a third resistor connected to the second transistor and generating a second voltage in response to a current flowing through the second transistor; a third transistor connected to the other end of the second resistor and having the second voltage applied to its control electrode; and terminals to which the first to third transistors, the third resistor, and a load to which a current from the first transistor is supplied are connected. [Effects of the Invention]

[0007] A semiconductor module capable of limiting the current flowing through a transistor can be provided.

[0008] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows an example of the configuration of a semiconductor module 10a. [Figure 2] 2 shows an example of the configuration of the boost circuit 32. [Figure 3] 1 shows an example of a cross-sectional view of a diode 27 mounted on a semiconductor module 10a. [Figure 4] 1 shows an example of time variations in signals, voltages, and currents within the semiconductor module 10a during normal operation. [Figure 5] 10 shows an example of time variations in signals, voltages, and currents within the semiconductor module 10a when an overcurrent is detected. [Figure 6] 1 shows an example of the configuration of a semiconductor module 10b. [Figure 7] 10 shows an example of voltages and signals related to the drive circuit 22b and the determination circuit 72 during normal operation. [Figure 8] 10 shows an example of time variations in signals, voltages, and currents within the semiconductor module 10a when an overcurrent is detected. [Figure 9] 1 shows an example of a schematic diagram of the voltage Vout at the terminal VO, the current Ids, and the voltage Vcmp output from the determination circuit 72. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0011] In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrical connection." In this specification, when a voltage or signal has a low (Lo) logical level, it is referred to as a Lo level, and when the logic level is a high (Hi) logical level, it is referred to as a Hi level.

[0012] In this specification, one side in a direction parallel to the depth direction of a semiconductor module is referred to as the "front" or "upper" side, and the other side is referred to as the "back" or "lower" side. Furthermore, the two main surfaces of a substrate, layer, or other member are referred to as the "front surface" and the "back" or "lower" side. Here, the "front" or "upper" and "back" or "lower" directions are not limited to the direction of gravity or the direction in which each member is attached to a substrate or the like when the semiconductor module is mounted.

[0013] In this specification, the ground potential is a reference potential of the entire system including the semiconductor module, and is 0V.

[0014] ===Example 1=== <<Configuration Example of Semiconductor Module 10a>> 1 shows an example of the configuration of a semiconductor module 10a. The semiconductor module 10a is an intelligent power switch (IPS) that drives a load 13 based on a signal S1 input from a microcomputer 11. The semiconductor module 10a is provided closer to the power supply 12, i.e., on the high side, relative to the load 13 so that the load 13 can be driven by a power supply voltage Vdd supplied from the power supply 12.

[0015] The microcomputer 11 outputs a signal S1 to a terminal SIN of the semiconductor module 10a. As an example, the microcomputer 11 is included in an electric control unit (ECU) of an automobile.

[0016] The power supply 12 applies a power supply voltage Vdd to a terminal VDD of the semiconductor module 10a. The terminal VDD is connected to a line L1 of the semiconductor module 10a, and therefore the power supply voltage Vdd is applied to the line L1. As an example, the power supply 12 is a car battery.

[0017] As an example, the load 13 is a solenoid valve used in an automatic transmission automobile gear shifting system. The solenoid valve includes a solenoid constituting an electromagnet and a valve (not shown). When the solenoid is conductive, the valve closes, and when the solenoid is non-conductive, the valve opens. Here, the load 13 includes an inductor 41 and a resistor 42.

[0018] The inductor 41 is, for example, a solenoid in a solenoid valve. The resistor 42 adjusts the voltage applied to the inductor 41. The resistor 42 is provided between the inductor 41 and ground.

[0019] <<Configuration Example of Semiconductor Module 10a>> The semiconductor module 10a includes a voltage generating circuit 21, a driving circuit 22a, MOS transistors 23, 24, and 29, terminals SIN, VDD, VG, and VO, resistors 25, 26, and 28, and a diode 27.

[0020] ==Voltage Generation Circuit 21== The voltage generating circuit 21 generates a voltage Vgnd that serves as the voltage on the ground side of the drive circuit 22a and applies the voltage Vgnd to the line L3. The voltage Vgnd is a voltage that is lower than the power supply voltage Vdd by a predetermined voltage (for example, 5V). The voltage generating circuit 21 is provided between the line L1 to which the power supply voltage Vdd is applied and the grounded terminal VG.

[0021] ==Outline of drive circuit 22a== The drive circuit 22a applies a voltage Vdrv to the line L2 to turn on the MOS transistors 23 and 24 in response to the input signal S1.

[0022] For example, when the signal S1 indicates a Hi level, the drive circuit 22a applies a voltage Vdrv to the line L2 to turn on the MOS transistor 23, and when the signal S1 indicates a Lo level, the drive circuit 22a applies a voltage Vdrv to the line L2 to turn off the MOS transistor 23.

[0023] ==MOS Transistor 23== The MOS transistor 23 is turned on and off based on the voltage Vdrv, and supplies the voltage Vout and the current Idrv to the load 13. As will be described in detail later, when the MOS transistor 29 is in the off state, the voltage Vdrv is applied to the control electrode of the MOS transistor 23.

[0024] The MOS transistor 23 is an N-type MOS transistor (VMOS transistor) having a vertical trench structure in which a drain electrode is formed on the back surface of the substrate and a source electrode is formed on the front surface. The MOS transistor 23 of this embodiment is a power semiconductor element (having, for example, an on-resistance of 100 mΩ) and a breakdown voltage of several tens of volts.

[0025] However, the MOS transistor 23 is not limited to a VMOS transistor, and may be a planar MOS transistor or a bipolar element such as an IGBT (Insulated Gate Bipolar Transistor).

[0026] The gate electrode of the MOS transistor 23 is connected to the line L2 via resistors 25 and 26, and the source electrode is connected to the terminal VO. The drain electrode of the MOS transistor 23 is connected to the line L1 to which the power supply voltage Vdd is applied. Therefore, the current Ids flowing through the MOS transistor 23 is supplied to the load 13 via the terminal VO. The gate electrode of the MOS transistor 23 corresponds to the "control electrode."

[0027] The terminal VO is connected to the MOS transistors 23 and 29, the resistor 28, and the load 13 to which the current Ids from the MOS transistor 23 is supplied.

[0028] ==MOS Transistor 24== The MOS transistor 24 is a sense MOS transistor that passes a current Isns corresponding to the current Ids that flows through the MOS transistor 23. For this reason, the drain electrode of the MOS transistor 23 and the drain electrode of the MOS transistor 24 are connected in parallel to a line L1.

[0029] The MOS transistor 24 has a structure similar to that of the MOS transistor 23. The MOS transistor 24 is designed to pass a current Isns that is 0.25% of the current Ids, and the current Isns is 0.1 to 1% of the current Ids.

[0030] ==Resistors 25, 26== The resistors 25 and 26 are resistors for lowering the voltages of the gate electrodes of the MOS transistors 23 and 24 to reduce the current Ids when the current Ids flowing through the MOS transistor 23 increases. As will be described in detail later, in this embodiment, when the MOS transistor 29 is in the on state, the resistors 25 and 26 divide the voltage Vdrv applied to the MOS transistor 23. The voltage divided by the resistors R1 and R2 is applied to the control electrodes of the MOS transistors 23 and 24.

[0031] As an example, resistor 25 has a resistance value R1, and resistor 26 has a resistance value R2. In this case, if the current flowing through line L2 is Ig, a voltage of Vg2=Vdrv−R1*Ig is applied to the control electrode of MOS transistor 24, and a voltage of Vg1=Vdrv−Vg2−R2*Ig is applied to the control electrode of MOS transistor 23.

[0032] In this way, when the MOS transistor 29 is in the on state, the resistors 25 and 26 adjust the ratio between the voltage Vg1 applied to the control electrode of the MOS transistor 23 and the voltage Vg2 applied to the control electrode of the MOS transistor 24. In particular, the resistors 25 and 26 adjust the voltage Vg1 and are set to resistance values ​​that make the current Ids flowing through the MOS transistor 23 equal to or less than a current value Ioc1, which will be described later.

[0033] One end of the resistor 25 is connected to the line L2, and the other end of the resistor 25 is connected to the control electrode of the MOS transistor 24. In addition, one end of the resistor 26 is connected to the side of the resistor 25 to which the MOS transistor 24 is connected, and the other end of the resistor 26 is connected to the control electrode of the MOS transistor 23.

[0034] ==Diode 27== When the voltage Vdrv is applied to the line L2, the diode 27 keeps the potential difference between the voltage Vg2 applied to the control electrode of the MOS transistor 24 and the voltage Vg1 applied to the control electrode of the MOS transistor 23 at a constant level or less.

[0035] The anode of the diode 27 is connected to the resistor 25, and the cathode of the diode 27 is connected to the control electrode of the MOS transistor 23. That is, the diode 27 is provided in parallel with the resistor 26.

[0036] Therefore, when the voltage applied to diode 27 exceeds the forward voltage of diode 27, a voltage that reduces the potential difference between voltages Vg1 and Vg2 is applied through the path of diode 27 in preference to the path of resistor 26. In other words, by providing diode 27, the potential difference between voltages Vg1 and Vg2 is maintained at or below the forward voltage of diode 27.

[0037] As described above, the size of the MOS transistor 23 is larger than the size of the MOS transistor 24. Therefore, when the drive circuit 22a outputs the voltage Vdrv for turning on the MOS transistors 23 and 24, a difference occurs between the voltage Vg2 of the MOS transistor 24 and the voltage Vg1 of the MOS transistor 23. If the diode 27 were not provided, the difference between the voltage Vg2 and the voltage Vg1 would be large, and even if the MOS transistor 24 is turned on, the MOS transistor 23 may not be turned on.

[0038] However, in this embodiment, by providing the diode 27, the potential difference between the voltages Vg1 and Vg2 is kept below a certain level, so that it is possible to avoid a state in which the MOS transistor 24 is turned on and the MOS transistor 23 is not turned on for a long time.

[0039] However, for example, if the driving capability of the driving circuit 22a is high and the parasitic resistance and capacitance of the control electrodes of the MOS transistors 23 and 24 are small, the potential difference between the voltages Vg1 and Vg2 may not become large. In such a case, the MOS transistors 23 and 24 turn on at the same timing, and the diode 27 can be omitted.

[0040] ==Resistor 28== Resistor 28 is a resistor (e.g., 20Ω) for detecting an overcurrent state of MOS transistor 23, and is connected between MOS transistor 24 and terminal VO. A voltage Vsns corresponding to current Isns is generated across resistor 28. Note that, as will be described in detail later, "MOS transistor 23 is in an overcurrent state" refers to a state in which the current value of current Ids of MOS transistor 23 is equal to or greater than a predetermined value.

[0041] ==MOS Transistor 29== When the MOS transistor 23 is in an overcurrent state, the MOS transistor 29 adjusts the voltages Vg1 and Vg2 by turning on in response to the voltage Vsns.

[0042] A control electrode of the MOS transistor 29 is connected to the node where the MOS transistor 24 and the resistor 28 are connected. As a result, a voltage Vsns is generated at the control electrode of the MOS transistor 29. When the voltage Vsns increases and exceeds the threshold voltage of the MOS transistor 29, the MOS transistor 29 is turned on.

[0043] The drain electrode of the MOS transistor 29 is connected to the other end of the resistor 26. When the MOS transistor 29 is turned on, the current output from the drive circuit 22a flows to the load 13 via the line L2, the resistors 25 and 26, the MOS transistor 29, and the terminal VO. As a result, the voltage Vg1 applied to the control electrode of the MOS transistor 23 and the voltage Vg2 applied to the control electrode of the MOS transistor 24 both decrease.

[0044] Therefore, when the MOS transistor 29 is turned on, the current Ids flowing through the MOS transistor 23 and the current Isns flowing through the MOS transistor 24 can be reduced.

[0045] Furthermore, when the current Isns of the MOS transistor 24 decreases, the voltage Vsns decreases, and the gate voltage of the MOS transistor 29 decreases. As a result, the current flowing through the MOS transistor 29 decreases. This gradually weakens the effect of the MOS transistor 29 in reducing the voltages Vg1 and Vg2 and the currents Ids and Isns.

[0046] As a result, the voltages Vg1, Vg2, and Vsns and the currents Ids and Isns gradually approach constant values. In this case, the current Ids approaches the current Ioc1, which will be described later.

[0047] In this way, the resistors 25 and 26 and the MOS transistor 29 of this embodiment can reduce the voltages Vg1 and Vg2 when the MOS transistor 23 is in an overcurrent state. Therefore, in this embodiment, it is possible to prevent the currents Ids and Isns from exceeding a certain value (current Ioc1).

[0048] <<Details of the drive circuit 22a>> The drive circuit 22 a includes a control circuit 31 , a boost circuit 32 , and a MOS transistor 33 .

[0049] ===Control circuit 31=== The control circuit 31 outputs a signal S2 in response to the input signal S1. When the input signal S1 is at a high level, the control circuit 31 outputs a low-level signal S2. On the other hand, when the signal S1 is at a low level, the control circuit 31 outputs a high-level signal S2.

[0050] ===Boost Circuit 32=== The boost circuit 32 boosts the power supply voltage Vdd in accordance with the logic level of the input signal S2 and applies the voltage Vdrv to the line L2. In this embodiment, when the signal S2 is at a low level, the boost circuit 32 boosts the power supply voltage Vdd. On the other hand, when the signal S2 is at a high level, the boost circuit 32 stops boosting the power supply voltage Vdd.

[0051] That is, the boost circuit 32 boosts the power supply voltage Vdd in response to the Lo level signal S2 for turning on the MOS transistors 23 and 24, and applies the voltage Vdrv to the line L2.

[0052] ===MOS Transistor 33=== The MOS transistor 33 is a cutoff element for turning off the MOS transistor 23 in accordance with the logic level of the input signal S2.

[0053] In this embodiment, when the signal S2 goes high, the MOS transistor 33 turns on. This causes a current to flow from the line L2 to the terminal VO through the MOS transistor 33. At this time, the MOS transistor 33 reduces the voltage Vdrv applied to the line L2, thereby reducing the voltages Vg1 and Vg2. As a result, the MOS transistors 23 and 24 turn off.

[0054] On the other hand, when the signal S2 is at Lo level, the MOS transistor 33 is turned off. In this case, the voltage Vdrv is applied to the line L2 from the boost circuit 32. Note that in this embodiment, the NMOS transistor 33 is used as a cutoff element for turning off the N-type MOS transistors 23 and 24, but this is not limiting and a bipolar transistor, for example, may also be used.

[0055] The signal S1 corresponds to the "input signal," and the voltage Vdrv corresponds to the "first voltage." The signal S2 corresponds to the "drive signal." The MOS transistor 23 corresponds to the "first transistor," the MOS transistor 24 corresponds to the "second transistor," and the MOS transistor 29 corresponds to the "third transistor."

[0056] Resistor 25 corresponds to the "first resistor," resistor 26 corresponds to the "second resistor," and resistor 28 corresponds to the "third resistor." Voltage Vsns corresponds to the "second voltage." Current value Ioc1 corresponds to the "first current value."

[0057] Line L1 corresponds to the "first line" and line L2 corresponds to the "second line."

[0058] <<Configuration of Booster Circuit 32>> 2 shows an example of the configuration of the boost circuit 32. The boost circuit 32 is a so-called charge pump circuit, and includes an oscillator circuit 50, diodes 51, 54, 56, and 58, an inverter 53, and capacitors 52 and 57. Here, the forward voltage of the diodes 51, 54, 56, and 58 is defined as "Vf."

[0059] The oscillator circuit 50 outputs a clock signal CLK of a predetermined frequency based on a signal S2 for turning on the MOS transistors 23 and 24. When the signal S2 goes low, the oscillator circuit 50 outputs the clock signal CLK, and when the signal S2 goes high, the oscillator circuit 50 stops outputting the clock signal CLK. The clock signal CLK changes between a voltage Vgnd (low level) and a power supply voltage Vdd (high level).

[0060] The diode 51 and the capacitor 52 constitute a first-stage boost circuit in the charge pump circuit. The power supply voltage Vdd is applied to the anode of the diode 51, and the cathode is connected to one end of the capacitor 52. The other end of the capacitor 52 is connected to the output of the oscillation circuit 50.

[0061] The inverter 53, diodes 54 and 56, and capacitor 57 constitute a second-stage boost circuit of the charge pump circuit. The inverter 53 is connected between Vgnd and Vdd.

[0062] The anode of the diode 54 is connected to one end of the capacitor 52, and the cathode is connected to one end of the capacitor 57. The power supply voltage Vdd is applied to the anode of the diode 56, and the cathode is connected to one end of the capacitor 57. The other end of the capacitor 57 is connected to the output of the inverter 53.

[0063] The voltage Vc2 at one end of the capacitor 57 in the second-stage booster circuit is output via the diode 58 as the voltage Vdrv.

[0064] <<Operation of the Booster Circuit 32>> As described above, the clock signal CLK changes between the voltage Vgnd (Lo level) and the power supply voltage Vdd (Hi level). However, since it would be complicated to express the voltages of the nodes of the boost circuit 32, the Lo level of the clock signal CLK will be described as 0 V for the sake of convenience.

[0065] First, when the clock signal CLK is at the Lo level, the voltage Vc1 at one end of the capacitor 52 is charged via the diode 51. As a result, the voltage Vc1 at one end of the capacitor 52 is expressed by the equation (1).

[0066] Vc1=Vdd-Vf (1) When the clock signal CLK becomes Hi level (the level of the power supply voltage Vdd), the voltage Vc1 at one end of the capacitor 52 is expressed by equation (2).

[0067] Vc1=2×Vdd-Vf (2) At this timing, the output of the inverter 53 is at the Lo level, so that the capacitor 57 is charged, and the voltage Vc2 of the capacitor 57 is expressed by equation (3).

[0068] Vc2=2×Vdd-2×Vf (3) Furthermore, when the clock signal CLK goes to Hi level, the voltage Vc2 at one end of the capacitor 57 is expressed by equation (4).

[0069] Vc2=3×Vdd-2×Vf (4) As a result, the voltage Vdrv output from the diode 58 is expressed by equation (5).

[0070] Vc2=3×Vdd-3×Vf (5) Although the booster circuit 32 of this embodiment includes a two-stage booster section, the present invention is not limited to this and may have any configuration as long as the voltage Vdrv is a voltage that can turn on the MOS transistors 23 and 24.

[0071] <<Configuration of Diode 27>> 3 shows an example of a cross-sectional view of the diode 27 mounted on the semiconductor module 10a. The diode 27 is composed of a substrate 61, an epitaxial layer 62, oxide films 63 and 67, dopant diffusion regions 64, 65 and 66, an anode 68, and a cathode 69.

[0072] In the regions marked with each conductivity type, a "+" sign means that the doping concentration is higher than in regions not marked with a "+", and a "-" sign means that the doping concentration is lower than in regions not marked with a "-".

[0073] The substrate 61 in this embodiment is a substrate on which the MOS transistors 23 and 24 are provided. That is, in this embodiment, the MOS transistors 23 and 24 and the diode 27 are provided on the same semiconductor chip. The substrate 61 has an N+ conductivity type.

[0074] The epitaxial layer 62 is a layer provided above the substrate 61. The epitaxial layer 62 is a layer provided by epitaxially growing the substrate 61. The epitaxial layer 62 of this embodiment has N-type conductivity.

[0075] The oxide film 63 is provided to cover the upper surface of the epitaxial layer 62. As an example, the oxide film 63 is a SiO2 film.

[0076] The dopant diffusion region 64 is a polysilicon region provided above the oxide film 63. A P-type dopant (e.g., boron (B)) is diffused into the dopant diffusion region 64. As an example, the dopant is diffused by ion implantation. The dopant diffusion region 64 in this embodiment has a P+ conductivity type.

[0077] The dopant diffusion region 65 is a polysilicon region provided above the oxide film 63. An N-type dopant (e.g., phosphorus (P)) is diffused into the dopant diffusion region 65. As an example, the dopant is diffused by ion implantation. The dopant diffusion region 65 in this embodiment has an N+ conductivity type.

[0078] The dopant diffusion region 66 is a region provided between and in contact with the dopant diffusion regions 64 and 65. In this embodiment, the dopant diffusion region 66 corresponds to a depletion layer provided between the P+ type region and the N+ type region of the diode. Therefore, the dopant diffusion region 66 in this embodiment has an N- type conductivity type that is lower than the N-type doping concentration, which is the substrate concentration.

[0079] The oxide film 67 is an oxide film provided above the dopant diffusion regions 64 to 66 so as to cover them. As an example, the oxide film 67 is provided using the same material as the oxide film 63.

[0080] The anode 68 is a terminal provided on the upper surface of the dopant diffusion region 64 in contact with the dopant diffusion region 64. The anode 68 is provided after etching the oxide film 67 provided above the dopant diffusion region 64 to expose the dopant diffusion region 64. As an example, the anode 68 is made of a metal (e.g., an aluminum silicon alloy, hereinafter referred to as AlSi).

[0081] The cathode 69 is a terminal provided on the upper surface of the dopant diffusion region 65 in contact with the dopant diffusion region 65. The cathode 69 is provided after etching the oxide film 67 provided above the dopant diffusion region 65 to expose the dopant diffusion region 65. As an example, the cathode 69 is made of the same material as the anode 68. In this embodiment, the cathode 69 is made of a metal (e.g., AlSi).

[0082] Here, the P-type conductivity corresponds to the “first conductivity type,” and the N-type conductivity corresponds to the “second conductivity type.” The dopant diffusion region 64 corresponds to the “first dopant diffusion region,” and the dopant diffusion region 65 corresponds to the “second dopant diffusion region.”

[0083] <<Timing diagram of semiconductor module 10a during normal operation>> FIG. 4 shows an example of the time variations of signals, voltages, and currents in the semiconductor module 10a during normal operation.

[0084] In this specification, "normal operation" of semiconductor module 10a or semiconductor module 10b (described later) refers to a state in which no short circuit or the like occurs in load 13 and MOS transistor 23 is not in an overcurrent state. In particular, when semiconductor modules 10a and 10b are in "normal operation," the drain-source current Ids flowing through MOS transistor 23 is smaller than a current value Ioc2 (described later).

[0085] In the figure, the voltage and signal outline is shown as Lo when the logic level is low (Lo) and as Hi when the logic level is high (Hi).

[0086] The microcomputer 11 outputs the signal S1 at a low level until time t1, at which time the microcomputer 11 switches the level of the signal S1 from a low level to a high level to turn on the MOS transistor 23.

[0087] When the signal S1 input to the drive circuit 22a switches to Hi level at time t1, the drive circuit 22a starts boosting the voltage Vdrv based on the power supply voltage Vdd, and accordingly the voltage Vg1 applied to the control electrode of the MOS transistor 23 increases.

[0088] Then, as the on-resistance of the MOS transistor 23 gradually decreases, the voltage Vout applied to the terminal VO connected to the MOS transistor 23 increases. When the MOS transistor 23 turns on, the voltage Vout becomes equal to the power supply voltage Vdd. Therefore, when the MOS transistor 23 turns on, the voltage Vout gradually approaches the power supply voltage Vdd.

[0089] When the MOS transistor 23 is turned on, the current Ids flowing through the MOS transistor 23 increases. In this embodiment, even if the current Ids flowing through the MOS transistor 23 increases, the current Ids is sufficiently smaller than the current value Ioc1 (for example, 50% or less of the current value Ioc1, which indicates an overcurrent state).

[0090] When the current Ids flowing through the MOS transistor 23 is sufficiently smaller than the current value Ioc1, the current Isns flowing through the MOS transistor 24 and the voltage Vsns generated across the resistor 28, which is proportional to the current Isns, also become small. In this case, the MOS transistor 29 does not turn on.

[0091] In this way, during normal operation, the MOS transistor 29 is not turned on, so that the voltage Vg1 applied to the control electrode of the MOS transistor 23 and the voltage Vg2 applied to the control electrode of the MOS transistor 24 on the line L2 are equal to the voltage Vdrv, and therefore the MOS transistor 23 is driven by the desired voltage Vdrv.

[0092] <<Timing diagram when an overcurrent is detected in the semiconductor module 10a>> 5 shows an example of time variations in the signals, voltages, and currents in the semiconductor module 10a when an overcurrent is detected. As described above, in this embodiment, the overcurrent state is a state in which the current Ids flowing through the MOS transistor 23 increases and reaches a predetermined current value Ioc1.

[0093] The microcomputer 11 outputs the signal S1 at a low level until time t2, at which time the microcomputer 11 switches the level of the signal S1 from a low level to a high level to turn on the MOS transistor 23.

[0094] When an overcurrent occurs, for example, the path from the terminal VO to the ground is short-circuited. In such a case, the resistance between the terminal VO and the ground is sufficiently smaller than the on-resistance of the MOS transistor 23. Therefore, the voltage Vout at the terminal VO hardly increases even when the MOS transistor 23 is turned on.

[0095] At time t2, the MOS transistor 23 turns on, increasing the current Ids flowing through the MOS transistor 23. When the current Ids increases, the current Isns flowing through the MOS transistor 24 also increases, and the voltage Vsns also rises.

[0096] Therefore, as time t3 approaches (for example, when current Ids exceeds 50% of current Ioc), MOS transistor 29 turns on. When MOS transistor 29 turns on, current flows from boost circuit 32 through line L2, resistors 25 and 26, MOS transistor 29, and terminal VO. As a result, the rise of voltages Vg1 and Vg2 becomes gradual.

[0097] Therefore, the current Ids flowing through the MOS transistor 23 and the current Isns flowing through the MOS transistor 24 also increase slowly. As a result, the voltage Vsns generated across the resistor 28 increases slowly in proportion to the current Isns.

[0098] At time t3, the voltages Vg1, Vg2, and Vsns and the currents Ids and Isns are balanced and reach constant values.

[0099] Then, at time t3, the current Ids flowing through the MOS transistor 23 reaches a current value Ioc1.

[0100] The voltage Vdrv that the drive circuit 22a applies to the line L2 gradually increases from time t2. At time t3, the drive circuit 22a applies the voltage Vdrv, which has reached a constant value Vdd-2Vf, to the line L2.

[0101] When the MOS transistor 29 is turned on, the voltage Vdrv output from the drive circuit 22a is divided by the resistors 25 and 26. The voltage Vg2 applied to the control electrode of the MOS transistor 24 starts to rise from time t2, and shows a constant value Vdd-Ig×R1 from time t3.

[0102] Similarly, the voltage Vg1 applied to the control electrode of the MOS transistor 23 starts to rise from time t2, and shows a constant value Vdd-Ig×(R1+R2) from time t3.

[0103] As described above, when a voltage Vsns larger than that at which the MOS transistor 29 turns on occurs across the resistor 28, the current Ids flowing through the MOS transistor 23 is adjusted to the current Ioc1, and is adjusted so that a current equal to or smaller than the current Ioc1 flows.

[0104] The voltage Vsns is proportional to the current Isns flowing through the MOS transistor 24, and the current Isns is proportional to the current Ids flowing through the MOS transistor 23.

[0105] That is, in the semiconductor module 10a, when a path other than the load 13 in the path between the terminal VO and ground is short-circuited, the current Ids flowing through the MOS transistor 23 increases, and an overcurrent state occurs, the MOS transistor 29 turns on and adjusts the current Ids so that it is equal to or less than the current value Ioc1.

[0106] This allows the semiconductor module 10a to limit the current when an overcurrent occurs due to a load short circuit or the like, thereby appropriately protecting the elements.

[0107] === Example 2 === <<Configuration Example of Semiconductor Module 10b>> Figure 6 shows an example of the configuration of semiconductor module 10b. The same components are denoted by the same reference numerals in Figure 1 and Figure 6. Therefore, the following description will mainly focus on the differences from semiconductor module 10a.

[0108] The semiconductor module 10b differs from the semiconductor module 10a in that it includes a drive circuit 22b, a reference voltage circuit 71, and a determination circuit 72.

[0109] ==Reference Voltage Circuit 71== The reference voltage circuit 71 generates a predetermined reference voltage Vref that serves as a reference for the determination circuit 72 to detect an overcurrent, and applies the voltage to one of the lines connected to the determination circuit 72 .

[0110] The reference voltage Vref is set as a voltage with a certain potential difference (for example, 100 mV) with respect to the voltage VO generated at the terminal VO. For example, if the resistor 28 is 20 Ω, an overcurrent is detected when the current Ids flowing through the MOS transistor 23 is 2 A, and the current Isns in this case is 5 mA, the reference voltage Vref is set to 20×0.005 (V)=100 (mV).

[0111] ==Judgment circuit 72== The determination circuit 72 determines whether the MOS transistor 23 is in an overcurrent state based on a comparison between the voltage Vsns generated across the resistor 28 and the reference voltage Vref generated by the reference voltage circuit 71. The determination circuit 72 is a comparator that outputs a voltage Vcmp of a different logic level depending on the determination result.

[0112] In this embodiment, the voltage Vcmp is input to a filter circuit 82, which will be described later.

[0113] When the voltage Vsns reaches the voltage Vref, the determination circuit 72 determines that the MOS transistor 23 is in an overcurrent state. In this case, the current Ids flowing through the MOS transistor 23 reaches a current value Ioc2. In this embodiment, the current value Ioc2 is set to be smaller than the current value Ioc1.

[0114] That is, the voltage Vref in this embodiment is a voltage at which the current Ids flowing through the MOS transistor 23 exhibits a current value Ioc2 that is smaller than the current value Ioc1. In this embodiment, the current value Ioc1 is a value for detecting whether the MOS transistor 23 is in an overcurrent state when the MOS transistor 23 is turned on.

[0115] On the other hand, the current value Ioc2 is a value for detecting whether the MOS transistor 23 is in an overcurrent state after the MOS transistor 23 is turned on. Generally, a larger current flows when the MOS transistor 23 is turned on than after the MOS transistor 23 is turned on. Therefore, in this embodiment, the current value Ioc2 after the MOS transistor 23 is turned on is set to be smaller than the current value Ioc1.

[0116] A reference voltage Vref is applied to one line connected to the determination circuit 72, and a voltage Vsns is applied to the other line connected to the determination circuit 72. During the period before the MOS transistors 23 and 24 are turned on and the signal S1 indicates a low level, the voltages applied to these lines are both low. In this case, the determination circuit 72 of this embodiment outputs a low-level voltage Vcmp to the filter circuit 82.

[0117] Furthermore, the determination circuit 72 of this embodiment is connected to the line L1 and the voltage generation circuit 21, and the difference voltage between the power supply voltage Vdd and the voltage Vgnd is used as a bias voltage.

[0118] ==Driver circuit 22b== The drive circuit 22b turns on and off the MOS transistor 23 based on the input signal S1 and the determination result of the determination circuit 72. Specifically, the drive circuit 22b of this embodiment turns on the MOS transistor 23 regardless of the filter period Tflt when the MOS transistor 23 turns on or the determination result of the determination circuit 72, and turns off the MOS transistor 23 after the filter period Tflt has elapsed if the determination circuit 72 determines that the MOS transistor 23 is in an overcurrent state.

[0119] The drive circuit 22b includes a boost circuit 32, a MOS transistor 33, and a drive signal output circuit 34. The boost circuit 32 and the MOS transistor 33 operate in accordance with the signal S2 in the same manner as the boost circuit 32 and the MOS transistor 33 of the semiconductor module 10a. The drive circuit 22b differs from the drive circuit 22a in that the drive circuit 22b includes the drive signal output circuit 34.

[0120] ===Drive signal output circuit 34=== The drive signal output circuit 34 outputs a signal S2 for turning on and off the MOS transistor 23 based on the input signal S1 and the determination result of the determination circuit 72. The drive signal output circuit 34 includes a control circuit 81 and a filter circuit 82.

[0121] ====Control circuit 81==== The control circuit 81 outputs a signal S2 based on the logic levels of the input signal S1 and the voltage Vflt input from the filter circuit .

[0122] The control circuit 81 outputs a Hi-level signal S2 when the voltage Vflt input from the filter circuit 82 is at a Lo level. On the other hand, the control circuit 81 outputs a Lo-level signal S2 when the voltage Vflt is at a Hi level and the signal S1 is at a Hi level, and outputs a Hi-level signal S2 when the voltage Vflt is at a Hi level and the signal S1 is at a Lo level.

[0123] ====Filter Circuit 82==== The filter circuit 82 sets a mask on the operation of the control circuit 81 for a predetermined filter period Tflt (for example, 10 μsec) when the MOS transistor 23 is turned on. Note that the "predetermined filter period Tflt when the MOS transistor 23 is turned on" here refers to the period from when the Hi-level signal S1 for turning on the MOS transistor 23 is input to the filter circuit 82 until the filter period Tflt has elapsed.

[0124] Specifically, before the period Tflt begins, the filter circuit 82 outputs a Hi-level voltage Vflt to the control circuit 81 in response to the input Lo-level signal S1. Furthermore, during the period Tflt, the filter circuit 82 outputs a Hi-level voltage Vflt to the control circuit 81 regardless of the determination result of the determination circuit 72. In this case, the control circuit 81 outputs a signal S2 in response to the signal S1. On the other hand, after the period Tflt has elapsed, the determination circuit 72 outputs to the control circuit 81 a voltage Vflt of a logical level equal to the logical level of the voltage Vcmp input from the determination circuit 72.

[0125] Meanwhile, during the time from when the signal S1 is input to the control circuit 81 until the circuits in the semiconductor module 10b become stable (for example, several microseconds), the determination circuit 72 may momentarily indicate a logic level that indicates an overcurrent state of the MOS transistor 23. The filter circuit 82 sets a mask on the determination result of the determination circuit 72, thereby enabling the circuit to operate stably.

[0126] Furthermore, the filter circuit 82 of this embodiment is connected to the terminal SIN, whereby the signal S1 is input to the filter circuit 82, and the filter circuit 82 can detect the timing at which the control circuit 81 starts the operation of turning on the MOS transistor 23.

[0127] In this embodiment, the judgment circuit 72 is connected to the control circuit 81 via the filter circuit 82, and the control circuit 81 operates based on the voltage Vflt, so that the control circuit 81 can operate indirectly based on the voltage Vcmp without connecting the judgment circuit 72 to the control circuit 81.

[0128] == Filter period Tflt and overcurrent detection == The semiconductor module 10b of this embodiment operates normally when (i) the current Ids flowing through the MOS transistor 23 is smaller than both the current values ​​Ioc1 and Ioc2.

[0129] (ii) If a short circuit of the load occurs during the filtering period Tflt, the current Ids flowing through the MOS transistor 23 is limited to a current value Ioc1 or less by the resistors 25, 26, and 28 and the MOS transistors 24 and 29. In the case of (ii), the determination circuit 72 does not perform a determination based on the current Ioc2 during the filtering period Tflt, and therefore protection is performed based on the current Ioc1.

[0130] In this case, after the filter period Tflt has elapsed, the determination circuit 72 determines that the MOS transistor 23 is in an overcurrent state, and the drive circuit 22b turns off the MOS transistor 23 based on the determination result.

[0131] (iii) If the current Ids becomes larger than the current value Ioc2 after the filter period Tflt, the judgment circuit 72 judges that the MOS transistor 23 is in an overcurrent state, and based on the judgment result of the judgment circuit 72, the drive circuit 22b turns off the MOS transistor 23.

[0132] As described above, the determination circuit 72 does not perform determination during the filter period Tflt to prevent erroneous detection of an overcurrent when the semiconductor module 10b starts up. On the other hand, in the case of (ii), if the MOS transistor 23 is not protected from an overcurrent even during the filter period Tflt, elements in the circuit may be damaged by the overcurrent during the filter period Tflt.

[0133] Therefore, in the semiconductor module 10b, by providing resistors 25 and 26, a MOS transistor 29, etc., the drain-source current Ids of the MOS transistor 23 can be limited to a current value Ioc1 or less even during the filter period Tflt. This allows the semiconductor module 10b to protect the MOS transistor 23 from overcurrents during the filter period Tflt. Below, we will explain in detail the operation of the semiconductor module 10b both during normal operation and when an overcurrent is detected.

[0134] The voltage Vref corresponds to a "third voltage." The current value Ioc2 corresponds to a "second current value."

[0135] <<Timing diagram of semiconductor module 10b during normal operation>> FIG. 7 shows an example of voltages and signals related to the drive circuit 22b and the determination circuit 72 during normal operation.

[0136] At time t4, the microcomputer 11 raises the signal S1 input to the terminal SIN from Lo level to Hi level in order to drive the MOS transistor 23. Furthermore, in order to continue driving the MOS transistor 23, the microcomputer 11 maintains the signal S1, which has been raised to Hi level, at Hi level.

[0137] When the MOS transistor 23 is turned on, the MOS transistor 24 is also turned on, thereby increasing the drain-source current Isns of the MOS transistor 24. As the drain-source current Isns of the MOS transistor 24 increases, the voltage Vsns generated across the resistor 28 also increases.

[0138] Furthermore, at time t6, the voltage Vsns indicates a steady value. In this embodiment, since the semiconductor module 10b operates normally, the voltage Vsns does not reach the reference voltage Vref at which the MOS transistor 23 enters an overcurrent state.

[0139] The voltage Vsns is input to one of the input terminals of the determination circuit 72, and the voltage Vref is input to the other input terminal from the reference voltage circuit 71. In this embodiment, when the semiconductor module 10b is operating normally, the determination circuit 72 outputs a high-level voltage Vcmp.

[0140] Since the determination circuit 72 is provided between the lines L1 and L3, when the voltage Vcmp output from the determination circuit 72 is at a Hi level, this means that the voltage Vcmp is at the power supply voltage Vdd, whereas when the voltage Vcmp is at a Lo level, this means that the voltage Vcmp is at the voltage Vgnd.

[0141] The filter circuit 82 of this embodiment is connected to a terminal SIN, and receives a signal S1 as input. The filter circuit 82 also receives a voltage Vcmp as input.

[0142] During the period before time t4, the voltage on the line input from the reference voltage circuit 71 to the determination circuit 72 is low. During this period, the MOS transistor 24 is not turned on, so the voltage across the resistor 28 is low, and the voltage Vsns input from the node between the MOS transistor 24 and the resistor 28 to the line of the determination circuit 72 is also low. In this case, the determination circuit 72 of this embodiment outputs a low-level voltage Vcmp.

[0143] On the other hand, in the period after time t4, the voltage Vref is applied from the reference voltage circuit 71 to the line of the determination circuit 72. Since the semiconductor module 10b of this embodiment performs normal operation and the voltage Vsns does not reach the voltage Vref, in the period after time t4, the determination circuit 72 outputs a Hi-level voltage Vcmp.

[0144] At time t4, the signal S1 switches from Lo level to Hi level, and in response thereto, the filter circuit 82 sets a mask on the voltage Vcmp output from the determination circuit 72 for time t5, which is a time period Tflt after time t4.

[0145] Specifically, from time t4 to time t5, the filter circuit 82 outputs a high-level voltage Vflt to the control circuit 81 regardless of the logic level of the voltage Vcmp. As a result, the logic level of the voltage Vcmp is masked for the control circuit 81 from time t4 to time t5. After time t5, the filter circuit 82 outputs a voltage flt having the same logic level as the voltage Vcmp. Furthermore, before time t4, the filter circuit 82 outputs a high-level voltage Vflt in response to a low-level signal S1.

[0146] The overcurrent detection of the semiconductor module 10b is performed using a voltage Vsns according to the current Isns that flows through the MOS transistor 24, which has an on-time shorter than that of the MOS transistor 23. Therefore, the period Tflt is set to a short time (for example, 10 μsec).

[0147] A signal S1 is input to the control circuit 81 from the microcomputer 11 via the terminal SIN. During the period before time t4, a low-level signal S1 is input to the control circuit 81 to turn off the MOS transistor 23. In response to the low-level signal S1, the control circuit 81 outputs a high-level signal S2. While the signal S2 is high, the boost circuit 32 does not boost the power supply voltage Vdd, and the MOS transistor 33 is turned on.

[0148] At time t4, when the signal S1 input to the control circuit 81 to turn on the MOS transistor 23 goes high, the control circuit 81 outputs a signal S2 that drops from high to low. When the signal S2 goes low, the boost circuit 32 boosts the power supply voltage Vdd to start generating the drive voltage Vdrv, which is applied to the MOS transistor 23. Furthermore, the MOS transistor 33 goes off.

[0149] In this embodiment, the semiconductor module 10b operates normally and no overcurrent state is detected. Therefore, after time t4, the control circuit 81 continues to output the signal S2 at a low level to maintain the on state of the MOS transistor 23.

[0150] <<Timing diagram when an overcurrent is detected in the semiconductor module 10b>> FIG. 8 shows an example of the time variations of the signals, voltages, and currents in the semiconductor module 10b when an overcurrent is detected.

[0151] At time t7, as in normal operation, the microcomputer 11 raises the signal S1 from low level to high level in order to drive the MOS transistor 23. Furthermore, in order to continue driving the MOS transistor 23, the microcomputer 11 maintains the signal S1, which has been raised to high level, at high level.

[0152] At time t7, the MOS transistors 23 and 24 are turned on. Accordingly, the current Isns of the MOS transistors 23 and 24 increases. In this embodiment, the voltage Vsns rises as the current Vsns increases, and when the voltage Vsns reaches the reference voltage Vref at time t9, the determination circuit 72 determines that the MOS transistor 23 is in an overcurrent state.

[0153] When the determination circuit 72 detects an overcurrent state of the MOS transistor 23, the drive circuit 22b turns off the MOS transistor 23. In this case, as the MOS transistor 23 turns off, the MOS transistor 24 also turns off. Therefore, the voltage Vsns generated across the resistor 28 drops after reaching the reference voltage Vref.

[0154] In this embodiment, in order to protect the MOS transistor 23 from an overcurrent state, the drive circuit 22b turns off the MOS transistor 23 for a predetermined period from time t9. Accordingly, the MOS transistor 24 also turns off, and the voltage Vsns generated across the resistor 28 is maintained at a value reduced to the voltage Vout.

[0155] During the period before time t7, the voltage supplied to the line from the reference voltage circuit 71 to the determination circuit 72 and the voltage supplied to the line from the node between the MOS transistor 24 and the resistor 28 to the determination circuit 72 are both low. In this case, the determination circuit 72 outputs a low-level voltage Vcmp.

[0156] During the period from time t7 to time t9, the voltage Vref is supplied to the line from the reference voltage circuit 71 to the determination circuit 72, and the voltage Vsns generated across the resistor 28 is supplied to the line from the node between the MOS transistor 24 and the resistor 28 to the determination circuit 72, so that the voltage Vsns generated across the resistor 28 is lower than the reference voltage Vref. In this case, the determination circuit 72 outputs a high-level voltage Vcmp to the filter circuit 82.

[0157] Meanwhile, at time t9, the voltage Vsns reaches the reference voltage Vref, and the determination circuit 72 determines that the MOS transistor 23 is in an overcurrent state. As a result, the determination circuit 72 outputs a low-level voltage Vcmp to the filter circuit 82. Furthermore, the determination circuit 72 continues to output the low-level voltage Vcmp for a predetermined period from time t9.

[0158] Furthermore, in the period before time t7, the filter circuit 82 outputs a high-level voltage Vflt in response to the low-level signal S1 input thereto.

[0159] During the period Tflt from time t7 to time t8, the filter circuit 82 outputs the Hi-level voltage Vflt regardless of the logic level of the voltage Vcmp. This masks the logic level of the voltage Vcmp for the control circuit 81.

[0160] In this embodiment, during the period Tflt from time t7 to time t8, the determination circuit 72 outputs the Hi-level voltage Vcmp. Even if the circuit operation in the semiconductor module 10 is unstable during this period and the determination circuit 72 outputs the Lo-level voltage Vcmp, the filter circuit 82 outputs the Hi-level voltage Vflt during this period.

[0161] On the other hand, after time t8, the filter circuit 82 outputs to the control circuit 81 the voltage Vflt having the same logic level as the voltage Vcmp.

[0162] Therefore, in this embodiment, the filter circuit 82 outputs a high-level voltage Vflt during the period before time t7 and during the period from time t7 to t9, and outputs a low-level voltage flt during a predetermined period after time t9.

[0163] During the period before time t7, a low-level signal S1 is input to the control circuit 81 to turn off the MOS transistor 23. In response to the low-level signal S1, the control circuit 81 outputs a high-level signal S2. While the signal S2 is high, the boost circuit 32 does not boost the power supply voltage Vdd, and the MOS transistor 33 is turned on.

[0164] At time t7, when the signal S1 goes high to turn on the MOS transistor 23, the control circuit 81 outputs the signal S2 that drops from high to low. When the signal S2 goes low, the boost circuit 32 starts boosting the power supply voltage Vdd to the voltage Vdrv, and applies the boosted voltage Vdrv to the MOS transistor 23. Furthermore, the MOS transistor 33 is turned off.

[0165] On the other hand, at time t9, the filter circuit 82 inputs the Lo-level voltage Vflt to the control circuit 81. This notifies the control circuit 81 that the Lo-level voltage Vflt has caused the MOS transistor 23 to enter an overcurrent state.

[0166] Therefore, in the period after time t9, the control circuit 81 outputs a high-level signal S2 in response to the low-level voltage Vflt input from the filter circuit 82. When the logic level of the signal S2 becomes high, the boost circuit 32 stops boosting the power supply voltage Vdd, the MOS transistor 33 turns on, and the MOS transistor 23 turns off.

[0167] <<Relationship between voltage and current in the period after the period Tflt in Example 2>> 9 shows an example of the outline of the voltage Vout at the terminal VO, the current Ids, and the voltage Vcmp output from the determination circuit 72. The graph shows the state in which the MOS transistor 23 is in the ON state after the signal S1 is switched from the Low level to the High level and a period Tflt has elapsed.

[0168] The relationship between the voltage Vout and the current Ids is shown. When the MOS transistor 23 is in the on state and the semiconductor module 10b is operating normally, the voltage Vout applied to the terminal VO indicates the power supply voltage Vdd.

[0169] The graph shows that when the drain-source current Ids of the MOS transistor 23 reaches a current Ioc2 (for example, 2 A) that indicates an overcurrent state, the voltage Vout applied to the terminal VO reaches a voltage Voc2 that indicates an overcurrent.

[0170] In this embodiment, when the voltage Vout applied to the terminal VO reaches the voltage Voc2, the voltage Vsns generated across the resistor 28 reaches the reference voltage Vref output by the reference voltage circuit 71. That is, the semiconductor module 10b operates normally in the range in which the voltage Vout applied to the terminal VO is greater than the voltage Voc and equal to or less than the power supply voltage Vdd.

[0171] When the voltage Vout is higher than the voltage Voc and lower than the power supply voltage Vdd, i.e., when the voltage Vsns is lower than the reference voltage Vref, the determination circuit 72 outputs a high-level voltage Vcmp. On the other hand, when the voltage Vout is lower than the voltage Voc, i.e., when the voltage Vsns is higher than the reference voltage Vref, the determination circuit 72 outputs a low-level voltage Vcmp.

[0172] The voltage flt indicates the same logic level as the voltage Vcmp.

[0173] ===Summary=== The semiconductor modules 10a and 10b of this embodiment have been described above.

[0174] In this embodiment, a semiconductor module 10a or 10b is provided, which includes: a MOS transistor 23 connected to a line L1 to which a power supply voltage Vdd is applied; a MOS transistor 24 connected in parallel to the MOS transistor 23 and to the line L1; drive circuits 22a and 22b that apply a voltage Vdrv to a line L2 to turn on the MOS transistors 23 and 24 in response to a signal S1; a resistor 25 having one end connected to the line L2 and the other end connected to a control electrode of the MOS transistor 24; a resistor 26 having one end connected to the other end of the resistor 25 and the other end connected to the control electrode of the MOS transistor 23; a resistor 28 connected to the MOS transistor 24 and generating a voltage Vsns corresponding to a current Isns flowing through the MOS transistor 24; a MOS transistor 29 connected to the other end of the resistor 26 and having a control electrode to which the voltage Vsns is applied; and a terminal VO to which the MOS transistors 23, 24, and 29, the resistor 28, and a load 13 to which the current Ids is supplied are connected.

[0175] This allows the current Ids to be limited to or below the current Ioc1 when an overcurrent occurs in the MOS transistor 23 due to a short circuit in a path other than the load 13 between the terminal VO and ground, causing a current Ids larger than that which turns on the MOS transistor 29.

[0176] The semiconductor modules 10a and 10b also include a diode 27 having an anode connected to the resistor 25 and a cathode connected to the control electrode of the MOS transistor .

[0177] This maintains the potential difference between the voltages Vg1 and Vg2 applied to the control electrodes of the MOS transistors 23 and 24 equal to or less than the forward voltage of the diode 27, stabilizing the operation of the semiconductor modules 10a and 10b when they are turned on.

[0178] In addition, the semiconductor modules 10a and 10b include a substrate 61 on which the MOS transistors 23 and 24 are provided, and an oxide film 63 provided above the substrate 61, and the diode 27 includes a P+ type dopant diffusion region 64 provided above the oxide film 63, and an N+ type dopant diffusion region 65 connected to the dopant diffusion region 64 and provided above the oxide film 63.

[0179] In this way, in the semiconductor modules 10a and 10b, by disposing the oxide film 63 above the substrate 61, the diode 27 can be integrated on the same semiconductor chip as the MOS transistors 23 and 24 and the like.

[0180] The semiconductor module 10b also includes a reference voltage circuit 71 that generates a predetermined voltage Vref, and a determination circuit 72 that determines whether the MOS transistor 23 is in an overcurrent state based on a comparison between the voltage Vsns and the voltage Vref, and the drive circuit 22b turns the MOS transistor 23 on and off based on the signal S1 and the determination result of the determination circuit 72.

[0181] This allows the elements in the semiconductor module 10b to be more thoroughly protected from overcurrent due to a load short circuit.

[0182] The resistors 25 and 26 have resistance values ​​that make the current Ids flowing through the MOS transistor 23 equal to or less than the current value Ioc1, and the voltage Vref is a voltage that makes the current Ids flowing through the MOS transistor 23 exhibit a current value Ioc2 that is smaller than the current value Ioc1.

[0183] That is, in the semiconductor module 10b of this embodiment, the current value Ioc2 at which the determination circuit 72 performs overcurrent protection is lower than the current value Ioc1 at which the resistors 25, 26 and the MOS transistor 29, etc., perform overcurrent limitation. Therefore, in the semiconductor module 10b, during the period when the determination circuit 72 can provide overcurrent protection, protection is performed based on the current value Ioc2, and during the period when the determination circuit 72 cannot provide protection, the current Ids is limited to or less than the current Ioc1, thereby protecting the elements of the semiconductor module 10b from overcurrent.

[0184] Furthermore, the drive circuit 22b turns on the MOS transistor 23 for a predetermined period Tflt when the MOS transistor 23 is turned on, regardless of the judgment result of the judgment circuit 72, and turns off the MOS transistor 23 after the predetermined period Tflt has elapsed, if the judgment circuit 72 judges that the MOS transistor 23 is in an overcurrent state.

[0185] That is, in the semiconductor module 10b, when the current Ids exceeds the current value Ioc1 except during the period Tflt, overcurrent protection is performed by turning off the MOS transistor 23, and during the period Tflt, overcurrent protection is performed by limiting the current Ids flowing through the MOS transistor 23 to less than or equal to the current Ioc1.

[0186] This allows the semiconductor module 10b to protect the MOS transistor 23 from an overcurrent during the filter period Tflt.

[0187] The drive circuit 22b includes a drive signal output circuit 34 that outputs a signal S2 for turning the MOS transistor 23 on and off based on the signal S1 and the determination result of the determination circuit 72, a boost circuit 32 that boosts the power supply voltage Vdd in response to the signal S2 for turning the MOS transistor 23 on and applies a voltage Vdrv to the line L2, and a MOS transistor 33 that lowers the voltage Vdrv on the line L2 in response to the signal S2 for turning the MOS transistor 23 off.

[0188] In this way, the semiconductor module 10b has the boost circuit 32 and the MOS transistor 33 that operate based on the signal S2, and can supply the voltage Vdrv for appropriately turning the MOS transistor 23 on and off.

[0189] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that the technical scope of the present invention may include forms incorporating such modifications and improvements and their equivalents without departing from the spirit of the invention.

[0190] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0191] 10a, 10b Semiconductor modules 11 Microcomputer 12 Power supply 13 Load 21 Voltage generation circuit 22a, 22b drive circuit 23, 24, 29 MOS transistors 25, 26, 28 Resistance 27 Diode 31 Control circuit 32 Boost circuit 33 MOS transistor 34 Drive signal output circuit 41 Inductor 42 Resistance 50 Oscillator Circuit 51, 54, 56, 58 Diodes 52,57 Capacitor 53 Inverter 61 PCB 62 Epitaxial layer 63,67 Oxide film 64,65,66 Dopant diffusion region 68 anodes 69 Cathode 71 Reference voltage circuit 72 Judgment circuit 81 Control circuit 82 Filter Circuit

Claims

1. a first transistor having a power supply side electrode connected to a first line to which a power supply voltage is applied; a second transistor connected in parallel to the first transistor and having a power supply side electrode connected to the first line; a drive circuit that applies a first voltage to a second line in response to an input signal to turn on the first transistor and the second transistor; a first resistor having one end connected to the second line and the other end connected to the control electrode of the second transistor; a second resistor having one end connected to the other end of the first resistor and the other end connected to the control electrode of the first transistor; a third resistor connected to a ground electrode of the second transistor and generating a second voltage corresponding to a current flowing through the second transistor; a third transistor having a power supply side electrode connected to the other end of the second resistor and having a control electrode to which the second voltage is applied; a terminal to which the first and third transistors, the third resistor, and a load are connected; a diode having an anode connected to the first resistor and a cathode connected to the control electrode of the first transistor; Equipped with the load is supplied with current from the first transistor; the second transistor is connected to the terminal via the third resistor; Semiconductor module.

2. 2. The semiconductor module according to claim 1, a substrate on which the first transistor and the second transistor are provided; an oxide film provided above the substrate; Equipped with the diode includes a first dopant diffusion region of a first conductivity type provided above the oxide film, and a second dopant diffusion region of a second conductivity type connected to the first dopant diffusion region and provided above the oxide film; Semiconductor module.

3. 3. The semiconductor module according to claim 1, a reference voltage circuit that generates a predetermined third voltage; a determination circuit that determines whether the first transistor is in an overcurrent state based on a comparison between the second voltage and the third voltage; Equipped with The drive circuit turning on and off the first transistor based on the input signal and the determination result of the determination circuit; Semiconductor module.

4. 4. The semiconductor module according to claim 3, the first and second resistors have resistance values ​​that cause a current flowing through the first transistor to be equal to or less than a first current value that indicates an overcurrent state; the third voltage is a voltage at which a current flowing through the first transistor exhibits a second current value that is smaller than the first current value; Semiconductor module.

5. 5. The semiconductor module according to claim 3, The drive circuit For a predetermined period when the first transistor is turned on, the first transistor is turned on regardless of the determination result of the determination circuit, and after the predetermined period has elapsed, if the determination circuit determines that the first transistor is in an overcurrent state, the first transistor is turned off. Semiconductor module.

6. The semiconductor module according to any one of claims 3 to 5, The drive circuit a drive signal output circuit that outputs a drive signal for turning on and off the first transistor based on the input signal and the determination result of the determination circuit; a booster circuit that boosts the power supply voltage in response to the drive signal for turning on the first transistor and applies the first voltage to the second line; a blocking element that reduces the voltage of the second line in response to the drive signal for turning off the first transistor; Including, Semiconductor module.

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